5 4 3 2 1

D D

LV115 Schematics
Skylake-U
C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 1 of 102
5 4 3 2 1
 5 4 3 2 1

CHARGER
Project code: BQ24780RUYR 44
PCB LAYER
LV115SK:4PD08B010001
LV114SK:4PD08A010001
LV115/LV114 SKL-U Block Diagram L1:Top
INPUTS
AD+
OUTPUTS

L2:VCC DCBATOUT
PCB P/N: 15277/15309 L3:Signal
BT+
Revision: SA 32.768KHz 24MHz L4:Signal SYSTEM DC/DC
L5:GND TPS51275CRUKR 45
IO Board: X7901 L6:Signal
27MHz INPUTS OUTPUTS
3D3V_AUX_S5
D SM Bus AMD GPU VRAM x4 5V_PWR_2 D
DCBATOUT 5V_S5
EXO Pro S3 GDDR3 / 1.5V
DDR4 SO-DIMM x1 13 DDR4 1866/2133MHz Channel A 900MHz 3D3V_S5
PEG x4 18W 76~80 81~84
Intel CPU CPU Core Power
NCP81208MNTXG 46~50
DDR4 MD x4 pcs DDR4 1866/2133MHz Channel B Skylake U LAN 10/100/1000
33
14 NCP81382MNTXG x 2
28W (UMA only) PCIe x 1 RJ45
RealTek RTL8111H NCP81382MNTXG(23e)
15W (UMA&DIS)
30
Conn. NCP81253MNTBG
Left side
USB3.0 x 2 INPUTS OUTPUTS
USB 3.0 SKT x2
DCBATOUT VCC_CORE
25MHz DCBATOUT +VCCGT
SKL PCH-LP
Right side DCBATOUT +V_VCCGTUS_VR
USB2.0 x 1 10 USB 2.0/1.1 ports PCIe x 1
USB 2.0 SKT x NGFF WLAN (23e only)
6 USB 3.0 ports
High Definition Audio
W/ Bluetooth DCBATOUT+VCCSA_VR
USB2.0 x 1 COMBO
3 SATA ports DDR3L SUS
61
6 PCIE ports TPS51716RUKR 51
LPC I/F INPUTS OUTPUTS
ACPI 5.0
14.0"/15.6" (FHD) eDP DCBATOUT 1D35V_S3
C C
0D65V_S0

CPU VCCIO 0.975V

RT8068AZQWID 52
HDMI V1.4b HDMI
57 INPUTS OUTPUTS
SATA(Gen3) x 1 HDD 60 3D3V_S5 +VCCIO_VR

CRT Travis eDP SATA(Gen2) x 1 CPU VCCPRIM_CORE

ODD 61
0.95V
TPS22961DNYT 52
INPUTS OUTPUTS
LPC BUS LPC Debug Port
Camera (HD) 3D3V_S5 VCCPRIM_CORE
USB2.0 x 1 65
52 CPU DCDC-V1D00A
D-MIC AOZ1268QI 53
SMBUS Thermal INPUTS OUTPUTS
SPI NUVOTON
2CH SPEAKER NCT7718W 26 DCBATOUT 1D0V_S5
(2CH 2W/4ohm) HDA
KBC LDO-V1D5V
CODEC TLV70215DBVR 54
B Realtek Flash ROM NPCE285 SMBUS 1ST Battery INPUTS OUTPUTS B

MIC_IN/GND
HDA
ALC3240 16MB 25 3D3V_S5 1D5V_S0
Universal Jack HP_R/L 29
27 LDO-V1D8V
RT9025-25ZSP 54
24
INPUTS OUTPUTS
3D3V_S5 1D8V_S5
SD Card Slot PS2 PWM 5V/3V S0
CardReader G5016KD1U 40
SDR50 USB2.0 x 1
INPUTS OUTPUTS
SSD/MMC Clickpad Int. 5V_S5 5V_S0
I2C FAN 3D3V_S5 3D3V_S0
62
KB 26 VCCSTG EOPIO/EDRAM (23e)
M5938ARD1U TPS22961DNYT 52
INPUTS OUTPUTS INPUTS OUTPUTS
1D0V_S5 +V_EDRAM_VR
1D0V_S5 +V1.00DX 40
PCB Halogen PN No Halogen PN 1D0V_S5 +V_EOPIO_VR
LV115SK MB 15277 15309 VCCST 3D3V VGA
LV115SK BTN BD 15902 15939 M5938ARD1U G5016KD1U 86
LV115SK AUDIO IO BD 15903 15940 INPUTS OUTPUTS INPUTS OUTPUTS
LV115SK ODD BD 15904 15941 1D0V_S5 +V1.00U_CPU 3D3V_S0 +V_EDRAM_VR
A 40 3D3V_S0 +V_EOPIO_VR
A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Block Diagram
Size Document Number Rev
C
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 2 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 3 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

+VCCST_CPU

1
R419

+VCCSTG
+VCCSTG = 1.0 V 1KR2J-1-GP +VCCSTG = 1.0 V

2
R420 +VCCSTG
PCH_THERMTRIP 1 2
D
DY H_THERMTRIP# 40 D

1
R401 0R2J-2-GP
[PECI] and [PROCHOT#] Rb 1KR2J-1-GP
Impedance control: 50 ohm TP401 CPU1D 4 OF 20

2
1 H_CATERR# D63 SKYLAKE_ULT
CATERR#
24 H_PECI A54 PECI
499R2F-2-GP 1 R403 2 H_PROCHOT#_R C65 JTAG
24,46 H_PROCHOT# PROCHOT#
PCH_THERMTRIP C63 PCH_JTAG_TDO 1 2
Ra THERMTRIP#
TP402 1SKTOCC# A65 SKTOCC# PROC_TCK B61 PROC_TCK 99 51R2J-2-GP R407
CPU MISC D60 PROC_TDI 99
C55
PROC_TDI
A61 DY
BPM#[0] PROC_TDO
#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm D55 BPM#[1] PROC_TMS C60 PROC_TMS 99
#544669 Rev0.52: B54 BPM#[2] PROC_TRST# B59 PROC_TRST# 99
Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohm C56 BPM#[3]

TP403 1 GPP_E3/CPU_GP0 A6 B56 PCH_JTAG_TCK 99

GPP_E3/CPU_GP0 PCH_JTAG_TCK
A7 GPP_E7/CPU_GP1 PCH_JTAG_TDI D59
BA5 GPP_B3/CPU_GP2 PCH_JTAG_TDO A56 PCH_JTAG_TDO 99
TP404 1 GPP_B4/CPU_GP3 AY5 C59 PROC_TCK R406 1 2 51R2J-2-GP
GPP_B4/CPU_GP3 PCH_JTAG_TMS
PCH_TRST# C61
2 1 CPU_POPIRCOMP AT16 PROC_POPIRCOMP JTAGX A59 DY
49D9R2F-GP 2 R412 1 PCH_POPIRCOMP AU16
49D9R2F-GP 2 R413 PCH_OPIRCOMP
1EDRAM_OPIO_RCOMP H66 OPCE_RCOMP
49D9R2F-GP 2 R414 1 EOPIO_RCOMP H65
49D9R2F-GP R415 OPC_RCOMP

SKYLAKE-U-GP
C C

071.SKYLA.000U

CPU BOM CTRL

(#543016) PROCHOT# Routing Guidelines

B B

M1,2,3,4,5: <3 inches

M6: 1-11 inches
MCPU: 0.3-1.5 inches
Mt <0.3 mils
Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(JTAG/CPU SIDE BAND)

Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 4 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

DDR4 ball type: Interleaved Type

M_A_BG1
D M_VREF_DQ_DIMM0 D

Reserve Testpoint only

CPU1C 3 OF 20
CPU1B 2 OF 20

SKYLAKE_ULT M_A_DQ32 AY39 SKYLAKE_ULT AN45

12 M_A_DQ32 DDR0_DQ[32]/DDR1_DQ[0] DDR1_CKN[0] M_B_CLK#0 13
12 M_A_DQ0 M_A_DQ0 AL71 AU53 12 M_A_DQ33 M_A_DQ33 AW39 AN46
M_A_DQ1 DDR0_DQ[0] DDR0_CKN[0] M_A_CLK#0 12 M_A_DQ34 DDR0_DQ[33]/DDR1_DQ[1] DDR1_CKN[1] M_B_CLK#1 13
12 M_A_DQ1 AL68 AT53 12 M_A_DQ34 AY37 AP45
M_A_DQ2 DDR0_DQ[1] DDR0_CKP[0] M_A_CLK0 12 M_A_DQ35 DDR0_DQ[34]/DDR1_DQ[2] DDR1_CKP[0] M_B_CLK0 13
12 M_A_DQ2 AN68 AU55 12 M_A_DQ35 AW37 AP46
M_A_DQ3 DDR0_DQ[2] DDR0_CKN[1] M_A_DQ36 DDR0_DQ[35]/DDR1_DQ[3] DDR1_CKP[1] M_B_CLK1 13
12 M_A_DQ3 AN69 AT55 12 M_A_DQ36 BB39
M_A_DQ4 DDR0_DQ[3] DDR0_CKP[1] M_A_DQ37 DDR0_DQ[36]/DDR1_DQ[4]
12 M_A_DQ4 AL70 12 M_A_DQ37 BA39 AN56
M_A_DQ5 DDR0_DQ[4] M_A_DQ38 DDR0_DQ[37]/DDR1_DQ[5] DDR1_CKE[0] M_B_CKE0 13
12 M_A_DQ5 AL69 BA56 12 M_A_DQ38 BA37 AP55
M_A_DQ6 DDR0_DQ[5] DDR0_CKE[0] M_A_CKE0 12 M_A_DQ39 DDR0_DQ[38]/DDR1_DQ[6] DDR1_CKE[1] M_B_CKE1 13
12 M_A_DQ6 AN70 BB56 12 M_A_DQ39 BB37 AN55
M_A_DQ7 DDR0_DQ[6] DDR0_CKE[1] M_A_DQ40 DDR0_DQ[39]/DDR1_DQ[7] DDR1_CKE[2]
12 M_A_DQ7 AN71 AW56 12 M_A_DQ40 AY35 AP53
M_A_DQ8 DDR0_DQ[7] DDR0_CKE[2] M_A_DQ41 DDR0_DQ[40]/DDR1_DQ[8] DDR1_CKE[3]
12 M_A_DQ8 AR70 AY56 12 M_A_DQ41 AW35
M_A_DQ9 DDR0_DQ[8] DDR0_CKE[3] M_A_DQ42 DDR0_DQ[41]/DDR1_DQ[9]
12 M_A_DQ9 AR68 12 M_A_DQ42 AY33 BB42
M_A_DQ10 DDR0_DQ[9] M_A_DQ43 DDR0_DQ[42]/DDR1_DQ[10] DDR1_CS#[0] M_B_CS#0 13
12 M_A_DQ10 AU71 AU45 12 M_A_DQ43 AW33 AY42
M_A_DQ11 DDR0_DQ[10] DDR0_CS#[0] M_A_CS#0 12 M_A_DQ44 DDR0_DQ[43]/DDR1_DQ[11] DDR1_CS#[1] M_B_CS#1 13
12 M_A_DQ11 AU68 AU43 12 M_A_DQ44 BB35 BA42
M_A_DQ12 DDR0_DQ[11] DDR0_CS#[1] M_A_DQ45 DDR0_DQ[44]/DDR1_DQ[12] DDR1_ODT[0] M_B_ODT0 13
12 M_A_DQ12 AR71 AT45 12 M_A_DQ45 BA35 AW42
M_A_DQ13 DDR0_DQ[12] DDR0_ODT[0] M_A_ODT0 12 M_A_DQ46 DDR0_DQ[45]/DDR1_DQ[13] DDR1_ODT[1] M_B_ODT1 13
12 M_A_DQ13 AR69 AT43 12 M_A_DQ46 BA33
M_A_DQ14 DDR0_DQ[13] DDR0_ODT[1] M_A_DQ47 DDR0_DQ[46]/DDR1_DQ[14] M_B_A5
12 M_A_DQ14 AU70 12 M_A_DQ47 BB33 AY48 M_B_A5 13
M_A_DQ15 DDR0_DQ[14] M_A_A5 M_B_DQ32 DDR0_DQ[47]/DDR1_DQ[15] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] M_B_A9
12 M_A_DQ15 AU69 BA51 M_A_A5 12 13 M_B_DQ32 AU40 AP50 M_B_A9 13
M_B_DQ0 DDR0_DQ[15] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] M_A_A9 M_B_DQ33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] M_B_A6
13 M_B_DQ0 AF65 DDR0_DQ[16] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BB54 M_A_A9 12 13 M_B_DQ33 AT40 BA48 M_B_A6 13
M_B_DQ1 DDR1_DQ[0]/DDR0_DQ[16] M_A_A6 M_B_DQ34 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] M_B_A8
13 M_B_DQ1 AF64 DDR0_DQ[17] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] BA52 M_A_A6 12 13 M_B_DQ34 AT37 BB48 M_B_A8 13
M_B_DQ2 DDR1_DQ[1]/DDR0_DQ[17] M_A_A8 M_B_DQ35 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] M_B_A7
13 M_B_DQ2 AK65 AY52 M_A_A8 12 13 M_B_DQ35 AU37 AP48 M_B_A7 13
M_B_DQ3 DDR1_DQ[2]/DDR0_DQ[18]DDR0_DQ[18] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] M_A_A7 M_B_DQ36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
13 M_B_DQ3 AK64
DDR1_DQ[3]/DDR0_DQ[19]DDR0_DQ[19] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
AW52 M_A_A7 M_B_DQ[32:39]
12 13 M_B_DQ36 AR40
DDR1_DQ[36]/DDR1_DQ[20] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
AP52 M_B_BG0 13
M_B_DQ[0:7] 13 M_B_DQ4 M_B_DQ4 AF66 AY55 13 M_B_DQ37 M_B_DQ37 AP40 AN50 M_B_A12 M_B_A12 13
DDR1_DQ[4]/DDR0_DQ[20]DDR0_DQ[20] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] M_A_BG0 12 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
13 M_B_DQ5 M_B_DQ5 AF67 AW54 M_A_A12 M_A_A12 12 13 M_B_DQ38 M_B_DQ38 AP37 AN48 M_B_A11 M_B_A11 13
M_B_DQ6 DDR1_DQ[5]/DDR0_DQ[21]DDR0_DQ[21]DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] M_A_A11 M_B_DQ39 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
13 M_B_DQ6 AK67 BA54 M_A_A11 12 13 M_B_DQ39 AR37 AN53 M_B_ACT_N 13
M_B_DQ7 DDR1_DQ[6]/DDR0_DQ[22]DDR0_DQ[22]DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M_B_DQ40 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR4 DDR3L
13 M_B_DQ7 AK66 BA55 M_A_ACT_N 12 13 M_B_DQ40 AT33 AN52 M_B_BG1 13
M_B_DQ8 DDR1_DQ[7]/DDR0_DQ[23]DDR0_DQ[23] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# M_A_BG1 M_B_DQ41 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
13 M_B_DQ8 AF70 AY54 1 13 M_B_DQ41 AU33
M_B_DQ9 DDR1_DQ[8]/DDR0_DQ[24] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] TP504 TPAD14-OP-GP M_B_DQ42 DDR1_DQ[41]/DDR1_DQ[25] M_B_A13 M_B_A14 AY44 AN52
13 M_B_DQ9 AF68 13 M_B_DQ42 AU30 BA43 M_B_A13 13
M_B_DQ10 DDR1_DQ[9]/DDR0_DQ[25] M_A_A13 M_B_DQ43 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] M_B_A15_CAS#
13 M_B_DQ10 AH71 AU46 M_A_A13 12 13 M_B_DQ43 AT30 AY43 M_B_A15_CAS# 13
M_B_DQ11 DDR1_DQ[10]/DDR0_DQ[26] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] M_A_A15_CAS# M_B_DQ44 DDR1_DQ[43]/DDR1_DQ[27] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] M_B_A14_WE# M_B_A15 AY43 AN53
13 M_B_DQ11 AH68
DDR1_DQ[11]/DDR0_DQ[27] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
AU48 M_B_DQ[40:47]
M_A_A15_CAS# 12 13 M_B_DQ44 AR33
DDR1_DQ[44]/DDR1_DQ[28] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
AY44 M_B_A14_WE# 13
M_B_DQ[8:15] 13 M_B_DQ12 M_B_DQ12 AF71 AT46 M_A_A14_WE# M_A_A14_WE# 12 13 M_B_DQ45 M_B_DQ45 AP33 AW44 M_B_A16_RAS# M_B_A16_RAS# 13
M_B_DQ13 DDR1_DQ[12]/DDR0_DQ[28] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] M_A_A16_RAS# M_B_DQ46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] M_B_A16 AW44 N/A
13 M_B_DQ13 AF69 AU50 M_A_A16_RAS# 12 13 M_B_DQ46 AR30 BB44 M_B_BA0 13
M_B_DQ14 DDR1_DQ[13]/DDR0_DQ[29] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] M_B_DQ47 DDR1_DQ[46]/DDR1_DQ[30] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] M_B_A2
13 M_B_DQ14 AH70 AU52 M_A_BA0 12 13 M_B_DQ47 AP30 AY47 M_B_A2 13
M_B_DQ15 DDR1_DQ[14]/DDR0_DQ[30] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] M_A_A2 M_A_DQ48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] M_B_BG1 AN52 N/A
C 13 M_B_DQ15 AH69 AY51 M_A_A2 12 12 M_A_DQ48 AY31 BA44 M_B_BA1 13 C
M_A_DQ16 DDR1_DQ[15]/DDR0_DQ[31] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] M_A_DQ49 DDR0_DQ[48]/DDR1_DQ[32] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] M_B_A10_AP
12 M_A_DQ16 BB65 AT48 M_A_BA1 12 12 M_A_DQ49 AW31 AW46 M_B_A10_AP 13
M_A_DQ17 DDR0_DQ[16]/DDR0_DQ[32] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M_A_A10_AP M_A_DQ50 DDR0_DQ[49]/DDR1_DQ[33] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] M_B_A1 M_B_BG0 AP52 N/A
12 M_A_DQ17 AW65 AT50 M_A_A10_AP 12 12 M_A_DQ50 AY29 AY46 M_B_A1 13
M_A_DQ18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] M_A_A1 M_A_DQ51 DDR0_DQ[50]/DDR1_DQ[34] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] M_B_A0
12 M_A_DQ18 AW63 BB50 M_A_A1 12 12 M_A_DQ51 AW29 BA46 M_B_A0 13
M_A_DQ19 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] M_A_A0 M_A_DQ52 DDR0_DQ[51]/DDR1_DQ[35] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] M_B_A3 M_B_PARITY AP43 N/A
12 M_A_DQ19 AY63 AY50 M_A_A0 12 12 M_A_DQ52 BB31 BB46 M_B_A3 13
M_A_DQ20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] M_A_A3 M_A_DQ53 DDR0_DQ[52]/DDR1_DQ[36] DDR1_MA[3] M_B_A4
12 M_A_DQ20 BA65 BA50 M_A_A3 12 12 M_A_DQ53 BA31 BA47 M_B_A4 13
M_A_DQ21 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[3] M_A_A4 M_A_DQ54 DDR0_DQ[53]/DDR1_DQ[37] DDR1_MA[4] M_B_ALERT_N AN43 GND
12 M_A_DQ21 AY65 BB52 M_A_A4 12 12 M_A_DQ54 BA29
M_A_DQ22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[4] M_A_DQ55 DDR0_DQ[54]/DDR1_DQ[38] M_A_DQS_DN4
12 M_A_DQ22 BA63 12 M_A_DQ55 BB29 BA38
M_A_DQ23 DDR0_DQ[22]/DDR0_DQ[38] M_A_DQS_DN0 M_A_DQ56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[4]/DDR1_DQSN[0] M_A_DQS_DP4 M_B_ACT_N AN53 N/A
12 M_A_DQ23 BB63 AM70 12 M_A_DQ56 AY27 AY38
M_A_DQ24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQSN[0] M_A_DQS_DP0 M_A_DQ57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSP[4]/DDR1_DQSP[0] M_A_DQS_DN5
12 M_A_DQ24 BA61 AM69 12 M_A_DQ57 AW27 AY34
M_A_DQ25 DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQSP[0] M_A_DQS_DN1 M_A_DQ58 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSN[5]/DDR1_DQSN[1] M_A_DQS_DP5
12 M_A_DQ25 AW61 AT69 12 M_A_DQ58 AY25 BA34
M_A_DQ26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQSN[1] M_A_DQS_DP1 M_A_DQ59 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] M_B_DQS_DN4
12 M_A_DQ26 BB59 AT70 12 M_A_DQ59 AW25 AT38
M_A_DQ27 DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQSP[1] M_B_DQS_DN0 M_A_DQ60 DDR0_DQ[59]/DDR1_DQ[43] DDR1_DQSN[4]/DDR1_DQSN[2] M_B_DQS_DP4 M_B_DQS4
12 M_A_DQ27 AW59 AH66 12 M_A_DQ60 BB27 AR38
M_A_DQ28 DDR0_DQ[27]/DDR0_DQ[43] DDR1_DQSN[0]/DDR0_DQSN[2] M_B_DQS_DP0 M_A_DQ61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_DQSP[4]/DDR1_DQSP[2] M_B_DQS_DN5
12 M_A_DQ28 BB61
DDR0_DQ[28]/DDR0_DQ[44] DDR1_DQSP[0]/DDR0_DQSP[2]
AH65 M_B_DQS0 12 M_A_DQ61 BA27
DDR0_DQ[61]/DDR1_DQ[45] DDR1_DQSN[5]/DDR1_DQSN[3]
AT32
12 M_A_DQ29 M_A_DQ29 AY61
DDR0_DQ[29]/DDR0_DQ[45] DDR1_DQSN[1]/DDR0_DQSN[3]
AG69 M_B_DQS_DN1 12 M_A_DQ62 M_A_DQ62 BA25
DDR0_DQ[62]/DDR1_DQ[46] DDR1_DQSP[5]/DDR1_DQSP[3]
AR32 M_B_DQS_DP5 M_B_DQS5
12 M_A_DQ30 M_A_DQ30 BA59 AG70 M_B_DQS_DP1 M_B_DQS1 12 M_A_DQ63 M_A_DQ63 BB25 BA30 M_A_DQS_DN6
M_A_DQ31 DDR0_DQ[30]/DDR0_DQ[46] DDR1_DQSP[1]/DDR0_DQSP[3] M_A_DQS_DN2 M_B_DQ48 DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSN[6]/DDR1_DQSN[4] M_A_DQS_DP6
12 M_A_DQ31 AY59 BA64 13 M_B_DQ48 AU27 AY30
M_B_DQ16 DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQSN[2]/DDR0_DQSN[4] M_A_DQS_DP2 M_B_DQ49 DDR1_DQ[48] DDR0_DQSP[6]/DDR1_DQSP[4] M_A_DQS_DN7 1D2V_S3
13 M_B_DQ16 AT66 AY64 13 M_B_DQ49 AT27 AY26
M_B_DQ17 DDR1_DQ[16]/DDR0_DQ[48] DDR0_DQSP[2]/DDR0_DQSP[4] M_A_DQS_DN3 M_B_DQ50 DDR1_DQ[49] DDR0_DQSN[7]/DDR1_DQSN[5] M_A_DQS_DP7
13 M_B_DQ17 AU66 AY60 13 M_B_DQ50 AT25 BA26
M_B_DQ18 DDR1_DQ[17]/DDR0_DQ[49] DDR0_DQSN[3]/DDR0_DQSN[5] M_A_DQS_DP3 M_B_DQ51 DDR1_DQ[50] DDR0_DQSP[7]/DDR1_DQSP[5] M_B_DQS_DN6
13 M_B_DQ18 AP65 BA60 M_B_DQ[48:55] 13 M_B_DQ51 AU25 AR25

1
M_B_DQ19 DDR1_DQ[18]/DDR0_DQ[50] DDR0_DQSP[3]/DDR0_DQSP[5] M_B_DQS_DN2 M_B_DQ52 DDR1_DQ[51] DDR1_DQSN[6] M_B_DQS_DP6 M_B_DQS6
M_B_DQ[16:23]13 M_B_DQ19 AN65
DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQSN[2]/DDR0_DQSN[6]
AR66 13 M_B_DQ52 AP27
DDR1_DQ[52] DDR1_DQSP[6]
AR27
13 M_B_DQ20 M_B_DQ20 AN66
DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQSP[2]/DDR0_DQSP[6]
AR65 M_B_DQS_DP2 M_B_DQS2 13 M_B_DQ53 M_B_DQ53 AN27
DDR1_DQ[53] DDR1_DQSN[7]
AR22 M_B_DQS_DN7 R505
13 M_B_DQ21 M_B_DQ21 AP66 AR61 M_B_DQS_DN3 13 M_B_DQ54 M_B_DQ54 AN25 AR21 M_B_DQS_DP7 M_B_DQS7 470R2F-GP
DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQ[54] DDR1_DQSP[7]
13 M_B_DQ22 M_B_DQ22 AT65
DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQSP[3]/DDR0_DQSP[7]
AR60 M_B_DQS_DP3 M_B_DQS3 13 M_B_DQ55 M_B_DQ55 AP25
DDR1_DQ[55]
13 M_B_DQ23 M_B_DQ23 AU65 13 M_B_DQ56 M_B_DQ56 AT22 AN43 M_B_ALERT_N 13

2
M_B_DQ24 DDR1_DQ[23]/DDR0_DQ[55] M_B_DQ57 DDR1_DQ[56] DDR1_ALERT# M_B_PARITY R504
13 M_B_DQ24 AT61 AW50 M_A_ALERT_N 12 13 M_B_DQ57 AU22 AP43 M_B_PARITY 13
M_B_DQ25 DDR1_DQ[24]/DDR0_DQ[56] DDR0_ALERT# M_A_PARITY M_B_DQ58 DDR1_DQ[57] DDR1_PAR SM_DRAMRST#
13 M_B_DQ25 AU61 AT52 M_A_PARITY 12 13 M_B_DQ58 AU21 AT13 1 2 DDR4_DRAMRST# 12,13
M_B_DQ26 DDR1_DQ[25]/DDR0_DQ[57] DDR0_PAR M_B_DQ59 DDR1_DQ[58] DRAM_RESET# SM_RCOMP_0
13 M_B_DQ26 AP60 M_B_DQ[56:63] 13 M_B_DQ59 AT21 AR18 1 R501 2 121R2F-GP
M_B_DQ27 DDR1_DQ[26]/DDR0_DQ[58] M_B_DQ60 DDR1_DQ[59] DDR_RCOMP[0] SM_RCOMP_1
M_B_DQ[24:31]13 M_B_DQ27 AN60 AY67 V_SM_VREF_CA 12 13 M_B_DQ60 AN22 AT18 1 R502 2 80D6R2F-L-GP 0R0402-PAD
M_B_DQ28 DDR1_DQ[27]/DDR0_DQ[59] DDR_VREF_CA M_VREF_DQ_DIMM01 TP503 TPAD14-OP-GP M_B_DQ61 DDR1_DQ[60] DDR_RCOMP[1] SM_RCOMP_2
13 M_B_DQ28 AN61 AY68 13 M_B_DQ61 AP22 AU18 1 R503 2 100R2F-L1-GP-U
M_B_DQ29 DDR1_DQ[28]/DDR0_DQ[60] DDR0_VREF_DQ M_B_DQ62 DDR1_DQ[61] DDR_RCOMP[2]
13 M_B_DQ29 AP61 BA67 V_SM_VREF_CNTB 13 13 M_B_DQ62 AP21

1
M_B_DQ30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_VREF_DQ M_B_DQ63 DDR1_DQ[62]
13 M_B_DQ30 AT60 13 M_B_DQ63 AN21 DDR CH - B

1
DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[63]

ED501

ED502
13 M_B_DQ31 M_B_DQ31 AU60 AW67 SM_PGCNTL #543016 C501

PESD5V0U1BL-GP-U1

PESD5V0U1BL-GP-U1
DDR1_DQ[31]/DDR0_DQ[63] DDR CH - A DDR_VTT_CNTL

SCD1U25V2KX-L-GP
SKYLAKE-U-GP
DY

2
SKYLAKE-U-GP

2
071.SKYLA.000U
071.SKYLA.000U
Design Guideline:
CPU BOM CTRL Layout Note:
SM_RCOMP keep routing length less than 500 mils.
CPU BOM CTRL
B B
M_A_DQS_DN0 M_A_DQS_DN0 12 M_B_DQS_DN0 M_B_DQS_DN0 13
M_A_DQS_DN1 M_A_DQS_DN1 12 M_B_DQS_DN1 M_B_DQS_DN1 13
M_A_DQS_DN2 M_A_DQS_DN2 12 M_B_DQS_DN2 M_B_DQS_DN2 13
M_A_DQS_DN3 M_A_DQS_DN3 12 M_B_DQS_DN3 M_B_DQS_DN3 13
M_A_DQS_DN4 M_A_DQS_DN4 12 M_B_DQS_DN4 M_B_DQS_DN4 13
M_A_DQS_DN5 M_A_DQS_DN5 12 M_B_DQS_DN5 M_B_DQS_DN5 13
M_A_DQS_DN6 M_A_DQS_DN6 12 M_B_DQS_DN6 M_B_DQS_DN6 13
M_A_DQS_DN7 M_A_DQS_DN7 12 M_B_DQS_DN7 M_B_DQS_DN7 13

M_B_DQS_DP0 M_B_DQS_DP0 13
M_A_DQS_DP0 M_A_DQS_DP0 12 M_B_DQS_DP1 M_B_DQS_DP1 13
1D2V_S3 3D3V_S0 M_A_DQS_DP1 M_B_DQS_DP2
M_A_DQS_DP1 12 M_B_DQS_DP2 13
M_A_DQS_DP2 M_A_DQS_DP2 12 M_B_DQS_DP3 M_B_DQS_DP3 13
M_A_DQS_DP3 M_A_DQS_DP3 12 M_B_DQS_DP4 M_B_DQS_DP4 13
1

M_A_DQS_DP4 M_A_DQS_DP4 12 M_B_DQS_DP5 M_B_DQS_DP5 13

R506 M_A_DQS_DP5 M_A_DQS_DP5 12 M_B_DQS_DP6 M_B_DQS_DP6 13
220KR2F-GP M_A_DQS_DP6 M_A_DQS_DP6 12 M_B_DQS_DP7 M_B_DQS_DP7 13
G

M_A_DQS_DP7 M_A_DQS_DP7 12
2

SM_PGCNTL S D DDR_PG_OUT 51

Q501
DMN5L06K-7-GP
84.05067.031
2nd = 084.00138.0A31

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(DDR)
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 5 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU CPU1S 19 OF 20

RESERVED SIGNALS-1

E68 SKYLAKE_ULT BB68 [#543016 Rev0.9]

CFG[0] RSVD_TP#BB68
B67 BB69
CFG[1] RSVD_TP#BB69
D65
CFG3 CFG[2] RSVD_TP_AK13
99 CFG3 D67 AK13 1
CFG4 CFG[3] RSVD_TP#AK13 RSVD_TP_AK12 TP605 TPAD14-OP-GP
E70 AK12 1
CFG[4] RSVD_TP#AK12 TP606 TPAD14-OP-GP
C68
CFG[5]
D68 BB2
CFG[6] RSVD#BB2
C67 BA3
CFG[7] RSVD#BA3
F71
CFG[8]
G69
CFG[9] TP5_AU5
F70 AU5 1
CFG[10] TP5 TP6_AT5 TP607 TPAD14-OP-GP
G68 AT5 1
CFG[11] TP6 TP608 TPAD14-OP-GP
H70
CFG[12]
G71
CFG[13]
D H69 D5 D
CFG[14] RSVD#D5
G70 D4
CFG[15] RSVD#D4
B2
RSVD#B2
E63 C2
CFG[16] RSVD#C2
F63
CFG[17]
B3
RSVD#B3
E66 A3
CFG[18] RSVD#A3
F66
CFG[19]
AW1
49D9R2F-GP CFG_RCOMP RSVD#AW1
2 1 R601 E60
CFG_RCOMP
E1
RSVD#E1
99 ITP_PMODE E8 E2
ITP_PMODE RSVD#E2
AY2 BA4
RSVD#AY2 RSVD#BA4
AY1 BB4
RSVD#AY1 RSVD#BB4
D1 A4
RSVD#D1 RSVD#A4
D3 C4
RSVD#D3 RSVD#C4
K46 BB5 TP4_BB5 1
RSVD#K46 TP4 TP609 TPAD14-OP-GP
K45
RSVD#K45
A69
RSVD#A69
AL25 B69
RSVD#AL25 RSVD#B69
AL27
RSVD#AL27 RSVD_AY3
AY3 1 R606 2
RSVD#AY3 0R2J-2-GP
C71
RSVD#C71
B70
RSVD#B70 RSVD#D71
D71 DY
C70
RSVD#C70
F60
RSVD#F60
C54
RSVD#C54
A52 D54
RSVD#A52 RSVD#D54
BA70 AY4 TP1_AY4 1
RSVD_TP#BA70 TP1 TP2_BB3 TP610 TPAD14-OP-GP
BA68 BB3 1
RSVD_TP#BA68 TP2 TP611 TPAD14-OP-GP
J71 AY71 VSS_AY71 1 R602 2 0R0402-PAD #54469 CRB.
RSVD#J71 VSS ZVM#
J68 AR56 ZVM# 40
RSVD#J68 ZVM#
1 RSVD_F65 F65 AW71
TPAD14-OP-GP TP612 RSVD_G65 VSS RSVD_TP#AW71
RSVD_TP_AW71 +VCCST_CPU
1 G65 AW70
TPAD14-OP-GP TP613 VSS RSVD_TP#AW70
RSVD_TP_AW70 R607
C F61 AP56 MSM# 1 2 0R2J-2-GP MSM#_R 1 TP617 C
RSVD#F61 MSM# TPAD14-OP-GP
E61
RSVD#E61 PROC_SELECT#
C64 DY
PROC_SELECT# 1 2
R603
SKYLAKE-U-GP 100KR2J-1-GP

PCH strap pin: 071.SKYLA.000U CPU BOM CTRL

CFG3
1

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

R604
1KR2J-1-GP 0 : ENABLED
DY
CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
2

1 : DISABLED

(#543016)
CFG4
1

DISPLAY PORT PRESENCE STRAP

R605
1KR2J-1-GP
0 : ENABLED
CFG[4]
An external Display Port device is connected to the Embedded Display Port.
2

1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

SKL(#543016):
Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*
B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(RESERVED)
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 6 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

CPU1L 12 OF 20 CPU1M 13 OF 20
VCC_CORE VCC_CORE +VCCGT
CPU POWER 1 OF 4
+VCCGT CPU POWER 2 OF 4
A30 G32 N70
VCC VCC VCCGT
A34 G33 A48 N71
VCC SKYLAKE_ULT VCC VCCGT SKYLAKE_ULT VCCGT +VDDQ_CPU_CLK 1D2V_S3
A39 G35 A53 R63
VCC VCC VCCGT VCCGT
A44 G37 A58 R64
VCC VCC VCCGT VCCGT
AK33 G38 A62 R65
VCC VCC VCCGT VCCGT
AK35 G40 A66 R66
VCC VCC VCCGT VCCGT

1
AK37 G42 AA63 R67
VCC VCC VCCGT VCCGT C722
AK38
VCC VCC
J30 AA64
VCCGT VCCGT
R68 DY SC1U10V2KX-1GP
AK40 J33 AA66 R69

2
VCC VCC VCCGT VCCGT

1
AL33 J37 AA67 R70
VCC VCC VCCGT VCCGT C719 +VCCIO
AL37 J40 AA69 R71
VCC VCC VCCGT VCCGT CPU1N 14 OF 20
AL40 K33 AA70 T62 SC1U10V2KX-1GP

2
VCC VCC VCCGT VCCGT +VCCIO(ICCMAX.=2.73A
AM32 K35 AA71 U65 CPU POWER 3 OF 4
VCC VCC VCCGT VCCGT
AM33 K37 AC64 U68
VCC VCC VCCGT VCCGT
AM35 K38 AC65 U71 AU23 AK28
D VCC VCC VCCGT VCCGT VDDQ VCCIO D
AM37 K40 AC66 W63 AU28 AK30
VCC VCC VCCGT VCCGT VDDQ SKYLAKE_ULT VCCIO
AM38 K42 AC67 W64 AU35 AL30
VCC VCC VCCGT VCCGT VDDQ VCCIO
G30 K43 AC68 W65 AU42 AL42
VCC VCC VCCGT VCCGT VDDQ VCCIO
AC69 W66 BB23 AM28
TPAD14-OP-GP TP701 +VCCCOREG0 VCCGT VCCGT VDDQ VCCIO
1 K32 RSVD_K32 E32 AC70 W67 BB32 AM30
RSVD#K32 VCC_SENSE VCC_SENSE 46 VCCGT VCCGT VDDQ VCCIO +VCCSA
E33 AC71 W68 BB41 AM42
TPAD14-OP-GP TP702 +VCCCOREG1 VSS_SENSE VSS_SENSE 46 VCCGT VCCGT VDDQ VCCIO
1 AK32 J43 W69 BB47
RSVD#AK32
RSVD_AK32
H_CPU_SVIDALRT# VCCGT VCCGT +VDDQ_CPU_CLK VDDQ
B63 J45 W70 BB51 AK23
VIDALERT# H_CPU_SVIDCLK VCCGT VCCGT VDDQ VCCSA
AB62 A63 J46 W71 AK25
3A +V_EDRAM_VR
P62
V62
VCCOPC
VCCOPC
VIDSCK
VIDSOUT
D64 H_CPU_SVIDDAT +VCCSTG J48
J50
VCCGT
VCCGT
VCCGT
VCCGT
Y62 SC10U6D3V3MX-GP2 1 C715
+VCCST_CPU AM40
VCCSA
VCCSA
G23
G25
VCCOPC +VCCFUSEPRG VCCGT +VCCGT VDDQC VCCSA
G20 1 R703 2 J52 G27
VCCSTG VCCGT SC1U10V2KX-1GP 2 VCCSA
H63 J53 AK42 1 C716 0.04 A A18 G28
140mA +V1.8S_EDRAM

1 R702 2 VCC_EDRAM_FUSEPRG G61

VCC_OPC_1P8 0R0603-PAD J55
J56
VCCGT
VCCGT
VCCGTX
VCCGTX
AK43
AK45
+VCCSTG
A22
VCCST VCCSA
VCCSA
J22
J23
VCC_OPC_1P8 VCCGT VCCGTX SC1U10V2KX-1GP 2 VCCSTG VCCSA
J58 AK46 1 C717 J27
0R0603-PAD VCCSENSE_EDRAM_VR VCCGT VCCGTX VCCSA
+V_EDRAM_VR VSSSENSE_EDRAM_VR
AC63
VCCOPC_SENSE
J60
VCCGT VCCGTX
AK48 DY 1D2V_S3
AL23
VCCPLL_OC VCCSA
K23
AE63 K48 AK50 K25
VSSOPC_SENSE VCCGT VCCGTX VCCSA
K50 AK52 K20 K27
VCCGT VCCGTX SCD1U16V2KX-3GP2 VCCPLL VCCSA
AE62 K52 AK53 1 C718 K21 K28
3A +V_EOPIO_VR
AG62
VCCEOPIO
VCCEOPIO
K53
VCCGT
VCCGT
VCCGTX
VCCGTX
AK55
VCCPLL VCCSA
VCCSA
K30
C701

C702

K55 AK56
VCCGT VCCGTX
1

VCCSENSE_EOPIO_VR AL63 K56 AK58 #544669 CRB. +V1.00U_CPU AM23 VCCIO_VR_FB

C710 C711 VSSSENSE_EOPIO_VR VCCEOPIO_SENSE VCCGT VCCGTX VCCIO_SENSE VSSIO_VR_FB
23e 23e AJ62 K58 AK60 AM22
SCD1U25V2KX-L-GP

SCD1U25V2KX-L-GP

VSSEOPIO_SENSE VCCGT VCCGTX VSSIO_SENSE

23e 23e K60 AK70
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
2

VCCGT VCCGTX 1D2V_S3 +VDDQ_CPU_CLK

C720

C721
L62
VCCGT VCCGTX
AL43 0.12 A VSSSA_SENSE
H21 VSSSA_SENSE 46

1
SKYLAKE-U-GP L63 AL46 H20
VCCGT VCCGTX VCCSA_SENSE VCCSA_SENSE 46
L64 AL50
VCCGT VCCGTX
071.SKYLA.000U L65 AL53 1 R705 2

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

2
VCCGT VCCGTX SKYLAKE-U-GP
L66 AL56
VCCGT VCCGTX 0R0603-PAD
L67 AL60
VCCGT VCCGTX
CPU BOM CTRL L68
VCCGT VCCGTX
AM48 071.SKYLA.000U (#543016 SKL U/Y PDG rev1.0)
L69 AM50
+V_EOPIO_VR VCCGT VCCGTX
L70 AM52
VCCGT VCCGTX
+V_EDRAM_VR
L71
VCCGT VCCGTX
AM53 CPU BOM CTRL
R724 M62 AM56
100R2J-2-GP VCCGT VCCGTX
23e N63
VCCGT VCCGTX
AM58
+VCCIO +VCCSTG +VCCIO
C703

C704

N64 AU58
VCCGT VCCGTX
1

23e 23e 1 2 VCCSENSE_EDRAM_VR N66 AU63 R710

VSSSENSE_EDRAM_VR VCCGT VCCGTX
1 2 N67 BB57 1 2 RN705
VCCGT VCCGTX 0R0402-PAD VCCIO_VR_FB
N69 BB66 1 4
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
2

R725 VCCGT VCCGTX VSSIO_VR_FB

100R2J-2-GP
23e 2 3
46 VCCGT_SENSE J70 AK62
VCCGT_SENSE VCCGTX_SENSE
46 VSSGT_SENSE J69
VSSGT_SENSE VSSGTX_SENSE
AL61 +VCCSTG(ICCMAX.=0.16A)
SRN100J-3-GP

+V_EOPIO_VR SKYLAKE-U-GP
R729
100R2J-2-GP +VCCSA
23e 071.SKYLA.000U
1 2 VCCSENSE_EOPIO_VR RN706
1 2 VSSSENSE_EOPIO_VR CPU BOM CTRL 1 4 VCCSA_SENSE
2 3 VSSSA_SENSE
R731 23e
100R2J-2-GP +VCCSA +VCCSA
SRN100J-3-GP

VCC_CORE

1
C C723 C724 C
SC1U10V2KX-1GP SCD1U16V2KX-3GP RN701
DY DY 2 3 VCC_SENSE 46

2
R2
1 R1
4 VSS_SENSE 46
SRN100F-1-GP
Layout Note:
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm
3. Length match<25mil
Layout Note:
SVID DATA The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).
Route the Alert signal between the Clock and the Data signals.

+VCCST_CPU

+VCCGT

RN702
1

CLOSE TO CPU 1 R1
4 VCCGT_SENSE 46
R726 2 R2
3 VSSGT_SENSE 46
100R2F-L1-GP-U #544669
SRN100F-1-GP
2

R709
H_CPU_SVIDDAT 1 2 VR_SVID_DATA 46
0R0402-PAD

+VCCST_CPU

SVID CLOCK #544669

1

CLOSE TO VR
R723
DY 54D9R2F-L1-GP
2

R732
H_CPU_SVIDCLK 1 2 VR_SVID_CLK 46
0R0402-PAD
SVID_543016:
B B

+VCCST_CPU

#544669
1

CLOSE TO CPU
R727
56R2J-4-GP
2

R728
H_CPU_SVIDALRT# 2 1 VR_SVID_ALERT# 46
220R2J-L2-GP

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(VCC_CORE)
Size Document Number Rev
A1
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 7 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

D D

CPU1A 1 OF 20

E55 SKYLAKE_ULT C47

57 HDMI_CRT_N0 DDI1_TXN[0] EDP_TXN[0] eDP_TX_CPU_N0 55
57 HDMI_CRT_P0 F55 DDI1_TXP[0] EDP_TXP[0] C46 eDP_TX_CPU_P0 55
57 HDMI_CRT_N1 E58 DDI1_TXN[1] EDP_TXN[1] D46 eDP_TX_CPU_N1 55
57 HDMI_CRT_P1 F58 C45
HDMI 57 HDMI_DATA0# F53
DDI1_TXP[1]
DDI1_TXN[2]
EDP_TXP[1]
EDP_TXN[2] A45
eDP_TX_CPU_P1 55

57 HDMI_DATA0 G53 DDI1_TXP[2] EDP_TXP[2] B45

57 HDMI_CLK# F56 DDI1_TXN[3] EDP_TXN[3] A47
57 HDMI_CLK G56 DDI1_TXP[3] EDP_TXP[3] B47

56 PCH_DPC_N0 C50 DDI2_TXN[0] DDI EDP_AUXN E45 eDP_AUX_CPU_N 55

D50 EDP F45
56 PCH_DPC_P0 DDI2_TXP[0] EDP_AUXP eDP_AUX_CPU_P 55
C52
CRT 56
56
PCH_DPC_N1
PCH_DPC_P1 D52
DDI2_TXN[1]
DDI2_TXP[1] EDP_DISP_UTIL B52 EDP_DISP_UTIL 1
A50 TP801 TPAD14-OP-GP
DDI2_TXN[2]
B50 DDI2_TXP[2] DDI1_AUXN G50
D51 DDI2_TXN[3] DDI1_AUXP F50
C51 DDI2_TXP[3] DDI2_AUXN E48 PCH_DPC_AUXN 56
3D3V_S0 F48
DDI2_AUXP PCH_DPC_AUXP 56
RSVD#G46 G46
DISPLAY SIDEBANDS
RN801 RSVD#F46 F46
C L13 C
2 3 CPU_DP1_CTRL_CLK HDMI 57 CPU_DP1_CTRL_CLK
57 CPU_DP1_CTRL_DATA L12
GPP_E18/DDPB_CTRLCLK
GPP_E19/DDPB_CTRLDATA
Strap
GPP_E13/DDPB_HPD0 L9 CPU_DP1_HPD 57
1 4 CPU_DP1_CTRL_DATA L7
GPP_E14/DDPC_HPD1 EC_SMI# CRT_HPD_PCH 56
56 DDPC_CLK N7 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 L6 EC_SMI# 24
56 DDPC_DATA N8 Strap N9 EC_SCI# 24
SRN2K2J-1-GP GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD L10 EDP_HPD 55
Check +VCCIO TPAD14-OP-GP N11
RN804 GPP_E22
R801
TP802 1 DDPD_CTRLDATA N12 GPP_E23
Strap EDP_BKLTEN R12 L_BKLT_EN 55
2 3 DDPC_CLK R11 L_BKLT_CTRL 55
DDPC_DATA EDP_COMP EDP_BKLTCTL
1 4 1 2 E52 EDP_RCOMP EDP_VDDEN U13 EDP_VDD_EN 55
24D9R2F-L-GP SKYLAKE-U-GP
SRN2K2J-1-GP
CPU BOM CTRL
CRT 071.SKYLA.000U
(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.

3D3V_S0
(#543016) eDP_RCOMP Guideline
Signal Trace Isolation Resistor Length
Width Spacing Value 3D3V_S5 EC_SMI# 1 R802 2 10KR2J-3-GP

eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1% Max = 100 mils

EC_SMI# 1 R806 2 10KR2J-3-GP EC_SCI# 1 R803 2 10KR2J-3-GP

B DY DY B

(#543016) DDI Disabling and Termination Guidelines R804

1 2 L_BKLT_EN
Port Strap Enable Port Disable Port 100KR2J-4-GP

PU to 3.3 V with 2.2-k

Port 1 DDPB_CTRLDATA ±5% resistor NC
PU to 3.3 V with 2.2-k R805
Port 2 DDPC_CTRLDATA ±5% resistor NC 1 2 CPU_DP1_HPD
100KR2J-4-GP

DY

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Design Guideline:
Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor. Title

CPU_(DISPLAY)
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 8 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)CPU
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 9 of 102
5 4 3 2 1
 D

-1
Wistron Corporation

Rev

102
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

of
CPU_(Power CAP1)

10
LV115 SKL-U
Sheet
1

1
Monday, April 25, 2016
Document Number
<Core Design>

Date:
Size
Title

A2
2

2
(#543016 PDG)
3

3
PC1027

SC1U10V2KX-L1-GP
SC22U6D3V5MX-L3-GP
PC1064

1 2 1 2
SC1U10V2KX-L1-GP
PC1026

PC1063
1 2
1 SC10U6D3V3MX-L-GP 2 SC22U6D3V5MX-L3-GP
PC1060
1 2
SC1U10V2KX-L1-GP
PC1062
1 2
PC1025

1 SC10U6D3V3MX-L-GP 2
PC1059 SC22U6D3V5MX-L3-GP
SC1U10V2KX-L1-GP 1 2
PC1053

PC1061
1 2
1 SC10U6D3V3MX-L-GP 2 SC22U6D3V5MX-L3-GP
PC1058
1 2
PC1052

1 2
SC22U6D3V5MX-L3-GP
PC1057 SC10U6D3V3MX-L-GP
1 2

1 2
PC1051

SC22U6D3V5MX-L3-GP
PC1056 SC10U6D3V3MX-L-GP
1D2V_S3

1 2
1 2
PC1050

PC1055 SC10U6D3V3MX-L-GP
SC22U6D3V5MX-L3-GP
1 2
4

4
PC1049

SC22U6D3V5MX-L3-GP
PC1081

1 2
SC22U6D3V5MX-L3-GP
1 2
PC1048

PC1080

SC22U6D3V5MX-L3-GP
1 2 SC22U6D3V5MX-L3-GP
1 2
PC1047

PC1078 PC1079

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP
1 2 1 2
PC1019 PC1020

SC22U6D3V5MX-L3-GP
1 2 SC22U6D3V5MX-L3-GP
PC1046

1 2
SC22U6D3V5MX-L3-GP
VCCSA

PC1076 PC1077

SC22U6D3V5MX-L3-GP 1 2
1 2 SC22U6D3V5MX-L3-GP
1 2
PC1009

PC1018

PC1045

PC1090

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP

+VCCSA

1 2 1 2 1 2 SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP
1 2 1 2
PC1007 PC1008

PC1016 PC1017

PC1075

PC1089

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP
SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP
1 2 1 2
SC1U10V2KX-L1-GP

1 2 1 2
PC1042 PC1043

PC1073 PC1074

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP
1 2 1 2 SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP
1 2 1 2
PC1005 PC1006

PC1014 PC1015

PC1028

PC1039

PC1087

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP
DY

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP

IccMax current-10ms max = 34 A

1 2 1 2
IccMax current-10ms max[A] = 67 A

1 2 1 2 1 2 1 2
PC1034 PC1041

PC1071 PC1072

PC1085 PC1086

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP 1 2
PC1038

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP

1D0V_S5

1 2 1 2
SC22U6D3V5MX-L3-GP
SLICED GT

1 2 1 2 1 2
PC1004

PC1013

PC1024

1 2
SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC18P50V2JN-1-GP
SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP
DY

1 2 1 2 1 2
Main Func = CPU

1 2 1 2 1 2
PC1002 PC1003

PC1011 PC1012

PC1022 PC1023
5

5
PC1033

PC1070

PC1084
U-line 23e 28W

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC18P50V2JN-1-GP

DY
+VCCIO(ICCMAX.=2.73A)

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP

DY

1 2 1 2 1 2
CORE

1 2 1 2 1 2
U-line 23e 28W

PC1031 PC1032

PC1044 PC1069

PC1082 PC1083

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP

1 2 1 2 1 2 SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP
1 2 1 2 1 2
PC1001

PC1010

PC1021

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP

PC1035 PC1036

1 2 1 2 1 2 SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP 1 2 1 2 1 2
1 2
VCC_CORE

SC22U6D3V5MX-L3-GP
+VCCIO

+VCCGT

1 2
DY
D

A
 5 4 3 2 1

Main Func = CPU

UNSLICED GT
+VCCGT
VCCIO
+VCCIO

+VCCIO(ICCMAX.=2.73A)
1

1
C1136 C1138 C1147 C1148 C1149 C1150 1U 0402 x 6
SC18P50V2JN-1-GP

DY
2

1
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC18P50V2JN-1-GP

SC1U10V2KX-1GP

SC18P50V2JN-1-GP
C1151 C1152 C1153 C1154

2
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
D D
DY DY

GTUS 20141114 Alden

PCH DERIVED RAILS +VCCGT

+V_VCCGTUS_VR can merge to +VCCGT

+VCCPGPPA(ICCMAX.=0.05A)

+V1.8A +VCCPGPPA
R1111
1 DY 2

1
PC1104 PC1105 PC1106 PC1107
3D3V_S5 0R3J-0-U-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP
23e 23e 23e 23e

2
1 R1109 2

0R0603-PAD

C C
3D3V_S5 +VCCPAZIO
L1101
1 2
BLM15EG221SN1D-GP
68.00084.C21

1D0V_S5 +VCCAPLL_1P0
L1102
1 2
BLM15EG221SN1D-GP
68.00084.C21

1D0V_S5

1D0V_S5 +VCCAMPHYPLL_1P0
1

1
C1174 C1182 C1104 C1105 1 R1102 2
B B
0R0603-PAD
2

1
SC1U10V2KX-1GP

SC18P50V2JN-1-GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
C1181
SC22U6D3V5MX-L3-GP C1172
SC1U10V2KX-1GP

2
DY DY DY

VCC_CORE

3D3V_S5 +VCCPGPPD_TCH

1 R1108 2
1

C1101 C1102 C1103 C1116 C1117

1U 0402 x 5 0R0603-PAD
2

2
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

+V1.8A
A R1129 A

1 DY 2

0R3J-0-U-GP

+VCCPGPPD_TCH
<Core Design>
U-line 23e 28W
IccMax current-10ms max = 34 A C1183
Wistron Corporation
1

SC10U6D3V3MX-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
2

Title

CPU_(Power CAP2)
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 11 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = DDR4 On Board with Single Rank

1D2V_S3 ODIMM1 1D2V_S3 ODIMM2

B3 A3 M_A_DQ7 M_A_DQ7 5 B3 A3 M_A_DQ24 M_A_DQ24 5

VDD DQU0 M_A_DQ0 VDD DQU0 M_A_DQ25
B9 B8 B9 B8
D1
G7
VDD
VDD
DQU1
DQU2
C3
C7
M_A_DQ3
M_A_DQ4
M_A_DQ0
M_A_DQ3
5
5 D1
G7
VDD
VDD
DQU1
DQU2
C3
C7
M_A_DQ26
M_A_DQ27
M_A_DQ25
M_A_DQ26
5
5 Ref. 549360_SKL_U_6L WP P47
VDD DQU3 M_A_DQ4 5 VDD DQU3 M_A_DQ27 5
J1 C2 M_A_DQ6 M_A_DQ6 5 J1 C2 M_A_DQ28 M_A_DQ28 5
J9 VDD DQU4 C8 M_A_DQ5 J9 VDD DQU4 C8 M_A_DQ29 1D2V_S3 M_VREF_DQ_DIMMB R1208 2 1 243R2F-L1-GP DDR4_ZQ_RAM1
VDD DQU5 M_A_DQ5 5 VDD DQU5 M_A_DQ29 5
L1 D3 M_A_DQ2 L1 D3 M_A_DQ30 R1212 ODIMM
VDD DQU6 M_A_DQ2 5 VDD DQU6 M_A_DQ30 5
L9 D7 M_A_DQ1 M_A_DQ1 5 L9 D7 M_A_DQ31 M_A_DQ31 5 1K8R2F-GP ODIMM
VDD DQU7 VDD DQU7
R1 R1 R1214
T9 VDD G2 M_A_DQ11 T9 VDD G2 M_A_DQ16 1 2 ODIMM
VDD DQL0 M_A_DQ11 5 VDD DQL0 M_A_DQ16 5
F7 M_A_DQ8 M_A_DQ8 5 F7 M_A_DQ23 M_A_DQ23 5 1 2 1 2 R1209 2 1 243R2F-L1-GP DDR4_ZQ_RAM2
DQL1 DQL1 V_SM_VREF_CA 5
A1 H3 M_A_DQ14 A1 H3 M_A_DQ18 ODIMM
VDDQ DQL2 M_A_DQ14 5 VDDQ DQL2 M_A_DQ18 5
A9 H7 M_A_DQ12 M_A_DQ12 5 A9 H7 M_A_DQ19 M_A_DQ19 5 R1213 ODIMM
2D7R2F-1-GP

1
VDDQ DQL3 M_A_DQ15 VDDQ DQL3 M_A_DQ20 1K8R2F-GP
C1 H2 M_A_DQ15 5 C1 H2 M_A_DQ20 5
D9 VDDQ DQL4 H8 M_A_DQ9 D9 VDDQ DQL4 H8 M_A_DQ21 C1221
VDDQ DQL5 M_A_DQ9 5 VDDQ DQL5 M_A_DQ21 5
F2 J3 M_A_DQ10 F2 J3 M_A_DQ22 SCD022U16V2KX-3GP R1210 2 1 243R2F-L1-GP DDR4_ZQ_RAM3
C1201 close to ODIMM1.M1 M_A_DQ10 5 M_A_DQ22 5

2
VDDQ DQL6 M_A_DQ13 VDDQ DQL6 M_A_DQ17 ODIMM ODIMM
F8 J7 F8 J7
G1 VDDQ DQL7 M_A_DQ13 5
C1202 close to ODIMM2.M1 G1 VDDQ DQL7 M_A_DQ17 5
+V_VREF_PATH3

1
VDDQ M_A_DQS_DN0 VDDQ M_A_DQS_DN3
G9 A7 M_A_DQS_DN0 5 G9 A7 M_A_DQS_DN3 5 R1215
J2 VDDQ DQSU_C B7 M_A_DQS_DP0 J2 VDDQ DQSU_C B7 M_A_DQS_DP3
VDDQ DQSU_T M_A_DQS_DP0 5 VDDQ DQSU_T M_A_DQS_DP3 5
2D5V_S3 J8 2D5V_S3 J8 24D9R2F-L-GP R1211 2 1 243R2F-L1-GP DDR4_ZQ_RAM4
D VDDQ M_A_DQS_DN1 VDDQ M_A_DQS_DN2 ODIMM ODIMM D
F3 M_A_DQS_DN1 5 F3 M_A_DQS_DN2 5
M_VREF_DQ_DIMMB B1 DQSL_C G3 M_A_DQS_DP1 1D2V_S3 M_VREF_DQ_DIMMB B1 DQSL_C G3 M_A_DQS_DP2 1D2V_S3
M_A_DQS_DP1 5 M_A_DQS_DP2 5

2
VPP DQSL_T VPP DQSL_T
R9 R9
VPP E2 VPP E2
M1 DMU#/DBIU# E7 M1 DMU#/DBIU# E7
DDR4_ZQ_RAM1 VREFCA DML#/DBIL# DDR4_ZQ_RAM2 VREFCA DML#/DBIL#
F9 F9
ZQ P9 ZQ P9
M_A_ALERT_N 5 M_A_ALERT_N 5
1

1
ALERT# ALERT#
C1201 5 M_A_A0 M_A_A0 P3 C1202 5 M_A_A0 M_A_A0 P3
SCD047U25V2KX-GP M_A_A1 P7 A0 M2 SCD047U25V2KX-GP M_A_A1 P7 A0 M2
5 M_A_A1 M_A_BG0 5 5 M_A_A1 M_A_BG0 5
2

2
ODIMM M_A_A2 A1 BG0 ODIMM M_A_A2 A1 BG0
5 M_A_A2 R3 5 M_A_A2 R3
M_A_A3 N7 A2 N2 M_A_A3 N7 A2 N2
5 M_A_A3 A3 BA0 M_A_BA0 5 5 M_A_A3 A3 BA0 M_A_BA0 5
5 M_A_A4 M_A_A4 N3 N8 5 M_A_A4 M_A_A4 N3 N8
A4 BA1 M_A_BA1 5 A4 BA1 M_A_BA1 5
5 M_A_A5 M_A_A5 P8 5 M_A_A5 M_A_A5 P8
M_A_A6 P2 A5 T7 M_A_A6 P2 A5 T7
5 M_A_A6 A6 NC#T7 5 M_A_A6 A6 NC#T7
5 M_A_A7 M_A_A7 R8 5 M_A_A7 M_A_A7 R8
M_A_A8 R2 A7 M_A_A8 R2 A7
5 M_A_A8 A8 5 M_A_A8 A8
5 M_A_A9 M_A_A9 R7 B2 5 M_A_A9 M_A_A9 R7 B2
M_A_A10_AP M3 A9 VSS E1 M_A_A10_AP M3 A9 VSS E1
5 M_A_A10_AP A10/AP VSS 5 M_A_A10_AP A10/AP VSS
5 M_A_A11 M_A_A11 T2 E9 5 M_A_A11 M_A_A11 T2 E9
M_A_A12 A11 VSS M_A_A12 A11 VSS
5 M_A_A12 M7 G8 5 M_A_A12 M7 G8
M_A_A13 T8 A12/BC# VSS K1 M_A_A13 T8 A12/BC# VSS K1
5 M_A_A13 A13 VSS 5 M_A_A13 A13 VSS
5 M_A_A14_WE# M_A_A14_WE# L2 K9 5 M_A_A14_WE# M_A_A14_WE# L2 K9
WE#/A14 VSS M9 WE#/A14 VSS M9
K2 VSS N1 K2 VSS N1
5 M_A_CKE0 CKE VSS 5 M_A_CKE0 CKE VSS
5 M_A_CLK#0 K8 T1 5 M_A_CLK#0 K8 T1
K7 CK_C VSS K7 CK_C VSS
5 M_A_CLK0 CK_T 5 M_A_CLK0 CK_T
A2 A2
M_A_A16_RAS# L8 VSSQ A8 M_A_A16_RAS# L8 VSSQ A8
5 M_A_A16_RAS# RAS# VSSQ 5 M_A_A16_RAS# RAS# VSSQ
5 M_A_A15_CAS# M_A_A15_CAS# M8 C9 5 M_A_A15_CAS# M_A_A15_CAS# M8 C9
CAS# VSSQ CAS# VSSQ
D2 D2
K3 VSSQ D8 K3 VSSQ D8
5 M_A_ODT0 ODT VSSQ 5 M_A_ODT0 ODT VSSQ
5 M_A_ACT_N L3 E3 5 M_A_ACT_N L3 E3
L7 ACT# VSSQ E8 L7 ACT# VSSQ E8
5 M_A_CS#0 CS# VSSQ 5 M_A_CS#0 CS# VSSQ
TPAD14-OP-GP TP1204 1DDR4_TEST_MODE_1 N9 F1 TPAD14-OP-GP TP1205 1DDR4_TEST_MODE_2 N9 F1
TEN VSSQ TEN VSSQ
5,13 DDR4_DRAMRST#
P1 H1 5,13 DDR4_DRAMRST#
P1 H1
T3 RESET# VSSQ H9 T3 RESET# VSSQ H9
5 M_A_PARITY PAR VSSQ 5 M_A_PARITY PAR VSSQ

K4A4G165WD-BCPB-GP K4A4G165WD-BCPB-GP

072.44165.000U 072.44165.000U

ODIMM BOM CTRL ODIMM BOM CTRL

1D2V_S3 ODIMM4
1D2V_S3 ODIMM3
B3 A3 M_A_DQ62 M_A_DQ62 5
B3 A3 M_A_DQ46 B9 VDD DQU0 B8 M_A_DQ56
VDD DQU0 M_A_DQ46 5 VDD DQU1 M_A_DQ56 5
B9 B8 M_A_DQ47 M_A_DQ47 5 D1 C3 M_A_DQ63 M_A_DQ63 5
VDD DQU1 M_A_DQ45 VDD DQU2 M_A_DQ60
D1 C3 G7 C7
G7
J1
VDD
VDD
DQU2
DQU3
C7
C2
M_A_DQ40
M_A_DQ42
M_A_DQ45
M_A_DQ40
5
5 J1
J9
VDD
VDD
DQU3
DQU4
C2
C8
M_A_DQ59
M_A_DQ61
M_A_DQ60
M_A_DQ59
5
5 DDR4 On Board RAM Power Decouple Cap
VDD DQU4 M_A_DQ42 5 VDD DQU5 M_A_DQ61 5
J9 C8 M_A_DQ44 M_A_DQ44 5 L1 D3 M_A_DQ58 M_A_DQ58 5
L1 VDD DQU5 D3 M_A_DQ43 L9 VDD DQU6 D7 M_A_DQ57
VDD DQU6 M_A_DQ43 5 VDD DQU7 M_A_DQ57 5
L9 D7 M_A_DQ41 M_A_DQ41 5 R1
R1 VDD DQU7 T9 VDD G2 M_A_DQ51
VDD VDD DQL0 M_A_DQ51 5
T9 G2 M_A_DQ32 F7 M_A_DQ53 1D2V_S3
VDD DQL0 M_A_DQ32 5 DQL1 M_A_DQ53 5
F7 M_A_DQ33 A1 H3 M_A_DQ54
A1
A9
VDDQ
DQL1
DQL2
H3
H7
M_A_DQ34
M_A_DQ35
M_A_DQ33
M_A_DQ34
5
5 A9
C1
VDDQ
VDDQ
DQL2
DQL3
H7
H2
M_A_DQ52
M_A_DQ50
M_A_DQ54
M_A_DQ52
5
5 VDDQ/VDD 10uF x10
C1 VDDQ
VDDQ
DQL3
DQL4
H2 M_A_DQ36
M_A_DQ35
M_A_DQ36
5
5 D9 VDDQ
VDDQ
DQL4
DQL5
H8 M_A_DQ49
M_A_DQ50
M_A_DQ49
5
5
LV115 use 1ch memory down , only need half of Caps
D9 H8 M_A_DQ37 M_A_DQ37 5 F2 J3 M_A_DQ55 M_A_DQ55 5
F2 VDDQ DQL5 J3 M_A_DQ38 F8 VDDQ DQL6 J7 M_A_DQ48
M_A_DQ38 5
C1204 close to ODIMM4.M1 M_A_DQ48 5

1
F8 VDDQ DQL6 J7 M_A_DQ39 G1 VDDQ DQL7 C1205 C1206 C1207 C1208 C1209 C1210 C1265 C1266 C1267 C1268
VDDQ DQL7 M_A_DQ39 5 VDDQ
G1 G9 A7 M_A_DQS_DN7 SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP
C1203 close to ODIMM3.M1 G9 VDDQ A7 M_A_DQS_DN5 M_A_DQS_DN5 5 J2 VDDQ DQSU_C B7 M_A_DQS_DP7
M_A_DQS_DN7
M_A_DQS_DP7
5
5 ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM

2
VDDQ DQSU_C M_A_DQS_DP5 2D5V_S3 VDDQ DQSU_T
J2 B7 M_A_DQS_DP5 5 J8
2D5V_S3 J8 VDDQ DQSU_T VDDQ F3 M_A_DQS_DN6
VDDQ DQSL_C M_A_DQS_DN6 5
F3 M_A_DQS_DN4 M_VREF_DQ_DIMMB B1 G3 M_A_DQS_DP6 1D2V_S3
DQSL_C M_A_DQS_DN4 5 VPP DQSL_T M_A_DQS_DP6 5
M_VREF_DQ_DIMMB B1 G3 M_A_DQS_DP4 1D2V_S3 R9
VPP DQSL_T M_A_DQS_DP4 5 VPP
R9 E2
VPP DMU#/DBIU#
E2 M1 E7
M1 DMU#/DBIU# E7 DDR4_ZQ_RAM4 F9 VREFCA DML#/DBIL#
DDR4_ZQ_RAM3 F9 VREFCA DML#/DBIL# ZQ P9 1D2V_S3
M_A_ALERT_N 5
VDDQ/VDD 1uF x32
1

ZQ ALERT#
P9
1

ALERT# M_A_ALERT_N 5
C1204 5 M_A_A0 M_A_A0 P3
C1203 M_A_A0 SCD047U25V2KX-GP M_A_A1 A0
C 5 M_A_A0 P3 5 M_A_A1 P7 M2 M_A_BG0 5 C
2

SCD047U25V2KX-GP M_A_A1 P7 A0 M2 ODIMM M_A_A2 R3 A1 BG0

5 M_A_A1 M_A_BG0 5 5 M_A_A2
2

ODIMM M_A_A2 R3 A1 BG0 M_A_A3 N7 A2 N2

5 M_A_A2 5 M_A_A3 M_A_BA0 5

1
M_A_A3 A2 M_A_A4 A3 BA0 C1213 C1214 C1215 C1216 C1217 C1218 C1219 C1220 C1222 C1223
5 M_A_A3 N7 N2 M_A_BA0 5 5 M_A_A4 N3 N8 M_A_BA1 5
M_A_A4 N3 A3 BA0 N8 M_A_A5 P8 A4 BA1 SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP
5 M_A_A4 A4 BA1 M_A_BA1 5 5 M_A_A5 A5
M_A_A5 P8 M_A_A6 P2 T7 ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM
5 M_A_A5 5 M_A_A6

2
M_A_A6 P2 A5 T7 M_A_A7 R8 A6 NC#T7
5 M_A_A6 A6 NC#T7 5 M_A_A7 A7
5 M_A_A7 M_A_A7 R8 5 M_A_A8 M_A_A8 R2
M_A_A8 A7 M_A_A9 A8
5 M_A_A8 R2 5 M_A_A9 R7 B2
M_A_A9 R7 A8 B2 M_A_A10_AP M3 A9 VSS E1
5 M_A_A9 A9 VSS 5 M_A_A10_AP A10/AP VSS
5 M_A_A10_AP M_A_A10_AP M3 E1 5 M_A_A11 M_A_A11 T2 E9
M_A_A11 T2 A10/AP VSS E9 M_A_A12 M7 A11 VSS G8
5 M_A_A11 A11 VSS 5 M_A_A12 A12/BC# VSS
5 M_A_A12 M_A_A12 M7 G8 5 M_A_A13 M_A_A13 T8 K1
M_A_A13 A12/BC# VSS M_A_A14_WE# A13 VSS 1D2V_S3
5 M_A_A13 T8 K1 5 M_A_A14_WE# L2 K9
M_A_A14_WE# L2 A13 VSS K9 WE#/A14 VSS M9
5 M_A_A14_WE# WE#/A14 VSS VSS
M9 5 M_A_CKE0 K2 N1
K2 VSS N1 K8 CKE VSS T1
5 M_A_CKE0 CKE VSS 5 M_A_CLK#0 CK_C VSS
5 M_A_CLK#0 K8 T1 5 M_A_CLK0 K7
CK_C VSS CK_T
5 M_A_CLK0 K7 A2

1
CK_T A2 M_A_A16_RAS# L8 VSSQ A8 C1237 C1232 C1238 C1235 C1236 C1234 C1249 C1250 C1251 C1252
VSSQ 5 M_A_A16_RAS# RAS# VSSQ
5 M_A_A16_RAS# M_A_A16_RAS# L8 A8 5 M_A_A15_CAS# M_A_A15_CAS# M8 C9 SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP
M_A_A15_CAS# M8 RAS# VSSQ C9 CAS# VSSQ D2 ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM
5 M_A_A15_CAS#

2
CAS# VSSQ D2 K3 VSSQ D8
VSSQ 5 M_A_ODT0 ODT VSSQ
5 M_A_ODT0 K3 D8 5 M_A_ACT_N
L3 E3
L3 ODT VSSQ E3 L7 ACT# VSSQ E8
5 M_A_ACT_N ACT# VSSQ 5 M_A_CS#0 CS# VSSQ
L7 E8 TPAD14-OP-GP TP1207 1DDR4_TEST_MODE_4 N9 F1
5 M_A_CS#0 CS# VSSQ TEN VSSQ
TPAD14-OP-GP TP1206 1DDR4_TEST_MODE_3 N9 F1 5,13 DDR4_DRAMRST#
P1 H1
P1 TEN VSSQ H1 T3 RESET# VSSQ H9
5,13 DDR4_DRAMRST# RESET# VSSQ 5 M_A_PARITY PAR VSSQ
5 M_A_PARITY
T3 H9
PAR VSSQ
K4A4G165WD-BCPB-GP 1D2V_S3
K4A4G165WD-BCPB-GP

072.44165.000U
072.44165.000U
ODIMM BOM CTRL

1
C1253 C1254 C1255 C1256 C1257 C1258 C1259 C1260 C1261 C1262
ODIMM BOM CTRL SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP
ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM

2
1D2V_S3

ALERT
R1220 1 2 49D9R2F-GP ODIMM M_A_ALERT_N

1D2V_S3

0D6V_S0

1
R1221 1 2 36R2F-1-GP ODIMM M_A_CLK0 C1263 C1264
CLK SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP
ODIMM ODIMM

2
R1222 1 2 36R2F-1-GP ODIMM M_A_CLK#0

R1223 1 2 34D8R2F-GP ODIMM M_A_CKE0 2D5V_S3

R1224
R1225
1
1
2
2
34D8R2F-GP
34D8R2F-GP
ODIMM
ODIMM
M_A_A0
M_A_A1
VPP 1uF x16
R1226 1 2 34D8R2F-GP ODIMM M_A_A2
R1227 1 2 34D8R2F-GP ODIMM M_A_A3
R1228 1 2 34D8R2F-GP ODIMM M_A_A4

1
R1229 1 2 34D8R2F-GP ODIMM M_A_A5 C1224 C1225 C1226 C1227 C1228 C1229 C1230 C1231 C1269 C1270
R1230 1 2 34D8R2F-GP ODIMM M_A_A6 SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP
R1231 1 2 34D8R2F-GP ODIMM M_A_A7 CTRL/CKE/CMD ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM

2
R1232 1 2 34D8R2F-GP ODIMM M_A_A8
R1233 1 2 34D8R2F-GP ODIMM M_A_A9
R1234 1 2 34D8R2F-GP ODIMM M_A_A10_AP
R1235 1 2 34D8R2F-GP ODIMM M_A_A11
R1236 1 2 34D8R2F-GP ODIMM M_A_A12
R1237 1 2 34D8R2F-GP ODIMM M_A_A13
R1238 1 2 34D8R2F-GP ODIMM M_A_A14_WE# 2D5V_S3
R1239 1 2 34D8R2F-GP ODIMM M_A_A15_CAS#
R1240 1 2 34D8R2F-GP ODIMM M_A_A16_RAS#
R1241 1 2 34D8R2F-GP ODIMM M_A_BA0
R1242 1 2 34D8R2F-GP ODIMM M_A_BA1
R1243 1 2 34D8R2F-GP ODIMM M_A_BG0

1
R1244 1 2 34D8R2F-GP ODIMM M_A_PARITY C1271 C1272 C1273 C1274 C1275 C1276
B B
R1245 1 2 34D8R2F-GP ODIMM M_A_ACT_N SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP
R1246 1 2 34D8R2F-GP ODIMM M_A_CS#0 ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM
2

2
R1247 1 2 34D8R2F-GP ODIMM M_A_ODT0

2D5V_S3

VPP 10uF x5

1
C1233 C1211 C1212 C1277 C1278
SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP
0D6V_S0 ODIMM ODIMM ODIMM ODIMM ODIMM
VTT 1uF x16

2
1

1
C1239 C1240 C1241 C1242 C1243 C1244 C1245 C1246 C1279 C1280
SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP
ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM 0D6V_S0
2

2
VTT 10uF x4

1
C1247 C1248 C1287 C1288
SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP
0D6V_S0 ODIMM ODIMM ODIMM ODIMM

2
1

1
C1281 C1282 C1283 C1284 C1285 C1286
SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP
ODIMM ODIMM ODIMM ODIMM ODIMM ODIMM
2

DDR4_DRAMRST#

For ODIMM1,ODIMM2,ODIMM3,ODIMM4
1

A A
ED1201 ED1202 ED1203 ED1204
PESD5V0U1BL-GP-U1

PESD5V0U1BL-GP-U1

PESD5V0U1BL-GP-U1

PESD5V0U1BL-GP-U1

ODIMM ODIMM ODIMM ODIMM

2

<Core Des ign>

Wistron Corporation
21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.

Title

DDR4-SODIMM1
Size Docum ent Num ber Rev
A0
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 12 of 102
5 4 3 2 1
 5 4 3 2 1

DIMM1A 1 OF 4 DIMM1B 2 OF 4 DIMM1D 4 OF 4

5 M_B_A0 144 8 M_B_DQ10 5 11 M_B_DQS_DN1 5 1 99

A0 DQ0 DQS0_C VSS VSS
5 M_B_A1 133 7 M_B_DQ14 5 13 M_B_DQS_DP1 5 2 102
A1 DQ1 DQS0_T VSS VSS
5 M_B_A2 132 20 M_B_DQ15 5 32 M_B_DQS_DN0 5 5 103
A2 DQ2 DQS1_C VSS VSS
5 M_B_A3 131 21 M_B_DQ12 5 34 M_B_DQS_DP0 5 6 106
A3 DQ3 DQS1_T VSS VSS
5 M_B_A4 128 4 M_B_DQ11 5 53 M_B_DQS_DN2 5 9 107
A4 DQ4 DQS2_C VSS VSS
5 M_B_A5 126 3 M_B_DQ9 5 55 M_B_DQS_DP2 5 10 167
A5 DQ5 DQS2_T VSS VSS
5 M_B_A6 127 16 M_B_DQ13 5 74 M_B_DQS_DN3 5 14 168
A6 DQ6 DQS3_C VSS VSS
5 M_B_A7 122 17 M_B_DQ8 5 76 M_B_DQS_DP3 5 15 171
A7 DQ7 DQS3_T VSS VSS
5 M_B_A8 125 28 M_B_DQ0 5 177 M_B_DQS_DN4 5 18 172
A8 DQ8 DQS4_C VSS VSS
5 M_B_A9 121 29 M_B_DQ1 5 179 M_B_DQS_DP4 5 19 175
A9 DQ9 DQS4_T VSS VSS
5 M_B_A10_AP 146 41 M_B_DQ7 5 198 M_B_DQS_DN5 5 22 176
A10/AP DQ10 DQS5_C VSS VSS
5 M_B_A11 120 42 M_B_DQ3 5 200 M_B_DQS_DP5 5 23 180
A11 DQ11 DQS5_T VSS VSS
5 M_B_A12 119 24 M_B_DQ4 5 219 M_B_DQS_DN6 5 26 181
A12 DQ12 DQS6_C VSS VSS
5 M_B_A13 158 25 M_B_DQ5 5 221 M_B_DQS_DP6 5 27 184
A13 DQ13 DQS6_T VSS VSS
5 M_B_A14_WE# 151 38 M_B_DQ6 5 240 M_B_DQS_DN7 5 30 185
WE#/A14 DQ14 DQS7_C VSS VSS
5 M_B_A15_CAS# 156 37 M_B_DQ2 5 242 M_B_DQS_DP7 5 31 188
CAS#/A15 DQ15 DQS7_T VSS VSS
5 M_B_A16_RAS# 152 50 M_B_DQ17 5 95 35 189
RAS#/A16 DQ16 DQS8_C 1D2V_S3 VSS VSS
49 M_B_DQ20 5 97 36 192
DQ17 DQS8_T VSS VSS
5 M_B_BA0 150 62 M_B_DQ22 5 39 193
BA0 DQ18 VSS VSS
5 M_B_BA1 145 63 M_B_DQ18 5 12 40 196
BA1 DQ19 DM0#/DBI0# VSS VSS
5 M_B_BG0 115 46 M_B_DQ16 5 33 43 197
BG0 DQ20 DM1#/DBI# VSS VSS
5 M_B_BG1 113 45 M_B_DQ21 5 54 44 201
BG1 DQ21 DM2#/DBI2# VSS VSS
58 M_B_DQ23 5 75 47 202
DQ22 DM3#/DBI3# VSS VSS
92 59 M_B_DQ19 5 178 48 205
D CB0/NC DQ23 DM4#/DBI4# VSS VSS D
91 70 M_B_DQ24 5 199 51 206
CB1/NC DQ24 DM5#/DBI5# VSS VSS
101 71 M_B_DQ31 5 220 52 209
CB2/NC DQ25 DM6#/DBI6# VSS VSS
105 83 M_B_DQ26 5 241 56 210
CB3/NC DQ26 DM7#/DBI7# VSS VSS
88 84 M_B_DQ29 5 96 57 213
CB4/NC DQ27 DM8#/DBI#/NC VSS VSS
87 66 M_B_DQ28 5 60 214
CB5/NC DQ28 VSS VSS
100
CB6/NC DQ29
67 M_B_DQ25 5 DDR4-260P-40-GP-U
062.10011.00W1 61
VSS VSS
217
104 79 M_B_DQ30 5 64 218
CB7/NC DQ30 VSS VSS
DQ31
80 M_B_DQ27 5 1ST = 062.10011.00W1 65
VSS VSS
222
5 M_B_CLK0 137 174 M_B_DQ33 5 68 223
CK0_T DQ32 VSS VSS
5 M_B_CLK#0 139
CK0_C DQ33
173 M_B_DQ34 5 2ND = 062.10011.00V1 69
VSS VSS
226
5 M_B_CLK1 138 187 M_B_DQ35 5 72 227
CK1_T/NF DQ34 VSS VSS
5 M_B_CLK#1 140
CK1_C/NF DQ35
186 M_B_DQ39 5 3RD = 062.10011.0F71 73
VSS VSS
230
170 M_B_DQ36 5 77 231
DQ36 VSS VSS
5 M_B_CKE0 109 169 M_B_DQ37 5 78 234
CKE0 DQ37 1D2V_S3 VSS VSS
5 M_B_CKE1 110 183 M_B_DQ38 5 81 235
CKE1 DQ38 DIMM1C 3 OF 4 3D3V_S0 VSS VSS
182 M_B_DQ32 5 82 238
DQ39 VSS VSS
5 M_B_CS#0 149 195 M_B_DQ41 5 85 239
CS0# DQ40 VSS VSS
5 M_B_CS#1 157 194 M_B_DQ44 5 111 255 86 243
CS1# DQ41 VDD VDDSPD VSS VSS
162 207 M_B_DQ42 5 112 89 244
C0/CS2#/NC DQ42 VDD 2D5V_S3 VSS VSS
165 208 M_B_DQ47 5 117 90 247
C1/CS3#/NC DQ43 VDD VSS VSS
191 M_B_DQ45 5 118 257 93 248
DQ44 VDD VPP VSS VSS

1
5 M_B_ODT0 155 190 123 259 C1328 C1329 94 251
ODT0 DQ45 M_B_DQ40 5 VDD VPP 0D6V_S0 DY VSS VSS

SCD1U16V2KX-L-GP

SC2D2U10V3KX-L-GP
5 M_B_ODT1 161 203 M_B_DQ46 5 124 98 252
ODT1 DQ46 VDD VSS VSS
204 129 258

2
DQ47 M_B_DQ43 5 VDD VTT
SA0_CHB_DIM0 256 216 130
SA0 DQ48 M_B_DQ53 5 VDD DDR4-260P-40-GP-U
SA1_CHB_DIM0 260 215 135
SA1 DQ49 M_B_DQ49 5 VDD
SA2_CHB_DIM0 166 228 136
SA2 DQ50 M_B_DQ55 5 VDD
DQ51
229 M_B_DQ54 5 141
VDD 062.10011.00W1
18,65 PCH_SMBDATA 254 211 M_B_DQ51 5 142
SDA DQ52 VDD
1D2V_S3 18,65 PCH_SMBCLK 253
SCL DQ53
212 M_B_DQ52 5 147
VDD 261
261 1ST = 062.10011.00W1
224 M_B_DQ48 5 148 262
DQ54 VDD 262
DQ55
225 M_B_DQ50 5 153
VDD 2ND = 062.10011.00V1
5,12 DDR4_DRAMRST# 108 237 M_B_DQ56 5 154
RESET# DQ56 VDD
5 M_B_ACT_N 114
ACT# DQ57
236 M_B_DQ57 5 159
VDD NP1
NP1 3RD = 062.10011.0F71
5 M_B_ALERT_N 116 249 M_B_DQ62 5 160 NP2
ALERT# DQ58 VDD NP2
1 R1313 2 240R2F-1-GP TS#_DIMM1_1 134 250 M_B_DQ63 5 163
EVENT#/NF DQ59 VDD
232 M_B_DQ61 5
DQ60
DY 5 M_B_PARITY 143
PARITY DQ61
233 M_B_DQ58 5 DDR4-260P-40-GP-U
245 M_B_DQ59 5
M_VREF_CA_DIMMB DQ62
164 246 M_B_DQ60 5
VREFCA DQ63
062.10011.00W1
DDR4-260P-40-GP-U
1ST = 062.10011.00W1
1

C1302 062.10011.00W1 2ND = 062.10011.00V1

SCD1U16V2KX-L-GP
2

1ST = 062.10011.00W1 3RD = 062.10011.0F71

2ND = 062.10011.00V1
1D2V_S3
3RD = 062.10011.0F71 3D3V_S0 0D6V_S0 0D6V_S0 0D6V_S0 2D5V_S3

DY
DDR4_DRAMRST# R1302 2 1 10KR2F-L1-GP SA0_CHB_DIM0
20151007 Change DIMM1 SKT PN

1
2 R1303 1 0R0402-PAD C1326 C1327 C1311 C1312 C1313 C1314

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP
EC1301 C1303 C1304 C1305 C1306 C1307 C1308 C1309 C1310 C1324 C1325 DY DY

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP
C SC33P50V2JN-3GP C
DY

2
2

2
DY 3D3V_S0

Ref. 549360_SKL_U_6L WP P47 R1306 2 1 10KR2F-L1-GP SA1_CHB_DIM0

DY DY
1D2V_S3 2 R1307DY
1 0R2J-L-GP
R1301

1
1KR2F-3-GP C1315 C1316 C1317 C1318 C1319 C1320 C1321 C1322
R1305

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP
1 2

2
1 2 M_VREF_CA_DIMMB 1 2 3D3V_S0
V_SM_VREF_CNTB 5
R1304 2R2F-GP DY
1

1KR2F-3-GP R1308 2 1 10KR2F-L1-GP SA2_CHB_DIM0

C1323 DY DY
SCD022U16V2KX-3GP 2 R1311 1 0R0402-PAD
2

+V_VREF_PATH2
1

R1309
24D9R2F-L-GP
2

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR4-SODIMM2
Size Document Number Rev
A1
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 13 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C
(Blanking) C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)SODIMM3_SODIMM4
Size Document Number Rev
A4
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 14 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

CPU1I 9 OF 20

CSI-2 SKYLAKE_ULT

A36 CSI2_DN0 CSI2_CLKN0 C37

B36 CSI2_DP0 CSI2_CLKP0 D37
D C38 CSI2_DN1 CSI2_CLKN1 C32 D
D38 CSI2_DP1 CSI2_CLKP1 D32
C36 CSI2_DN2 CSI2_CLKN2 C29
D36 CSI2_DP2 CSI2_CLKP2 D29 DC resistance < 0.5ohm.
A38 CSI2_DN3 CSI2_CLKN3 B26
B38 CSI2_DP3 CSI2_CLKP3 A26 R1501
C31 E13 CSI2_COMP 1 2
CSI2_DN4 CSI2_COMP
D31 CSI2_DP4 GPP_D4/FLASHTRIG B7
C33 CSI2_DN5 100R2F-L1-GP-U
D33 CSI2_DP5 EMMC
A31 CSI2_DN6
B31 CSI2_DP6 GPP_F13/EMMC_DATA0 AP2
A33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP1 [#545659 Rev0.7]
B33 CSI2_DP7 GPP_F15/EMMC_DATA2 AP3
GPP_F16/EMMC_DATA3 AN3 GPP_F: VCCPGPPF = 1.8V Only
A29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN1
B29 CSI2_DP8 GPP_F18/EMMC_DATA5 AN2
C28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM4
D28 CSI2_DP9 GPP_F20/EMMC_DATA7 AM1
A27 CSI2_DN10
B27 CSI2_DP10 GPP_F21/EMMC_RCLK AM2
C27 CSI2_DN11 GPP_F22/EMMC_CLK AM3
D27 CSI2_DP11 GPP_F12/EMMC_CMD AP4 R1502
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP
SKYLAKE-U-GP 200R2F-L-GP
C C
071.SKYLA.000U

CPU BOM CTRL

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(CS-2/EMMC)
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 15 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

#543016:
220 nF nominal capacitors are recommended for Gen 3. CPU1H 8 OF 20
100 nF nominal capacitors are recommended for Gen 2. SKYLAKE_ULT
SSIC / USB3
PCIE/USB3/SATA

USB3_1_RXN
H8
USB30_RX_CPU_N1 36
(#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.
G8
USB3_1_RXP USB30_RX_CPU_P1 36
H13 C13
76 PEG_RX_CPU_N0
76 PEG_RX_CPU_P0 G13
PCIE1_RXN/USB3_5_RXN
PCIE1_RXP/USB3_5_RXP
USB3_1_TXN
USB3_1_TXP
D13
USB30_TX_CPU_N1
USB30_TX_CPU_P1
36
36
USB1 (USB3.0 Port1)
76 PEG_TX_GPU_N0 C1606 1 2 SCD22U10V2KX-L1-GP PX PEG_TX_CPU_N0 B17
C1605 PCIE1_TXN/USB3_5_TXN
76 PEG_TX_GPU_P0 1 2 SCD22U10V2KX-L1-GP PX PEG_TX_CPU_P0 A17 J6
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_RXN USB30_RX_CPU_N2 36
H6
76 PEG_RX_CPU_N1 G11
PCIE2_RXN/USB3_6_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
B13
USB30_RX_CPU_P2
USB30_TX_CPU_N2
36
36
USB2 (USB3.0 Port2)
76 PEG_RX_CPU_P1 F11 A13 USB30_TX_CPU_P2 36
C1608 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_TXP
76 PEG_TX_GPU_N1 1 2 SCD22U10V2KX-L1-GP PX PEG_TX_CPU_N1 D16
C1607 PCIE2_TXN/USB3_6_TXN
76 PEG_TX_GPU_P1 1 2 SCD22U10V2KX-L1-GP PX PEG_TX_CPU_P1 C16 J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN
H10
GPU 76 PEG_RX_CPU_N2 H16
PCIE3_RXN
USB3_3_RXP
USB3_3_TXN
B15
76 PEG_RX_CPU_P2 G16 A15
C1610 PCIE3_RXP USB3_3_TXP
76 PEG_TX_GPU_N2 1 2 SCD22U10V2KX-L1-GP PX PEG_TX_CPU_N2 D17
C1609 PCIE3_TXN
76 PEG_TX_GPU_P2 1 2 SCD22U10V2KX-L1-GP PX PEG_TX_CPU_P2 C17 E10
PCIE3_TXP USB3_4_RXN
F10
USB3_4_RXP
76 PEG_RX_CPU_N3 G15 C15
D PCIE4_RXN USB3_4_TXN D
76 PEG_RX_CPU_P3 F15 D15
C1612 PCIE4_RXP USB3_4_TXP
76 PEG_TX_GPU_N3 1 2 SCD22U10V2KX-L1-GP PX PEG_TX_CPU_N3 B19
C1611 PCIE4_TXN
1 2 SCD22U10V2KX-L1-GP PX PEG_TX_CPU_P3 A19 AB9
76 PEG_TX_GPU_P3 PCIE4_TXP USB2N_1
USB2P_1
AB10
USB_CPU_PN0
USB_CPU_PP0
36
36
USB1 (USB2.0 port1)
61 PCIE_RX_CPU_N5 F16
SCD1U16V2KX-3GP PCIE5_RXN
E16 AD6
WLAN 61 PCIE_RX_CPU_P5
61 PCIE_TX_CON_N5 C1601 1 2 PCIE_TX_CPU_N5 C19
PCIE5_RXP
PCIE5_TXN
USB2N_2
USB2P_2
AD7
USB_CPU_PN1
USB_CPU_PP1
36
36
USB2 (USB2.0 Port2)
61 PCIE_TX_CON_P5 C1602 1 2 PCIE_TX_CPU_P5 D19
SCD1U16V2KX-3GP PCIE5_TXP USB_CPU_PN2
AH3
G18
PCIE6_RXN
USB2N_3
USB2P_3
AJ3 USB_CPU_PP2
USB_CPU_PN2
USB_CPU_PP2
66
66
USB3 (IO BD/USB2.0 Port3)
F18
PCIE6_RXP USB_CPU_PN3 TP1605
D20 AD9 1
PCIE6_TXN USB2N_4 USB_CPU_PP3 TP1606
C20 AD10 1
PCIE6_TXP USB2P_4
F20 AJ1
60 SATA_RX_CPU_N0
60 SATA_RX_CPU_P0 E20
PCIE7_RXN/SATA0_RXN
PCIE7_RXP/SATA0_RXP
USB2N_5
USB2P_5
AJ2
USB_CPU_PN4
USB_CPU_PP4
55
55
CAMERA (USB2.0 Port5)
B21 USB2
HDD (SATA GEN.3) 60 SATA_TX_CPU_N0
60 SATA_TX_CPU_P0 A21
PCIE7_TXN/SATA0_TXN
PCIE7_TXP/SATA0_TXP USB2N_6
AF6 USB_CPU_PN5 1 TP1603
AF7 USB_CPU_PP5 1 TP1604
USB2P_6
60 SATA_RX_CPU_N1 G21
PCIE8_RXN/SATA1A_RXN USB_CPU_PN6 TP1601
60 SATA_RX_CPU_P1 F21 AH1 1
PCIE8_RXP/SATA1A_RXP USB2N_7 USB_CPU_PP6 TP1602
D21 AH2 1
ODD (SATA GEN.2) 60 SATA_TX_CPU_N1
60 SATA_TX_CPU_P1 C21
PCIE8_TXN/SATA1A_TXN
PCIE8_TXP/SATA1A_TXP
USB2P_7
AF8
E22
PCIE9_RXN
USB2N_8
USB2P_8
AF9
USB_CPU_PN7
USB_CPU_PP7
61
61
Bluetooth (USB2.0 Port8)
E23
PCIE9_RXP
B23 AG1
A23
PCIE9_TXN
PCIE9_TXP
USB2N_9
USB2P_9
AG2
USB_CPU_PN8
USB_CPU_PP8
33
33
USB2.0 Card Reader (USB2.0 Port9)
F25 AH7
PCIE10_RXN USB2N_10
E25 AH8
PCIE10_RXP USB2P_10
D23
PCIE10_TXN USBCOMP
C23 AB6 1 R1603 2 113R2F-GP USBCOMP DC resistance < 0.5ohm.
PCIE10_TXP USB2_COMP
AG3
PCIE_RCOMPN USB2_ID Unused SATA[3:0]GP pins must be terminated to either
F5 AG4
R1604 1 PCIE_RCOMPP PCIE_RCOMPN USB2_VBUSSENSE 3.3V rail or GND using 8.2K
to 10K
on the
2 E5
100R2F-L1-GP-U PCIE_RCOMPP USB_OC0# motherboard. Either pull-up or pull-down is acceptable.
A9
GPP_E9/USB2_OC0# USB_OC1# USB_OC0# 36
99 XDP_PRDY# D56 C9
PROC_PRDY# GPP_E10/USB2_OC1# USB_OC2# USB_OC1# 36
99 XDP_PREQ# D61 D9
10KR2J-3-GP 2 PROC_PREQ# GPP_E11/USB2_OC2# USB_OC2# 66
3D3V_S0 1R1607 PIRQA# BB11 B9 USB_OC3#
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28
PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0
J1 DEVSLP0_HDD_CON 60 (#543016) When used as DEVSLP, no external pull-up or pull-down
SATA_ODD_DA# 3D3V_S0
DY E27 J2 SATA_ODD_DA# 60 termination required from SATA Host DEVSLP.
PESD5V0U1BL-GP-U1

PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1
1

D24 J3 DEVSLP2_mSATA
PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 R1610
ED1602

C24
PCIE11_TXP/SATA1B_TXP GPP_E0/SATAXPCIE0/SATAGP0 DEVSLP0_HDD_CON
31 PCIE_RX_CPU_N6 E30 H2 2 1 10KR2J-3-GP
SCD1U16V2KX-3GP PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 SATA_ODD_PRSNT# 3D3V_S5
31 PCIE_RX_CPU_P6
C1603 1 PCIE_TX_CPU_N6
F30
PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1
H3
SATAXPCIE2
SATA_ODD_PRSNT# 60 3D3V_S0 DY
2 A25 G4
LAN 31 PCIE_TX_CON_N6
2

C1604 1 PCIE_TX_CPU_P6 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 RN1602

31 PCIE_TX_CON_P6 2 B25 R1611
SCD1U16V2KX-3GP PCIE12_TXP/SATA2_TXP SATA_LED# USB_OC2#
H1 SATA_LED# 64 8 1
GPP_E8/SATALED# USB_OC0# DEVSLP2_mSATA
7 2 2 1 10KR2J-3-GP
USB_OC3# 6 3 DY
SKYLAKE-U-GP RN1601 USB_OC1# 5 4 R1608
SATAXPCIE2 8 1
071.SKYLA.000U GPP_E0/SATAXPCIE0/SATAGP0 7 2 SATA_ODD_DA# 2 1 10KR2J-3-GP
Recommended Layout for PCIE_RCOMPP/N: SATA_LED# 6 3 SRN10KJ-6-GP
1. Trace Width: 4 mils min (breakout) 12-15 mils (trace) SATA_ODD_PRSNT# 5 4
C Note: Must maintain low DC resistance routing (<0.1 ohm). CPU BOM CTRL C
2. Isolation Spacing: At least 12 mils to any adjacent SRN10KJ-6-GP
high speed I/O.

(#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND
PCIE Table USB 2.0 Table using 8.2 KΩ to 10 KΩ on the motherboard.
Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable.
Pair Device

0 USB3.0 port1 (Debug Port)

Port Device Share BUS
1 USB2.0 Port2
1 GPU L0
2 USB2.0 Port3 (IOBD)
2 GPU L1
3
3 GPU L2
4 CAMERA
4 GPU L3
5
5 WLAN
6
6 N/A
7 Bluetooth
7 N/A SATA0 (HDD)
8 USB2.0 Card Reader
8 N/A SATA1 (ODD)
9
9 N/A

10 N/A

11 N/A
20151024 Modify PCIE/USB2.0 Mapping Table
12 LAN

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(PCIE/SATA/USB)
Size Document Number Rev
A1
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 16 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

3D3V_S5

R1709
1 2 AC_PRESENT
10KR2J-3-GP

RN1701 SIO_SLP_S3# 1 TP1701

1 4 SIO_PWRBTN#
2 3 PCH_WAKE#

SRN10KJ-5-GP
R1713
R1723 PCH_PLTRST#
24,31,40,61,68,76 PLT_RST# 1 2
D 1 2 PCH_BATLOW# D

1
10KR2J-3-GP 33R2J-2-GP

1
RTC_AUX_S5 3D3V_S0 3D3V_S5 R1715
47KR2J-2-GP C1701
SC100P50V2JN-3GP [#543016 Rev0.7]

2
EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k
DY

2
1

1
1 2 SM_INTRUDER# pull-down that is active during the early portion of the power up sequence
R1730 1MR2J-1-GP R1711 R1701
3KR2J-2-GP CPU1K 11 OF 20
10KR2J-3-GP
DY SYSTEM POWER MANAGEMENT

2
AT11 SIO_SLP_S0# 1 TP1709
ED1704 SKYLAKE_ULT GPP_B12/SLP_S0#
AP15 SIO_SLP_S3# 24,40,51,52,54
R1733 1 10KR2J-3-GP PM_RSMRST# PCH_PLTRST# GPD4/SLP_S3#
2 2 1 AN10 BA16 SIO_SLP_S4# 24,40,51
XDP_DBRESET# GPP_B13/PLTRST# GPD5/SLP_S4# SIO_SLP_S5# 3D3V_S5
B5 AY16 1
PM_RSMRST# SYS_RESET# GPD10/SLP_S5# TP1703
AY17
PESD5V0U1BL-GP-U1 RSMRST# SIO_SLP_SUS# TP1710
DY H_CPUPWRGD SLP_SUS#
AN15
SLP_LAN#
1
0R2J-2-GP
1 R1736 2 A68 AW15 1
40 H_THERMTRIP_EN PROCPWRGD SLP_LAN# R1731
#544669 Rev0.52 CRB: H_VCCST_PWRGD_R 1 2 60D4R2F-GP H_VCCST_PWRGD B65 BB17 GPD9/SLP_WLAN# 1 TP1704
R1734 VCCST_PWRGD GPD9/SLP_WLAN# SIO_SLP_A# TP1705 EXT_PWR_GATE#
No PL resistor on THERMTRIP#. AN16 1 2 1
ED1701 SYS_PWROK GPD6/SLP_A# TP1706
24 SYS_PWROK B6
H_CPUPWRGD R1706 1 PM_PCH_PWROK SYS_PWROK
2 1 40 PCH_PWROK 2 0R0402-PAD BA20 BA15 SIO_PWRBTN# 24
PM_RSMRST# R1704 1 0R0402-PAD PCH_DPWROK PCH_PWROK GPD3/PWRBTN# AC_PRESENT 20KR2J-L2-GP
DY 2 BB20
DSW_PWROK GPD1/ACPRESENT
AY15
PCH_BATLOW#
AC_PRESENT 24
AU13
1

PESD5V0U1BL-GP-U1 ME_SUS_PWR_ACK_R AR13 GPD0/BATLOW#

BATLOW#:

1
20,24 ME_SUS_PWR_ACK_R SUSACK#_R GPP_A13/SUSWARN#/SUSPWRDNACK
AP11 Pull-up required even if not implemented.
1
PM_PCH_PWROK R1735 GPP_A15/SUSACK# PME#
1 2 AU11 1
GPP_A11/PME#
ED1703
R1732 8K2R2F-1-GP DY 10KR2J-3-GP 24,31,79 PCH_WAKE# BB15 AP16 SM_INTRUDER# TP1707
PESD5V0U1BL-GP-U1

AFTP1702 PCH_WAKE# R1707 GPD2/LAN_WAKE# WAKE# INTRUDER#

3D3V_S5 1 2 10KR2J-3-GP AM15
R1717 SYS_PWROK GPD2/LAN_WAKE# EXT_PWR_GATE#
2 DY 1 10KR2J-3-GP AW17 AM10

2
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# GPP_B2/VRALERT#
AT15 AM11 1
2

GPD7/RSVD#AT15 GPP_B2/VRALERT# TP1708

(PDG#543016)
SKYLAKE-U-GP
WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns.
071.SKYLA.000U CPU BOM CTRL

3D3V_S5

SCD1U16V2KX-3GP
C C1702 C
+VCCST_CPU

1
2
Dis-wire with XDP_PM_RSMRST_PWRGD_XDP

1
U1701 R1722
1KR2J-1-GP
1 5
NC#1 VCC
VCCST_PWRGD / HWM201:

2
24,40 ALL_SYS_PWRGD 2
A
3 4 H_VCCST_PWRGD_R
GND Y
EC1708

1
74LVC1G07GW-GP DY
73.01G07.0HG

SCD1U16V2KX-3GP
2
1
R1716
DY 2
100KR2F-L1-GP

1
R1719

1
47KR2F-GP
EC1709
DY
DY
SCD1U16V2KX-3GP

2
#543016 Rev0.7
1. VCCST_PWRGD is only 1.0 V tolerant.
2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST
B B

XDP_DBRESET#
SYS_PWROK
PLT_RST#
PCH_PWROK

DY

1
R1708 DY DY DY DY
ME_SUS_PWR_ACK_R 1 2 SUSACK#_R EC1706 EC1702 EC1703 EC1704 ED1702
0R2J-2-GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
PESD5V0U1BL-GP-U1

2
DY

2
3D3V_AUX_KBC R1727
100KR2J-1-GP
1 2
2

R1726
10KR2J-3-GP

1KR2J-1-GP
Q1701
1

R1702
4 3 PM_RSMRST# 1 2 PCH_RSMRST# 24
3V_5V_POK# 5 2 3V_5V_POK_C 1 R1728 2 3V_5V_POK 45,54
6 1 0R0402-PAD EC1711 EC1712
1

DY DY
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

A 2N7002KDW-GP A
2

84.2N702.A3F
2nd = 075.063D1.007C <Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(POWER MANAGEMENT)
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 17 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH PCH strap pin: PCH Prim

PCH strap pin: PCH Prim
eSPI or LPC Sampled at rising edge of RSMRST# 3D3V_S5
BOOT HALT 3D3V_S5
SML0ALERT# / This signal has a weak internal pull-down. 3D3V_S5

1
0 = LPC Is selected for EC. SPI0_MOSI 0 = ENABLED
GPP_C5

1
DY R1822 1 = DISABLED
1 = eSPI Is selected for EC. R1824
1KR2J-1-GP WEAK INTERNAL PU DY SML1_SMBDATA
RN1807
This signal has a weak internal pull-down. 1KR2J-1-GP 8 1
This signal has a weak internal pull-up. SML1_SMBCLK 7 2

2
SML0_DATA 6 3

2
GPP_C5/SML0ALERT# SML0_CLK 5 4
SPI_SI0_R

1
SRN2K2J-4-GP

1
DY R1823
1KR2J-1-GP DY R1825
1KR2J-1-GP

2
3D3V_S5
3D3V_S5 PLACE WITHIN 1.1 INCH OF PCH GPP_C2/SMBALERT# 1 R1827 2
(#543016)Optional, can be left as OPEN/No-Connect. DY 10KR2J-3-GP
1

RN1811
1

R1835
D R1834 MEM_SMBCLK 4 1 D
1KR2J-1-GP
DY 1KR2J-1-GP DY MEM_SMBDATA 3 2
2
2

SPI_HOLD_0# SRN2K2J-1-GP
1

LPC_AD0 1 R1805 2 0R0402-PAD LPC_LAD0_R add Circuit for NFC

R1836 24,68 LPC_AD0 LPC_AD2 1 R1806 2 0R0402-PAD LPC_LAD2_R
SPI0_WP# 24,68 LPC_AD2 LPC_AD1
1KR2J-1-GP 1 R1807 2 0R0402-PAD LPC_LAD1_R
24,68 LPC_AD1 LPC_AD3 1 R1808 2 0R0402-PAD LPC_LAD3_R
24,68 LPC_AD3
2

3D3V_S0 CPU1E 5 OF 20
Resister value will check later
SPI - FLASH
SMBUS, SMLINK
R1840 SKYLAKE_ULT 3D3V_S5
24,25 SPI_CLK_R AV2 R7 MEM_SMBCLK
SIO_RCIN# SPI0_CLK GPP_C0/SMBCLK MEM_SMBDATA
1 2 24,25 SPI_SO_R AW3 R8
10KR2J-3-GP SPI0_MISO GPP_C1/SMBDATA GPP_C2/SMBALERT#
24,25 SPI_SI0_R AV3 Strap R10
SPI0_MOSI GPP_C2/SMBALERT# R1814
R1841 25 SPI0_WP# AW2
SPI0_IO2 SML0_CLK SUS_STAT#/LPCPD#
INT_SERIRQ
25 SPI_HOLD_0# AU4
SPI0_IO3 GPP_C3/SML0CLK
R9
SML0_DATA
2 DY 1
1 2 24,25 SPI_CS0#_R AU3 W2
10KR2J-3-GP SPI0_CS0# GPP_C4/SML0DATA GPP_C5/SML0ALERT# 10KR2J-3-GP
AU2 W1
AU1
SPI0_CS1# Strap GPP_C5/SML0ALERT# 3D3V_S0
SPI0_CS2# SML1_SMBCLK
SERIRQ PH: GPP_C6/SML1CLK
W3 SML1_SMBCLK 24,79
PDG: 8.2k V3 SML1_SMBDATA R1818
SPI - TOUCH GPP_C7/SML1DATA SML1_SMBDATA 24,79
AM7 CLKRUN#_R 1 2
CRB: 10k MD_ID1 GPP_B23/SML1ALERT#/PCHHOT#
M2
MD_ID2 GPP_D1/SPI1_CLK 8K2R2F-1-GP
M3
MD_ID3 GPP_D2/SPI1_MISO
J4
TPAD14-OP-GP TP1804 GPP_D3/SPI1_MOSI 20140820 DAIVD
1 CPU_D4_TP V1
TPAD14-OP-GP TP1805 GPP_D21/SPI1_IO2
1 CPU_D5_TP V2
MD_ID0 GPP_D22/SPI1_IO3 LPC_LAD0_R
M1 LPC AY13
GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 LPC_LAD1_R
BA13
GPP_A2/LAD1/ESPI_IO1 LPC_LAD2_R
BB13
C LINK GPP_A3/LAD2/ESPI_IO2 LPC_LAD3_R R1801
AY12
GPP_A4/LAD3/ESPI_IO3 LPC_LFRAME#_R
61 CL_CLK G3 BA12 2 1 LPC_FRAME# 24,68
CL_CLK GPP_A5/LFRAME#/ESPI_CS# SUS_STAT#/LPCPD# 0R0402-PAD
61 CL_DATA G2 BA11
CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET#
61 CL_RST# G1
CL_RST#
AW9 PCI_CLK_LPC0 R1820 1 2 22R2J-2-GP CLK_PCI_KBC 24
GPP_A9/CLKOUT_LPC0/ESPI_CLK PCI_CLK_LPC1 R1804 1
RCIN#: 24 SIO_RCIN# AW13 AY9 2 22R2J-2-GP CLK_PCI_DB 68
GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 CLKRUN#_R
Frequency to Avoid: 33 MHz AW11 1 R1819 2 PM_CLKRUN#_EC_R 24
GPP_A8/CLKRUN#
24 INT_SERIRQ AY11
GPP_A6/SERIRQ 0R0402-PAD
1

SKYLAKE-U-GP
EC1805
SCD1U16V2KX-3GP 071.SKYLA.000U
2

DY 3D3V_S0
CPU BOM CTRL
RN1810
3 2 3D3V_S0
4 1
3D3V_S5
SRN10KJ-5-GP Memory Down Strap
2N7002KDW-GP
C R1839 1 C
2 1KR2J-1-GP MID0_H MD_ID0 R1828 1 2 1KR2J-1-GP MID0_L
MEM_SMBDATA 6 1 R1831 1 2 1KR2J-1-GP MID1_H MD_ID1 R1830 1 2 1KR2J-1-GP MID1_L
PCH_SMBDATA 13,65
R1832 1 2 1KR2J-1-GP MID2_H MD_ID2 R1833 1 2 1KR2J-1-GP MID2_L
84.2N702.A3F 5 2 R1837 1 2 1KR2J-1-GP MID3_H MD_ID3 R1838 1 2 1KR2J-1-GP MID3_L
2nd = 075.063D1.007C
4 3

Q1801

PCH_SMBCLK 13,65 0=L,1=H

RAMID MD_ID3 MD_ID2 MD_ID1 MD_ID0 LENOVO PN VENDOR PN WISTRON PN VENDOR Density
MEM_SMBCLK
0 0 0 0 0 SAMSUNG 1GB
1 0 0 0 1 MICRON 1GB
RTC_X1
C1801
2 0 0 1 0 HYNIX 1GB
1 2 RTC_X2 XTAL24_IN 2 1
R1815 10MR2J-L-GP 3 0 0 1 1 SAMSUNG 2GB
X1802 SC15P50V2JN-L-GP
4 0 1 0 0 MICRON 2GB

1
1 4 X1801 5 0 1 0 1 HYNIX 2GB

1
XTAL-24MHZ-81-GP
R1802 6 0 1 1 0 SM30K11219 K4A8G165WB-BCPB 072.48165.000U SAMSUNG 4GB
1MR2J-1-GP 82.30004.841

2
2 3 7 0 1 1 1 SM30K59902 MT40A512M16HA-083E:A 072.40512.0A0U MICRON 4GB

4
C1804 C1803

2
SC4P50V2CN-GP SC4P50V2CN-GP C1802
XTAL24_OUT 8 1 0 0 0 SM30K59899 H5AN8G6NAFR-TFC N/A HYNIX 4GB

1
XTAL-32D768KHZ-67-GP XTAL24_OUT 2 1
CPU1J 10 OF 20 9 1 0 0 1
CLOCK SIGNALS 82.30001.G11 SC15P50V2JN-L-GP
DY 10 1 0 1 0

1
ED1803
GPU 76 PEG_CLK_CPU# D42 11 1 0 1 1

PESD5V0U1BL-GP-U1
CLKOUT_PCIE_N0 SKYLAKE_ULT
76 PEG_CLK_CPU C42
CLKREQ_PEG#0 CLKOUT_PCIE_P0
76 CLKREQ_PEG#0 AR10
GPP_B5/SRCCLKREQ0# 12 1 1 0 0

2
WLAN 61 PEG_CLK1_CPU# B42
CLKOUT_PCIE_N1 13 1 1 0 1
61 PEG_CLK1_CPU A42 F43 SUSCLK_R
CLKREQ_PCIE#1 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N
61 CLKREQ_PCIE#1 AT7
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
E43 14 1 1 1 0

2
R1813 RTC_AUX_S5
D41 BA17 SUSCLK_R 1 2 PCH_SUSCLK_KBC 61 DY EC1803 15 1 1 1 1
CLKOUT_PCIE_N2 GPD8/SUSCLK
C41

SC4D7P50V2BN-GP
CLKREQ_PCIE#5 CLKOUT_PCIE_P2 XTAL24_IN 0R0402-PAD 1D0V_S5
AT8 E37
GPP_B7/SRCCLKREQ2# XTAL24_IN XTAL24_OUT +V1.05S_AXCK_LCPLL
E35
XTAL24_OUT

2
1
3D3V_S0 D40
CLKOUT_PCIE_N3 XCLK_BIASREF
C40 E42 1 R1803 2 RN1813
RN1802 CLKREQ_PCIE#3 CLKOUT_PCIE_P3 XCLK_BIASREF 2K7R2F-GP
AT10 SRN20KJ-1-GP
CLKREQ_PEG#0 GPP_B8/SRCCLKREQ3# RTC_X1 R1810
1 4 AM18
CLKREQ_PCIE#1 RTCX1 RTC_X2 Intel recommend: 2.71k ohm 5%
2 3 B40 AM20 1 2
CLKOUT_PCIE_N4 RTCX2 0R0402-PAD
A40
Check Clock Mapping

3
4
CLKREQ_PCIE#4 CLKOUT_PCIE_P4 SRTC_RST#
AU8 AN18
SRN10KJ-5-GP GPP_B9/SRCCLKREQ4# SRTCRST# RTC_RST# Q1803
AM16
RTCRST#
31 PEG_CLK2_CPU# E40 24 RTCRST_ON G
RN1801 CLKOUT_PCIE_N5 SRTC_RST#
E38
B
8 1 CLKREQ_PCIE#5 LAN 31 PEG_CLK2_CPU
31 CLKREQ_PCIE#2 CLKREQ_PCIE#2 AU7
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#
1
D RTC_RST# B
7 2 CLKREQ_PCIE#2 DY R1821

SC1U10V2KX-1GP
1

2
6 3 CLKREQ_PCIE#4 10KR2J-3-GP S
DY DY

1
ED1802

C1806
5 4 CLKREQ_PCIE#3 Notice:ZZ.2N702.J3101
G1801
PESD5V0U1BL-GP-U1

1
SCD1U16V2KX-3GP

2N7002K-2-GP C1805 <Core Design>

2

1
EC1808

GAP-OPEN

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
SKYLAKE-U-GP SC1U10V2KX-1GP
DY 84.2N702.J31

2
SRN10KJ-6-GP

EC1806

EC1807
DY DY
Wistron Corporation
2

2
071.SKYLA.000U

2
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
(#514849)
Taipei Hsien 221, Taiwan, R.O.C.
CPU BOM CTRL 2ND = 84.2N702.031
3rd = 84.2N702.W31 Title

Layout: Place at the open door area. CPU_(LPC/SPI/SMBUS/CL/CLK)

Size Document Number Rev
A1
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 18 of 102

A A

5 4 3 2 1
 5 4 3 2 1

Main Func = PCH Strap pin:

Port B /
Sampled at rising edge of PCH_PWROK
Port C Detected

0 = Port B is not detected.

DDPB_CTRLDATA * 1 = Port B is detected.

DDPC_CTRLDATA *
D D
R1915
CPU1G 7 OF 20 BT_DISABLE# 2 1
These two signals have weak internal pull-down.
0 = Port C is not detected.
AUDIO 10KR2J-3-GP
1 = Port C is detected. SKYLAKE_ULT
HDA_SYNC BA22
HDA_BITCLK HDA_SYNC/I2S0_SFRM
AY22 HDA_BLK/I2S0_SCLK
HDA_SDOUT BB22 SDIO/SDXC
HDA_SDO/I2S0_TXD
27 HDA_SDIN0 BA21 HDA_SDI0/I2S0_RXD
AY21 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB11 BT_DISABLE# 61
HDA_RST# AW22 AB13
HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 SATA_ODD_PW RGT 60
J5 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 AB12
AY20 I2S1_SFRM GPP_G3/SD_DATA2 W12 PE_GPIO0 76
AW20 I2S1_TXD GPP_G4/SD_DATA3 W11
GPP_G5/SD_CD# W10
AK7 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W8
AK6 GPP_F0/I2S2_SCLK GPP_G7/SD_WP W7
AK9 GPP_F2/I2S2_TXD
AK10 GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BA9
BB9 CPU_A16_TP 1 TP1902
GPP_A16/SD_1P8_SEL TPAD14-OP-GP
H5 AB7 SD_RCOMP 1 R1901 2
GPP_D19/DMIC_CLK0 SD_RCOMP
D7 GPP_D20/DMIC_DATA0
200R2F-L-GP
D8 GPP_D17/DMIC_CLK1 GPP_F23 AF13
24,76,85 DGPU_PW ROK DGPU_PW ROK C8 GPP_D18/DMIC_DATA1
27 SPKR SPKR AW5
C GPP_B14/SPKR C

SKYLAKE-U-GP
PCH strap pin:
PCH strap pin: CPU BOM CTRL
Flash Descriptor Security Overide/ NO REBOOT
3D3V_S0
Intel ME Debug Mode 1KR2J-1-GP
Low = Default * Low = Enable (Default) R1916
HDA_SDOUT High = Enable HDA_SPKR
* 1 DY 2 SPKR
High = Disable
The internal pull-down is disabled after
PLTRST# deasserts The internal pull-down is disabled after
PLTRST# deasserts

27 HDA_CODEC_BITCLK R1917 1 2 0R0402-PAD HDA_BITCLK

27 HDA_CODEC_SDOUT R1918 1 2 0R0402-PAD HDA_SDOUT

24 ME_FW P_EC R1909 1 2 1KR2J-1-GP

EC1901 1 2 HDA_CODEC_BITCLK
B B

SC10P50V2JN-L1-GP

DY R1919
27 HDA_CODEC_SYNC 1 2 0R0402-PAD HDA_SYNC
27 HDA_CODEC_RST# R1920 1 2 0R0402-PAD HDA_RST#

HDA_CODEC_RST#
1

DY EC1902
SCD1U16V2KX-3GP
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(AUDIO/SDIO/SDXC)
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 19 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH 3D3V_S0

R2004 RN2007
10KR2J-3-GP 2 1 DGPU_HOLD_RST# NO_USE_PCH_I2C0_SCL 2 3
2 1 DGPU_PWR_EN 20151013 Change VIDEO_THERM_ALERT# PIN to GPP_B20 NO_USE_PCH_I2C0_SDA 1 4
10KR2J-3-GP R2006 DY DY SRN2K2J-1-GP

1
R2011 1 CAMERA_EN RN2008
2
10KR2J-3-GP EC2002
DY CPU1F 6 OF 20 I2C1_SCL 1 4
I2C1_SDA DY

SC1KP50V2KX-1GP
2 3
DY

2
LPSS ISH
SKYLAKE_ULT
USB_UART_SEL_D9 1 TP2006 TPAD14-OP-GP SRN2K2J-1-GP
AN8 P2
GPP_B15/GSPI0_CS# GPP_D9 DGPU_HOLD_RST#
AP7 P3 DGPU_HOLD_RST# 76
GPP_B16/GSPI0_CLK GPP_D10 RN2009
AP8 P4
GPP_B18/GSPI0_MOSI GPP_B17/GSPI0_MISO GPP_D11 ISH_GP_0_R
AR7 P1 1 4
PCH strap pin: GPP_B18/GSPI0_MOSI
Strap GPP_D12 CAMERA_EN 55
ISH_GP_1_R 2 3
RTC_DET_R AM5 M4
25 RTC_DET_R GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA
D Boot BIOS Strap Bit BBS 1 R2040 20R0402-PAD VIDEO_THERM_ALERT#_R AN7 N3 SRN10KJ-5-GP D
79 VIDEO_THERM_ALERT# GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
GPP_B22/GSPI1_MOSI
AP5
GPP_B21/GSPI1_MISO I2C1_SDA
DY
AN5 N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA I2C1_SCL
Boot BIOS * Low = SPI (Default) GPP_D8/ISH_I2C1_SCL
N2
High = LPC ON_BOARD_RAM_CFG AB1
Destination DIMM_SKT_CFG GPP_C8/UART0_RXD
AB2 AD11 1.8V Only
CPU_15W_28W_CFG GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
W4 AD12
The internal pull-down is disabled after PLTRST# deasserts DGPU_PRSNT# AB3
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#
GPP_F11/I2C5_SCL/ISH_I2C2_SCL 20151013 ADD R2041 to Connect DGPU_PWR_EN and PE_GPIO1
Need double confirm, GPIO table set to GPI AD1 U1 DGPU_PWR_EN 1 R2041 2 0R0402-PAD PE_GPIO1 85,86
GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
AD2 U2
if that's needed PH or PL AD3
GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
U3
GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# UART0_CTS# TP2011 TPAD14-OP-GP
AD4 U4 1
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
(PDG#543016) Ensure that all I2C interface on-board terminations are pulled up
AC1 UART1_RXD 1 TP2012 TPAD14-OP-GP to the same voltage rail as the device/end point.
3D3V_S0 NO_USE_PCH_I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD UART1_TXD TP2013 TPAD14-OP-GP
U7 AC2 1
NO_USE_PCH_I2C0_SCL GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD UART1_RTS# TP2014 TPAD14-OP-GP
U6 AC3 1
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# UART1_CTS# TP2015 TPAD14-OP-GP
AB4 1
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
U8
GPP_C18/I2C1_SDA ISH_GP_0_R
U9 AY8
GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 ISH_GP_1_R
BA8
R2001 1 CAMERA_EN GPP_A19/ISH_GP1
DY 2 10KR2J-3-GP AH9 BB7
GPP_F4/I2C2_SDA GPP_A20/ISH_GP2
AH10 BA7
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3
AY7
GPP_A22/ISH_GP4 NO_USE_PCH_01
AH11 AW7
GPP_F6/I2C3_SDA GPP_A23/ISH_GP5
AH12 AP13
GPP_F7/I2C3_SCL SX_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL

R2003 1 2 1KR2J-L2-GP GPP_B22/GSPI1_MOSI SKYLAKE-U-GP

DY 071.SKYLA.000U (PDG#543016) If the UART/GPIO functionality is also not used,

the signals can be left as no-connect.
PCH Prim CPU BOM CTRL
PCH strap pin: 3D3V_S0 3D3V_S0 3D3V_S0

C C
No Reboot Sampled at rising edge of PCH_PWROK
1

1
DY R2007 R2005 R2053
GSPI0_MOSI / 0 = Disable “No Reboot” mode. 1KR2J-1-GP
UMA 10KR2J-3-GP DY 10KR2J-3-GP
GPP_B18 1 = Enable “No Reboot” mode (PCH will disable the TCO
Timer system reboot feature). This function is useful
2

2
when running ITP/XDP. GPP_B18/GSPI0_MOSI DGPU_PRSNT# NO_USE_PCH_01
1

The signal has a weak internal pull-down.

1
DY R2019
1KR2J-1-GP R2008 R2054
10KR2J-3-GP 10KR2J-3-GP
PX DY
2

2
3D3V_S5 3D3V_S5 3D3V_S5
1

1
R2010 R2013 R2015
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
ON BOARD RAM STUFF DIMM SKT STUFF CPU_28W
2

2
ON_BOARD_RAM_CFG DIMM_SKT_CFG CPU_15W_28W_CFG
1

1
R2009 R2012 R2014
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
3D3V_S5 ON BOARD RAM DY DIMM SKT DY CPU_15W
2

2
R2039 1 2 10KR2J-3-GP
ME_SUS_PWR_ACK_R 17,24
B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(LPSS/ISH)
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 20 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

RTC_AUX_S5

1D0V_S5 CPU1O 15 OF 20

1
CPU POWER 4 OF 4 3D3V_S5 C2119 C2118 C2117
AB19 SCD1U16V2KX-3GP SCD1U16V2KX-3GP SC1U10V2KX-1GP

2
VCCPRIM_1P0
AB20
VCCPRIM_1P0 SKYLAKE_ULT VCCPGPPA
AK15 +VCCPGPPA DY
P18 AG15
VCCPRIM_1P0 VCCPGPPB
Y16
VCCPGPPC
2.57A AF18
VCCPRIM_CORE VCCPGPPD
Y15 CAP need close to VCCRTC
AF19 T16

1
VCCPRIM_CORE VCCPGPPE
V20 1.8V Only AF16 +V1.8A
VCCPRIM_CORE VCCPGPPF C2106 C2107
D V21 AD15 D
+VCCDSW_1P0 VCCPRIM_CORE VCCPGPPG SC1U10V2KX-1GP SC1U10V2KX-1GP

2
AL1 V19 3D3V_S5
1

C2120 1D0V_S5 DCPDSW_1P0 VCCPRIM_3P3

SC1U10V2KX-1GP K17 T1 1D0V_S5
VCCMPHYAON_1P0 VCCPRIM_1P0
L1
2

VCCMPHYAON_1P0
AA1 +V1.8A
VCCATS_1P8
N15
VCCMPHYGT_1P0
N16 AK17 3D3V_S5
VCCMPHYGT_1P0 VCCRTCPRIM_3P3
N17
VCCMPHYGT_1P0
P15 AK19 RTC_AUX_S5
+VCCAMPHYPLL_1P0 VCCMPHYGT_1P0 VCCRTC
P16 BB14
VCCMPHYGT_1P0 VCCRTC
K15 BB10 VCCRTCEXT C2112 1 2 SCD1U16V2KX-3GP
+VCCAPLL_1P0 VCCAMPHYPLL_1P0 DCPRTC
L15
VCCAMPHYPLL_1P0
A14 1D0V_S5
VCCCLK1
V15

1
1D0V_S5 VCCAPLL_1P0
K19 1D0V_S5
VCCCLK2 C2109 C2110 C2111
AB17
3D3V_S5 VCCPRIM_1P0 SC1U10V2KX-1GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP
Y18 L21 1D0V_S5

2
VCCPRIM_1P0 VCCCLK3
AD17 N20 1D0V_S5
VCCDSW_3P3 VCCCLK4
AD18
+VCCPAZIO VCCDSW_3P3
AJ17 L19 1D0V_S5
3D3V_S5 VCCDSW_3P3 VCCCLK5
AJ19 A10 1D0V_S5
VCCHDA VCCCLK6
AJ16 AN11 V0.85A_VID0 1 TP2101 TPAD14-OP-GP
VCCSPI GPP_B0/CORE_VID0
AN13 V0.85A_VID1 1 TP2102 TPAD14-OP-GP
GPP_B1/CORE_VID1
1D0V_S5 AF20
VCCSRAM_1P0
AF21
3D3V_S5 VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3

1D0V_S5 AK20
VCCPRIM_1P0
1

N18
C2105 VCCAPLLEBB_1P0
SC1U10V2KX-1GP
2

C SKYLAKE-U-GP C

071.SKYLA.000U

CPU BOM CTRL

1D0V_S5 +VCCDSW_1P0 +V1.8A

1

C2101 C2102 C2104 C2103 C2108

SC18P50V2JN-1-GP SC18P50V2JN-1-GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP
2

DY DY

1D0V_S5

B B
1

C2113 C2114 C2115 C2116 C2121

SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC1U10V2KX-1GP SC2D2U10V3KX-L-GP
2

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(POWER1)
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 21 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

D D

CPU1T 20 OF 20
SKYLAKE_ULT
SPARE

AW69 RSVD#AW69 RSVD#F6 F6

AW68 RSVD#AW68 RSVD#E3 E3
AU56 RSVD#AU56 RSVD#C11 C11
AW48 RSVD#AW48 RSVD#B11 B11
C7 RSVD#C7 RSVD#A11 A11
U12 RSVD#U12 RSVD#D12 D12
U11 RSVD#U11 RSVD#C12 C12
H11 RSVD#H11 RSVD#F52 F52

SKYLAKE-U-GP

C
071.SKYLA.000U C

CPU BOM CTRL

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(RSVD)
Size Document Number Rev
A4
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 22 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

CPU1P 16 OF 20

GND 1 OF 3
CPU1Q 17 OF 20 CPU1R 18 OF 20
A5 SKYLAKE_ULT AL65
VSS VSS GND 2 OF 3
D A67 VSS VSS AL66 GND 3 OF 3 D
A70 VSS VSS AM13 F8 VSS VSS L18
AA2 AM21 AT63 SKYLAKE_ULT BA49 G10 L2
VSS VSS VSS VSS VSS SKYLAKE_ULT VSS
AA4 VSS VSS AM25 AT68 VSS VSS BA53 G22 VSS VSS L20
AA65 VSS VSS AM27 AT71 VSS VSS BA57 G43 VSS VSS L4
AA68 VSS VSS AM43 AU10 VSS VSS BA6 G45 VSS VSS L8
AB15 VSS VSS AM45 AU15 VSS VSS BA62 G48 VSS VSS N10
AB16 VSS VSS AM46 AU20 VSS VSS BA66 G5 VSS VSS N13
AB18 VSS VSS AM55 AU32 VSS VSS BA71 G52 VSS VSS N19
AB21 VSS VSS AM60 AU38 VSS VSS BB18 G55 VSS VSS N21
AB8 VSS VSS AM61 AV1 VSS VSS BB26 G58 VSS VSS N6
AD13 VSS VSS AM68 AV68 VSS VSS BB30 G6 VSS VSS N65
AD16 VSS VSS AM71 AV69 VSS VSS BB34 G60 VSS VSS N68
AD19 VSS VSS AM8 AV70 VSS VSS BB38 G63 VSS VSS P17
AD20 VSS VSS AN20 AV71 VSS VSS BB43 G66 VSS VSS P19
AD21 VSS VSS AN23 AW10 VSS VSS BB55 H15 VSS VSS P20
AD62 VSS VSS AN28 AW12 VSS VSS BB6 H18 VSS VSS P21
AD8 VSS VSS AN30 AW14 VSS VSS BB60 H71 VSS VSS R13
AE64 VSS VSS AN32 AW16 VSS VSS BB64 J11 VSS VSS R6
AE65 VSS VSS AN33 AW18 VSS VSS BB67 J13 VSS VSS T15
AE66 VSS VSS AN35 AW21 VSS VSS BB70 J25 VSS VSS T17
AE67 VSS VSS AN37 AW23 VSS VSS C1 J28 VSS VSS T18
AE68 VSS VSS AN38 AW26 VSS VSS C25 J32 VSS VSS T2
AE69 VSS VSS AN40 AW28 VSS VSS C5 J35 VSS VSS T21
AF1 VSS VSS AN42 AW30 VSS VSS D10 J38 VSS VSS T4
AF10 VSS VSS AN58 AW32 VSS VSS D11 J42 VSS VSS U10
AF15 VSS VSS AN63 AW34 VSS VSS D14 J8 VSS VSS U63
AF17 VSS VSS AP10 AW36 VSS VSS D18 K16 VSS VSS U64
AF2 VSS VSS AP18 AW38 VSS VSS D22 K18 VSS VSS U66
C AF4 AP20 D25 K22 U67 C
VSS VSS VSS VSS VSS
AF63 VSS VSS AP23 AW41 VSS VSS D26 K61 VSS VSS U69
AG16 VSS VSS AP28 AW43 VSS VSS D30 K63 VSS VSS U70
AG17 VSS VSS AP32 AW45 VSS VSS D34 K64 VSS VSS V16
AG18 VSS VSS AP35 AW47 VSS VSS D39 K65 VSS VSS V17
AG19 VSS VSS AP38 AW49 VSS VSS D44 K66 VSS VSS V18
AG20 VSS VSS AP42 AW51 VSS VSS D45 K67 VSS VSS W13
AG21 VSS VSS AP58 AW53 VSS VSS D47 K68 VSS VSS W6
AG71 VSS VSS AP63 AW55 VSS VSS D48 K70 VSS VSS W9
AH13 VSS VSS AP68 AW57 VSS VSS D53 K71 VSS VSS Y17
AH6 VSS VSS AP70 AW6 VSS VSS D58 L11 VSS VSS Y19
AH63 VSS VSS AR11 AW60 VSS VSS D6 L16 VSS VSS Y20
AH64 VSS VSS AR15 AW62 VSS VSS D62 L17 VSS VSS Y21
AH67 VSS VSS AR16 AW64 VSS VSS D66
AJ15 VSS VSS AR20 AW66 VSS VSS D69
AJ18 VSS VSS AR23 AW8 VSS VSS E11
AJ20 VSS VSS AR28 AY66 VSS VSS E15
AJ4 AR35 B10 E18 SKYLAKE-U-GP
VSS VSS VSS VSS
AK11 VSS VSS AR42 B14 VSS VSS E21
AK16 VSS VSS AR43 B18 VSS VSS E46 071.SKYLA.000U
AK18 VSS VSS AR45 B22 VSS VSS E50
AK21 VSS VSS AR46 B30 VSS VSS E53
AK22 VSS VSS AR48 B34 VSS VSS E56 CPU BOM CTRL
AK27 VSS VSS AR5 B39 VSS VSS E6
AK63 VSS VSS AR50 B44 VSS VSS E65
AK68 VSS VSS AR52 B48 VSS VSS E71
AK69 VSS VSS AR53 B53 VSS VSS F1
AK8 VSS VSS AR55 B58 VSS VSS F13
AL2 VSS VSS AR58 B62 VSS VSS F2
B B
AL28 VSS VSS AR63 B66 VSS VSS F22
AL32 VSS VSS AR8 B71 VSS VSS F23
AL35 VSS VSS AT2 BA1 VSS VSS F27
AL38 VSS VSS AT20 BA10 VSS VSS F28
AL4 VSS VSS AT23 BA14 VSS VSS F32
AL45 VSS VSS AT28 BA18 VSS VSS F33
AL48 VSS VSS AT35 BA2 VSS VSS F35
AL52 VSS VSS AT4 BA23 VSS VSS F37
AL55 VSS VSS AT42 BA28 VSS VSS F38
AL58 VSS VSS AT56 BA32 VSS VSS F4
AL64 VSS VSS AT58 BA36 VSS VSS F40
F68 VSS VSS F42
BA45 VSS VSS BA41
SKYLAKE-U-GP

071.SKYLA.000U SKYLAKE-U-GP

CPU BOM CTRL 071.SKYLA.000U

CPU BOM CTRL

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(VSS)
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 23 of 102
5 4 3 2 1
 5 4 3 2 1

SSID = KBC MODEL ID

3D3V_AUX_KBC Model_ID_BOM Ctrl
PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

1
R2441 LV115 Intel skylake 100.0K 10.0K 64.10025.6DL 3.0V
10KR2F-2-GP
BOM Ctrl_Model LV114 Intel skylake 100.0K 20.0K 64.20025.L0L 2.75V

2
NA 100.0K 33.0K 64.33025.L0L 2.48V
MODEL_ID
NA 100.0K 47.0K 64.47025.6DL 2.24V

1
R2442 NA 100.0K 64.9K 64.64925.6DL 2.0V
100KR2F-L1-GP
NA 100.0K 76.8K 64.76825.6DL 1.87V

2
NA 100.0K 215.0K 64.21535.6DL 1.048V

3D3V_AUX_KBC 3D3V_AUX_S5

D R2479 D
Non PSL SPEC: ADT PWR Detection Function V1 3
1 2

0R5J-5-GP
1 R2493 2 VBAT 3D3V_AUX_KBC
PCB VERSION
0R0603-PAD

1
C2426 C2420 PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

SC2D2U10V3KX-L-GP

SCD1U16V2KX-L-GP
R2469 R2437
2D2R3-1-U-GP 64K9R2F-1-GP SA 100.0K 10.0K 3.0V

2
BOM Ctrl_VER
SB 100.0K 20.0K 2.75V
2

2
PCB_VER SC 100.0K 33.0K 2.48V
EC_AGND
NPCE285G

1
3D3V_AUX_KBC_VCC SD 100.0K 47.0K 2.24V
R2436
100KR2F-L1-GP -1 100.0K 64.9K 2.0V
U2403
KROW[0..7] 65
SE 100.0K 76.8K 1.87V

2
1

1
C2401 C2404 C2405 C2430 C2429 C2421 19 54 KROW0
VCC KBSIN0/GPIOA0/N2TCK
SC2D2U10V3KX-L-GP

SCD1U16V2KX-L-GP

SCD1U25V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP
DY 46 55 KROW1 Reserved 100.0K 100.0K 1.65V
VCC KBSIN1/GPIOA1/N2TMS KROW2
76 56
2

2
VCC KBSIN2/GPIOA2 KROW3
88 57
3D3V_S0 VCC KBSIN3/GPIOA3 KROW4
115 58
VCC KBSIN4/GPIOA4 KROW5
59
KBSIN5/GPIOA5 KROW6
102 60
AVCC KBSIN6/GPIOA6 KROW7
61
KBSIN7/GPIOA7 3D3V_AUX_KBC
4
R2481 VDD KCOL[0..17] 65
1 2 EC_VTT 12 53 KCOL0 45W_65W#
1D0V_S5 VTT KBSOUT0/GPOB0/SOUT_CR/JENK# DELTA Model:ADP65FD BB-PD03 ADP
0R0402-PAD
KBSOUT1/GPIOB1/TCK
52 KCOL1
High: 45W / Low 65W
1

1
C2402 C2428 C2427 1 DY2 SCD1U25V2KX-L-GP 51 KCOL2 R2407
EC_AGND KBSOUT2/GPIOB2/TMS ADP internal Resis 287ohm
1
SCD1U16V2KX-L-GP

SC2D2U10V3KX-L-GP

C2425
44 AD_IA 97
GPIO90/AD0 KBSOUT3/GPIOB3/TDI
50 KCOL3 DISCRETE#
SCD1U16V2KX-3GP PCB_VER 98 49 KCOL4 RN2405 750R2F-L-GP
3.3*287/1037=0.91V (65W)
2

GPIO91/AD1 KBSOUT4/GPOB4
ADT_TYPE 99 48 KCOL5 LPC_AD3_C1 1 8 LPC_AD3 High: UMA / Low: Discrete
2

MODEL_ID GPIO92/AD2 KBSOUT5/GPIOB5/TDO KCOL6 LPC_AD2_C1 LPC_AD2 LPC_AD3 18,68

100 47 2 7

2
GPIO93/AD3 KBSOUT6/GPIOB6/RDY# KCOL7 LPC_AD1_C1 LPC_AD1 LPC_AD2 18,68
17,31,79 PCH_WAKE# 108 43 3 6
NO_USE_07 GPIO05/AD4 KBSOUT7/GPIOB7 KCOL8 LPC_AD0_C1 LPC_AD0 LPC_AD1 18,68 ADT_TYPE R2499 1
96 42 4 5 2 AD_ID 43
NO_USE_08 GPIO04/AD5 KBSOUT8/GPIOC0 KCOL9 LPC_AD0 18,68 0R0402-PAD
95 41
VD_IN2 GPIO03/EXT_PURST#/AD6KBSOUT9/GPOC1/SDP_VIS# KCOL10
Thermal VD 26 VD_IN2 94
GPIO07/AD7/VD_IN2 KBSOUT10/P80_CLK/GPIOC2
40

1
39 KCOL11 SRN33J-4-GP
KBSOUT11/P80_DAT/GPIOC3 KCOL12 R2408
38
KBB_DEFINE1_R KBSOUT12/GPO64/TEST# KCOL13 100KR2F-L1-GP
101 37
KB_MATRIX_DEBUG GPIO94/DA0 KBSOUT13/GP(I)O63/TRIST# KCOL14
105 36 DY
FAN_REVERSE_CTRL# GPIO95/DA1 KBSOUT14/GP(I)O62/XORTR# KCOL15 LPC_FRAME#_C1 33R2J-2-GP R2498
26 FAN_REVERSE_CTRL# 106 35 1 2

2
GPIO96/DA2 KBSOUT15/GPIO61/XOR_OUT KCOL16 LPC_FRAME# 18,68
1 1D0V_S5
17,40 ALL_SYS_PWRGD 107
GPIO97/DA3 GPIO60/KBSOUT16/DSR1#
34
33 KCOL17
SA
AFTP2404 GPIO57/KBSOUT17/DCD1#
NOTE:
43,44 BAT_SCL 70 Please be aware that the SPI interface trace length between
GPIO17/SCL1/N2TCK LPC_AD0_C1
BATTERY / CHARGER ----> 43,44 BAT_SDA 69
GPIO22/SDA1/N2TMS LAD0/GPIOF1
126
PCH and EC should not exceed 6500mils,. The mismatch
67 127 LPC_AD1_C1 EMI
18,79 SML1_SMBCLK GPIO73/SCL2/N2TCK LAD1/GPIOF2 of SPI interface signals between EC and SPI flash should
68 128 LPC_AD2_C1 C2431
18,79 SML1_SMBDATA GPIO74/SDA2/N2TMS LAD2/GPIOF3
NO_USE_03 119
GPIO23/SCL3/N2TCK LAD3/GPIOF4
1 LPC_AD3_C1 1 2
DYSC220P50V2KX-3GP not exceed 500mils.
NO_USE_06 120 2 CLK_PCI_KBC_R 2 R2457 1
GPIO31/SDA3/N2TMS LCLK/GPIOF5 CLK_PCI_KBC 18
PROCHOT_EC 24 3 LPC_FRAME#_C1 0R0402-PAD
NO_USE_05 28
GPIO47/SCL4A/N2TCK LFRAME#/GPIOF6
7 PLT_RST#_EC 1 R2473 2
Prevent BIOS data loss solution
GPIO53/SDA4A/N2TMS LRESET#/GPIOF7 PLT_RST# 17,31,40,61,68,76
R2445 2 1 0R0402-PAD DGPU_PWROK_EC 26 0R0402-PAD
C 19,76,85 DGPU_PWROK GPIO51/TA3/N2TCK 3D3V_AUX_KBC C
STOP_CHG# 123
44 STOP_CHG# GPIO67/SOUT1/N2TMS
90 EC_SPI_CS#_C R2485 2 1 33R2J-2-GP
GPIOC6/F_CS0# SPI_CS0#_R 18,25
92 EC_SPI_CLK_C R2497 2 1 33R2J-2-GP NOTE: ECRST#
GPIOC7/F_SCK SPI_CLK_R 18,25

1
RTCRST_ON
TP----> 65 TPCLK 72
71
GPIO37/PSCLK1 GPIO30/F_WP#/RTS1#
109
80
RTCRST_ON 18 Locate resistors R2415 and R2417 close
65
1
TPDATA
AOU_IFLG# 10
GPIO35/PSDAT1 GPIO41/F_WP#/PSL_GPIO41
87 EC_SPI_DO_C
BAT_IN# 43
2 3
to the U2401. R2471
GPIO26/PSCLK2 GPIOC5/F_SDIO/F_SDIO0 SPI_SI0_R 18,25
TP2424 11 86 EC_SPI_DI_C RN2411 1 4 10KR2J-3-GP
GPIO27/PSDAT2 GPIOC4/F_SDI/F_SDIO1 SPI_SO_R 18,25

1
61 WLAN_PCIE_WAKE# DGPUHOT NUM_LED
25 91

E
79 DGPUHOT GPIO50/PSCLK3 GPIO81/F_WP#/F_SDIO2 NO_USE_13 NUM_LED 65 SRN33J-5-GP-U
20150724 Need check DGPUHOT 27 77 1 < ----06/26 LT41 USB_CHAR_SEL 1 R2489 2 R2495 C2424
55 BLON_OUT GPIO52/PSDAT3 GPIO00/32KCLKIN/F_SDIO3 TP2421 8 EC_SMI# 0R0402-PAD PURE_HW_SHUTDOWN# PURE_HW_SHUTDOWN#_B Q2401 SC1U10V2KX-L1-GP
1 2 B

2
26,40 PURE_HW_SHUTDOWN#
R2416 1 2 100KR2J-1-GP 3D3V_AUX_S5 10KR2J-3-GP MMBT3906-4-GP DY
26 FAN_TACH1 31 73 AC_IN_KBC# 1 R2433 2 R2486 84.T3906.A11

C
GPIO56/TA1 PSL_IN1#/GPI70 AC_IN# 44
117 93 KBC_PWRBTN_EC# 0R0402-PAD 1 2 ECSCI#_KBC
17 SIO_PWRBTN# CAP_LED GPIO20/TA2/IOX_DIN_DIO
PSL_IN2#/GPI06/EXT_PURST# EC_ENABLE# PSL 8 EC_SCI# DY 0R2J-2-GP
65 CAP_LED 63
GPIO14/TB1 PSL_OUT#/GPIO71
74 1
TP2418 PSL 1ST = 84.T3906.A11
17,40,51,52,54 SIO_SLP_S3# 64
WLAN_PCIE_WAKE# R2405 GPIO01/TB2
1 2 0R2J-2-GP PCH_WAKE# 2nd = 84.T3906.E11
29 ECSCI#_KBC
ECSCI#/GPIO54 ECRST# 3D3V_AUX_KBC
DY 64 DC_BATFULL
32
GPIO15/A_PWM EXT_RST#
85
27 KBC_BEEP
44 CHG_ON#
KBC_BEEP
CHG_ON#
118
62
GPIO21/B_PWM KBRST#/GPIO86
122
SIO_RCIN# 18 KBC PWR supply at PSL mode. U2402
GPIO13/C_PWM KBC_VSBY 0R0402-PAD 1
Modified 20151007 64 CHARGE_LED 65 75 2 R2494 3D3V_AUX_S5 1 DY
NO_USE_04 GPIO32/D_PWM VSBY KBC_VBKUP 0R0402-PAD 1 GND
22 114 2 R2488 RTC_AUX_S5 3
GPIO45/E_PWM/DTR1#_BOUT1 VBKUP VDD
Delete DS3 Relative Components TP2425 1 NO_USE_09 16
GPIO40/F_PWM/1_WIRE/RI1# VCORF
44 KBC_VCORF C2422 1 2 2
RESET#
26 FAN1_PWM 81 13 PECI R2474 1 2 SC1U10V2KX-L1-GP 74.03809.07B
GPIO66/G_PWM/PSL_GPIO66 PECI H_PECI 4
KBC_DPWROK 1 2 VD1_EN# 66 125 43R2J-GP < ---- Viber Del TPM
GPO33/H_PWM/VD1_EN# SERIRQ/GPIOF0 INT_SERIRQ 18
R2463 0R0402-PAD 6 < ---08/06 AD_OFF TPS3809K33-2-GP
VD_IN1 GPIO24 AD_OFF 43,44
26 VD_IN1 104 15
GPIO80/VD_IN1 GPIO36/TB3/CTS1#
1

PCH_RSMRST# 17
R2430 Thermal VD 26 VD_OUT1# VD_OUT1# 110 21 NOVO button Fun define: one key to recover OS.
GPIO82/IOX_LDSH/VD_OUT1 GPIO44/SCL4B SIO_SLP_S4# 17,40,51 3D3V_AUX_S5 3D3V_AUX_KBC
1KR2J-L2-GP VD_OUT2# 112 20 KBC_NOVO_BTN# < ---06/24 AOU_IFLG#
06/16 MAX R1717 DY
DY
26 VD_OUT2# GPIO84/IOX_SCLK/VD_OUT2 PSL_IN4#/GPI43
PSL_IN3#/GPI42
17
23
LID_CLOSE#
LID_CLOSE# 66
NOVO button wake KBC at PSL mode.
Nuvoton KBC PSL Power Switched Logic
2

GPIO46/SDA4B/CIRRXM ME_FWP_EC 19
84
17 SYS_PWROK GPIO77/SPI_MISO 3D3V_AUX_S5 C2406
83 113 USB_PWR_EN 36
17 AC_PRESENT WIRELESS_EN GPIO76/SPI_MOSI GPIO87/CIRRXM/SIN_CR
61 WIRELESS_EN 82
GPIO75/SPI_SCK GPIO34/SIN1/CIRRXL
14
S5_ENABLE 40
KBC_NOVO_BTN# KBC_PWRBTN_EC#
5V_EN
40,45 5V_EN
79
GPIO02/SPI_CS#
1
AFTP2403
1.Enter PSL mode (Entry S5 after 10sec) : 1 2

1
GND
5
PECI
Low Low 3D3V_AUX_KBC : OFF (KBC PWR supply) R2410
SCD1U16V2KX-L-GP
31 LAN_PWR_ON
PM_SUSWARN#_KBC
124
GPIO10/LPCPD# GND
18
330KR2J-L-GP
PSL
17,20 ME_SUS_PWR_ACK_R 1
R2402
2
0R2J-2-GP E51_TXD_KBC
121
GPIO85/GA20 GND
45 2.At PSL mode (SPEC: S5<10mW)
111
GPIO83/SOUT_CR GND
78 PSL

1
DY 9 89

S
55 PANEL_BLEN GPIO65/SMI# GND R2409 R2411
R2403 116 C2403 PSL mode(AC or DC): PSL
1 2 PM_CLKRUN#_EC 8
GND DY SC100P50V2JN-3GP KBC_PWRBTN_EC#:Low EC_ENABLE# 1 2 EC_ENABLE#_G_1 1 2 EC_ENABLE#_G G Q2402

2
18 PM_CLKRUN#_EC_R GPIO11/CLKRUN#
0R0402-PAD 1 R2472 2
G
30 103 R2472 close to Pin103 DMP2130L-7-GP
27 AMP_MUTE# GPIO55/CLKOUT/IOX_DIN_DIO AGND 0R0402-PAD (1) 4sec: PWR EC_ENABLE#_G S5_ENABLE 3D3V_AUX_KBC 1KR2F-3-GP 20KR2J-L3-GP D 84.02130.031
61 WLAN_PWRON R2404 1 AOAC 2 0R2J-2-GP NPCE285PA0DX-1-GP Button shut down PSL PSL 2nd = 84.00102.031

D
2013/9/12 Hi Low OFF
Reserved AOAC 071.00285.0A0G
EC_AGND
GPIO83/SOUT_CR & GPIO87/SIN_CR
(2) 8sec: KBC reset
Need reserved TP for Debug
6/18 U2403 Change Part Number to 71.00285.0A0G (285P)
PSL Wake(AC or DC): Q2403
NOTE: G
B PWM Signal : B
EC_ENABLE#_G S5_ENABLE 3D3V_AUX_KBC D S5_ENABLE
NOTE: 1. If unused, select altrnative GPIO function
Connect GND and AGND planes via either and enable internal pull-down. S PSL
0R resistor or one point layout connection. 2. Please measure and make sure that the Low Hi ON
Notice:ZZ.2N702.J3101

rise time of VCC_POR is less than 10us. 2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.2N702.W31

EC GPIO PH EC GPIO PL EC_GPIO47 High Active

3D3V_AUX_KBC
Q2405
3D3V_S5 R2450 PROCHOT_EC G
RN2403
AMP_MUTE# 1 2 10KR2J-3-GP R2478
2 3 BAT_SCL
DY D H_PROCHOT#_EC 1 2 H_PROCHOT# 4,46

1
1 4 BAT_SDA R2448
1 2 USB_PWR_EN S 0R0402-PAD
100KR2J-1-GP DY R2480 Notice:ZZ.2N702.J3101

SRN4K7J-8-GP R2452 KBB_DEFINE1_R 2 R2440

65 KBB_DEFINE1_R 1 10KR2J-3-GP 100KR2J-1-GP 2N7002K-2-GP
RN2407 1 2 WLAN_PCIE_WAKE# 84.2N702.J31

2
1 4 NO_USE_04 10KR2J-3-GP DGPUHOT 2 R2443 1 10KR2J-3-GP 2ND = 84.2N702.031
2 3 NO_USE_05 3rd = 84.2N702.W31
AD_OFF 1 R2476 2 1KR2J-1-GP
SRN4K7J-8-GP 3D3V_AUX_S5
R2435
DY
1 2 BAT_IN#
R2458 100KR2J-1-GP RN2404 RN2410
E51_TXD_KBC 2 1 E51_TXD 1 4 LID_CLOSE# CAP_LED 1 4
E51_TXD 61
0R0402-PAD R2434 2 3 KBC_NOVO_BTN# KBC_NOVO_BTN# 66 NUM_LED 2 3
2 1 ECRST#
R2451 10KR2J-3-GP SRN10KJ-5-GP SRN10KJ-5-GP
USB_PWR_EN E51_RXD RN2406 3D3V_AUX_S5
0R2J-2-GP
1 2 E51_RXD 61
S5_ENABLE KB_MATRIX_DEBUG 2 R2444
DY
1 4 1 10KR2J-3-GP
DY 2 3 5V_EN 3D3V_S0

1
SRN10KJ-5-GP
RN2408 R2477
1 4 NO_USE_03 R2447 2 1 FAN_REVERSE_CTRL# 10KR2J-3-GP
2 3 NO_USE_06 100KR2J-4-GP
DY DY

2
SRN10KJ-5-GP R2484
1 2 KBC_PWRBTN_EC#
65,66 KBC_PWRBTN#
RN2409 470R2J-2-GP
1 4 NO_USE_07

1
2 3 NO_USE_08

1
DY R2492 C2423
SRN10KJ-5-GP 100KR2J-1-GP SC220P50V2KX-3GP
R2438
DY

2
2 1 KBB_DEFINE1_R

2
10KR2J-3-GP
R2439 DY KB_MATRIX_DEBUG
2 1
10KR2J-3-GP
A A
R2446
DY FAN_REVERSE_CTRL#
2 1
100KR2J-4-GP

Nuvoton KBC PSL Logic

KBB_DEFINE1_R use MODEL_ID to Define Lenovo Key:

LV115: "Fast Forward" Key <Core Design>
LV114: "Delete" Key
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

NPCE285
Size Document Number Rev
A1
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 24 of 102
5 4 3 2 1
 5 4 3 2 1

3D3V_SPI
3D3V_S5
R2501

0R0402-PAD
1 2
SSID = Flash.ROM SPI ROM Equal length need to less than 500mil

1
C2501 C2502
SC10U6D3V3MX-L-GP SCD1U16V2KX-L-GP
DY Test point

2
U2502
3D3V_SPI
1ST GIGA DEVICE 8MB 072.25B64.0C01
2ND WINBOND 8MB 72.25Q64.Q01 3D3V_S5 1 TP2503

D 3RD TPAD14-OP-GP D

1
DY
R2505 R2506
4K7R2J-2-GP 10KR2J-3-GP

2
3D3V_SPI
U2502
R2502
18,24 SPI_CS0#_R 2 1 SPI_CS0# 1 8
RN2501 2 0R0402-PAD SPI_SO CS# VCC SPI_HOLD_0#_1 R2551
18,24 SPI_SO_R 3 2 7 1 2 33R2J-2-GP SPI_HOLD_0# 18
SPI0_WP#_1 SO IO3 SPI_CLK_R_1 R2552
18 SPI0_WP# 1 4 3 6 1 2 33R2J-2-GP SPI_CLK_R 18,24
IO2 SCLK SPI_SI0_R_1 R2553
4 5 1 2 33R2J-2-GP SPI_SI0_R 18,24
SRN33J-5-GP-U VSS SI

1
C2503

1
SC4D7P50V2CN-1GP GD25B64CSIGR-GP C2504 C2505

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP
DY DY DY

2
072.25B64.0C01

2
1ST = 072.25B64.0C01

2ND = 72.25Q64.Q01

C C

B B

SSID = RBATT

SSID = RBATT
High Detect
3D3V_AUX_S5 Need to Check whether to PD in PCH Side
RTC_AUX_S5 Q2501
Q2503
2
+RTC_VCC DMN5L06K-7-GP
3 RTC1
R2504 RTC_PWR D S RTC_DET 1 R2514 2
RTC_PWR RTC_DET_R 20
1 1 2 1 0R0402-PAD
1

1KR2J-1-GP PWR
C2506
2
GND 84.05067.031
BAS40CW-GP NP1

1
SC1U10V2KX-L1-GP NP1
83.00040.E81 NP2 2nd = 084.00138.0A31
2

NP2 5V_S0 R2508

A 6D2MR2J-GP A

Width=20mils
BAT-060003HA002M213ZL-GP-U1

2
62.70014.001
<Core Design>
1ST = 62.70014.001
Test point 2ND = 62.70001.061
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1 +RTC_VCC Taipei Hsien 221, Taiwan, R.O.C.
AFTP2501
1 Title
AFTP2502
Flash(KBC+PCH)/RTC
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 25 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = Thermal Sensor

*Layout* 15 mil
5V_FAN_S0

1
D2601 C2604 C2605

SC4D7U25V5KX-L2-GP
RB551V30-GP SCD1U16V2KX-L-GP
83.R5003.H8H

2
A
2nd = 83.R5003.T8F
D D

07/31 C2604 Change part number 78.47523.5BL to 78.47522.L4L,

值原4.uF, 0805, 不不不不25V
FAN1
7
24 FAN_REVERSE_CTRL# 1

24 FAN1_PWM 2
FAN_TACH1_C 3
4
5 1 FAN_REVERSE_CTRL#
5V_FAN_S0
6 AFTP2605 1 FAN1_PWM
AFTP2601 1 FAN_TACH1_C
AFTP2602 1 5V_FAN_S0
3D3V_S0 5V_FAN_S0 AFTP2603 1 5V_S0 5V_FAN_S0
ACES-CON5-22-GP-U AFTP2604
20.F1639.005

1
1ST = 20.F1639.005 R2630
R2614 R2613 1 2
10KR2J-L-GP DY 10KR2J-L-GP 2ND = 020.F0146.0005 0R0603-PAD

2
D2602
2.System Sensor, Put on palm rest A K FAN_TACH1_C
24 FAN_TACH1

Close to Thermal sensor RB551V30-GP

3D3V_AUX_KBC
TBD PU 3D3V_AUX_KBC Note: Need R1717 PD: Enable Thermal VD Fun.
83.R5003.H8H
2nd = 83.R5003.T8F DY
Note: (1) VD_IN1 for System sensor R2618
1
06/11 Delete R2611 & R2621 Connect to 3D3V_AUX_S5

1 2 3D3V_S0 3D3V_S0
R2615
16KR2F-GP
(2) VD_IN2 for CPU sensor
C TV 0R2J-L-GP C

1
R2617 R2624 R2625
Close to CPU chips
2

3D3V_S0 1 2 DY 2KR2F-3-GP DY 2KR2F-3-GP

0R0402-PAD

2
1
VD_IN1 24
R2607
1

2KR2F-3-GP D2603
R2610
1

TV NTC-100K-11-GP-U C2615 C2616 2

2
VD_OUT1# 24
SCD1U16V2KX-L-GP SC100P50V2JN-3GP Q2603
69.60013.201 TV TV
Notice:ZZ.2N702.J3101
S THERM_SYS_SHDN# 3 DY
2

D 1
2

VD_IN1_C 24,40 PURE_HW_SHUTDOWN# VD_OUT2# 24

1 R2612 2
0R0402-PAD G BAW56-5-GP
VR_RDY 40,46

1
TBD PU 3D3V_AUX_KBC

1
R2606 C2607 2N7002K-2-GP 83.00056.Q11

SC4D7U6D3V3KX-GP
3D3V_AUX_KBC 10KR2J-L-GP 84.2N702.J31
DY
DY 2ND = 84.2N702.031 1ST = 83.00056.Q11

2
3rd = 84.2N702.W31

2
2ND = 75.00056.07D
1

R2616
16KR2F-GP
TV
Close to KBC chips
2

VD_IN2 24
1

R2619
1

NTC-100K-11-GP-U C2617 C2618

TV SCD1U16V2KX-L-GP SC100P50V2JN-3GP
69.60013.201 TV TV
2

2
2

VD_IN2_C 1 R2620 2
B 0R0402-PAD T8=85 degree B

Thermal config
Function
Thermal VD NCT7718W
LOCATION
U2601 DY ASM
Q2601 DY ASM
Q2602 DY ASM
RN2601 DY ASM
R2601 DY ASM
R2605 DY ASM
C2601 DY ASM
C2602 DY ASM
C2603 DY ASM

R2610 ASM DY
R2619 ASM DY
R2615 ASM DY
R2616 ASM DY
A R2612 ASM DY A

R2620 ASM DY
R2624 ASM DY
R2625 ASM DY <Core Design>
C2615 ASM DY
C2617 ASM DY Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
C2616 ASM DY Taipei Hsien 221, Taiwan, R.O.C.

C2618 ASM DY Title

D2603 ASM DY THERMAL NCT7718W/Fan

R1717 ASM DY Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 26 of 102
5 4 3 2 1
 5 4 3 2 1

5V_S0 AUD_5VD
Current > 2A
1 R2703 2
1

1
0R0603-PAD C2706 C2716 SCD1U25V2KX-L-GP SCD1U25V2KX-L-GP
C2705
C2707 C2708
SC1U10V2KX-L1-GP

DY
2

2
SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP
D D

MOAT
5V_S0 AUD_5VA

1 R2726 2
1

0R0603-PAD C2727
SC10U6D3V3MX-L-GP
2

AUD_3VD

ALC_AGND

1
SCD1U25V2KX-L-GP R2702 1 2 0R0402-PAD
C2701
C2702

SC1U10V2KX-L1-GP
C2704 1 2 SCD1U25V2KX-L-GP
MOAT

2
3D3V_S5 AUD_3V3_S5 Place close to pin1 Place close to pin8
1 R2705 2
1

0R0603-PAD C2712
SC10U6D3V3MX-L-GP AUD_5VA
2

1
ALC_AGND SCD1U25V2KX-L-GP
C2709 C2714
SC2D2U10V3KX-L-GP

2
3D3V_S0 AUD_3VD
Place close to pin26
1 R2701 2
ALC_AGND
1

0R0603-PAD C2703
SC10U6D3V3MX-L-GP
AUD_1D8VD
2

MOAT

1
C C
1D8V_S0 AUD_1D8VD C2711
SC4D7U6D3V3KX-L-GP

2
1 R2704 2
RING2/SLEEVE Trace width must > 40mils
1

0R0603-PAD C2710 ALC_AGND U2701

SC10U6D3V3MX-L-GP RN2701
1 11 AUDIO_PC_BEEP C2723 1 2 AUDIO_BEEP 1 4
2

AUD_3V3_S5 DVDD PCBEEP SPKR 19

SCD1U25V2KX-L-GP 2 3 KBC_BEEP 24
DVDD_IO 8 13
DVDD-IO MIC2-L(PORT-F-L)/RING2 RING2 66
ALC_AGND 14 SLEEVE 66

1
MIC2-R(PORT-F-R)/SLEEVE MIC2 C2724 1
20 15 2 SC4D7U6D3V3KX-L-GP SRN10KJ-5-GP
AUD_5VD AVDD1 MIC2-CAP R2709
33
AVDD2
17 2K2R2J-L1-GP
LINE1-R(PORT-C-R)
16 18
VD33STB LINE1-L(PORT-C-L) ALC_AGND

2
34 35 AUD_SPK_L+ 29
AUD_1D8VD PVDD1 SPK-OUT-LP
39 36 AUD_SPK_L- 29
PVDD2 SPK-OUT-LN SPK 4Ω 40mils
29 38
MOAT 20151024 modify CPVDD SPK-OUT-RP
37
AUD_SPK_R+
AUD_SPK_R-
29
29
1

C2715 1 VREF SPK-OUT-RN

2 SC1U10V2KX-L1-GP 22 RN2702
C2713 C2717 1 CPVEE VREF HP_OUT_L_AUD
2 SC1U10V2KX-L1-GP 27 25 1 4 HP_OUT_L 66
ALC_AGND
SC4D7U6D3V3KX-L-GP R2720 1 DY CPVEE HPOUT-L(PORT-I-L) HP_OUT_R_AUD
2 100KR2J-1-GP 26 2 3 HP_OUT_R 66
2

C2718 1 LDO1_CAP HPOUT-R(PORT-I-R)

2 SC4D7U6D3V3KX-L-GP 21
ALC_AGND C2719 1 LDO2_CAP LDO1-CAP
2 SC4D7U6D3V3KX-L-GP 32 SRN47J-7-GP
C2720 1 LDO3_CAP LDO2-CAP
2 SC4D7U6D3V3KX-L-GP 6
LDO3-CAP AUD_CBN
1 R2719 2 Tied at one point only under 28 C2725 1 2 SC1U10V2KX-L1-GP
ALC_AGND CBN AUD_CBP
Codec or near the Codec 30
0R0603-PAD C2726 1 DMIC_DATA_C CBP
2 SC22P50V2JN-L-GP 2
C2721 1 DMIC_CLK_C GPIO0/DMIC-DATA12 SLEEVE
2 SC22P50V2JN-L-GP 3 R2715 R2716 1 2 2KR2F-3-GP
GPIO1/DMIC-CLK MIC2V MIC2_VREFO R2717 RING2
23 1 2 1 2 2KR2F-3-GP
MIC2-VREFO
19 HDA_CODEC_SDOUT 4 24
R2710 AC97_DATIN SDATA-OUT LINE1-VREFO-L 0R0402-PAD
19 HDA_SDIN0 1 2 7
0R0402-PAD SDATA-IN
R2713 1 2 0R0402-PAD HDA_CODEC_BITCLK_C 5
19 HDA_CODEC_BITCLK BCLK
G2701 1 2 GAP-CLOSE 1 2 9 19
SYNC AVSS1
Near AVDD1 and AVDD2 power source input C2722 SC22P50V2JN-L-GP 10 31
G2702 AUD_SD# DC_DET AVSS2
1 2 GAP-CLOSE 40
PDB
12 41
HP/LINE1-JD(JD1) GND
B 19 HDA_CODEC_SYNC B
ALC_AGND ALC_AGND
ALC3240-VA3-CG-GP
ERN2701
1 4 DMIC_DATA_C
55 DMIC_DATA 071.03240.0A03
0R3J-0-U-GP DMIC_CLK_C
ER2722 1 DY 2
SA_ESD 55 DMIC_CLK 2 3

0R3J-0-U-GP SRN22-3-GP
ER2721 1 DY AUD_3VD
2 ERN2701 SET 22 ohm in SA
R2708 1 2 100KR2J-L-GP
EC2701 1 2 SCD1U25V2KX-L-GP R2721 1 2 200KR2F-L-3-GP ALC233_SENSE_A
DY 66 HP_DET#
EC2702 1 2 SCD1U25V2KX-L-GP DY R2708 power should follow DVDD (pin1) power rail.
EC2703 1 2 SCD1U25V2KX-L-GP DY If DVDD=3.3V, R7 power source should be change to 3.3V
EC2704 1 2 SCD1U25V2KX-L-GP DY

ALC_AGND

3D3V_S5

Q2701
1 6

2 5 3D3V_S0

AUD_PD#_1 3 4 HDA_CODEC_RST#
1

DMN5L06DWK-7-GP R2722
DY 1KR2J-1-GP
D2701 DY
R2724 1 2 0R2J-2-GP DY AUD_PD#_2 2
24 AMP_MUTE#
2

A A
AUD_SD#
DY 3

19 HDA_CODEC_RST# R2723 1 2 0R2J-2-GP DY AUD_PD#_1 1

R2725 1 2 22R2J-2-GP BAW56-5-GP

<Core Design>
83.00056.Q11
FAE
HDA_RST#_CODEC:
1ST = 83.00056.Q11 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
High=1.8V 2ND = 75.00056.07D Taipei Hsien 221, Taiwan, R.O.C.
Low=0V
this signal might cause AUD_SD# always low when R2710=0ohm Title
You should add level shift on HDA_RST#_CODEC signal when Codec PIN9 DVDDIO= 1.5V.
Audio Codec ALC3234
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 27 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A1
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 28 of 102
5 4 3 2 1
 5 4 3 2 1

INTERNAL STEREO SPEAKERS

D D

RIGHT SIDE
R2903 1 2 0R0603-PAD AUD_SPK_R+_C
27 AUD_SPK_R+
R2904 1 2 0R0603-PAD AUD_SPK_R-_C
27 AUD_SPK_R-

1
Place these EMI components C2902 C2903
close to speaker connector. DY DY

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
SPK1

2
5

Only needed if speaker 1

connector is physically far from
2
audio codec. When in doubt, it's 3
always a good idea to have 4
population option.
LEFT SIDE 6

ACES-CON4-17-GP-U1 1 R2907 2
20.F1621.004 0R0402-PAD
R2905 1 2 0R0603-PAD AUD_SPK_L+_C
27 AUD_SPK_L+
2nd = 20.F1937.004 1 R2908 2
R2906 1 2 0R0603-PAD AUD_SPK_L-_C 0R0402-PAD
C
27 AUD_SPK_L- C
3rd = 020.F0243.0004 R2909 1 DY 2 0R2J-2-GP
1

C2904 C2905 R2910 2 0R2J-2-GP

1 DY
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

08/12 SPK1 20.F2348.007 Change to 20.F1621.004

2

06/12 SPK1 原原原4Pin, 換7 pin 接 Hall Sensor 訊訊

ALC_AGND

1 AUD_SPK_L+_C 1 AUD_SPK_R+_C
AFTP2910 1 AUD_SPK_L-_C AFTP2908 1 AUD_SPK_R-_C
AFTP2911 AFTP2909
1
AFTP2912
1

1
ED2901 ED2902 ED2904 ED2903
Only needed if speaker
ESD5B5D0ST1G-GP-U

ESD5B5D0ST1G-GP-U

ESD5B5D0ST1G-GP-U

ESD5B5D0ST1G-GP-U
connector is physically far from
Place these EMI components audio codec. When in doubt, it's DY DY DY DY
B close to speaker connector. always a good idea to have B
population option.
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio IO
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 29 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = Audio

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 30 of 102
5 4 3 2 1
 5 4 3 2 1

REGOUT R3103 1 2 0R0805-PAD VDD10

C3138 close to Pin3 , C3139 close to Pin8
3D3V_LAN_S5 C3140 close to Pin30,C3136 close to Pin22

1
C3140 C3138 C3139 C3137 C3136 C3141

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SC1U10V2KX-L1-GP
R3102 1 DY 2 0R3J-0-U-GP C3142
SCD1U16V2KX-3GP

2
3D3V_S5 Q3101 DY
AO3413L-GP
S D Need check whether change to R3101

1
1

1
C3152 C3150
For RTL8111G(S) Series/ RTL8111GUS Series/ RTL8111H(S) Series/

G
C3154 C3153 R3131 SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP
SCD1U16V2KX-3GP SCD1U16V2KX-3GP 100KR2J-1-GP 84.03413.B31 RTL8106EUS Series/ RTL8107E(S) Series/ RTL8118AS Series
2

2
DY For RTL8111G(S)/ RTL8111GUS/ RTL8106EUS

2
D
*Place C3138 to C3141 close to each VDD10 pin-- 3, 8, 22, 30 C3132,C3133 close to Pin22 D

LAN_PWR_ON_T 1 2 LAN_PWR_ON_T2
For RTL8111G(S)/ RTL8111GUS/ RTL8106EUS

1
R3132 *Place C20 and C21 close to each VDD10 pin-- 22 (Reserved) VDD10
Q3102 1KR2J-1-GP C3151
24 LAN_PWR_ON G SC1U10V2KX-L1-GP

2
DY

1
D C3130 C3131
For RTL8106E Series

SCD1U16V2KX-L-GP

SC1U10V2KX-L1-GP
S
C3130,C3131 close to Pin30

2
Notice:ZZ.2N702.J3101

2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.2N702.W31 08/12 add 3D3V_S5 to 3D3V_LAN_S5 Circuit

U3101

VDD10 3 12
AVDD10 CLKREQ# CLKREQ_PCIE#2 18
8 21 PCIE_LAN_WAKE#_R 1 R3130 2
AVDD10 LANWAKE# PCH_WAKE# 17,24,79
30 20 ISOLATE# 0R0402-PAD R3108 1 2 1KR2J-1-GP
AVDD10 ISOLATE# 3D3V_S0
19 PLT_RST#
PERST# PLT_RST# 17,24,40,61,68,76
3D3V_LAN_S5 32
AVDD33 LAN_XTAL1 R3111 1
11 28 2 15KR2J-1-GP
AVDD33 CKXTAL1 LAN_XTAL2
29
1

1
C3147 C3143 C3144 C3145 C3146 CKXTAL2
3D3V_LAN_S5 23
VDDREG
SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SC4D7U6D3V3KX-L-GP

SC4D7U6D3V3KX-L-GP

DY DY REFCLK_N
16 PEG_CLK2_CPU# 18
22 15
2

2
DVDD10 REFCLK_P PEG_CLK2_CPU 18
R3113
31 RSET 1 2 2K49R2F-GP
RSET
32 MDI0+ 1
MDIP0 REGOUT
32 MDI0- 2 24
MDIN0 REGOUT
32 MDI1+ 4
MDIP1
5
32
32
MDI1-
MDI2+ 6
MDIN1
MDIP2 HSIN
14 PCIE_TX_CON_N6 16
For RTL8111G(S) Series/ RTL8111GUS Series/ RTL8111H(S) Series/
7 13
C
32
32
MDI2-
MDI3+ 9
MDIN2
MDIP3
HSIP PCIE_TX_CON_P6 16 RTL8106EUS Series/ RTL8107E(S) Series/ RTL8118AS Series C
10 18 PCIE_RXN4_L C3117 1 2 SCD1U16V2KX-L-GP
32 MDI3- PCIE_RX_CPU_N6 16
MDIN3 HSON
HSOP
17 PCIE_RXP4_L C3116 1 2 SCD1U16V2KX-L-GP PCIE_RX_CPU_P6 16 C3132,C3133 close to Pin22
27
C3147 close to Pin23 32 MB_LAN_ACT#
26
LED0
LED1/GPO
25 33
C3143 close to Pin32 32 MB_LAN_LINKUP# LED2 GND VDD10

C3144 close to Pin11 RTL8111GUS-CG-GP-U2

1
C3133 C3132
71.08111.W03 BOM CHANGE TO RTL8111H:SC50H01259

SCD1U16V2KX-L-GP

SC1U10V2KX-L1-GP
2

2
25MHz XTAL LAN_BOM_CTRL

C3109
1 2

X3101 SC15P50V2JN-L-GP

LAN_XTAL1 1 4
LAN and Transformer Config:
1

R3114
1MR2J-L3-GP C3108
DY 2 3 1 2
LAN/Transformer
2

LAN_XTAL2 SC15P50V2JN-L-GP

XTAL-25MHZ-181-GP

82.30020.G71
B 2nd = 82.30020.D41 B

Crystal 27MHz
MAIN HASONIC 82.30020.G71 78.15034.L1L
2ND HARMONY 82.30020.D41 78.18034.1FL

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LAN_RTL8111
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 31 of 102
5 4 3 2 1
 5 4 3 2 1

10/100M/1000M Lan Transformer 10/100/1000 LAN surge circuit

For test stuff
XF3201
Change LAN CONN 20151007 LAN Connector
1 12 RJ45_6
31 MDI1- RD+ RX+ RJ45_3
31 MDI1+ 2 11
XRF_TDC_1 RD- RX- MCT4
3 10
RDCT RXCT MCT4 RJ45
4 9
1

C3204 TDCT TXCT RJ45_2 R3220 MB_LAN_ACT#_R

31 MDI0- 5 8 2 1 330R2J-3-GP B2
SCD1U16V2KX-L-GP TD+ TX+ RJ45_1 31 MB_LAN_ACT# R3223 MB_LAN_ACT_PWR B2
31 MDI0+ 6 7 3D3V_LAN_S5 1 2 0R0402-PAD B1 AMBER
TD- TX- B1
2

D
XFORM-208-GP
1ST = 68.HD081.30B RJ45_1
9
CHASSIS#9 D
1
MDO0+
2ND = 68.68167.30D RJ45_2
68.68161.30A RJ45_3
2
MDO0- 1ST = 022.10001.00B1
3
RJ45_4 MDO1+
XF3202 RJ45_5
4
MDO2+ 2ND = 022.10001.00U1
5
RJ45_6 MDO2-
RJ45_4 RJ45_7
6
MDO1- 3RD = 022.10001.00Z1
31 MDI2+ 1 12 7
RD+ RX+ RJ45_5 RJ45_8 MDO3+
31 MDI2- 2 11 8
RD- RX- MCT4 MDO3-
3 10 10
RDCT RXCT MCT4 CHASSIS#10
4 9
TDCT TXCT RJ45_7 R3222 MB_LAN_LINKUP#_R
31 MDI3+ 5 8 2 1 330R2J-3-GP A2
TD+ TX+ RJ45_8 31 MB_LAN_LINKUP# R3224 MB_LAN_LINKUP_PWR A2 Green
31 MDI3- 6 7 3D3V_LAN_S5 1 2 0R0402-PAD A1
1

TD- TX- A1 RJ45

C3202 RJ45-12P-64-GP-U
SCD1U25V2KX-L-GP XFORM-208-GP 022.10001.00B1
2

DY
68.68161.30A 1ST = 68.HD081.30B
LAN GIGA 2ND = 68.68167.30D
RJ45_1 1
RJ45_2 ED3202
1 AFTP3202
RJ45_3 1 AFTP3203
RJ45_4 AFTP3204 MCT4 R3214 MCT4_C
1 2 1 1 2
RJ45_5 1 AFTP3205 75R5F-1-GP
RJ45_6 1 AFTP3206
RJ45_7 1 AFTP3207
RJ45_8 AFTP3208 THW4006KV-SMB-GP
1

2
AFTP3209 069.A0002.0001
1ST = 069.A0002.0001 C3203
RJ45 Pin define SC100P3KV8JN-2-GP

1
2ND = 069.A0007.0001
3rd = 069.A0007.0011
10/6 Change ED3202 1st & 3rd source

C C

3D3V_S0
3D3V_S0

ED3203 ED3204

MDI0+ 6 1 MDI1+ MDI2+ 6 1 MDI3+

31 MDI0+ I/O4 I/O1 MDI1+ 31 31 MDI2+ I/O4 I/O1 MDI3+ 31
5 2 5 2
VDD GND VDD GND
MDI0- 4 3 MDI1- MDI2- 4 3 MDI3-
31 MDI0- I/O3 I/O2 MDI1- 31 31 MDI2- I/O3 I/O2 MDI3- 31

AZC099-04S-2-GP AZC099-04S-2-GP

075.09904.0A7C 075.09904.0A7C
DY DY

8/25 將ED3203,ED3204 屬屬ESD STUFF OPTION 改改DY, 上上上上上Wake on Lan

10/13 ED3203,ED3204 改改跟ED3501一

一一, 增加增增Source
10/23 將3rd Source將
將將 75.09904.07C, 因原因有因因50米
米米此米不米(Part number跟
跟ED3501一
一一,BOM別
別別別)
改 DY,不
10/23 ED3203, ED3204 ESD STUFF OPTION改 不上上

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RJ45&Transformer
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 32 of 102
5 4 3 2 1
 5 4 3 2 1

Card Reader RTS5170

R3320
6K2R2F-GP
2 1
1 R3327 2 0R0402-PAD USB_SD_DP

USB_SD_DM
16 USB_CPU_PP8

USB_SD_DP
1 R3328 2 0R0402-PAD USB_SD_DM

RREF
16 USB_CPU_PN8

SD_CLK_L and CARD_CTRL0 trace length shorter , surround with GND.

U3301

25

17

3
2
RTS5170-GR-GP +3.3V_RUN_CARD

GPIO0

DP
GND

RREF

DM
D D
OPEN TYPE SD Socket
22 14
SD_DATA2 SP14 SP7 SD_CD#
21 13

SC4D7U6D3V3KX-GP
SD_DATA3 SP13 SP6
20 12

SCD1U16V2KX-3GP
SP12 SP5 SD_DATA0 C3307 C3308
19 11

1
SD_CMD SP11 SP4 SD_DATA1
18 10
SP10 SP3
16 9

CARD_3V3
SD_CLK SP9 SP2 SD_WP
15 8

2
XD_CD#
SP8 SP1

SDREG
SD1

3V3_IN
XD_D7

V18
4 NP1
VDD NP1
NP2
NP2
SD_CLK trace length shorter , 71.05170.003

7
23

24
surround with GND. SD_CMD_L 2
SD_CLK_L CMD
5 12

+3.3V_RUN_CARD
SD_CD#_L CLK 12
10 13
VDD18 SD_WP_L CD 13
1 2 11 14

SDRGE
WP 14
15
C3302 SC1U10V2KX-1GP 3D3V_S0 SD_DATA0_L 15
7
C3301 SD_DATA1_L DAT0
8
3D3V_S0_CARD_VIN R3317 SD_DATA2_L DAT1
2 1 1 2 0R0603-PAD 9 3
SD_DATA3_L DAT2 VSS
1 6
SC1U10V2KX-1GP CD/DAT3 VSS

SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
1

1
C3305 C3306 CARDBUS11P-SKT-11-GP

020.I0004.0001

2
1ST = 020.I0004.0001
SD_CLK_L and CARD_CTRL0 trace length shorter , surround with GND.
2ND = 020.I0003.0001
20151013 move R3317,Delete C3303/C3304
3RD = 020.I0002.0001

C C

SD_WP_L 1 R3323 2 0R0402-PAD SD_WP

SD_DATA1_L 1 R3324 2 0R0402-PAD SD_DATA1

SD_CMD_L R3302 1 2 0R0402-PAD SD_CMD

SD_CLK_L R3301 1 2 0R0402-PAD SD_CLK

SD_DATA0_L 1 R3321 2 0R0402-PAD SD_DATA0

SD_CD#_L 1 R3322 2 0R0402-PAD SD_CD#

SD_DATA2_L 1 R3325 2 0R0402-PAD SD_DATA2

SD_DATA3_L 1 R3326 2 0R0402-PAD SD_DATA3

EC3313 EC3315 EC3314 EC3312 EC3311

1

DY DY DY DY DY
SC15P50V2JN-L-GP

SC15P50V2JN-L-GP

SC15P50V2JN-L-GP

SC15P50V2JN-L-GP

SC15P50V2JN-L-GP
2

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 33 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB Charger
Size Document Number Rev
Custom
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 34 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 35 of 102
5 4 3 2 1
 5 4 3 2 1

5V_S5
USB3.0 Port1 5V_USB1_S3 5V_USB1_S3
U3601
Support 2A AFTP3606
at least 80 mil 5V_USB1_S3
at least 80 mil AFTP3610
5 1 1
R3613 IN OUT USB31
2

1
1

1
GND
C3605 1 2 USB_PWR_EN_D1 4 3 USB30_OC#0_D 1 R3615 2 USB_OC0# 16

1
24 USB_PWR_EN EN OC#
SCD1U16V2KX-L-GP

C3630 C3612 C3625 1 10 AFTP3608 1

VBUS CHASSIS#10

SC10U10V5KX-L1-GP

SC1U10V2KX-L1-GP
SC10U6D3V3MX-L-GP 0R0402-PAD 0R0402-PAD DY DY 11
2

G524B1T11U-GP USB_PN0_TVS CHASSIS#11

2 12

1
D- CHASSIS#12
074.00524.0B9F TC3603 USB_PP0_TVS 3
D+ CHASSIS#13
13
SE220U6D3VM-30-GP C3626
2ND = 74.06288.07F 77.52271.09L SCD1U16V2KX-L-GP

2
USB3_1_RX1_N_R 5
USB3_1_RX1_P_R SSRX-
D 2ND = 77.92271.03L 6
SSRX+ D
4
USB3_1_TX1_N_R PGND
DY USB3_1_TX1_P_R
8
SSTX-
9 7
SSTX+ GND
AFTP3607 USB3.0
1
20151012 Modify TC3603 PN AFTP3609 1 SKT-USB13-206-GP
C3629
16 USB30_TX_CPU_P1 1 2 USB3_1_TX1_P_1 R3617 1 2 USB3_1_TX1_P_R
SCD1U16V2KX-L-GP 0R0402-PAD 022.10005.00P1

1ST = 022.10005.00P1
2ND = 022.10005.00Z1
3RD = 022.10005.01B1
EMI Request ED3602
5V_USB1_S3
ED3601 USB_PN0_TVS 1 6 USB_PN0_TVS

C3628 USB3_1_TX1_P_R 1 10 USB3_1_TX1_P_R

1 2 USB3_1_TX1_N_1 R3610 1 2 USB3_1_TX1_N_R 2 5
16 USB30_TX_CPU_N1 USB3_1_TX1_N_R USB3_1_TX1_N_R
SCD1U16V2KX-L-GP 0R0402-PAD 2 9
3 8

USB3_1_RX1_P_R 4 7 USB3_1_RX1_P_R
USB_PP0_TVS 3 4 USB_PP0_TVS
USB3_1_RX1_N_R 5 6 USB3_1_RX1_N_R

L12ESDL5V0C6-4C-GP
L05ESDL5V0NA-4-GP
075.01256.007C
075.00550.0071
2ND = 75.01043.073 2ND = 075.09904.0A7C
R3611 1 2 USB3_1_RX1_P_R EMI TEST EMI TEST
16 USB30_RX_CPU_P1
0R0402-PAD

TR3603
3 4 USB_PP0_TVS
16 USB_CPU_PP0
C 2 1 USB_PN0_TVS C
16 USB_CPU_PN0
FILTER-4P-137-GP-U

68.01012.20B
1ST = 68.01012.20B
16 USB30_RX_CPU_N1 R3616 1 2 USB3_1_RX1_N_R 2ND = 68.00396.001
0R0402-PAD
EMI TEST

USB2.0 Port2 5V_USB1_S3

5V_USB2_S3

20151012 ADD Circuit to support USB3.0 R3620 1 2 0R0805-PAD AFTP3601

5V_USB2_S3

5V_S5 R3621 2 0R0805-PAD 5V_USB2_S3 USB32

1 Support 2A

1
at least 80 mil U3602
at least 80 mil 1 10
VBUS CHASSIS#10
5 1 11
R3607 IN OUT AFTP3602 USB_PN1_TVS CHASSIS#11
2 1 2 12
1

1
GND D- CHASSIS#12
C3604 1 2 USB_PWR_EN_D2 4 3 USB20_OC#1_D 1 R3609 2 USB_OC1# 16 AFTP3603 1 USB_PP1_TVS 3 13

1
24 USB_PWR_EN EN OC# D+ CHASSIS#13
SCD1U16V2KX-L-GP

DY C3622 C3611 C3617 TC3602 C3652 C3618

SC1U10V2KX-L1-GP

SC22U6D3V5MX-L3-GP
SC10U6D3V3MX-L-GP 0R0402-PAD 0R0402-PAD ST150U6D3VDM-28-GP SCD1U16V2KX-L-GP
2

2
SC22U6D3V5MX-L3-GP
DY G524B1T11U-GP DY 077.51571.0001 USB3_2_RX2_N_R 5

2
SSRX-
074.00524.0B9F USB3_2_RX2_P_R 6
SSRX+
AFTP3605 1
4
USB3_2_TX2_N_R PGND
2ND = 74.06288.07F USB3_2_TX2_P_R
8
SSTX-
9 7
SSTX+ GND
B
DY USB3.0 B
SKT-USB13-206-GP

022.10005.00P1
USB_P2 BOM CTRL
For USB2.0 Change to 022.10005.0S91 1ST = 022.10005.0S91
C3621
USB3_2_TX2_P_1 R3602 USB3_2_TX2_P_R
16 USB30_TX_CPU_P2 1 2
SCD1U16V2KX-L-GP
1 2
0R0402-PAD
2nd = 022.10005.03J1
3RD = 022.10005.03N1

EMI Request USB_P2 BOM CTRL

ED3603 ED3604
5V_USB2_S3
USB3_2_TX2_P_R 1 10 USB3_2_TX2_P_R USB_PN1_TVS 1 6 USB_PN1_TVS

USB3_2_TX2_N_R 2 9 USB3_2_TX2_N_R
C3620 3 8 2 5
1 2 USB3_2_TX2_N_1 R3603 1 2 USB3_2_TX2_N_R
16 USB30_TX_CPU_N2
SCD1U16V2KX-L-GP 0R0402-PAD USB3_2_RX2_P_R 4 7 USB3_2_RX2_P_R

USB3_2_RX2_N_R USB3_2_RX2_N_R
USB_P2 BOM CTRL 5 6
USB_PP1_TVS USB_PP1_TVS
3 4

L05ESDL5V0NA-4-GP
075.00550.0071 L12ESDL5V0C6-4C-GP
2ND = 75.01043.073 075.01256.007C
USB_P2 BOM CTRL 2ND = 075.09904.0A7C
EMI TEST
R3604 1 2 USB3_2_RX2_P_R
16 USB30_RX_CPU_P2
0R0402-PAD

A A
TR3604
3 4 USB_PP1_TVS
16 USB_CPU_PP1
2 1 USB_PN1_TVS
16 USB_CPU_PN1
FILTER-4P-137-GP-U <Core Design>

R3605 1 2 USB3_2_RX2_N_R 68.01012.20B

16 USB30_RX_CPU_N2
0R0402-PAD Wistron Corporation
1ST = 68.01012.20B 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2ND = 68.00396.001
Title
EMI TEST
USB30
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 36 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 37 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 38 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 39 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = Power Plane & Sequence

Power Good 3D3V_S0

OSLO do not connect to 3D3V_S0

1
R4005
So reserved 20150724 1KR2J-1-GP
51 1D2V_VTT_PWRGD 1 R4011 2 0R0402-PAD

ROSA Run Power

2
D4002
53 RSMRST_PWRGD# RSMRST_PWRGD# 3 1 ALL_SYS_PWRGD 17,24
DY 2
R4002
LBAS16LT1G-GP 1 2 VR_EN 46,52
83.00016.P11 0R0402-PAD
5V_S5
2ND = 83.00016.H11

1
5V_S5 5V_S0 3D3V_S5
U4001
5V_S0 C4024

SCD1U16V2KX-3GP
SCD47U25V3KX-1GP

2
4 13 5V_S0 1 C4023
VBIAS OUT1#13 AFTP4001
14
OUT1#14

1
D 12 3V5V_CT1 3D3V_S0 5V_S0 Comsumption D
CT1 C4005
1 Peak current 5A
IN1#1

SC10U25V5KX-L-GP
R4010 2 8

2
3V5V_S0_ON IN1#2 OUT2#8 3D3V_S0
17,24,51,52,54 SIO_SLP_S3# 1 2 3 9 1

0R0402-PAD
EN1 OUT2#9
CT2 10 3V5V_CT2
3D3V_S0 AFTP4002
U4007

C4002
SC470P50V2KX-3GP

C4001
SC470P50V2KX-3GP
3D3V_S5 6 IN2#6

1
7
IN2#7 GND
11 3D3V_S0 Comsumption 26,46 VR_RDY 1
A VCC
5
5 15 C4004 ALL_SYS_PWRGD 2
EN2 GND Peak current 2.5A B

SC10U25V5KX-L-GP
3 4 PCH_PWROK 17

2
GND Y
G5016KD1U-GP
SN74AUP1G08DCKR-GP
074.05016.0093
2ND = 074.22966.0093
R4018
1 2
H_THERMTRIP# 4
0R2J-2-GP
DY

Q4002
MMBT2222A-3-GP DY DY

1
84.02222.V11

ED4003

ED4004
17 H_THERMTRIP_EN H_THERMTRIP_EN B

PESD5V0U1BL-GP-U1

PESD5V0U1BL-GP-U1
DY

C
R4007

2
C4003

1
17,24,31,61,68,76 PLT_RST# 1 2 SCD1U16V2KX-3GP
DY

VCCSTG

2
4K7R2J-2-GP
1

DY R4003
2K2R2J-2-GP
DY 20151007 Delete Reserved Circuit
DY DY
2
1

DY
Power Source Keep VCCIO (R710)
ED4001

ED4002

ED4005

ED4006

R4015 1 2 0R2J-2-GP
PESD5V0U1BL-GP-U1

PESD5V0U1BL-GP-U1

PESD5V0U1BL-GP-U1

PESD5V0U1BL-GP-U1
2

D4001 +VCCSTG(ICCMAX.=0.16A)
45,54 3V_EN 1 3 PURE_HW_SHUTDOWN# 24,26
2
VCCSTG should only ramp up equal to or after VCCST.
LBAS16LT1G-GP
C C
83.00016.P11
1

2ND = 83.00016.H11
DY R4006
DY
GT3 Low Power Circuit (ZVM)
200KR2F-L-GP
2

R4009
1 2 S5_ENABLE 24 20151209 Reserved Circuit 3D3V_S0 3D3V_S0
2KR2F-3-GP

1
R4030
2K2R2J-L1-GP R4031
23e 100KR2J-1-GP
23e

2
Q4003 DY
D4003 ZVM#_G G 23e
1 3 D4004 DY

C
24,45 5V_EN R4029
2 D ZVM#_EN_EDRAM A K ZVM#_EN_EDRAM_D R4019 1 2 ALL_SYS_PWRGD
ZVM# 1 2 ZVM#_B B Q4001 0R2J-2-GP
6 ZVM#
1

LBAS16LT1G-GP 2K2R2J-L1-GP METR3904-G-GP S RB551V30-GP

DY R4008 83.00016.P11 23e 23e Notice:ZZ.2N702.J3101

E
2ND = 83.00016.H11 2N7002K-2-GP 84.2N702.J31 83.R5003.H8H
200KR2F-L-GP

2ND = 84.2N702.031 2nd = 83.R5003.T8F

3rd = 84.2N702.W31
2

DY
R4024 1 2 0R2J-2-GP DY R4025 1 2 0R0402-PAD EN_EDRAM_VR 52

Need to Check
1D8V_S5
V1.8A +V1.8A

PG4004 1 2 GAP-CLOSE-PWR-3-GP

PG4005 1 2 GAP-CLOSE-PWR-3-GP

Discharge circuit

1
C4021 PG4006 1 2 GAP-CLOSE-PWR-3-GP C4020

SCD1U16V2KX-3GP
C4017 SC1U10V2KX-1GP DY
SC22U6D3V5MX-L3-GP

2
B B
+VCCSTG
+V1.8S_EDRAM

Q4008 3D3V_S5
220R3F-1-GP 1 R4021 2 1D8V_DIS_Q 3 4
Q4009 3D3V_S5 DY
220R3F-1-GP 1 R4028 2 1D0V_DIS_Q 3 4 2 5
17,24,51,52,54 SIO_SLP_S3#
DY 1D8V_DIS
2 5 1 6 2 R4020 1
17,24,51,52,54 SIO_SLP_S3#
1 6 1D0V_DIS 2 R4022 1 100KR2J-4-GP
2N7002KDW-GP
100KR2J-4-GP 84.2N702.A3F DY
2N7002KDW-GP 2nd = 075.063D1.007C
84.2N702.A3F DY
2nd = 075.063D1.007C
DY
DY

V1.8S
MANAGEMENT RAIL POWER GENERATION VCCST, VCCSTG, and VCCPLL can remain powered during S4 and S5 power states for board VR optimization. +V1.8A
Q4006
DMP2130L-7-GP
+V1.8S_EDRAM

5V_S5 1D0V_S5
1D0V_S5 +V1.00U_CPU VCCST 100mA
S
D

D
1

G
SC1U10V2KX-L1-GP

R4027 23e

1
23e C4026 R4044

G
1

1
SCD1U16V2KX-3GP

C4015 C4006 1 DY 2 23e 10KR2J-3-GP C4022 84.02130.031 C4027

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
0R6J-3-GP SC1U10V2KX-1GP
DY DY R4041 DY

2
2nd = 84.00102.031
2

2
1 2 1D8S_EN_R#
+V1.00U_CPU
23e 23e

1D8S_EN#
U4006 Q4007 20KR2J-L2-GP

17,24,51,52,54 SIO_SLP_S3# G 23e

1 8
IN#1 OUT#8
2 IN#2 OUT#7 7 D
R4023 3 6
VCCSTU_EN_R VBIAS OUT#6
17,24,51 SIO_SLP_S4# 1 2 4 5 S
ON GND Notice:ZZ.2N702.J3101
1

A 0R2J-2-GP EC4001 9 1D0V_S5 2N7002K-2-GP A

IN#9
1

DY C4012 84.2N702.J31
1

SC10U25V5KX-L-GP 2ND = 84.2N702.031

SCD1U16V2KX-3GP

AOZ1335DI-GP C4013 3rd = 84.2N702.W31

2

SC10U25V5KX-L-GP
074.01335.0093
2

2ND = 074.08939.0093

+VCCSTG +VCCST_CPU
VIL > 0.7 V, VIH < 2 V <Core Design>
Rds(on) = 11 mΩ @ VDD = 4 V 0.04 A
Ids(max) 10 A R4045
1 DY 2 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
0R2J-2-GP Taipei Hsien 221, Taiwan, R.O.C.

+V1.00U_CPU Title

R4036
Power Plane EN Sequence
1 2 Size Document Number Rev
Custom
0R0402-PAD LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 40 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = Power Plane & Sequence

D D

C C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Connected_Standby(1/2)+DS3
Size Document Number Rev
A4
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 41 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = DIMM1

Main Func = DIMM2

D D

VREF CIRCUITRY

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Connected_Standby(2/2)
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 42 of 102
5 4 3 2 1
 5 4 3 2 1

BT+

F4301
1

FUSE-10A32V-1-GP
2
1ST BATTERY CONNECTOR
69.41002.101

1
EC4301
PC4301 PC4302 SCD1U50V3KX-GP
SCD1U50V3KX-L-GP SC2K2P50V2KX-L-GP BAT1

2
9 11
1
RN4301 1ST = 020.F0266.0008
24 BAT_IN# 1 8 BAT_IN#_1 BT+_IN1 2
2 7 BATA_SCL_1 3 2ND = 020.F0661.0008
24,44 BAT_SCL
3 6 BATA_SDA_1 4
24,44 BAT_SDA
4 5 BAT_IN#_1 5
6
K

SRN33J-4-GP 7
PD4301 PL4301 PL4302 PL4303 PC4304 PC4305 8

2
MMSZ5232BS-7-F-GP PC4303 10 12

1
VARISTOR-5D5V-29-GP

VARISTOR-5D5V-29-GP

VARISTOR-5D5V-29-GP
SC1KP50V2KX-L-1-GP

SC100P50V2JN-L-GP

SC100P50V2JN-L-GP
DY DY DY ALP-CON8-24-GP
DY
A

2
D D
020.F0266.0008

1
AFTP4301 1 BAT_IN#_1
AFTP4302 1 BATA_SDA_1
AFTP4303 1 BATA_SCL_1

AFTP4305 1 BT+_IN1
AFTP4306 1
AFTP4309 1

AFTP4307 1
AFTP4308 1
AFTP4310 1

C C

B AD_ID
Adaptor in to generate DCBATOUT B

DY
K

AD_JK PD4302
08/01 EC4308 Change part number 78.10622.L5L to 78.10622.51L(1206 to 0805) AZ5013-01HDR7G-GP
83.05013.0AF
DC Jack
A

TP4312 TP4313

AD+
AD_JK AD_JK_F
1

1
SC10U25V5KX-GP

F4302 PU4301
1

DCCN1 1 2 1 S D 8
EC4308 S D 7
DY 2
S D 6
7 FUSE-10A32V-1-GP 3
2

AD+_2 G D 5
5 69.41002.101 4
K
1

4 EC4307 PC4307 PR4301

SCD1U50V3KX-L-GP

3 SCD1U50V3KX-L-GP PD4303 PC4308 AO4407AL-GP

2

1
200KR2F-L-GP
2 P6SMB27A-GP
2

SCD22U25V3KX-GP
AFTP4311 84.04407.G37
1 1 83.P6SMB.JAG
A

2
6
PQ4301

2
R2
2
ACES-CON5-38-GP AD_OFF#_1 1 R1
AD_ID_R 3
020.F0498.0005 LTA024EUB-FS8-GP
1

1
1ST = 020.F0498.0005 PR4303 PR4302
2ND = 020.F0698.0005 84.00024.01K 100KR2J-1-GP
100KR2J-1-GP
R4304 06/25 Delete PR4303,PR4304,PR4305,PR4306 DY
2

2
AD_ID_R 1 2 AD_ID

0R0402-PAD

PQ4302
AD+_2 trace width > 8mil
PR4304
R1
3 Length < 500mil
AD_ID 24 24,44 AD_OFF 1 2AD_OFF_RC 1
0R0402-PAD 2
R2 08/06 add AD_OFF Circuit
1

PC4309 LTC024EUB-FS8-GP
SCD01U50V2KX-L-GP 84.00024.A1K
2

DY

Test point
AFTP4314 1 AD_JK
A AFTP4315 A
1
AFTP4316 1

AFTP4317 1

<Core Design>
AFTP4318 1 AD_ID

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DCIN & BATT Com

Size Document Number Rev
A1
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 43 of 102

5 4 3 2 1
 5 4 3 2 1

20151012 Modify PU4401 PN 84.08131.037 20151012 Modify PU4402 PN

AD+_TO_SYS DCBATOUT BT+
1ST = 84.08131.037
SSID = Charger PU4401 2ND = 84.07403.037 1
PU4402
S D 8 84.08131.037
8 D S 1 2 S D 7
AD+
D S 1 PR4402 2 S D
7 2 3 6 1ST = 84.08131.037

1
6 D S 3 D01R3721F-GP-U D 5
D PR4403 AD+ G
20151230 Power Team update Table 5
G 100KR2J-1-GP TPCC8131-GP
2ND = 84.07403.037
D D

4
TPCC8131-GP

4
1
A8( ANNIE/ASTRO)

1
PR4404 AD+_G_2

1
PR4007,PR4008 10KR2F-2-GP Id= -10A PG4402 PG4403 Id= -10A

1
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP PR4406
Qg= -22nC PR4405 470KR2J-2-GP Qg= -22nC

2
AD+ total power R1 R2 Rdson=14~22mohm 49K9R2F-L-GP Rdson=14~22mohm

DC_IN_D

2
51K

2
45w 64.51025.6DL 100K PQ4402
PC4402 2 1 SCD1U50V3KX-L-GP

AD+_G_1
120K 3 4
65w 64.12035.6DL 100K
AC_IN 2 5
DCBATOUT
100K 1 6

1
AD_JK_F PC4403 PC4404
2N7002KDW-GP SCD1U50V3KX-L-GP SCD1U50V3KX-L-GP
100K

2
84.2N702.A3F

PWR_CHG_ACN
PWR_CHG_ACP

1
2ND = 075.063D1.007C PC4406 PC4407

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
1 2 BQ24737_VCC BQ24737_REGN PC4405
PR4407 CHG_AGND SCD1U25V2KX-L-GP

2
CHG_AGND

1
20R5F-1GP

5
6
7
8
PR4408 PC4408

BQ24737_BTST_R
PR4409

D
D
D
D
3D3V_AUX_KBC 316KR3F-2-GP SC1U50V5ZY-1-GP-U PC4409 PU4403

2
1 2 K A 1 2 SC1U10V2KX-L1-GP SIS412DN-T1-GE3-GP
CHG_AGND 1D5R2F-GP

1
PU4404 PD4401 84.00412.037
BQ24737_REGN RB520SM-30T2R-GP

ACP

ACN
2

G
S
S
S
PWR_CHG_IOUT 20 83.1R003.N8F 1ST = 84.00412.037

1
PR4401 VCC

4
3
2
1
10KR2F-2-GP STOP_CHG# PR4410 PR4411 2ND = 084.03319.0A37

1
R1 12K4R2F-GP 100KR2J-1-GP BQ24737_ACDET 6 17 BQ24737_BTST
connects to KBC 1
ADT BOM CTRL
ACDET BTST PC4410
Charger Current=1.4~3.6A
1

PR4412 1 SCD1U50V3KX-L-GP

1 2

2
49K9R2F-L-GP PC4411 BQ24737_CMPOUT 16
24 STOP_CHG# SCD01U50V2KX-L-GP REG
2

1
PR4414 3
D

PQ4401 PR4413 120KR2F-L-GP CMPOUT BQ24737_HIDRV

18
100KR2F-L1-GP PR4415 HIDRV PL4403 PR4416 BT+
C R2 C
Notice:ZZ.2N702.J3101

CHG_AGND 3D3MR2J-GP 4 D01R3721F-GP-U

2
CMPIN BQ24737_PHASE BT+_R
19 1 2 1 2
84.2N702.J31

2
CHG_AGND BQ24737_CMPIN PHASE IND-4D7UH-88-GP-U

GAP-CLOSE-PWR-3-GP
2ND = 84.2N702.031 68.4R710.20D

GAP-CLOSE-PWR-3-GP
9 15 BQ24737_LODRV
3rd = 84.2N702.W31 24,43 BAT_SCL

1
SCL LODRV

PG4401
2N7002K-2-GP CHG_AGND PC4413 PC4414 PC4401

PG4404
S

5
6
7
8

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
PC4415

D
D
D
D
8 PU4405 SCD1U50V3KX-L-GP
24,43 BAT_SDA

2
SDA

SIS412DN-T1-GE3-GP
3D3V_AUX_S5 PR4417 PC4412

1
BQ24737_CMPOUT 10R2F-L-GP SC470P50V2KX-L-GP

2
13 BQ24737_SRP 1 2
1

BQ24737_ILIM SRP
10
ILIM

G
S
S
S
PR4418 12 BQ24737_SRN 1 2
100KR2J-1-GP SRN PR4419

4
3
2
1
CHG_AGND BQ24737_REGN_R 11 7D5R2F-GP 84.00412.037
BM#
2

1
1ST = 84.00412.037
PR4420
10KR2F-2-GP
PWR_CHG_IOUT
2ND = 084.03319.0A37
DY 5
ACOK# IOUT
7 1 2 AD_IA 24
PR4421 BQ24737_CSOP_1

GND

GND
2
BQ24737_REGN 0R0402-PAD
1

21

14
PR4422 HPA02224RGRR-1-GP

1
33KR2F-GP
DY 74.02224.073
D

PQ4403 3D3V_AUX_KBC PC4416

1 2 SCD1U50V3KX-L-GP
Notice:ZZ.2N702.J3101
2

2
PR4424
1

1
0R0402-PAD PC4417 BQ24737_CSON_1
PR4423 SC100P50V2JN-L-GP
100KR2J-1-GP

2
CHG_AGND

1
3D3V_AUX_KBC 2N7002K-2-GP CHG_AGND
84.2N702.J31
S

PC4418
2ND = 84.2N702.031 SCD1U25V2KX-L-GP

2
1 DY 2 BAT_SCL 3D3V_AUX_S5
CHG_ON# 24
PR4425 3K3R2J-3-GP 3rd = 84.2N702.W31
1

CHG_AGND CHG_AGND
B PR4427 B
1 DY 2 BAT_SDA 100KR2J-1-GP
PR4426 3K3R2J-3-GP DY
3D3V_AUX_S5
2
1

PR4428
100KR2J-1-GP AC_IN#
24 AC_IN#
2

AC_IN

PQ4404 PQ4405
AC_IN# G G AD_OFF 24,43
D D

S S
Notice:ZZ.2N702.J3101 Notice:ZZ.2N702.J3101

2N7002K-2-GP 2N7002K-2-GP

84.2N702.J31 84.2N702.J31
2ND = 84.2N702.031 2ND = 84.2N702.031
3rd = 84.2N702.W31 3rd = 84.2N702.W31

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CHARGER
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 44 of 102
5 4 3 2 1
 A B C D E

08/20 add 5V_EN

PWR_5V_EN1 1 PR4501 2 DCBATOUT PWR_DCBATOUT_5V

5V_EN 24,40
0R2J-2-GP PG4510

2
EC4501
DY
PR4507
1 2
GAP-CLOSE-PWR-6-GP
0R0402-PAD

2
SCD1U16V2KX-L-GP PG4511
1 2

1
GAP-CLOSE-PWR-6-GP
PWR_3D3V_EN2 1 PR4502 2
3V_EN 40,54 PG4512
0R0402-PAD 1 2

1
4 EC4502 GAP-CLOSE-PWR-6-GP 4
SC68P50V2JN-1GP
PG4513
DY

2
1 2
12/18 PR4501,PR4502 Change to Short PAD GAP-CLOSE-PWR-6-GP
08/06 Change to Close GAP
PG4514
1 2
DCBATOUT PWR_DCBATOUT_3D3V GAP-CLOSE-PWR-6-GP
12/11 上上上)
Change Part number ZZ.CLOSE.001(上
PG4504 PG4524
1 2 1 2
GAP-CLOSE-PWR-6-GP GAP-CLOSE-PWR-6-GP

PG4505
1 2 PG4525
GAP-CLOSE-PWR-6-GP 1 2
GAP-CLOSE-PWR-6-GP
08/06 Change to Close GAP PG4515
1 2
GAP-CLOSE-PWR-6-GP
上上上)
12/11 Change Part number ZZ.CLOSE.001(上

DCBATOUT

PWR_DCBATOUT_5V
PWR_DCBATOUT_3D3V

1
SC10U25V5KX-GP
PC4507 PC4508
1

5
6
7
8

1
SCD01U50V2KX-L-GP
PC4501 PC4502 EC4503 PC4512 PC4513 PC4514
DY

D
D
D
D
SC4D7U25V5KX-L2-GP

SC4D7U25V5KX-L2-GP

SCD1U50V3KX-L-GP

SCD1U50V3KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
PU4504

SCD1U50V3KX-L-GP
D EC4504 AON7410-GP
2

2
D 8
D 7
D 6
D 5

2
PU4502
AON7410-GP

12

G
S
S
S
PU4501 84.07410.A37
84.07410.A37

VIN

4
3
2
1
Design Current=3.1A 2nd = 84.01528.037 2nd = 84.01528.037

S
S
S
G
3 3
OCP <6.2A PC4503 PR4503 PR4509 PC4509 Design Current=6.4A
1
2
3
4
S G 1 2PWR_3D3V_VBST2_1
1 2PWR_3D3V_VBST2 9 17 PWR_5V_VBST1 1 2PWR_5V_VBST1_1 1 2
SCD1U50V3KX-L-GP 1D5R3F-GP BOOT2 BOOT1 1D5R3F-GP SCD1U50V3KX-L-GP OCP < 12.8A
3D3V_S5 PL4502
PL4501 PWR_3D3V_DRVH2 10 16 PWR_5V_DRVH1 5V_S5
UGATE2 UGATE1
1 2 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2
COIL-3D3UH-26-GP PHASE2 PHASE1 IND-2D2UH-179-GP
1

PWR_3D3V_DRVL2 PWR_5V_DRVL1
68.3R310.20V D 11 15

1
LGATE2 LGATE1
2nd = 68.3R31A.10V 68.2R21A.20B
D 8
D 7
D 6
D 5

1
PR4504 PR4511 PC4516 TC4503
PG4506 2D2R5F-2-GP PU4503 PWR_5V_VO1 2D2R5F-2-GP
14 2nd = 68.2R21B.10J DY
1

5
6
7
8
BYP1

SCD1U25V2KX-L-GP

SE220U6D3VM-30-GP
AON7410-GP
DY DY
2

2
1

D
D
D
D
GAP-CLOSE-PWR-3-GP

PC4504 TC4501 PWR_3D3V_FB2 4 2 PWR_5V_FB1 PU4505 PG4509

1PWR_5V_SNUB
2

1
FB2 FB1 AON7410-GP
DY
1PWR_3D3V_SNUB
SCD1U25V2KX-L-GP

SE220U6D3VM-30-GP

GAP-CLOSE-PWR-3-GP
2

G
S
S
S
G

PWR_3D3V_EN2 6 20 PWR_5V_EN1
1
2
3
4

2
EN2 EN1

G
S
S
S
S
77.52271.09L

4
3
2
1
PWR_3D3V_CS2 5 1 PWR_5V_CS1 PC4515
CS2 CS1 SC560P50V-GP
84.07410.A37
3V_FEEDBACK

1
PC4505
77.52271.09L DY 2ND = 77.92271.03L

2
SC330P50V3KX-GP PR4505 19 PR4510 2nd = 84.01528.037
105KR2F-1-GP VCLK 210KR2F-GP
DY 84.07410.A37
2

2ND = 77.92271.03L 20151012 Modify TC4503 PN

2nd = 84.01528.037 7 21
2

2
PGOOD GND

LDO3

LDO5
20151012 Modify TC4501 PN 074.06575.0A43
1

PR4516 PR4506 RT6575DGQW-GP

13
6K65R2F-GP 0R2J-2-GP 5V_AUX_S5

1
3D3V_AUX_S5 PR4512
DY

PWR_5V3D3V_VREG3

PWR_5V3D3V_VREG5
PG4507 PG4508 R402-PAD-H16-GP
2

1
3D3V_S5 PWR_3D3V_FB2_R
1 2 1 2 ZZ.00RES.021
AFTP4501 PR4514
1 ASM_RES_PAD_DY
1

AFTP4502 1 5V_S5 PC4506 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP 15KR2F-GP

1 2
SC18P50V2JN-1-GP PWR_5V_FB1_R
PC4517
DY
2

2
SC18P50V2JN-1-GP
2 2
DY

2
1

3D3V_S5
PR4517
1

1
10KR2F-2-GP PC4510 PC4511
1

SC10U25V5KX-L-GP SC10U25V5KX-L-GP PR4515

PR4508 10KR2F-2-GP
2

100KR2J-1-GP
DY Close to VFB Pin (pin2)

2
2

3V_5V_POK
17,54 3V_5V_POK
Close to VFB Pin (pin5)

1 1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SYN256_5V/3D3V
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 45 of 102
A B C D E
 5 4 3 2 1

Main Func = CPU_CORE

PR4611 23e change to 64.27425.6DL

1 2 33K2R2F-GP

PC4632
1 2

SC1KP50V2KX-L-1-GP
PR4602
D PC4602 81208_AGND D
1 2 PWR_VCCSA_COMP_R 1 2 PWR_VCCSA_CSN 50

2
SCD015U25V2KX-GP
1K5R2F-2-GP
PC4606 PR4606

1
SCD015U25V2KX-GP NTC-100K-1-GP-U

1
PC4603 PC4604 1 2 SC15P50V2JN-L-GP
SC1KP50V2KX-L-1-GP PC4607 69.60028.011

2
SC3300P50V2KX-1GP 14K3R2F-GP

1
PWR_VCCSA_VSN_R 1 2 23e:DY PR4609 1 2 PWR_VCCSA_CSN_NTC
81208_AGND
PR4605
7 VSSSA_SENSE PR4604 1 2 0R0402-PAD 1 2 PR4612 1 2 8K06R3F-AS-GP PWR_VCCSA_CSP 50
3D3V_S0
PR4613
825R2F-GP

2
1 2 102KR2F-GP

1
PC4605
SC1KP50V2KX-L-1-GP 23e change to 64.84525.6DL PR4614

1
PC4609 1 2 SC220P50V2KX-3GP 10KR2F-2-GP
7 VCCSA_SENSE PR4607 1 2 0R0402-PAD PR4608 1 2 2K61R2F-1-GP

2
PC4608 81208_AGND PR4670 1 2 0R0402-PAD VR_RDY
PWR_VCCSA_VSP_R VR_RDY 26,40
1 2 1 2
PR4616 SC1KP50V2KX-L-1-GP PR4630 1 2 0R0402-PAD
0R0402-PAD VR_EN 40,52
+VCCST_CPU
PWR_VCCSA_VSP_RC PSYS

PR4615 2 1 20KR2F-L-GP

75R2F-2-GP
PR4622

100R2F-L1-GP-U
PR4623

1
PC4610
81208_AGND SCD1U25V2KX-L-GP +VCCST_CPU +VCCSTG Check +VCCST_CPU or +VCCSTG

2
7 VCCGT_SENSE PR4617 1 2 0R0402-PAD

1
45D3R2F-L-GP
PR4621
DY

1
[#543016]
PC4611
SC1KP50V2KX-L-1-GP

1
C PR4619 C
7 VSSGT_SENSE PR4618 1 2 0R0402-PAD 2 1 1KR2F-3-GP PR4624 PR4669
1KR2F-3-GP
VR_SVID_CLK 7 DY DY 75R2F-2-GP
PWR_VCCGT_VSN_R 1 2 VR_SVID_ALERT# 7

2
PC4612 SC2K2P50V2KX-L-GP
PG4601 VR_SVID_DATA 7
GAP-CLOSE-PWR-3-GP

50

47,48,50
PR4668

PWR_VCCSA_PWM
2 1

PWR_VCORE_DRVON
1

PR4665

PR4666

PR4667
1 2 H_PROCHOT# 4,24
PR4625 100R2F-L1-GP-U
37D4R2F-GP
81208_AGND

PWR_VCORE_VR_RDY
1

PWR_VCCSA_CSP1B
PR4626

PWR_VCCSA_COMP
2

PWR_VCCSA_IOUT

49D9R2F-GP

0R0402-PAD

10R2F-L-GP
PWR_VCCGT_VSN

PWR_VCCSA_VSN
PWR_VCCGT_VSP

PWR_VCCSA_VSP

PWR_VCCSA_ILIM
1KR2F-3-GP PC4613 1 2 SC470P50V2KX-L-GP

PWR_VCORE_EN

1
PWR_VCCGT_FB_R PR4627
PR4628 1 2 110KR2F-GP 1 2 PWR_VCORE_CSP 47
1

8K06R3F-AS-GP
2

PR4632 23e change to 64.10035.6DL

PC4614
SC470P50V2KX-L-GP 1 2 26K1R2F-2-GP 81208_AGND
2

2
PR4629
81208_AGND
1 2 PWR_VCORE_CSNNTC
1

PWR_VCORE_VRHOT#
PWR_VCORE_ALERT#

2
PR4631 14KR2F-GP

49

48
47
46
45
44
43
42
41
40
39
38
37

PWR_VCORE_SCLK

PWR_VCORE_SDIO
PC4617 4K75R2F-1-GP 1 2 PU4601
1

1
SC10P50V2JN-L1-GP PR4633

PSYS
VSP_1B
VSN_1B
COMP_1B
ILIM_1B
CSN_1B
CSP_1B
IOUT_1B
VR_RDY
GND

VSN_2PH
VSP_2PH

EN
PWR_VCCGT_ILIM_R

PC4615 PC4634 PC4616 NTC-100K-1-GP-U

2

SC470P50V2KX-L-GP SCD022U25V2KX-GP SCD01U50V2KX-L-GP

69.60028.011
2

2
PWR_VCCGT_COMP_R
1

PR4634 81208_AGND PWR_VCORE_CSN 47

1
1 2 PC4618 PWR_VCCGT_IOUT 1 36
SC2K2P50V2KX-L-GP PWR_VCCGT_DIFFOUT IOUT_2PH PWM_1B
2 35 1 PR4635 2 59KR2F-GP
2

PR4638 NTC-220K-5-GP-U PWR_VCCGT_FB DIFFOUT_2PH DRVON

3 34
PR4637 165KR2F-GP PWR_VCCGT_COMP FB_2PH SCLK
4 33
PWR_VCCGT_ILIM COMP_2PH ALERT#
48 PWR_VCCGT_CSPA 1 2 2 1 1 PR4639 2 PR4640 1 2 5 32
12K4R2F-GP PWR_VCCGT_CSCOMP ILIM_2PH SDIO
6 074.81208.0D73 31 PR4636
1

47K5R3F-GP PC4621 23e change to 64.16225.6DL PWR_VCCGT_CSSUM CSCOMP_2PH VR_HOT# PWR_VCORE_IOUT PC4633 81208_AGND
7 30
75KR2F-GP PC4620 SC100P50V2JN-L-GP PWR_VCCGT_CSREF CSSUM_2PH IOUT_1A PWR_VCORE_CSP_1A PC4601 1 PWR_VCORE_COMP_R
23e change to 64.73225.55L SC1KP50V2KX-L-1-GP
8
CSREF_2PH CSP_1A
29 1 2 2 1 2
9 28 SC1KP50V2KX-L-1-GP SC1500P50V2KX-2GP
2

CSP2_2PH CSN_1A PWR_VCORE_ILIM

48 PWR_VCCGT_CSPB 1 PR4641 2 23e 10 27 2K49R2F-GP
CSP1_2PH ILIM_1A PWR_VCORE_COMP PC4619 1
11 2 SC15P50V2JN-L-GP

ROSC_COREGT
26
TSENSE_2PH COMP_1A

ADDR_VBOOT
B 73K2R3F-1-GP 12 25 PWR_VCORE_VSN 2 1PWR_VCORE_VSN_R 81208_AGND B

TSENSE_1PH
ICCMAX_2PH
ROSC_SAUS
PR4643 2 VRMP VSN_1A
1 10R2F-L-GP PC4622 SC1KP50V2KX-L-1-GP

ICCMAX_1A
ICCMAX_1B
PWM1_2PH
PWM2_2PH
48 PWR_VCCGT_CSNB
23e 5V_S5
PWR_VCORE_VRMP

PWM_1A

VSP_1A
1 2 PR4645 2 1 0R0402-PAD VSS_SENSE 7
1

PR4644
VCC
1

1
48 PWR_VCCGT_CSNA PR4646 2 1 10R2F-L-GP PC4623 PC4624 PR4671 422R2F-2-GP
SCD033U25V2KX-GP SCD033U25V2KX-GP 1KR2F-3-GP PC4625
23e:DY NCP81208MNTXG-4-GP PR4647 SC1KP50V2KX-L-1-GP
23e
2

13
14
15
16
17
18
19
20
21
22
23
24

2
1 2 3K83R2F-GP PR4648 2 1 0R0402-PAD VCC_SENSE 7
2

PWR_VCCGT_CSP2
1

PWR_VCORE_VCC_R

PC4626 23e:change to 64.34815.6DL

PWR_VCORE_ROSC_SAUS

SCD01U50V2KX-L-GP PWR_VCCGT_CSP1 PWR_VCORE_VSP PR4649 2PWR_VCORE_VSP_RC 1 PWR_VCORE_VSP_R

PWR_VCORE_ROSC_COREGT

1 2
PWR_VCCGT_TSENSE 3K83R2F-GP PC4627 SC1KP50V2KX-L-1-GP
2

PR4650
DCBATOUT PWR_VCORE_TSENSE 2 1 PWR_VCORE_NTC
PR4651 81208_AGND PWR_VCORE_PWM 47 0R0402-PAD
48 PWR_VCCGT_CSPA 1 2 PR4601 PWR_VCORE_ADDR_BOOT

2
1 2 1KR2F-3-GP PWR_VCCSA_ICCMAX

1
4K87R2F-GP PWR_VCORE_ICCMAX PR4652
PR4654 1 2 PWR_VCCGT_ICCMAX PC4628 12K7R2F-GP PR4653
48 PWR_VCCGT_CSPB
1

6K98R2F-GP SCD1U25V2KX-L-GP NTC-100K-1-GP-U

2
PC4629 69.60028.011

2
SCD01U50V2KX-L-GP
2

1
PR4662 PR4658 PR4660 PR4663

1
PWR_VCCGT_NTC 1 2

48D7KR2F-GP

90K9R2F-GP

10KR2F-2-GP
15K8R2F-GP
PR4655
0R0402-PAD 81208_AGND 81208_AGND
2

5V_S5
2

2
1

PR4656 PR4657
NTC-100K-1-GP-U PR4661 PC4630 2D2R2F-GP PR4664 PR4659
12K7R2F-GP SCD1U25V2KX-L-GP 24KR2F-GP 24KR2F-GP
1 2 23e:change to 64.19125.6DL
2

69.60028.011 23e:change to 64.10035.6DL

2

2
1
1

PC4631
SC1U10V2KX-L1-GP 81208_AGND
2

81208_AGND PWR_VCCGT_PWMB 48
81208_AGND 81208_AGND 81208_AGND
PWR_VCCGT_PWMA 48
A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_VCORE(1/3)
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 46 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

DCBATOUT

1
D PC4701 PC4702 PC4703 PC4704 PC4705 D

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
PC4710
SCD1U25V2KX-L-GP

2
PR4701
1 2 PW R_VCORE_BOOT_RC

PWR_VCORE_BOOT
3D9R3-GP

1
5V_S5 PC4706
SCD22U25V3KX-GP
PR4702

2
2D2R2F-GP

25
26
27
28
29
30

33

35
1
2 1 PW R_VCORE_VCC PU4701

THWN

VIN
VIN
VIN
VIN
VIN
VIN

GH

BOOT
1
PC4708 VCC_CORE
SC1U10V2KX-L1-GP 6
2
C VCC PW R_VCORE_PHASED C
PHASED 34 PL4701 1ST = 68.R1510.20A
7 VCCD PHASEF 32
1

PC4707 PW R_VCORE_SW
2ND = 68.R1510.201
VSW#12 12 1 2
SC2D2U10V3KX-L-GP 5 13
2

CGND VSW#13
VSW#14 14 COIL-D15UH-2-GP
074.81382.0CE3 VSW#15 15
46 PW R_VCORE_PW M
4 PWM VSW#16 16 68.R1510.20A
PR4704 17
PW R_VCORE_DISB# 2 VSW#17
1 2 DISB# VSW#18 18

1
46,48,50 PW R_VCORE_DRVON PT4701
0R0402-PAD 36 ZCD_EN

1
PG4707 PG4708

ST220U2VDM-5-GP
2
GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
5V_S5 3 PR4703

1
SMOD# 2D2R5F-2-GP
DY
GL#10
GL#11

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9

2
NCP81382MNTXG-3-GP PW R_VCORE_SNUB
8
9
10
11

19
20
21
22
23
24
31
37

1
PC4709 79.22719.2BL
PW R_VCORE_GL SC2200P50V2KX-2GP
DY

2
1ST = 074.81382.0CE3 Confirm with EE:
22uF/0805 total 32pcs (DY 5 pcs)
B 2ND = 074.81381.0A73 for Pentium B
46 PW R_VCORE_CSP

46 PW R_VCORE_CSN

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_VCORE(2/3)
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 47 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

DCBATOUT

1
PC4820 PC4827 PC4828 PC4829 PC4830

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
D PC4811 D
SCD1U25V2KX-L-GP

2
PR4802
1 2

PWR_VCCGT_BOOTA
3D9R3-GP
PWR_VCCGT_BOOTA_RC

5V_S5

1
PC4809
SCD22U25V3KX-GP
PR4803

2
2D2R2F-GP

25
26
27
28
29
30

33

35
1
2 1 PWR_VCCGT_VCCA PU4801

THWN

VIN
VIN
VIN
VIN
VIN
VIN

GH

BOOT
1

PC4808
SC1U10V2KX-L1-GP 6 +VCCGT
2

VCC PWR_VCCGT_PHASEDA
PHASED
34 PL4801 1ST = 68.R1510.20A
7 32
1

PC4807 VCCD PHASEF

SC2D2U10V3KX-L-GP PWR_VCCGT_SWA
2ND = 68.R1510.201
VSW#12
12 1 2 Confirm with EE:
5 13 COIL-D15UH-2-GP
2

CGND VSW#13 22uF/0805 total 35pcs (DY 5 pcs)

VSW#14
14 68.R1510.20A
074.81382.0CE3 VSW#15
15
4 16
46 PWR_VCCGT_PWMA PR4808 PWM VSW#16
17
PWR_VCCGT_DISB#_A VSW#17
1 2 2 18

2
46,47,50 PWR_VCORE_DRVON DISB# VSW#18
0R0402-PAD 36

1
5V_S5 ZCD_EN PG4808 PG4809

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
C 3 PR4804 C

1
SMOD# 2D2R5F-2-GP
DY
GL#10
GL#11

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9

2
NCP81382MNTXG-3-GP
8
9
10
11

19
20
21
22
23
24
31
37
PWR_VCCGT_SNUB_1

1
PWR_VCCGT_GL1
PC4810
SC2200P50V2KX-2GP
DY

2
1ST = 074.81382.0CE3
2ND = 074.81381.0A73 for Pentium
46 PWR_VCCGT_CSPA

46 PWR_VCCGT_CSNA

DCBATOUT
1

1
PC4802 PC4803 PC4804 PC4805 PC4806
SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
PC4812
SCD1U25V2KX-L-GP
23e 23e 23e 23e 23e 23e
2

2
B B

PR4805
1 2
PWR_VCCGT_BOOTB

3D9R3-GP
PWR_VCCGT_BOOTB_RC

23e
5V_S5
1

PC4845
23e SCD22U25V3KX-GP
PR4806
2

2D2R2F-GP
25
26
27
28
29
30

33

35

23e
1

2 1 PWR_VCCGT_VCCB PU4802
THWN

VIN
VIN
VIN
VIN
VIN
VIN

GH

BOOT
1

23e
PC4847
SC1U10V2KX-L1-GP 6
2

VCC PWR_VCCGT_PHASEDB +VCCGT

PHASED
34 PL4802 1ST = 68.R1510.20A
7 32
1

PC4846 VCCD PHASEF

23e PWR_VCCGT_SWB
2ND = 68.R1510.201
SC2D2U10V3KX-L-GP 12 1 2
VSW#12 COIL-D15UH-2-GP
5 13
2

CGND VSW#13
VSW#14
14 68.R1510.20A
074.81382.0CE3 VSW#15
15
46 PWR_VCCGT_PWMB
4
PWM VSW#16
16 23e

1 PT4801

1 PT4803
PR4809 17
PWR_VCCGT_DISB#_B VSW#17
1 2 2 23e 18
2

46,47,50 PWR_VCORE_DRVON DISB# VSW#18

0R0402-PAD 36
1

ZCD_EN PG4815 PG4816

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

5V_S5 3 PR4807 DY
1

SMOD# 2D2R5F-2-GP
DY
2

2
GL#10
GL#11

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9

SE330U2VDM-L-GP

SE330U2VDM-L-GP
2

A A
NCP81382MNTXG-3-GP
8
9
10
11

19
20
21
22
23
24
31
37

PWR_VCCGT_SNUB_2
1

PWR_VCCGT_GL2
PC4814 <Core Design>
SC2200P50V2KX-2GP
DY
2

Wistron Corporation
1ST = 074.81382.0CE3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2ND = 074.81381.0A73 for Pentium 79.33719.L01 79.33719.L01
46 PWR_VCCGT_CSPB Title
1ST = 79.33719.L01 1ST = 79.33719.L01
CPU_VCCGT3/3)
2ND = 79.33719.20C 2ND = 79.33719.20C Size Document Number Rev
46 PWR_VCCGT_CSNB A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 48 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_VCCGTUS
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 49 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

D D

DCBATOUT

1
PC5029

SC10U25V5KX-L-GP
PC5002

5
6
7
8
PR5013 SCD1U25V2KX-L-GP

2
D
D
D
D
1 2 PW R_VCCSA_BST_RC PU5002
SIS412DN-T1-GE3-GP #544669 Intel CRB Rev0.53
2D2R3-1-U-GP +VCCSA(ICCMAX.=6A)
PWR_VCCSA_BST

G
S
S
S
PC5008
SCD22U25V3KX-GP 84.00412.037

4
3
2
1
2
C PU5001
1ST = 84.00412.037 +VCCSA C
PL5001
1ST = 68.R4710.10M
PW R_VCCSA_DRVH
2ND = 084.03319.0A37
1 BST DRVH 8
PW R_VCCSA_SW
2ND = 68.R4710.20K
2 PWM SW 7 1 2
46 PW R_VCCSA_PW M 3 6
46,47,48 PW R_VCORE_DRVON EN GND IND-D47UH-22-GP-U
5V_S5 4 VCC DRVL 5
68.R4710.10M

1
GND 9
1

PC5001 PR5014
SC2D2U10V3KX-L-GP 2D2R5F-2-GP
DY

5
6
7
8

1
NCP81253MNTBG-1-GP
2

D
D
D
D

SC47U6D3V5MX-1-GP
074.81253.0AE3 PU5003 PC5003

2
PG5021 PG5022

PWR_VCCSA_SNUB
SIS412DN-T1-GE3-GP

2
GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
DY

1
PW R_VCCSA_DRVL

G
S
S
S
4
3
2
1

1
84.00412.037 PC5031
1ST = 84.00412.037 DY SC2200P50V2KX-2GP

2
2ND = 084.03319.0A37

B B

Confirm with EE:

46 PW R_VCCSA_CSP 22uF/0805 total 20pcs (DY 5 pcs)

46 PW R_VCCSA_CSN

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_VCCSA
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 50 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = VDDQ

DCBATOUT PWR_DCBATOUT_VDDQ

PG5117
1 2
GAP-CLOSE-PWR-6-GP

PG5118
1 2
GAP-CLOSE-PWR-6-GP

PG5137
VID 1 2
GAP-CLOSE-PWR-6-GP 1D2V_PWR 1D2V_S3
Logic-High = 0.75V
PG5138
Logic-Low = 0.3V 1 2
PR5107 GAP-CLOSE-PWR-6-GP
5D1R2F-GP
PWR_VDDQ_VID 2 1 5V_S5 PG5139
1 2

1
PC5102 GAP-CLOSE-PWR-6-GP
SC1U10V2KX-L1-GP
PWR_DCBATOUT_VDDQ PG5140

2
RF RESERVED 1 2
GAP-CLOSE-PWR-6-GP

D OCP setting PG5141 D

1 2

1
PR5109 PC5103 PC5104 PC5105 FC5101 FC5102 GAP-CLOSE-PWR-6-GP

SC4D7U25V5KX-L2-GP

SC4D7U25V5KX-L2-GP

SCD1U25V2KX-L-GP
PWR_VDDQ_CS PWR_VDDQ_VDD 1 2

SCD1U25V2KX-L-GP

SCD1U25V2KX-L-GP
5V_S5
PG5142

2
1
0R0402-PAD 1 2

1
PR5114 PC5107 GAP-CLOSE-PWR-6-GP
287KR2F-GP SC1U10V2KX-L1-GP
PG5143

5
6
7
8
1 2

D
D
D
D
PU5108 GAP-CLOSE-PWR-6-GP
AON7410-GP
3D3V_S5 84.07410.A37 PG5144
PU5101 1 2
RT8231AGQW-GP 1ST = 84.07410.A37 GAP-CLOSE-PWR-6-GP

13

11

12
1

G
S
S
S
PR5111 074.08231.0073 PR5112 PC5108
10KR2F-L1-GP 2D2R3F-L-GP SCD1U50V3KX-L-GP
Design Current : 15.6A PG5145
2ND = 84.01528.037

CS

VID

VDD

4
3
2
1
PWR_DCBATOUT_VDDQ
DY OCP : 21.84A 1 2
18 PWR_VDDQ_BOOT 1 2 PWR_VDDQ_BOOT_A 1 2 GAP-CLOSE-PWR-6-GP
PR5113 1D2V_VTT_PWRGD BOOT
10

2
40 1D2V_VTT_PWRGD PGOOD
750KR2F-L-GP PG5146
Freq. setting PWR_VDDQ_TON PWR_VDDQ_HG
1 2 9 17 1 2
TON UGATE GAP-CLOSE-PWR-6-GP
750K -> 350K Hz PWR_VDDQ_EN PL5101 1D2V_PWR
8
S5 IND-1UH-94-GP-U PG5147
PWR_VTT_EN 7 16 PWR_VDDQ_PH 1 2 1 2
PG5115 S3 PHASE GAP-CLOSE-PWR-6-GP
68.1R01B.10K
1D2V_PWR 1 2 PWR_VDDQ_VLDOIN 19 2nd = 68.1R010.20I
VLDOIN PG5148
RF RESERVED
1
GAP-CLOSE-PWR-3-GP PC5109 15 PWR_VDDQ_LG 1 2
LGATE

5
6
7
8
PG5116 SC10U6D3V3MX-L-GP GAP-CLOSE-PWR-6-GP
Close to output cap pin1, not

D
D
D
D

1
1 2 PU5104 PC5110 PC5111 PC5112 PC5113 PC5114 FC5104 FC5103
2

inside of the output cap

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP
AON7506-GP DY DY PG5149

SCD1U25V2KX-L-GP

SCD1U25V2KX-L-GP
GAP-CLOSE-PWR-3-GP 1 14 84.07506.037 1 2

2
VTTGND PGND GAP-CLOSE-PWR-6-GP
PWR_VDDQ_VTT

SC22U6D3V5MX-L3-GP
PG5101

G
4 1ST = 84.07506.037

S
S
S
5 PWR_VDDQ_VDDQ 2 1 1D2V_PWR PG5150
PWR_2D5V_PG VDDQ
1 PR5108 2 0R0402-PAD PWR_VDDQ_EN 2ND = 84.01525.037 1 2

3
2
1
20 6 PWR_VDDQ_FB GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-6-GP
VTT FB
1

PC5106 2 PG5151
SCD1U16V2KX-L-GP VTTSNS

VTTREF
1 2
2

1
DY DY GAP-CLOSE-PWR-6-GP
S5

GND

GND
PR5116

1
15K4R2F-GP PC5115 PG5152
R1 SC18P50V2JN-1-GP 1 2
21

4
GAP-CLOSE-PWR-6-GP

2
PG5153

PWR_VDDQ_VTTREF
1 2
1 PR5119 2 0R0402-PAD PWR_VTT_EN GAP-CLOSE-PWR-6-GP
5 DDR_PG_OUT

PR5120 1 2 0R2J-L-GP
17,24,40,52,54 SIO_SLP_S3# R2
S3

1
DY PR5117
20KR2F-L3-GP

C C
Vout Setting

2
1

PC5116 Vout = Vref * ( 1 + R1/R2 )

SCD033U25V2KX-GP
= 0.675 * ( 1 + 15.8K / 20K)
2

= 1.2V

VID vs Vref Table

VID Logic-High => Vref = 0.675 V
VID Logic-Low => Vref = 0.75 V 2D5V_LDO 3D3V_S5
PD = (Vin Vout ) x Iout
= ( 3.3 - 2.5 ) x 0.3A = 0.24W
PWR_2D5V_LDO 2D5V_S3
Vout = 0.6V note. Vref can only be changed form PD de-rating(%) = 0.24W/1.33W = 18.0%
Iomax = 1.2A 0.675v to 0.75v after power-on PG5110 PG5112
1 2 1 2
0D6V_S0 PWR_VDDQ_VTT GAP-CLOSE-PWR-6-GP GAP-CLOSE-PWR-6-GP
PG5113
1 2 PG5111 PU5106 PG5119

1
GAP-CLOSE-PWR-6-GP 1 2 PC5130 PC5131 1 2
PWR_2D5V_PG 1 9 GAP-CLOSE-PWR-6-GP
PGOOD GND

1
SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP
PG5114 DY PWR_2D5V_S3_EN 2 8 PC5144 PC5143

2
GAP-CLOSE-PWR-6-GP PWR_2D5V_S3_LDO_PVDD 3 EN GND PWR_2D5V_S3_LDO_FB
1 2 7
VIN ADJ
1

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP
PC5117 PC5118 5V_S5 PWR_2D5V_S3_LDO_VDD 4 6

2
VDD VOUT
SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

5
GAP-CLOSE-PWR-6-GP NC#5
2

RT9025-25ZSP-2-GP

1
074.09025.003D PC5136
R1 PR5131

2
PR5130 24K3R2F-1-GP SC22P50V2JN-L-GP
2D2R2F-GP 1ST = 074.09025.003D

2
1 2
2ND = 74.09661.07D PWR_2D5V_S3_LDO_FB

1
PC5135 R2 PR5134

SC1U10V2KX-L1-GP
PWR_2D5V_S3_EN 11K3R2F-2-GP

2
SY8288 For DDR4

1
PC5139

SCD1U16V2KX-L-GP
Enable DY Vout Setting

Vout = 2.5V

2
EN_Logic-High = 1.4V Vout = 0.8 * ( 1 + R1/R2 )
EN_Logic-Low = 0.8V = 0.8 * ( 1 + 24.3 / 11.3K)
= 2.5204V

B B
PWR_DCBATOUT_2D5V
1

PC5142 PC5141 PC5140

SC4D7U25V5KX-L2-GP

SC4D7U25V5KX-L2-GP

SCD1U25V2KX-L-GP

DCBATOUT PWR_DCBATOUT_2D5V
2

DY DY DY PG5103
1 2
GAP-CLOSE-PWR-6-GP
3D3V_S5
PG5104
PR5137 PC5137 1 2
1

2D2R3F-L-GP SCD1U50V3KX-L-GP GAP-CLOSE-PWR-6-GP

PR5133 DY
1

100KR2J-1-GP PWR_2D5V_BOOT 1 2 PWR_2D5V_BOOT_A 1 2

PC5132
Design Current :4A
SC2D2U10V3KX-L-GP DY OCP : 7 A
2

2D5V_PWR 2D5V_S3
DY
PU5105 PL5102 2D5V_PWR
IND-1UH-94-GP-U
PWR_DCBATOUT_2D5V SY8288RAC_LDO_OUT 17 6 PWR_2D5V_PH 1 2 PG5105
VCC LX#6
LX#19
19 68.1R01B.10K 1 2
PWR_2D5V_PG 20 2nd = 68.1R010.20I GAP-CLOSE-PWR-6-GP
LX#20
2
IN#2 PG5106
3
IN#3 NC#10
10 DY DY
4 12 1 2
IN#4 NC#12
1

1
5 16 PC5150 PC5149 PC5148 PC5147 PC5151 PC5145 GAP-CLOSE-PWR-6-GP
IN#5 NC#16
SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SCD1U16V2KX-L-GP
PWR_2D5V_BOOT 1 PG5107
2

2
PWR_2D5V_PG BS
9 1 2
3D3V_S5 PWR_2D5V_S3_EN PG GAP-CLOSE-PWR-6-GP
11 7
PWR_2D5V_CS EN GND
13 8 Close to output cap pin1, not
PG5136 PWR_2D5V_FB ILMT GND PG5108
14 18
PWR_2D5V_BYP FB GND inside of the output cap
2 1 15 21 1 2
BYP GND GAP-CLOSE-PWR-6-GP
GAP-CLOSE-PWR-3-GP
SY8288RAC-GP PG5135
Reference OSLO & LT41S 20150724
1

PC5134 PWR_2D5V_FB_G 2 1 2D5V_PWR DY

SC1U10V2KX-L1-GP 074.08288.0043 DY DY DY DY
DY GAP-CLOSE-PWR-3-GP
2

DY
2

1 PR5135 2 0R0402-PAD PWR_2D5V_S3_EN

17,24,40 SIO_SLP_S4# PC5138
1

SC22P50V2JN-L-GP
1

PR5138 DY
1

PC5133 63K4R2F-2-GP PWR_2D5V_FB_A

SCD1U16V2KX-L-GP R1 DY
2

DY
2

PR5140
A 0R0402-PAD A
Enable
20150604 power modify
1

PWR_2D5V_FB

OCP setting R2
1

PR5139
20KR2F-L3-GP

PWR_2D5V_CS
DY
Vout Setting
2
2

Vout = Vref * ( 1 + R1/R2 )

PR5103
0R0402-PAD = 0.6 * ( 1 + 63.4K / 20K) <Core Design>

= 2.502 V
Wistron Corporation
1

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Current Limit Title
Low : OCP 8A
MEM&MEMVTT
Floating : OCP 12A Size Document Number Rev
A1
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 51 of 102

5 4 3 2 1
 A B C D E

VCCIO
+VCCIO(ICCMAX = 2.73A)
+VCCIO 1D0V_S5
5V_S5 1D0V_S5
Cyntec. 2.5mm×2.0mmX1.2mm
DCR: 59m Ohm
PU5203
Idc : 3 A , Isat : 3A
1 8
VIN#1 VOUT#8
2 7
VIN#2 VOUT#7
3 6
PWR_VCCIO_EN VBIAS VOUT#6
17,24,40,51,54 SIO_SLP_S3# 1 2 4 5
PR5216 0R2J-2-GP ON GND
9

1
PC5227 VIN#9
1 2 SC22P50V2JN-L-GP
40,46 VR_EN PR5218 0R2J-2-GP TPS22961DNYT-GP
DY

2
DY 074.22961.0093
Power modify 20140815
4 4

EOPIO and EDRAM 5V_S5 1D0V_S5

PU5204
PR5221
+V_EDRAM_VR
+V_EDRAM_VR
40 EN_EDRAM_VR 1 8 V_EDRAM_EOPIO_R 1 2 Voltage = 1.0 V ± 50 mV
VIN#1 VOUT#8 0R1206-PAD-1-GP
2 7
PR5217 3
VIN#2 VOUT#7
6 Imax = 6 A Imax = 3.2 A
EN_EDRAM_VR VBIAS VOUT#6 Rds on = 4.65mohm TRISE = 240 us
17,24,40,51,54 SIO_SLP_S3# 1 2 4 5
ON GND
0R2J-2-GP 23e 9 1D0V_S5
[#544669 Rev0.7] CRB: ALL_SYS_PWRGD_PMIC VIN#9
DY
[#543977 Rev0.7] PDDG: PM_SLP_S3# V_EDRAM_EOPIO_R
TPS22961DNYT-GP
074.22961.0093
PC5211
+V_EOPIO_VR

1
SCD1U16V2KX-L-GP
3 PC5210 3
Voltage = 1.0 V ± 50 mV

SC10U10V5KX-2GP
23e DY Imax = 2.8 A

2
TRISE = 240 us
V_EDRAM_EOPIO_R +V_EOPIO_VR

PR5222 2 1
1D0V_S5 0R1206-PAD-1-GP
1

PC5215 PC5216 PC5217

SC1U10V2KX-L1-GP SCD1U16V2KX-L-GP SC10U6D3V3MX-L-GP
2

23e DY DY

2 2

1 1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DCDC-0D975V_VCCIO
Size Document Number Rev
Custom
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 52 of 102
A B C D E
 5 4 3 2 1

Main Func = 1D0V

DCBATOUT PWR_DCBATOUT_1D0V
AOZ1268 for 1D0V
D D
PG5311 5V_S5
1 2

GAP-CLOSE-PWR-6-GP
PG5312
TDC : 10A

1
1 2 MAG. 7*7*3
PC5302

SC1U10V2KX-L1-GP
GAP-CLOSE-PWR-6-GP DCR: 8.9m +/-7% Ohm

2
PG5313
1 2 Idc : 11 A , Isat : 22A
PWR_DCBATOUT_1D0V PU5301 1D0V_S5
GAP-CLOSE-PWR-6-GP
PL5301
21 18 PWR_1D0V_LX 1 2 IND-1UH-94-GP-U PC5303 PC5305 PC5301 PC5316 PC5318 PC5306 PC5307
VCC LX#18
LX#17
17 68.1R01B.10K

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SCD1U25V2KX-L-GP
16 2nd = 68.1R010.20I 11/25 JAIME
LX#16
11
LX#11

1
7 10
IN#7 LX#10

2
8 PC5304
IN#8

PC5308
C PR5301 9 20 PWR_1D0V_BOOT
1 2 SCD1U25V2KX-L-GP PG5315 C

2
93K1R2F-L-GP IN#9 BST
PWR_1D0V_FB GAP-CLOSE-PWR-6-GP
DY DY
5

1
FB

1
PC5309 PC5312 PC5317 1 2 PWR_1D0V_TON 6
TON

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
SCD1U25V2KX-L-GP
PWR_1D0V_PG 1 4

2
PGOOD AGND PWR_1D0V_VFB1
PWR_1D0V_EN 2 19
EN PGND
14
PWR_1D0V_PFM PGND
3 13
PFM# PGND
PGND
12 DY

1
PWR_1D0V_SS 22 15
SS PGND PR5302 PC5319

SC220P50V2KX-3GP
2K8R2F-GP
R1

2
PR5303 AOZ2262QI-10-GP-U

1
100KR2F-L1-GP 074.02262.0043

2
PC5313
SCD01U50V2KX-L-GP

2
PWR_1D0V_LX

B 3D3V_S5 B

1
1 PR5305 2 10KR2J-3-GP

1
PR5304
11/07 jaime 10K2R2F-GP R2 Vo=0.8x(1+R1/R2) RFC5301
0R0402-PAD SC8P50V2DN-1GP

2
1 PR5306 2 PWR_1D0V_PG =0.8x(1+8.06/31.6) DY

2
40 RSMRST_PWRGD#
=1.004
0R0402-PAD
54 PWR_1D8V_PWRGD# 1 PR5312 2 PWR_1D0V_EN
1

PC5314
SC1KP50V2KX-L-1-GP
2

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DCDC-V1D00A
Size Document Number Rev
Custom
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 53 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = 1D5V

3D3V_S5
S-1339D18for 1D8V_S0

1
PC5408
SC1U10V2KX-L1-GP

2
Design Current = 16mA

PU5402 1D8V_PWR_AUDIO 1D8V_S0

PG5404
D 1 5 1 2 D
VIN VOUT
2
VSS
17,24,40,51,52 SIO_SLP_S3# 1 2PWR_1D8V_EN_AUDIO 3 4 GAP-CLOSE-PWR-6-GP
ON/OFF NC#4
PR5405 PC5407

1
0R0402-PAD DY S-1339D18-N5T3U3-GP
PC5409

SCD1U16V2KX-3GP
SC1U10V2KX-L1-GP
074.01339.0B3F

2
3D3V_S5

1
PR5414
11/07 jaime 100KR2F-L1-GP

1D8V_S5 Design Current = 665mA

2
1 PR5416 2 0R0402-PAD
53 PWR_1D8V_PWRGD#
C 3D3V_S5 C
1D8V_PWR 11/25 jaime 1D8V_S5
PG5401 PG5405
GAP-CLOSE-PWR-6-GP GAP-CLOSE-PWR-6-GP
1 2 1 2

PG5402 PG5406
GAP-CLOSE-PWR-6-GP PU5401 GAP-CLOSE-PWR-6-GP
1

1 2 PC5406 PC5402 1 2
SC10U6D3V3MX-L-GP

SC22P50V2JN-L-GP

PC5401 PWR_1D8V_POK 1 9

1
PGOOD GND
SC1U10V2KX-L1-GP

11/25 jaime PWR_1D8V_EN 2 8 PC5410 PC5411 PG5407

2

PWR_1D8V_S5_PVDD EN GND 1.8V_RUN_FB GAP-CLOSE-PWR-6-GP

3 7
VIN ADJ

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP
PWR_1D8V_S5_VDD 4 6 1 2

2
VDD VOUT
5
NC#5

RT9025-25ZSP-2-GP

1
PC5405
074.09025.003D PR5406 SC22P50V2JN-L-GP
R1 12K7R2F-GP

2
5V_S5 PR5408 1ST = 074.09025.003D
2D2R2F-GP

2
1 2 2ND = 74.09661.07D
1.8V_RUN_FB
PC5421
1

1
SC1U10V2KX-L1-GP

R2 PR5403
2

10KR2F-L1-GP

2
Vout Setting
Vout = 0.8 * ( 1 + R1/R2 )
1 PR5407 2 0R0402-PAD PWR_1D8V_EN = 0.8 * ( 1 + 12K7 / 10K)
17,45 3V_5V_POK
= 1.816V
1

B PC5404 11/28 jaime B

SC22P50V2JN-L-GP
PR5409 1 2 0R2J-L-GP DY
2

40,45 3V_EN

DY

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DCDC V1D8V
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 54 of 102
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
SSID = VIDEO LCD POWER (Do Not use SW 74.09724.09F)
INVERTER POWER Close to eDP connector
LCD_BRIGHTNESS
2014/2/5:Change U5201 to 074.06288.007B
DCBATOUT_LCD 3D3V_S0
Layout 40 mil LCDVDD
DCBATOUT
F5501 U5501
2 1
5 1
POLYSW-1D1A24V-GP-U R5507 IN OUT
2
1

1
C5506 C5504 C5505 C5511 EC5502 LCDVDD_EN GND
1 2 4 3

SC33P50V2JN-3GP
8 EDP_VDD_EN EN OC#
SC4D7U25V5KX-L2-GP

SC1KP50V2KX-1GP

SCD1U50V3KX-GP

SC68P50V2JN-1GP
DY
DY 69.50007.A31 DY

1
0R0402-PAD C5508
2

1
FC5501 SY6288C20AAC-GP

SC33P50V2JN-3GP
D D

SC4D7U6D3V3KX-GP
1
1ST = 69.50007.A31 DY

2
1

1
SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
C5509 C5507
074.06288.007B

2
R5514
2ND = 69.50007.A41 100KR2J-1-GP
DY

2
2
eDP Device
Panel BL brightness/Power En/BL En
R5510
Item Device 8 L_BKLT_EN
1 2 PANEL_BLEN 24
0R0402-PAD
1 EMB_HPD_R R5503
eDP Panel BLON_OUT_C
24 BLON_OUT 1 21KR2J-1-GP

2
2 Camera R5516
3 DMIC 100KR2F-L1-GP

1
R5508

1
SC100P50V2JN-3GP
5 1 2 L_BKLT_CTRL_1 C5510
8 L_BKLT_CTRL 0R0402-PAD

eDP connector

1
6

2
R5532
R5530 100KR2J-1-GP
100KR2J-1-GP DY

2
DCBATOUT_LCD

1
EDP1 C5527
31 SC100P50V2JN-3GP
1

2
C C
2
3
4 R5515
5 LCD_BRIGHTNESS 1 2 L_BKLT_CTRL_1
6 BLON_OUT_C 33R2J-2-GP
7
8
9
DMIC_DATA 27
DMIC_CLK 27
DMIC Test point
10
11 USB_PN4_R
12 USB_PP4_R Camera
13
14 eDP_AUXN_CPU_C C5528 1
eDP_AUXP_CPU_C C5526 1
2 SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
eDP_AUX_CPU_N 8
Layout 40 mil CAMERA POWER
15 2 eDP_AUX_CPU_P 8
16 3D3V_CAMERA_S0 3D3V_S0 1 AFTP5525
17 eDP_TXN1_CPU_C C5514 1 2 DYSCD1U16V2KX-L-GP R5518
18 eDP_TXP1_CPU_C C5513 1 2 DYSCD1U16V2KX-L-GP
eDP_TX_CPU_N1 8
eDP_TX_CPU_P1 8
eDP Panel 1 2
19 0R0603-PAD LCDVDD_R 1 AFTP5501
20 eDP_TXN0_CPU_C C5532 1 2 SCD1U16V2KX-L-GP U5504
eDP_TX_CPU_N0 8
21 eDP_TXP0_CPU_C C5529 1 2 SCD1U16V2KX-L-GP R5522
eDP_TX_CPU_P0 8
22 1 DY 2 3D3V_S0_CAMERA 1 5 DCBATOUT_LCD 1 AFTP5535
EMB_HPD_R OUT IN BLON_OUT_C
23 1 2 R5542 EDP_HPD 8 0R3J-0-U-GP 2 1 AFTP5543
EDP_DCR_EN 0R0402-PAD GND LCD_BRIGHTNESS 1 AFTP5542
24 3 DY 4 CAMERA_EN 20

1
3D3V_CAMERA_S0 C5531 OC# EN
25
26 DMIC1_VCC SC10U6D3V3MX-L-GP

1
27 G524B1T11U-GP C5530

2
28 074.00524.0B9F SC10U6D3V3MX-L-GP
29 R5528 DY

2
1

LCDVDD_R C5523 C5525

30 1 2 LCDVDD 2ND = 74.06288.07F
SCD1U16V2KX-L-GP

SC1U10V2KX-L1-GP

32 0R0603-PAD EDP_DCR_EN 1 AFTP5538

DY
2

2
1

C5522 C5524
SCD1U16V2KX-L-GP

SC1U10V2KX-L1-GP

ACES-CON30-20-GP-U
20.K0848.030 R5509
2

USB_PN4_R 1 2 USB_CPU_PN4
USB_CPU_PN4 16
1ST = 20.K0848.030 10/20 AFTP5503, AFTP5504 USB_PN3, USB_PP3 change to USB_PN3_R, USB_PP3_R
0R2J-L-GP
2ND = 20.K0809.030 R5506
08/18 add C5523(0.1uF), C5525(1uF) USB_PP4_R 1 2 USB_CPU_PP4
USB_CPU_PP4 16
B
3RD = 020.K0160.0030 B
0R2J-L-GP 1 AFTP5541

EMB_HPD_R 1 AFTP5545
eDP_TXP0_CPU_C 1 AFTP5546
R5531 eDP_TXN0_CPU_C 1 AFTP5547
3D3V_S0 3D3V_S0 eDP_TXP1_CPU_C 1 AFTP5548
0R0402-PAD eDP_TXN1_CPU_C 1 AFTP5549
DMIC1_VCC 1 2 eDP_AUXP_CPU_C 1 AFTP5550
ED5507 eDP_AUXN_CPU_C 1 AFTP5551
1
SCD1U16V2KX-3GP

C5534 DMIC_DATA 1 6 USB_PP4_R

2

2 5

DMIC_CLK 3 4 USB_PN4_R

AZC199-04S-R7G-GP

75.00199.07C

1ST = 75.00199.07C

2ND = 75.00005.D7C

DY

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
LCD&CAM&DMC&Touch
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 55 of 102
5 4 3 2 1
 5 4 3 2 1

5V_CRT_S0_R

1
C5602 5V_S0
EMI Request SCD1U16V2KX-L-GP

2
CRT
CRT ED5603
1 2 CRT_DDCDATA_CON CRT1 5V_CRT_S0_R 1
CRT_DDCDATA_CON 1 AFTP5601
ESD5B5D0ST1G-GP-U 9 4 CRT_DDCCLK_CON 1 AFTP5602 ED5602
ED5604 VCC_CRT NC#4 CRT_R AFTP5603
CRT CRT_DDCCLK_CON NC#11
11
CRT_G
1
AFTP5604 CRT_VSYNC_CON 5V_CRT_S0_R 5V_CRT_S0 5V_S0
1 2 1 1 6
D 12 CRT_B 1 AFTP5605 D
DDCDATA_ID1 D5601
ESD5B5D0ST1G-GP-U 15 CRT_VSYNC_CON 1 AFTP5606
DDCCLK_ID3 F5601
ED5605 CRT_HSYNC_CON AFTP5607
CRT CRT_R GND
5 1
AFTP5608
2 5
1 2 1 6 2 1 K A
CRT_G CRT_RED GND
ESD5B5D0ST1G-GP-U CRT_B
2
CRT_GREEN GND
7
CRT_HSYNC_CON
75.00099.07C FUSE-1D1A6V-8GP
3 8 3 4
ED5606 CRT_BLUE GND RB551VM-30TE-17-GP
CRT CRT_VSYNC_CON 14 GND
10
1 2 16 CRT CRT

1
CRT_HSYNC_CON 13 VSYNC GND FC5603
17

SC33P50V2JN-3GP
HSYNC GND BAV99S-4-GP
ESD5B5D0ST1G-GP-U
DY 83.R5003.N8F
CRT ED5607 CRT

2
1 2 D-SUB-15-148-GP-U3 1ST = 83.R5003.N8F
ESD5B5D0ST1G-GP-U
20.20978.015
near CRT conn 2nd = 83.55130.08F
CRT ED5608 CRT
1 2

ESD5B5D0ST1G-GP-U 05/12 Add FC5603 for RF.

CRT ED5609
1 2

ESD5B5D0ST1G-GP-U

DP_CRT_HSYNC_CON R5620
CRT CRT_HSYNC_CON
1 2 47R2J-2-GP

L5601
DP_CRT_VSYNC_CON R5621
CRT CRT_VSYNC_CON
CRT 1 2 47R2J-2-GP
DP_CRT_R 1 2 CRT_R CRT_DDCDATA_CON
CRT_DDCCLK_CON
BLM18BB220SN-GP CRT_VSYNC_CON
CRT_HSYNC_CON

L5602
DP_CRT_G
CRT CRT_G
1 2

1
SC100P50V2JN-3GP

SC100P50V2JN-3GP
C5603 C5604 C5605 C5606

SC33P50V2JN-3GP

SC33P50V2JN-3GP
BLM18BB220SN-GP DY DY CRT CRT CRT_HPD_PCH

2
CRT_HPD_PCH 8
C C
L5603
CRT 04/23 Change Net Name to CRT_HPD_PCH

1
DP_CRT_B 1 2 CRT_B
5V_CRT_S0 R5611
BLM18BB220SN-GP 100KR2J-4-GP
CRT

2
1

1
C5610 C5611 C5612
LAYOUT NOTE:
1

R5617 R5618 R5619 C5607 C5608 C5609 CRT CRT CRT

2
1
CRT CRT CRT CRT CRT CRT
75R3F-GP

75R3F-GP

75R3F-GP

SC2P50V2CN-GP

SC2P50V2CN-GP

SC2P50V2CN-GP
All cap need close to chip
2

RN5604
SC2P50V2CN-GP

SC2P50V2CN-GP

SC2P50V2CN-GP
2

SRN2K2J-5-GP
2

especially C616 close pin5 CRT

C618 and C619 close pin19

3
4
C620 and C621 close pin9 CRT_DDCDATA_CON

C617 close pin20 CRT_DDCCLK_CON

C614 close pin25

C613 lose pin24
3D3V_S0 AVCC33
5V_S0 HVSYNC_POWER
L5605
1 2 R5630 1 2
1

MHC1005S600LBP-GP 0R0402-PAD
1

CRT C5615 C5640 C5641

SC10U10V5KX-L1-GP SC4D7U6D3V3KX-GP SCD1U16V2KX-L-GP
2

CRT CRT CRT U5602

2

B CRT C5614 1 2 SCD1U16V2KX-L-GP VCCK_12 4 2 PCH_DPC_AUXP_C SCD1U16V2KX-L-GP 2 1 C5634 CRT B

CRT AVCC_12 AUX_P PCH_DPC_AUXN_C CRT PCH_DPC_AUXP 8
C5618 1 2 SCD1U16V2KX-L-GP 3 SCD1U16V2KX-L-GP 2 1 C5623
CRT AUX_N PCH_DPC_AUXN 8
C5632 1 2 SC2D2U10V3KX-L-GP 25
3D3V_S0 VDD_DAC_33 CRT C5631 1 SC10U6D3V3MX-L-GP VCCK_12 PCH_DPC_P0_C SCD1U16V2KX-L-GP CRT
2 5 2 1 C5624 PCH_DPC_P0 8
CRT C5613 1 SCD1U16V2KX-L-GP AVCC33 LANE0_P PCH_DPC_N0_C SCD1U16V2KX-L-GP CRT
2 1 6 2 1 C5625 PCH_DPC_N0 8
AVCC_33 LANE0_N PCH_DPC_P1_C SCD1U16V2KX-L-GP CRT
L5606 7 2 1 C5627 PCH_DPC_P1 8
CRT C5616 1 3D3V_S0 LANE1_P PCH_DPC_N1_C CRT
2 SCD1U16V2KX-L-GP 14 8 SCD1U16V2KX-L-GP 2 1 C5628 PCH_DPC_N1 8
VCC_33 LANE1_N
1 2
CRT C5620 1 2 SCD1U16V2KX-L-GP VDD_DAC_33 20 17 HVSYNC_POWER
1

MHC1005S600LBP-GP CRT C5633 1 VDD_DAC_33 HVSYNC_PWR DP_CRT_HSYNC_CON

2 SC10U10V5KX-L1-GP 19
C5626 CRT C5617 1 3D3V_S0 HSYNC DP_CRT_VSYNC_CON
CRT 2 SCD1U16V2KX-L-GP 26 18
SC10U10V5KX-L1-GP PVCC_33 VSYNC
2

DP_CRT_B
CRT CRT_DDCCLK_CON BLUE_P
21
DP_CRT_G
15 22
CRT_DDCDATA_CON VGA_SCL GREEN_P DP_CRT_R
16 23
VGA_SDA RED_P
DDPC_CLK 30 27
DDPC_DATA SMB_SCL LDO_RSTB RTD2166_EXT_CLK_IN
29 28
SMB_SDA EXT_CLK_IN
31
RTD2166_GPI1 EXT1.2V_CTRL CRT_HPD_PCH
11 32
3D3V_S0 3D3V_S0 RTD2166_GPI2 GPI1/SPI_CLK HPD
12
GPI2/SPI_SI
13
GPI3/SPI_SO
24
3D3V_S0 3D3V_S0 POL1 GND
10 33
POL2 POL1/SPI_CEB GND
9
RTD2166_EXT_CLK_IN POL2
1

R5625
RTD2166-CGT-GP
1

R5623 R5622 4K7R2J-L-GP

1

R5616 R5624 R5614 R5615 DY 071.02166.0003

4K7R2J-L-GP 4K7R2J-L-GP
2

DY CRT 4K7R2J-L-GP 4K7R2J-L-GP 4K7R2J-L-GP 4K7R2J-L-GP CRT

DY DY DY DY
2

POL1 POL2

RTD2166_GPI1
DDPC_CLK 8
1

R5608 R5609
DDPC_DATA 8
RTD2166_GPI2
A 4K7R2J-L-GP 4K7R2J-L-GP A

CRT DY 04/23 Change Net Name to DDPC_CLK

2

04/23 Change Net Name to DDPC_DATA

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CRT
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 56 of 102

5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO HDMI CONNECTOR 3D3V_S0

AFTP5701 1 HDMI_DATA2_R_C 5V_S0 5V_CRT_PH
AFTP5702 1 HDMI_DATA2_R_C#
AFTP5703 1 HDMI_DATA1_R_C R5721 5V_HDMI

2
AFTP5704 1 HDMI_DATA1_R_C# 1 2 0R3J-0-U-GP
AFTP5705 1 HDMI_DATA0_R_C HDMI1 R5720
AFTP5706 1 HDMI_DATA0_R_C# D5702 69.48001.081 10KR2J-3-GP
AFTP5707 1 HDMI_CLK_R_C A K F5701 1 2 5V_HDMI 18 15 DDC_CLK_HDMI
AFTP5708 HDMI_CLK_R_C# +5V_POWER SCL DDC_DATA_HDMI
1 16

1
AFTP5709 DDC_CLK_HDMI SDA
1 B0530WS-7-F-GP DY

1
AFTP5710 1 DDC_DATA_HDMI DY HDMI_DATA0_R_C 7
AFTP5711 5V_HDMI POLYSW-1D1A6V-9-GP-U C5701 HDMI_DATA0_R_C# TMDS_DATA0+ HDMI_CEC AFTP5714
HDMI Passive Level Shifter AFTP5712
1
1 HPD_HDMI_CON
83.R5003.G8H HDMI_DATA1_R_C
9
4
TMDS_DATA0- CEC
13
17
1

2
AFTP5713 R5704 SCD1U16V2KX-L-GP HDMI_DATA1_R_C# TMDS_DATA1+ DDC/CEC_GROUNG HPD_HDMI_CON
D 1 2 1 6 19 D
0R3J-0-U-GP HDMI_DATA2_R_C TMDS_DATA1- HOT_PLUG_DETECT
Close to HDMI Connector HDMI_DATA2_R_C#
1
TMDS_DATA2+
DY 3
TMDS_DATA2- RESERVED#14
14

8
TMDS_DATA0_SHIELD
5
TMDS_DATA1_SHIELD
2
TMDS_DATA2_SHIELD
20
GND
8 HDMI_CLK
C5702 1 2 SCD1U16V2KX-L-GP HDMI_CLK_C 11 21
TMDS_CLOCK_SHIELD GND
8 HDMI_CLK#
C5703 1 2 SCD1U16V2KX-L-GP HDMI_CLK_C# HDMI_CLK_R_C 10 22
HDMI_CLK_R_C# TMDS_CLOCK+ HDMI GND
12 23
TMDS_CLOCK- GND
8 HDMI_DATA0#
C5704 1 2 SCD1U16V2KX-L-GP HDMI_DATA0_C# (A_Type)
8 HDMI_DATA0
C5705 1 2 SCD1U16V2KX-L-GP HDMI_DATA0_C
SKT-HDMI23-156-GP-U
8 HDMI_CRT_P1
C5706 1 2 SCD1U16V2KX-L-GP HDMI_DATA1_C
8 HDMI_CRT_N1
C5707 1 2 SCD1U16V2KX-L-GP HDMI_DATA1_C# 022.10025.00J1
8 HDMI_CRT_N0
C5708 1 2 SCD1U16V2KX-L-GP HDMI_DATA2_C# ESD STUFF OPTION
8 HDMI_CRT_P0
C5709 1 2 SCD1U16V2KX-L-GP HDMI_DATA2_C HDMI_DATA2_R_C R5706 1 2 HDMI_DATA2_R_C# 1ST = 022.10025.00J1
150R2F-4-L-GP ESD STUFF OPTION
HDMI_DATA1_R_C R5707 1 2 HDMI_DATA1_R_C#
150R2F-4-L-GP ESD STUFF OPTION 2ND = 022.10025.00L1
HDMI_DATA0_R_C R5708 1 2 HDMI_DATA0_R_C#
150R2F-4-L-GP ESD STUFF OPTION 3RD = 022.10025.00K1

5
6
7
8

5
6
7
8
HDMI_CLK_R_C R5709 1 2 HDMI_CLK_R_C#
RN5705 RN5706 150R2F-4-L-GP
SRN470J-5-GP SRN470J-5-GP

4
3
2
1

4
3
2
1
5V_CRT_PH Q5704 5V_S0
HDMI_PLL_GND AO3413L-GP

S D

HDMI DDC Passive Level Shifter 5V_S0 DY 84.03413.B31

G
1

1
C5710

SC4D7U6D3V3KX-GP

SCD1U16V2KX-L-GP
C5711
DY

2Q5105_VDD_EN#
C D5701 DY C

2
BAW56-5-GP

83.00056.Q11

1
1ST = 83.00056.Q11
HDMI A type pin define

DDC_DATA_HDMI_R

2
DDC_CLK_HDMI_R
2ND = 75.00056.07D
R5713 R5714
10KR2J-3-GP
DY
10KR2J-3-GP
DY
(Total: 19pin)

1
3D3V_S0
Q5101_VDD_EN#
1

3D3V_S0

D
3
4
R5701 EC5701 Q5705
1

Q5701 1MR2J-1-GP 3D3V_S0 RN5707

Notice:ZZ.2N702.J3101
1 6 HDMI_PLL_GND SRN2K2J-5-GP
84.2N702.J31 DY
2

2 SCD1U16V2KX-L-GP

2 5
2ND = 84.2N702.031

2
1
HPD_HDMI_CON 3 4 CPU_DP1_HPD 8 3rd = 84.2N702.W31 2N7002K-2-GP

G
Q5703 5V_S0
2N7002KDW-GP 1 6 DDC_DATA_HDMI
8 CPU_DP1_CTRL_DATA
1

84.2N702.A3F
R5703 2nd = 075.063D1.007C 2 5
100KR2J-1-GP
3 4
2

HPD_HDMI_CON_R 2N7002KDW-GP 禁待) to 84.2N702.J31

07/02 Change Part Number 84.07002.I31(禁
1

84.2N702.A3F DDC_CLK_HDMI
R5712 2nd = 075.063D1.007C
0R0402-PAD 8 CPU_DP1_CTRL_CLK
2

B ED5701 B

HDMI_DATA2_R_C 1 10 HDMI_DATA2_R_C

HDMI_DATA2_R_C# 2 9 HDMI_DATA2_R_C#
3 8
HDMI_DATA0_C 1 R5705 2 HDMI_DATA0_R_C HDMI_DATA1_C 1 R5718 2 HDMI_DATA1_R_C
0R0402-PAD 0R0402-PAD HDMI_DATA1_R_C 4 7 HDMI_DATA1_R_C

HDMI_DATA1_R_C# 5 6 HDMI_DATA1_R_C#

L05ESDL5V0NA-4-GP
075.00550.0071
2ND = 75.01043.073
EMI TEST
HPD_HDMI_CON DDC_CLK_HDMI DDC_DATA_HDMI
HDMI_DATA0_C# 1 R5715 2 HDMI_DATA0_R_C# HDMI_DATA1_C# 1 R5719 2 HDMI_DATA1_R_C# ED5702
0R0402-PAD 0R0402-PAD
HDMI_CLK_R_C 1 10 HDMI_CLK_R_C

HDMI_CLK_R_C# 2 9 HDMI_CLK_R_C#
EMI Request
3 8

1
HDMI_CLK_C 1 R5710 2 HDMI_CLK_R_C HDMI_DATA2_C 1 R5711 2 HDMI_DATA2_R_C HDMI_DATA0_R_C 4 7 HDMI_DATA0_R_C ED5705 ED5703 ED5704
0R0402-PAD 0R0402-PAD VARISTOR-27V-2-GP VARISTOR-27V-2-GP VARISTOR-27V-2-GP
HDMI_DATA0_R_C# HDMI_DATA0_R_C#
5 6 69.80005.081 69.80005.081 69.80005.081
EMI TEST DY DY

2
L05ESDL5V0NA-4-GP
075.00550.0071
2ND = 75.01043.073
EMI TEST

ED5706
HDMI_CLK_C# 1 R5717 2 HDMI_CLK_R_C# HDMI_DATA2_C# 1 R5716 2 HDMI_DATA2_R_C#
0R0402-PAD 0R0402-PAD DDC_CLK_HDMI 1 10 DDC_CLK_HDMI
A A
DDC_DATA_HDMI 2 9 DDC_DATA_HDMI
3 8

HPD_HDMI_CON 4 7 HPD_HDMI_CON

HDMI_CEC 5 6 HDMI_CEC <Core Design>

L05ESDL5V0NA-4-GP Wistron Corporation

075.00550.0071 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2ND = 75.01043.073 Taipei Hsien 221, Taiwan, R.O.C.

EMI TEST Title

HDMI
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 57 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DP
Size Document Number Rev
A1
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 58 of 102

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Demultiplexer
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 59 of 102
5 4 3 2 1
 5 4 3 2 1

HDD1
SSID = SATA 5V_S0_HDD
AFTP6001 1 HDD_CON_P1 P1 16
AFTP6002 HDD_CON_P2 V33 16
1 P2 17
V33 17
16 DEVSLP0_HDD_CON 1 R6002 2HDD_CON_P3 P3
R6001 0R0402-PAD V33 ED6001
1 2 5V_S0_HDD P7
5V_S0 V5
0R0805-PAD P8 8520B_SATA_TXP0_C 1 10 8520B_SATA_TXP0_C

1
V5
P9
C6005 C6006 C6007 V5 8520B_SATA_TXN0_C 8520B_SATA_TXN0_C
2 9
SC10U25V5KX-L-GP SCD1U16V2KX-L-GP SC18P50V2JN-1-GP AFTP6003 1 HDD_CON_P13 P13 S1 3 8

2
AFTP6004 HDD_CON_P14 V12 GND
DY AFTP6005
1
HDD_CON_P15
P14
V12 GND
S4
8520B_SATA_RXN0_C 8520B_SATA_RXN0_C
1 P15 S7 4 7
V12 GND
P4
GND 8520B_SATA_RXP0_C 8520B_SATA_RXP0_C
E P5 5 6 E
SCD01U50V2KX-L-GP 8520B_SATA_TXP0_C GND
2 1C6001 S2 P6
16 SATA_TX_CPU_P0 SCD01U50V2KX-L-GP 8520B_SATA_TXN0_C TX+ GND
2 1C6002 S3 P10
16 SATA_TX_CPU_N0 TX- GND L05ESDL5V0NA-4-GP
P12
SCD01U50V2KX-L-GP 8520B_SATA_RXP0_C GND
2 1C6004 S6 R6008
16 SATA_RX_CPU_P0 SCD01U50V2KX-L-GP 8520B_SATA_RXN0_C RX+ DAS1
2 1C6003 S5 P11 2
16 SATA_RX_CPU_N0 RX- DAS/DSS 075.00550.0071
SATA_HDD 0R0402-PAD
SKT-SATA7P-15P-195-GP
2ND = 75.01043.073
022.10014.0101

3D3V_S0 5V_S0 3D3V_S0 1ST = 022.10014.0101

2ND = 022.10014.0131
1

1
R6005 R6006 R6007
100KR2J-1-GP 100KR2J-1-GP 47KR2J-2-GP
DY DY DY
2

2
3D3V_S0
ODD_PWRGT# SATA_ODD_DA#_C SATA Zero Power ODD
SUPPORT ZERO SATA ODD
5V_S0 PG6001 1 2 GAP-CLOSE-PWR-6-GP
1

2
1
6

R6009 RN6001 R6004

Q6001 DY 0R2J-2-GP SRN10KJ-5-GP PG6002 1 2 GAP-CLOSE-PWR-6-GP ODD_PWR_5V_IN 1 2 0R0805-PAD ODD_PWR_5V
2N7002KDW-GP
DY

1
D U6001 D
84.2N702.A3F DY Current limit
2

C6008 PG6003 1 2 GAP-CLOSE-PWR-6-GP

1

3
4
2nd = 075.063D1.007C SC10U25V5KX-GP 5 Active High

2
OC#
ODD 4
EN OUT#6
6 typ =>2A
SATA_ODD_DA# 16 3 7
IN#3 OUT#7
2 8 100 mil
IN#2 OUT#8
1 9
SATA_ODD_DA# SATA_ODD_DA# GND GND
19 SATA_ODD_PWRGT SATA_ODD_PWRGT

1
G548A1F51U-GP
DY C6009
SATA_ODD_PWRGT GPIO setting change to NC SC1U10V2KX-1GP

2
2016/4/21 74.00548.A79 ODD

2015/10/3
Change Switch IC to 74.00548.A79

ODD_PWR_5V
Need check PIN Define
ODD1

P2 P4 SATA_ODD_DA#_C
+5V MD SATA_ODD_PRSNT#
P3 P1 SATA_ODD_PRSNT# 16
+5V DP
C ODD14 C

1
S1
SATA_TX_CPU_N1 C6016 SATA_TX_CPU_N1_C2 GND
1 2 SCD01U50V2KX-L-GP S3 S4 R6003
SATA_TX_CPU_P1 C6017 SATA_TX_CPU_P1_C2 A- GND
1 2 SCD01U50V2KX-L-GP S2 S7 10KR2J-3-GP
A+ GND
ODD14 ODD14 GND
P5
P6
DY

2
SATA_RX_CPU_N1 C6014 SATA_RX_CPU_N1_C2 GND
1 2 SCD01U50V2KX-L-GP S5 14
SATA_RX_CPU_P1 C6015 SATA_RX_CPU_P1_C2 B- GND
1 2 SCD01U50V2KX-L-GP S6 15
B+ GND

ODD14 NP1
NP1
NP2
NP2

SKT-SATA7P-6P-123-GP
22.10300.H81 ED6002

SATA_TX_CPU_P1_C2 SATA_TX_CPU_P1_C2
ODD14 1 10
1ST = 22.10300.H81 SATA_TX_CPU_N1_C2 SATA_TX_CPU_N1_C2
2 9
2ND = 22.10300.H31 3 8

SATA_RX_CPU_N1_C2 SATA_RX_CPU_N1_C2
OAD1
3RD = 22.10300.H61 4 7

SATA_RX_CPU_P1_C2 5 6 SATA_RX_CPU_P1_C2
ODD15 14
16 SATA_TX_CPU_P1 ODD15 SCD01U50V2KX-L-GP 2 1 C6010 SATA_TX_CPU_P1_C1 12
16 SATA_TX_CPU_N1 SCD01U50V2KX-L-GP 2 1 C6011 SATA_TX_CPU_N1_C1 11 L05ESDL5V0NA-4-GP
ODD15 10
16 SATA_RX_CPU_N1 SCD01U50V2KX-L-GP 2 1 C6012 SATA_RX_CPU_N1_C1 9
16 SATA_RX_CPU_P1 ODD15 SCD01U50V2KX-L-GP 2 1 C6013 SATA_RX_CPU_P1_C1 8 075.00550.0071
7
16 SATA_ODD_PRSNT# R6010 1 2 0R2J-2-GP SATA_ODD_PRSNT#_ODD15
SATA_ODD_DA#_C
6 ODD15 2ND = 75.01043.073
5
B DY 4 B
ODD_PWR_5V 3 LV115
2

1
13

ACES-CON12-21-GP-U

20.K0422.012
1ST = 20.K0422.012
2ND = 20.K0391.012

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SATA IF_HDD/ODD
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 60 of 102
5 4 3 2 1
 5 4 3 2 1

3D3V_S5 3D3V_WLAN

AOAC
Q6103 3D3V_S0 3D3V_WLAN 3D3V_WLAN

1
AO3413L-GP

100KR2J-1-GP
1
C6111 S D 1 R6121 2

SCD1U16V2KX-L-GP
R6102
AOAC 84.03413.B31 0R0603-PAD

1
AOAC C6112 C6113 C6110

SCD1U16V2KX-L-GP

SC1U10V2KX-L1-GP

SC10U6D3V3MX-GP
10/16 R6121 原原原NON_AOAC, 改原DUMMY PAD

2
D D
WLAN_PWRON#_C 10/20 R6121 改改原原原NON_AOAC DY

1
AOAC R6125 AOAC Change to 100K (TBC)

1
10KR2J-3-GP
Q6101 R6126

2
3 WLAN_PWRON#
1 R1 100KR2J-1-GP
24 WLAN_PWRON
2

2
R2
SB LTC024EUB-FS8-GP
84.00024.A1K
1
100KR2J-1-GP

DY
R6127 AOAC
2

3D3V_WLAN

WLAN1

76 77
76 77
74 75
3_3VAUX GND
72 73
3_3VAUX RESERVED#73
70 71
RESERVED#70 RESERVED#71
68 69
RESERVED#68 GND
66
64
RESERVED#66 RESERVED#67/2ND_LANE_PERN1
67
65
06/27 WLan1 不不待62.10043.I91, 此待 1ST 062.10007.0291 , 2nd 062.10007.0251
GPIO0_NFC_RESET#/MGPIO7 RESERVED#65/2ND_LANE_PERP1
62 63
NFC_I2C_IRQ/MGPIO5 GND
60 61
NFC_I2C_SM_CLK RESERVED#61/2ND_LANE_PETN1
58 59
NFC_I2C_SM_DATA RESERVED#59/2ND_LANE_PETP1
24 WIRELESS_EN 56 57
W_DISABLE#1 GND
C
19 BT_DISABLE# 1 R6110 2 BT_DISABLE#_R 54 55 PCIE_WAKE#_1 1 R6108 2 WLAN_PCIE_WAKE# 24 C
0R0402-PAD RESERVED#54/W_DISABLE#2 PEWAKE0# PCIE_CLK_WLAN_REQ#_R 0R0402-PAD
17,24,31,40,68,76 PLT_RST# 52 53
PERST0# CLKREQ0#
18 PCH_SUSCLK_KBC 1 2 PCH_SUSCLK_KBC_R 50 51
R6109 0R2J-2-GP SUSCLK_32KHZ GND
DY E51_RXD_R
48
46
COEX1 REFCLKN0
49
47
PEG_CLK1_CPU# 18
E51_TXD_R COEX2 REFCLKP0 PEG_CLK1_CPU 18
44 45
CL_CLK_WLAN_R COEX3 GND
18 CL_CLK DY 1 2
CL_DATA_WLAN_R
42
CLINK_CLK PERN0
43 PCIE_RX_CPU_N5 16
18 CL_DATA DY1 R6111 0R2J-2-GP
2
CL_RST_WLAN#_R
40
CLINK_DATA PERP0
41 PCIE_RX_CPU_P5 16
18 CL_RST# DY1 R6112 0R2J-2-GP
2
R6113 0R2J-2-GP
38
CLINK_RESET GND
39
36 37 PCIE_TX_CON_N5 16
UART_CTS PETN0
34 35 PCIE_TX_CON_P5 16
UART_RTS PETP0
32 33
UART_TX GND

22 23
UART_RX SDIO_RESET
20 21
UART_WAKE SDIO_WAKE
18
GND SDIO_DAT3
19 06/05 Wlan_DP_MLDIR 此此線此線, 待待待待待待待,將
將此此將將
16 17 WLAN_DP_MLDIR 1 2
LED#2 SDIO_DAT2 R6114 0R2J-2-GP
14
12
PCM_OUT SDIO_DAT1
15
13
DY
PCM_IN SDIO_DAT0
10 11
PCM_SYNC SDIO_CMD
8 9
PCM_CLK SDIO_CLK
6 7
LED#1 GND
4 5 USB_CPU_PN7 16
3_3VAUX USB_D-
2 3 USB_CPU_PP7 16
3_3VAUX NGFF_KEY_E_75P USB_D+
GND
1 AFTP6103 1

NP2 NP1
NP2 NP1 AFTP6104 PCIE_WAKE#_1
1
AFTP6105 1 BT_DISABLE#_R
SKT-MINI67P-2-GP-U AFTP6106 1 PCIE_CLK_WLAN_REQ#_R
3D3V_WLAN AFTP6107 1 PEG_CLK1_CPU#
1

2
AFTP6108 1 PEG_CLK1_CPU
62.10043.I91 ED6101
ESDR0502BT1G-GP
AFTP6109
AFTP6110
1
1
WIRELESS_EN
PLT_RST#
1st = 62.10043.I91 83.00502.BA1
B

2nd = 062.10003.0B11 AFTP6111 PCIE_RX_CPU_N5

DY 1
3

AFTP6112 1 PCIE_RX_CPU_P5
R1

Q6102 3rd = 062.10007.0511

B LTC015TEBFS8TL-GP B
4TH = 062.10007.0371 ESD RESERVED
84.00015.B1H AFTP6115 1 PCIE_TX_CON_N5
AFTP6116 1 PCIE_TX_CON_P5
E

2ND = 84.00015.01H
PCIE_CLK_WLAN_REQ#_R CLKREQ_PCIE#1 18
AFTP6119 1 CL_CLK_WLAN_R
1 2 E51_RXD_R R6119 1
DY 2 0R2J-2-GP E51_RXD 24 AFTP6120 1 CL_DATA_WLAN_R
R6123 DY 0R2J-2-GP E51_TXD_R R6120 1
DY 2 0R2J-2-GP AFTP6121 1 CL_RST_WLAN#_R
E51_TXD 24

E51_TXD_R R6122 1
DY 2 0R2J-2-GP AFTP6113 1 E51_RXD_R
E51_RXD_R R6124 1 2 0R2J-2-GP AFTP6114 1 E51_TXD_R
DY

06/05 E51_RXD_R & E51_TXD_R 此此此此此此此?

原原SIT有
10/8 84.00115.E1K EOL(原 有有,SIV將
將將, 加加84.00015.01H) AFTP6122 1 E51_RXD
AFTP6123 1 E51_TXD

AFTP6124 1 3D3V_WLAN

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

NGFF_WLAN CONN
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 61 of 102
5 4 3 2 1
 A B C D E

4 4

3
(Blanking) 3

2 2

<Core Design>

1
Wistron Corporation 1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RESERVED
Size Document Number Rev
A4
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 62 of 102
A B C D E
 5 4 3 2 1

D D

C C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RESERVED
Size Document Number Rev
A4
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 63 of 102
5 4 3 2 1
 5 4 3 2 1

Test point
CHARGER LED LED1
5V_AUX_S5

ORG
Q6401 3 Orange

R6415 1 5V_AUX_S5_R 1 R6411 2

4 3 DC_BATFULL#_Q 1 2 330R2J-3-GP DC_BATFULL#_R 2 0R0402-PAD
Yellow Green
83.12222.070
24 DC_BATFULL
5 2
CHARGE_LED 24 GREEN
LED-OYG-1-GP 1ST = 83.12222.070
6 1

CHARGE_LED
LED14 2ND = 83.00326.B70
D D
2N7002KDW-GP LED2
ORG
84.2N702.A3F
1
2

2nd = 075.063D1.007C CHARGE_LED#_R 3 Orange

RN6401 1 5V_AUX_S5_R AFTP6409 1

SRN100KJ-6-GP DC_BATFULL#_R 2
Yellow Green

R6414 GREEN 83.12222.070

CHARGE_LED#_Q 1 2 330R2J-3-GP CHARGE_LED#_R LED-OYG-1-GP
4
3

1ST = 83.12222.070
LED15 AFTP6401 5V_AUX_S5
2ND = 83.00326.B70 1
DC_BATFULL
AFTP6402 1
AFTP6403 1 CHARGE_LED

AFTP6406 1

C C

SATA LED 3D3V_S0

1

R6418
120R2J-2-GP
2

LED3

K A SATA_LED#_D
16 SATA_LED#

LED-G-107-GP-U 1ST = 83.00270.B70

LV114 2ND = 83.02721.H70
83.00270.B70
LED4

K A

LED-G-107-GP-U 1ST = 83.00270.B70

LV115 2ND = 83.02721.H70
83.00270.B70
B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LED Board&Power Button

Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 64 of 102
5 4 3 2 1
 5 4 3 2 1

Internal KeyBoard Connector

KROW[0..7] 24

3D3V_S5
KCOL[0..17] 24

For 14" and 15" CONN

CAP_LED_3V3 R6512 1 2 330R2J-3-GP DY
SSID = Touch.Pad
KBB1 3D3V_S0 3D3V_S0 TouchPad
33
1 CAP_LED_3V3
NUM_LED_C 1 R6502
2 CAP_LED_C NUM_LED_3V3 R6510 1 2 330R2J-3-GP NUM_LED_3V3 1 AFTP6543 1 2
3 KCOL15 CAP_LED_3V3 R6511 1 2 330R2J-3-GP AFTP6542 0R0402-PAD
CAP_LED_C 1 4 KCOL10
CAP_LED_3V3 1 AFTP6541 5 KCOL11
KCOL15 1 AFTP6540 6 KCOL14 TouchPad
KCOL10 1 AFTP6501 7 KCOL13

1
KCOL11 1 AFTP6502 8 KCOL12 C6502 C6501

SCD1U16V2KX-L-GP
KCOL14 1 AFTP6503 9 KCOL3 DY

SCD1U25V2KX-L-GP
KCOL13 1 AFTP6504 10 KCOL6

2
1
2
KCOL12 1 AFTP6505 11 KCOL8 R6505 2 1 100R2J-L-GP KBB_DEFINE1_R 24
D KCOL3 1 AFTP6506 12 KCOL7 RN6501 D
KCOL6 1 AFTP6507 13 KCOL4 SRN10KJ-5-GP TP2
KCOL8 1 AFTP6508 14 KCOL2
KCOL7 1 AFTP6509 15 KROW0 DY R6503 8
KCOL4 1 AFTP6510 16 KCOL1 KBB1_DEFINE1 R6506 2 1 100R2J-L-GP KBC_PWRBTN# 24,66 1 2 0R2J-L-GP TP_SW_R_CON 6

4
3
13,18 PCH_SMBDATA
KCOL2 1 AFTP6511 17 KCOL5 1 R6504 2 0R2J-L-GP TP_SW_L_CON 5
13,18 PCH_SMBCLK
KROW0 1 AFTP6512 18 KROW3 RN6502 DY 4
KCOL1 1 AFTP6513 19 KROW2
DY TPDATA 2 3 TP_DATA 3
24 TPDATA

2
KCOL5 1 AFTP6514 20 KCOL0 24 TPCLK TPCLK 1 4 TP_CLK 2

1
VARISTOR-5D5V-29-GP
KROW3 1 AFTP6515 21 KROW5 L6501 C6508 C6507
KROW2 1 AFTP6516 22 KROW4 SRN33J-5-GP-U 1
KCOL0 1 AFTP6517 23 KCOL9 SC1KP50V2KX-L-1-GP SC1KP50V2KX-L-1-GP 7

2
KROW5 1 AFTP6518 24 KROW6

1
KROW4 1 AFTP6519 25 KROW7 C6506 C6505

SC100P50V2JN-3GP

SC100P50V2JN-3GP
KCOL9 1 AFTP6520 26 KROW1 DY DY DY
KROW6 1 AFTP6521 27 KCOL16 1 FOX-CON6-6-GP

2
KROW7 1 AFTP6522 28 KCOL17 1 AFTP6530
AFTP6523 29 NUM_LED_3V3 AFTP6529 020.K0048.0006
KROW1 1 30 NUM_LED_C
AFTP6524 31 KBB1_DEFINE1 1ST = 020.K0206.0006
1 32 KBB1_DEFINE2 R6507 2 1 0R0402-PAD
AFTP6525 34 2ND = 20.K0841.006
AFTP6501~AFTP6525 PTWO-CON32-3-GP 020.K0223.0032
CLOSE keyboard connector 1ST = 020.K0223.0032
2ND = 020.K0233.0032

TP_SW_R

1 TP_DATA
AFTP6536 1 TP_CLK
Q6501 Q6502 AFTP6537
G G TPSW41 TPSW51
24 CAP_LED 24 NUM_LED SW-TACT-124-GP SW-TACT-124-GP

5
D CAP_LED_C D NUM_LED_C
1 TouchPad 2 1 TP_SW_R 2 1
S S KCOL3 EC6501 1 2SC100P50V2JN-3GP AFTP6533
Notice:ZZ.2N702.J3101 Notice:ZZ.2N702.J3101
KCOL4 EC6502 1 2SC100P50V2JN-3GP 62.40078.001 62.40078.001
2N7002K-2-GP 2N7002K-2-GP KCOL6 EC6503 1 2SC100P50V2JN-3GP 1
84.2N702.J31 84.2N702.J31 KCOL7 EC6504 1 2SC100P50V2JN-3GP AFTP6532 4 3 4 3
2ND = 84.2N702.031 2ND = 84.2N702.031 KCOL8 EC6505 1 2SC100P50V2JN-3GP
3rd = 84.2N702.W31 3rd = 84.2N702.W31 LV114 LV115

6
RN6504
1ST = 62.40078.001 1ST = 62.40078.001
TP_SW_R_CON 1 4 2ND = 62.40009.D71 2ND = 62.40009.D71
TP_SW_L_CON 2 3
For EMC Recommend
C
3RD = 62.40056.041 3RD = 62.40056.041 C
SRN100J-3-GP

TP_SW_L

TPSW42 TPSW52
SW-TACT-124-GP SW-TACT-124-GP

5
2 1 TP_SW_L 2 1

62.40078.001 62.40078.001
4 3 4 3

LV114 LV115

6
1ST = 62.40078.001 1ST = 62.40078.001
2ND = 62.40009.D71 2ND = 62.40009.D71
3RD = 62.40056.041 3RD = 62.40056.041

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Key Board&Touch Pad

Size Document Number Rev
A1
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 65 of 102
5 4 3 2 1
 5 4 3 2 1

IO BD Device
Item Device
1
2
3
4

D D

IO BD connector
3D3V_S0
IOCN1
13
1

2 1 HP_OUT_R
24 KBC_NOVO_BTN# HP_OUT_R 27
3 AFTP6601 1 HP_OUT_L
AFTP6602 HP_OUT_L 27 3D3V_S0
4
5 1 SLEEVE
SLEEVE 27
2

27 HP_OUT_R AFTP6603 RING2

6 1 RING2 27
27 HP_OUT_L
VARISTOR-5D5V-29-GP

L6602 7 AFTP6604 1 HP_DET#

27 HP_DET# HP_DET# 27

1
8 AFTP6605
9 C6604
Audio Jack 27 SLEEVE
10 1 ALC_AGND SCD1U25V2KX-L-GP

2
11 AFTP6606
27 RING2
1

12
14

STAR-CON12-1-GP 1ST = 020.K0125.0012

ALC_AGND 020.K0125.0012 2ND = 020.K0049.0012

3RD = 020.K0190.0012

5V_S5
IO2
21
1

3D3V_S0 2
3
4
C
16 USB_OC2# 5 C
KBC_NOVO_BTN# 6 5V_S5
7
8
USB_CPU_PN2 9
16 USB_CPU_PN2

1
USB_CPU_PP2 10
16 USB_CPU_PP2
11 C6603
12 SCD1U25V2KX-L-GP

2
27 HP_OUT_R
13 DY
14
27 HP_OUT_L
27 HP_DET# 15
16
27 SLEEVE 17
18
27 RING2 19
20
22

ACES-CON20-29-GP-U
20.K0637.020
ALC_AGND
DY

PWR BTN BD connector

B B

Modified Pin Define and PN 20151208

PW1
6

4
3 KBC_PWRBTN# 1
2 AFTP6607

24,65 KBC_PWRBTN# 1

PTWO-CON4-9-GP-U1
1

2
VARISTOR-5D5V-29-GP

G6601 G6602 L6601 20.K0382.004

GAP-OPEN GAP-OPEN 1ST = 20.K0382.004

2

2ND = 020.K0150.0004

3D3V_AUX_S5
HALL2

LID_CLOSE# R6601 1 2 100R2J-2-GP LID_CLOSE#_2 3

A 24 LID_CLOSE# OUT A
R6610 2 1 3D3V_AUX_S5_HALL 2
0R0402-PAD VDD
1
1

VSS
D6601
1

A K C6610 C6601
SCD1U16V2KX-3GP SCD047U16V2KX-1-GP C6602 S-5712ACDL1-M3T1U-GP
2

SCD1U16V2KX-L-GP
RB551V30-GP DY DY 74.05712.0BB
2

<Core Design>
83.R5003.H8H
2nd = 83.R5003.T8F 1ST = 74.05712.0BB
DY 2ND = 074.08132.007B Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
3RD = 074.09247.009B Taipei Hsien 221, Taiwan, R.O.C.

Title

IO Board Connector
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 66 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RESERVED
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 67 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = Debug

D D

Debug Connector
3D3V_S0
DB1
11
1

R6801 1
DY 0R2J-2-GP LPC_AD0_R
18,24 LPC_AD0 R6802 1
DY 2
0R2J-2-GP LPC_AD1_R
2
18,24 LPC_AD1 R6803 1
DY 2
0R2J-2-GP LPC_AD2_R
3
C
18,24 LPC_AD2 R6804 1
DY 2
0R2J-2-GP LPC_AD3_R
4 C

18,24 LPC_AD3 R6805 1

DY 2
0R2J-2-GP LPC_FRAME#_R
5
18,24 LPC_FRAME# 2 6
17,24,31,40,61,76 PLT_RST# 7
8
18 CLK_PCI_DB 9
10
12

ACES-CON10-1-GP-U1

20.F0714.010
DY

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Debug connector
Size Document Number Rev
A4
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 68 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 69 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

G Sensor
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 70 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 71 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 72 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 73 of 102

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 74 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 75 of 102
5 4 3 2 1
 5 4 3 2 1

GPU1A 1 OF 7
PCIE lane maping
CPU >> GPU
1 0
AF30 AH30 PEG_RX_CON_P0 C7669 1 2 SCD22U10V2KX-L1-GP PX PEG_RX_CPU_P0
2 1 16 PEG_TX_GPU_P0
16 PEG_TX_GPU_N0 AE31
PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
AG31 PEG_RX_CON_N0 C7670 1 2 SCD22U10V2KX-L1-GP PX PEG_RX_CPU_N0
PEG_RX_CPU_P0
PEG_RX_CPU_N0
16
16
3 2 AE29 AG29 PEG_RX_CON_P1 C7671 1 2 SCD22U10V2KX-L1-GP PX PEG_RX_CPU_P1
16 PEG_TX_GPU_P1 PCIE_RX1P PCIE_TX1P PEG_RX_CPU_P1 16
D 4 3 16 PEG_TX_GPU_N1 AD28
PCIE_RX1N PCIE_TX1N
AF28 PEG_RX_CON_N1 C7672 1 2 SCD22U10V2KX-L1-GP PX PEG_RX_CPU_N1
PEG_RX_CPU_N1 16 D

AD30 AF27 PEG_RX_CON_P2 C7666 1 2 SCD22U10V2KX-L1-GP PX PEG_RX_CPU_P2

16 PEG_TX_GPU_P2 PCIE_RX2P PCIE_TX2P PEG_RX_CON_N2 PEG_RX_CPU_N2 PEG_RX_CPU_P2 16
16 PEG_TX_GPU_N2 AC31 AF26 C7667 1 2 SCD22U10V2KX-L1-GP PX PEG_RX_CPU_N2 16
PCIE_RX2N PCIE_TX2N

AC29 AD27 PEG_RX_CON_P3 C7668 1 2 SCD22U10V2KX-L1-GP PX PEG_RX_CPU_P3

16 PEG_TX_GPU_P3 PCIE_RX3P PCIE_TX3P PEG_RX_CON_N3 PEG_RX_CPU_N3 PEG_RX_CPU_P3 16
16 PEG_TX_GPU_N3 AB28 AD26 C7673 1 2 SCD22U10V2KX-L1-GP PX PEG_RX_CPU_N3 16
PCIE_RX3N PCIE_TX3N

AB30 AC25
PCIE_RX4P PCIE_TX4P
AA31 AB25
PCIE_RX4N PCIE_TX4N
AC-Coupling Capacitor:
PCIe Gen1,Gen2 : 0.1uF
AA29 Y23
PCIE_RX5P PCIE_TX5P PCIe Gen3 : 0.22uF
Y28 Y24
PCIE_RX5N PCIE_TX5N

Y30 AB27
PCIE_RX6P PCIE_TX6P
W31 AB26
PCIE_RX6N PCIE_TX6N

3D3V_VGA_S0
W29 Y27
PCIE_RX7P PCIE_TX7P
V28 Y26
PCIE_RX7N PCIE_TX7N

2
V30 W24
NC#V30 NC#W24 R7301
U31 W23
NC#U31 NC#W23
0R2J-2-GP
20141119_KAMUS
U29 V27 DY

1
NC#U29 NC#V27 R7602 DGPU_PWROK_G
T28 U26 19,24,85 DGPU_PWROK 2 1
NC#T28 NC#U26
0R0402-PAD

PCI EXPRESS INTERFACE

T30 U24
NC#T30 NC#U24
R31 U23
NC#R31 NC#U23 Q7601
G
R29 T26
NC#R29 NC#T26
P28 T27 D
NC#P28 NC#T27 18 CLKREQ_PEG#0
C C
PX
Notice:ZZ.2N702.J3101
S
P30 T24
NC#P30 NC#T24 2N7002K-2-GP
N31 T23
NC#N31 NC#T23
84.2N702.J31
2ND = 84.2N702.031
N29
NC#N29 NC#P27
P27 3rd = 84.2N702.W31
M28 P26
NC#M28 NC#P26

PE_GPIO0 PE_GPIO0 = ATI_RST# M30

NC#M30 NC#P24
P24
L31 P23
NC#L31 NC#P23

H dGPU mode
L29 M27
NC#L29 NC#M27
L IGPU K30
NC#K30 NC#N26
N26

H IGPU with BACO

CLOCK
1 R7604 2 0R0402-PAD CLK_PCIE_VGA_R AK30
18 PEG_CLK_CPU PCIE_REFCLKP
1 R7605 2 0R0402-PAD CLK_PCIE_VGA#_R AK32
18 PEG_CLK_CPU# PCIE_REFCLKN
Mars/Sun setting
CALIBRATION
PCIE_CALR_TX 1K69R2F-2-GP 2
PX R7622
Y22 1 0D95V_VGA_S0
PCIE_CALR_TX
1KR2F-3-GP 2
PX PWRGOOD PCIE_CALR_RX
PX
1 R7601 N10 AA22 1KR2F-3-GP 2 1 R7618
TEST_PG PCIE_CALR_RX

2 R7603 1 0R0402-PAD VGA_RST# AL27

20 DGPU_HOLD_RST# PERST#

JET-XT-S3-GP
1

C7609
DY SC47P50V2JN-3GP PX
2

3D3V_VGA_S0
1

B PX support B
PE_GPIO0: VGA_RESET
PE_GPIO1: VGA_PowerEnable R7625
10KR2J-L-GP
DY DY
2

R7623 2 1 0R2J-2-GP

2 D7601
19 PE_GPIO0
BAW56-5-GP
DY 3

17,24,31,40,61,68 PLT_RST# 1

83.00056.Q11
1ST = 83.00056.Q11
2ND = 75.00056.07D

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU(1/5) PEG
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 76 of 102
5 4 3 2 1
 5 4 3 2 1

GPU1E 5 OF 7 GPU1G 7 OF 7

DP POWER NC/DP POWER

AA27
AB24
GND GND
A3
A30
1.8V and 0.95V for Clock resource AG15
NC_DP_VDDR#AG15 NC#AE11
AE11
GND GND AG16 AF11
AB32 AA13 NC_DP_VDDR#AG16 NC#AF11
GND GND AF16 AE13
AC24 AA16 NC_DP_VDDR#AF16 NC#AE13
GND GND AG17 AF13
AC26 AB10 1D8V_VGA_S0 DPLL_PVDD DPLL_PVDD NC_DP_VDDR#AG17 NC#AF13
GND GND AG18 AG8
AC27 AB15 NC_DP_VDDR#AG18 NC#AG8
AG19 AG10
AD25
GND
GND
GND
GND
AB6 1 R7704 2
40mA AF14
NC_DP_VDDR#AG19 NC#AG10
AD32 AC9 DP_VDDR
GND GND

1
AE27 AD6 0R0603-PAD C7713 C7711 C7710
GND GND
AF32 AD8 SC10U6D3V3MX-L-GP SC1U10V2KX-L1-GP SCD1U16V2KX-L-GP
GND GND
AG27 AE7 DY
D GND GND PX PX D

2
AH32 AG12 AG20 AF6
GND GND NC_DP_VDDC#AG20 NC#AF6
K28 AH10 AG21 AF7
GND GND 0D95V_VGA_S0 DPLL_VDDC DPLL_VDDC NC_DP_VDDC#AG21 NC#AF7
K32 AH28 AF22 AF8
GND GND NC_DP_VDDC#AF22 NC#AF8
L27 B10 AG22 AF9
M32
GND
GND
GND
GND
B12 1 R7705 2
32mA AD14
NC_DP_VDDC#AG22 NC#AF9
N25 B14 DP_VDDC
GND GND

1
N27 B16 0R0603-PAD C7715 C7714
GND GND
P25 B18 SC1U10V2KX-L1-GP SCD1U16V2KX-L-GP
GND GND
P32 B20
GND GND PX PX AG14 AE1

2
R27 B22 NC_DP_VSSR#AG14 NC#AE1
GND GND AH14 AE3
T25 B24 NC_DP_VSSR#AH14 NC#AE3
GND GND AM14 AG1
T32 B26 NC_DP_VSSR#AM14 NC#AG1
GND GND AM16 AG6
U25 B6 NC_DP_VSSR#AM16 NC#AG6
GND GND AM18 AH5
U27 B8 GPU1F 6 OF 7 NC_DP_VSSR#AM18 NC#AH5
GND GND AF23 AF10
V32 C1 NC_DP_VSSR#AF23 NC#AF10
GND GND AG23 AG9
W25 C32 1V_VGACORE_S0_TOPAZ NC_DP_VSSR#AG23 NC#AG9
GND GND AM20 AH8
W26 E28 NC_DP_VSSR#AM20 NC#AH8
GND GND AM22 AM6
W27 F10 NC_DP_VSSR#AM22 NC#AM6
GND GND NC_VARY_BL
AB11 Topaz only AM24
NC_DP_VSSR#AM24 NC#AM8
AM8
Y25 F12 AB12 AF19 AG7
GND GND NC_DIGON NC_DP_VSSR#AF19 NC#AG7
Y32 F14 AF20 AG11
GND GND NC_DP_VSSR#AF20 NC#AG11
F16 AE14
GND DP_VSSR
F18
GND
F2
GND
F20 AL15
GND NC_UPHYAB_TMDPA_TX0N
M6 F22 AK14 AF17 AE10
GND GND NC_UPHYAB_TMDPA_TX0P NC_UPHYAB_DP_CALR NC#AE10
N13 F24
GND GND
N16 F26 AH16
GND GND NC_UPHYAB_TMDPA_TX1N
N18 F6 AJ15
GND GND NC_UPHYAB_TMDPA_TX1P
N21 GND F8 JET-XT-S3-GP
GND GND
P6 G10 AL17 PX
GND GND NC_UPHYAB_TMDPA_TX2N
P9 G27 AK16
GND GND NC_UPHYAB_TMDPA_TX2P
R12 G31
GND GND
R15 G8 AH18
GND GND NC_UPHYAB_TMDPA_TX3N
R17 H14 AJ17
GND GND NC_UPHYAB_TMDPA_TX3P
R20 H17
GND GND
T13 H2 AL19
GND GND NC_TXOUT_L3P
T16 H20 AK18
GND GND NC_TXOUT_L3N
T18 H6
GND GND
T21 J27
GND GND TMDP
T6 J31
GND GND
C U15 K11 C
GND GND
U17 K2 AH20
GND GND NC_UPHYAB_TMDPB_TX0N
U20 K22 AJ19
GND GND NC_UPHYAB_TMDPB_TX0P
U9 K6
GND GND
V13 AL21
GND NC_UPHYAB_TMDPB_TX1N
V16 AK20
GND NC_UPHYAB_TMDPB_TX1P
V18
GND
Y10 AH22
GND NC_UPHYAB_TMDPB_TX2N
Y15 AJ21
GND NC_UPHYAB_TMDPB_TX2P
Y17
GND
Y20 AL23
GND VSS_MECH1 1 TP7701 NC_UPHYAB_TMDPB_TX3N
R11 A32 AK22
GND VSS_MECH VSS_MECH2 1 TP7740 NC_UPHYAB_TMDPB_TX3P
T11 AM1
GND VSS_MECH VSS_MECH3 1 TP7730
AA11 AM32 AK24
GND VSS_MECH NC_TXOUT_U3P
M12 AJ23
GND NC_TXOUT_U3N
N11
GND
V11
GND

JET-XT-S3-GP JET-XT-S3-GP
PX PX

1V_VGACORE_S0 1V_VGACORE_S0_TOPAZ

R7706
1 2

0R3J-0-U-GP
1

C7716
PX_TOPAZ SC1U10V2KX-L1-GP
PX_TOPAZ
2

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU (2/5) DIGITALOUT

Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 77 of 102
5 4 3 2 1
 5 4 3 2 1

GPU1C 3 OF 7

GDDR5/DDR3 GDDR5/DDR3
81 DQA0_[31..0] DQA0_0 K27 K17 MAA0 81,83
DQA0_1 DQA0_0 MAA0_0
J29 J20 MAA1 81,83
DQA0_2 DQA0_1 MAA0_1
H30 H23 MAA2 81,83
DQA0_3 DQA0_2 MAA0_2
H32 G23 MAA3 81,83
DQA0_4 DQA0_3 MAA0_3
G29 G24 MAA4 81,83
DQA0_5 DQA0_4 MAA0_4
F28 H24 MAA5 81,83
DQA0_6 DQA0_5 MAA0_5
F32 J19 MAA6 81,83
DQA0_7 DQA0_6 MAA0_6
F30 K19 MAA7 81,83
DQA0_8 DQA0_7 MAA0_7
C30 G20 MAA13 81,83
DQA0_9 DQA0_8 MAA0_8
F27 L17 MAA15 81,83
DQA0_10 DQA0_9 MAA0_9
A28
DQA0_11 DQA0_10
C28 J14 MAA8 81,83
DQA0_12 DQA0_11 MAA1_0
D E27 K14 MAA9 81,83 D
DQA0_13 DQA0_12 MAA1_1
G26 J11 MAA10 81,83
DQA0_14 DQA0_13 MAA1_2
D26 J13 MAA11 81,83
DQA0_15 DQA0_14 MAA1_3
F25 H11 MAA12 81,83
DQA0_16 DQA0_15 MAA1_4
A25 G11 MAA_BA2 81,83
DQA0_17 DQA0_16 MAA1_5
C25 J16 MAA_BA0 81,83
DQA0_18 DQA0_17 MAA1_6
E25 L15 MAA_BA1 81,83
DQA0_19 DQA0_18 MAA1_7
D24 G14 MAA14 81,83
DQA0_20 DQA0_19 MAA1_8 VSSRHA TP7801
E23 L16 1

MEMORY INTERFACE
DQA0_21 DQA0_20 MAA1_9
F23
DQA0_22 DQA0_21
D22 E32 DQMA0 81
DQA0_23 DQA0_22 WCKA0_0
F21 E30 DQMA1 81
DQA0_24 DQA0_23 WCKA0#_0
E21 A21 DQMA2 81
DQA0_25 DQA0_24 WCKA0_1
D20 C21 DQMA3 81
DQA0_26 DQA0_25 WCKA0#_1
F19 E13 DQMA4 83
DQA0_27 DQA0_26 WCKA1_0
A19 D12 DQMA5 83
DQA0_28 DQA0_27 WCKA1#_0
Please MVREF drivers and Caps close to ASIC DQA0_29
D18
F17
DQA0_28 WCKA1_1
E3
F4
DQMA6 83
DQA0_29 WCKA1#_1 DQMA7 83
DQA0_30 A17
DQA0_31 DQA0_30
C17 H28 QSAP_0 81
83 DQA1_[31..0] DQA1_0 DQA0_31 EDCA0_0
E17 C27
DDR3/GDDR3 Memory Stuff Option(JET/TOPAZ) DQA1_1 D16
DQA1_0 EDCA0_1
A23
QSAP_1 81
DQA1_2 DQA1_1 EDCA0_2 QSAP_2 81
F15 E19 QSAP_3 81
DQA1_3 DQA1_2 EDCA0_3
A15 E15 QSAP_4 83
DQA1_4 DQA1_3 EDCA1_0
GDDR5 GDDR3 DDR3 D14
DQA1_4 EDCA1_1
D10 QSAP_5 83
DQA1_5 F13 D6
DQA1_5 EDCA1_2 QSAP_6 83
DQA1_6 A13 G5
DQA1_6 EDCA1_3 QSAP_7 83
MVDDQ 1.5V 1D35V 1.5V DQA1_7 C13
DQA1_8 DQA1_7
E11 H27 QSAN_0 81
DQA1_9 DQA1_8 DDBIA0_0
A11 A27 QSAN_1 81
DQA1_10 DQA1_9 DDBIA0_1
Ra 40.2R 40.2R 40.2R C11
DQA1_10 DDBIA0_2
C23 QSAN_2 81
DQA1_11 F11 C19
DQA1_11 DDBIA0_3 QSAN_3 81
DQA1_12 A9 C15
DQA1_12 DDBIA1_0 QSAN_4 83
Rb 100R 100R 100R DQA1_13 C9 E9
DQA1_13 DDBIA1_1 QSAN_5 83
DQA1_14 F9 C5
DQA1_14 DDBIA1_2 QSAN_6 83
DQA1_15 D8 H4
DQA1_15 DDBIA1_3 QSAN_7 83
DQA1_16 E7
DQA1_17 DQA1_16
A7 L18 ODTA0 81
1D5V_VGA_S0 1D5V_VGA_S0 DQA1_18 DQA1_17 ADBIA0
C7 K16 ODTA1 83
DQA1_19 DQA1_18 ADBIA1
F7
DQA1_20 DQA1_19
A5 H26 CLKA0 81
1

DQA1_21 DQA1_20 CLKA0

C E5 H25 CLKA0# 81
C
R7817 R7830 DQA1_22 DQA1_21 CLKA0#
Ra C3
40D2R2F-GP 40D2R2F-GP DQA1_23 DQA1_22
Ra DQA1_24
E1
DQA1_23 CLKA1
G9
CLKA1 83
PX PX DQA1_25
G7
DQA1_24 CLKA1#
H9
CLKA1# 83
G6
2

MVREFDA MVREFSA DQA1_26 DQA1_25

G1 G22
DQA1_27 DQA1_26 RASA0# RASA0# 81
G3 G17
1

DQA1_28 DQA1_27 RASA1# RASA1# 83

J6
PX PX
2

R7818 R7814 DQA1_29 DQA1_28

Rb Rb J1 G19 CASA0# 81
100R2F-L1-GP-U SC1U10V2KX-L1-GP 100R2F-L1-GP-U SC1U10V2KX-L1-GP DQA1_30 DQA1_29 CASA0#
J3 G16 CASA1# 83
C7805 C7801 DQA1_31 DQA1_30 CASA1#
PX PX J5
1

DQA1_31
H22
2

CSA0#_0 CSA0#_0 81
MVREFDA K26 J22
MVREFSA MVREFDA CSA0#_1
J26
MVREFSA Modify 20151007
G13
Jet Setting J25
CSA1#_0
K13
CSA1#_0 83
NC#J25 CSA1#_1
R7820 1 2 120R2F-GP MEM_CALRP0 K25
MEM_CALRP0
K20 CKEA0 81
CKEA0
Place all these componets very close to GPU (within 25mm) and keep all PX CKEA1
J17 CKEA1 83
components close to each other G25
DRAM_RST_VGA1 WEA0# WEA0# 81
This basic topology should be used for DRAM_RST for DDR3/GDDR5 L10 H10
DRAM_RST# WEA1# WEA1# 83
CLKTESTA K8
1D5V_VGA_S0 CLKTESTB CLKTESTA
L7
CLKTESTB
1

1
1

C7822 C7821 JET-XT-S3-GP

R7802 SCD1U16V2KX-3GP SCD1U16V2KX-3GP
2

2K2R2J-2-GP DY DY PX
CLKTESTA_C

CLKTESTB_C

DY 49D9R2F-GP PX 10R2J-L-GP
R7804 R7803 Debug only, for
2

1 2 DRAM_RST_R 1 2 DRAM_RST_VGA1
81,83 DRAM_RST clock observation,
PX if not needed, DNI
1

C7802 R7819
SC120P50V2JN-1GP 5K1R2F-2-GP R7810 R7809
2

51D1R2F-GP 51D1R2F-GP
PX PX
DY DY
2

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU (3/5) VRAM I/F

Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 78 of 102
5 4 3 2 1
 5 4 3 2 1

3D3V_VGA_S0

R7910 2 1 10KR2J-3-GP PX_JET VIDEO_THERM_ALERT#

R7903 1 2 1KR2F-3-GP DY TESTEN

#3
Pull-High Pull-Low
PS0 ~ PS3 Setting R7928 R7929 AMD suggest Aperture Size = 256MB
11000
Cap Value (nF) Bits [5:4] R_pu (Ω) R_pd (Ω) Bits [3:1] 11001
GPU1B 2 OF 7 680 00 NC 4750 000 1D8V_VGA_S0
1D8V_VGA_S0
82 01 8450 2000 001

1
10 10 4530 2000 010 8K45R2F-2-GP

1
AF2 8K45R2F-2-GP DY R7930
NC#AF2 AF4 NC 11 6980 4990 011 R7926
PINs for debug NC#AF4 PX
4530 4990 100
TP7909 1 DBG_DATA16 N9 AG3
3240 5620 101

2
TP7914 DBG_DATA15 DBG_DATA16 NC#AG3 PS_2
1 L9 AG5

2
DBG_DATA15 NC#AG5
TP7915 1 DBG_DATA14 AE9 DPA 3400 10000 110 PS_0

1
TP7916 1 DBG_DATA13 Y11 DBG_DATA14 AH3
4750 NC 111 PX

1
TP7917 DBG_DATA12 DBG_DATA13 NC#AH3 R7931
1 AE8 AH1 DY

1
DBG_DATA12 NC#AH1 4K75R2F-1-GP
AD9
DBG_DATA11 Note: 0402 1% resistors are required. R7927 C7918 C7920
SCD68U16V3KX-GP-U
AC10 AK3 2KR2F-3-GP SCD082U16V2KX-GP

2
AD7 DBG_DATA10 NC#AK3 AK1 PX 680nF

2
AC8 DBG_DATA9 NC#AK1
DVO

2
DBG_DATA8
AC7
DBG_DATA7 NC#AK5
AK5 DY
AB9
AB8
DBG_DATA6 NC#AM3
AM3 Board Configure [5:1]
AB7 DBG_DATA5 AK6
AB4 DBG_DATA4 NC#AK6 AM5 Bit 5 4 3 2 1
DBG_DATA3 NC#AM5
3D3V_VGA_S0
AB2
DBG_DATA2
DPB
## PS_3[3-1] => MEM_ID setting, need decide for AMD
Y8 AJ7 PS_1[1]=0 => KABINI only PCIe GEN2 is supported
DBG_DATA1 NC#AJ7
Y7
DBG_DATA0 NC#AH6
AH6 PS0 1 1 0 0 1 11101
3
RN7901
2 TOPAZ_U1 NC#AK8
AK8 11001 SC_change to GEN3
D 1D8V_VGA_S0
TOPAZ_U3 AL7 PS1 0 0 0 0 0 1D8V_VGA_S0 D

3
4
4 1 NC#AL7 1D8V_VGA_S0
RN7902

1
SRN4K7J-8-GP
SRN4K7J-8-GP PX_TOPAZ W6 PS2 0 0 0 0 0

1
V6 NC#W6 8K45R2F-2-GP R7932
PX PX NC#V6 3K24R2F-GP
V4 PX R7928
NC#V4
Q7901 2 AC6 U5 PS3 1 1 refer below table VRAM Strapping
1
R7912 NC#AC6 NC#U5
6 1 GPIO_VGA_04_CLK 1 2 GPIO_VGA_04_CLK_R AC5

2
18,24 SML1_SMBCLK NC#AC5 PS_3
0R0402-PAD W3

2
5 2 AA5 NC#W3 V2 PS_1 SVT

1
NC#AA5 NC#V2
AA6 DPC

1
1
4 3 NC#AA6 Y4 R7929 R7933 C7921
DY

1
NC#Y4 5K62R2F-GP SCD01U50V2KX-1GP
W5
NC#W5
2N7002KDW-GP DY 2KR2F-L1-GP C7919 VRAM Strapping DY

2
84.2N702.A3F TOPAZ_U1 U1 AA3 TOPAZ_AA3 R7904 1 2 16K2R2F-GP SCD68U16V3KX-GP-U
680nF

2
2
NC#U1 NC#AA3
2nd = 075.063D1.007C W1 Y2

2
18,24 SML1_SMBDATA R7914 NC#W1 NC#Y2
GPIO_VGA_03_DATA 1 2 GPIO_VGA_03_DATA_R TOPAZ_U3 U3
NC#U3
PX
0R0402-PAD Y6 J8
TP7902 1 TOPAZ_AA1 AA1 NC#Y6 NC#J8
NC#AA1

I2C PX_TOPAZ_CHECK Pull-High Pull-Low

D7901
R1 TOPAZ_AJ27 1 3 Board Configure [2:0] R7932 R7933 Lenovo PN Wistron PN Vendor PN
SCL PCH_WAKE# 17,24,31
3D3V_VGA_S0 R3 2
SDA
0 0 0 NC 4750
SV20H30107 072.4563C.0A0U Hynix H5TC4G63CFR-N0C 512MB GDDR3/GDDR3L
AM26 LBAS16LT1G-GP
NC_R AK26 83.00016.P11
1

TP7918 1 GPU_DPRSLP_R U6 GENERAL PURPOSE I/O NC_AVSSN#AK26

2ND = 83.00016.H11 0 0 1 8450 2000
SV20K59920 072.41256.0D0U MICRON MT41J256M16LY-091G:N 512MB GDDR3
R7921 GPIO_0
U10 AL25
Q7902 10KR2J-3-GP NC_GPIO_1 NC_G
T10 AJ25
1
R7937
2 DGPUHOT_R G PX GPIO_VGA_03_DATA_R U8 NC_GPIO_2 NC_AVSSN#AJ25
0 1 0 4530 2000
SV20H30106 072.4G164.0B0U SAMSUNG K4W4G1646E-BC1A 512MB GDDR3/GDDR3L
24 DGPUHOT GPIO_VGA_04_CLK_R SMBDATA
2

0R0402-PAD U7 AH24
GPIO_5_AC_BATT GPIO_5_AC_BATT SMBCLK NC_B 3D3V_VGA_S0
D T9 AG25
T8 GPIO_5_AC_BATT NC_AVSSN#AG25
S
85 TOPAZ_OCP
T7
GPIO_6 DAC1
AH26 0 1 1
6980 4990 SV20H30107 072.4563C.0A0U Hynix H5TC4G63CFR-N0C 512MB GDDR3/GDDR3L
Notice:ZZ.2N702.J3101
TP7905 1 GPIO_8_ROMSO P10 NC_GPIO_7 NC_HSYNC AJ27 TOPAZ_AJ27 R7916 1 2 4K7R2J-2-GP PX_TOPAZ
2N7002K-2-GP TP7906 1 GPIO_9_ROMSI P4 GPIO_8_ROMSO NC_VSYNC
GPIO_9_ROMSI 4530 4990
84.2N702.J31 TP7901 1 GPIO_10_ROMSCK P2
GPIO_10_ROMSCK 1 0 0
2ND = 84.2N702.031 N6
NC_GPIO_11 NC_RSET
AD22
3rd = 84.2N702.W31 N5
NC_GPIO_12 3240 5620
PX 1V_VGACORE_S0_TOPAZ Topaz only N3
NC_GPIO_13 NC_AVDD
AG24 1 0 1
Y9 AE22
JET_SVD NC_GPIO_14 NC_AVSSQ
N1
TP7903 1 GPIO16_VGA M4 GPIO_15_PWRCNTL_0 AE23 3400 10000
GPIO_16 NC_VDD1DI 1 1 0
20 VIDEO_THERM_ALERT# R6 AD23
W10 GPIO_17_THERMAL_INT NC_VSS1DI
M2 NC_GPIO_18
FutureASIC/SEYMOUR/PARK 1 1 1 4750 NC
CLK REQUEST ? JET_SVC P8
P7
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
CEC_1
AM12

TP7910 1 GPIO_22_ROMCS# N8
TP7919 1 H_VID3 AK10 GPIO_22_ROMCS# AK12 TOPAZ_SVD
GPIO_29 NC_SVI2#AK12
TP7920 1 H_VID4 AM10
GPIO_30 NC_SVI2#AL11
AL11 VGA_SVT 85 64.84515.6DL 8450
TP7921 1 PEG_CLKREQ#_VGA N7 AJ11 TOPAZ_SVC
18,76 CLKREQ_PEG#0 CLKREQ# NC_SVI2#AJ11
TP7907 1 JTAG_TRST#_VGA L6
JTAG_TRST#
64.69815.6DL 6980
TP7908 1 JTAG_TDI_VGA L5
TP7911 1 JTAG_TCK_VGA L3 JTAG_TDI
JTAG_TCK
TP7912 1 JTAG_TMS_VGA L1
JTAG_TMS NC_GENLK_CLK
AL13 64.49915.6DL 4990
TP7913 1 JTAG_TDO_VGA K4 AJ13
R7902 JTAG_TDO NC_GENLK_VSYNC
2 1 4K7R2J-2-GP PX TESTEN K7 Pre-PWROK METAL VID CODES
TESTEN
AF24
NC#AF24 64.45315.6DL 4530
LK41:R7902 10K PD AG13
NC_SWAPLOCKA
NC_SWAPLOCKB
AH12 SVC SVD Output Voltage
1V_VGACORE_S0_TOPAZ Topaz only AB13
NC_GENERICA 64.20015.L0L 2000
W8 0 0 1.1
W9 NC_GENERICB
SVID PWR Sequencing NC_GENERICC PS_0
W7 AC19 0 1 1.0 64.34015.6DL 3400
NC_GENERICD PS_0
AD10
JET AJ9 NC_GENERICE_HPD4 AD19 PS_1 #3 AMD suggestion 1 0 0.9
AL9
NC#AJ9 PS_1 NC on JET
DBG_CNTL0 AE17 PS_2
63.10334.1DL 10000
PS_2 1 1 0.8 AB13 U10 W9 Y9 W10 T10 AC14 AB12 AB11 AC11 AC13
TOPAZ AC14
TP7930 PX_EN NC_HPD1 PS_3
1 AB16 AE20 64.47515.6DL 4750
PX_EN PS_3

AE19
AC16 TS_A
NC_DBG_VREFG
VRAM R8105 R8106 R8301 R8302
C
CPU Side C
Single Rank 40.2OHM 64.40R25.6DL DDC/AUX
GPIOxx GPIOxx
AE6
PLL/CLOCK NC_DDC1CLK
AE5
NC_DDC1DATA
Dual Rank 80.6OHM 64.80R65.6DL UMA 0 900M Hz 0
AD2
NC_AUX1P AD4 PX 1 1G 1
NC_AUX1N
AC11 Topaz only 1V_VGACORE_S0_TOPAZ
NC_DDC2CLK AC13
TP7904 NC_DDC2DATA
XTALIN AM28 AD13
XTALOUT XTALIN NC_AUX2P VDDCI Voltage and Ground Sense Feedback on TOPAZ only
AK28 AD11
RN7904 XTALOUT NC_AUX2N
1

3 2 XO_IN AC22 AD20 TOPAZ_VGA_CORE_FBN 1 TP7922

XO_IN2 XO_IN NC#AD20 TOPAZ_VGA_CORE_FBP TP7923
4 1 AB22 AC20 1
XO_IN2 NC#AC20
SRN10KJ-5-GP PX NC#AE16
AE16
AD16
NC#AD16
SEYMOUR/FutureASIC AC1
1 GPU_DPLUS T4 NC_DDCVGACLK AC3
R7935 DY GPU_DMINUS DPLUS THERMAL NC_DDCVGADATA
TP7924 1 T2
TP7925 MLPS_EN# DMINUS
3D3V_VGA_S0 1 2
1D8V_VGA_S0
1

10KR2J-3-GP 13mA R5
GPIO28_FDO
PWR_VGA_CORE_VDDIO R7936 R7936 AD17
0: Enable MLPS, disable GPIO PINSTRAP AC17 TSVDD
10KR2J-3-GP
1

1: Disable MLPS, enable GPIO PINSTRAP TSVSS

PX C7914
2

PX SC1U10V2KX-L1-GP
2
1

JET-XT-S3-GP
R7918 PX
1KR2F-3-GP
PX R7923
1 2 0R2J-2-GP PX_TOPAZ TOPAZ_SVC
2

R7919 1 2 0R2J-2-GP PX_JET JET_SVC

85 VGA_SVC

R7924 1 2 0R2J-2-GP PX_TOPAZ TOPAZ_SVD

R7920 1 2 0R2J-2-GP PX_JET JET_SVD

85 VGA_SVD PX
2 1 XTALIN
SC5D6P50V2CN-1GP C7901
1

R7922 PX
1

1KR2F-3-GP XTAL-27MHZ-159-GP
PX
PX 1MR2J-1-GP
4 1
2

R7901
2

3 2

X7901

2 1 PX XTALOUT
SC5D6P50V2CN-1GP C7903

B B

A A

<Core Des ign>

Wistron Corporation
21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.

Title

GPU (4/5) GPIO/STRAP

Size Docum ent Num ber Rev
A0
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 79 of 102
5 4 3 2 1
 5 4 3 2 1

AMD ORB 10U x 1 LF145M 10U x 1

2.2U x 5 1U x 10 GPU1D 4 OF 7 1D8V_VGA_S0

1D5V_VGA_S0 0.1U x 1 0.1U x 1 AM30

0.1A
20141117 PCIE_PVDD
0.01U x1 0.01U x 1

PCIE
MEM I/O
1A

1
H13 AB23 C8008
7" to 13" H16
VDDR1 NC#AB23
AC23 SC1U10V2KX-L1-GP C8002
SC10U6D3V3MX-L-GP

1
C8003 C8010 C8004 VDDR1 NC#AC23
KAMUS H19 AD24 PX PX

2
C8001 SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP VDDR1 NC#AD24
SC10U6D3V3MX-L-GP J10 AE24
VDDR1 NC#AE24
PX PX PX PX J23 AE25

2
VDDR1 NC#AE25
J24 AE26
1D5V_VGA_S0 VDDR1 NC#AE26
J9 AF25
VDDR1 NC#AF25
20141121_7" to 13"_KAMUS K10 AG26
VDDR1 NC#AG26 0D95V_VGA_S0
K23
VDDR1 AMD ORB 10U x 1 LF145M 10U x 1
K24
2.5A
1

1
D C8042 C8005 C8006 PX C8007 K9
VDDR1
L23 1U x 6 1U x 6 D
SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP C8014 SCD1U16V2KX-L-GP VDDR1 PCIE_VDDC
L11 L24

1
SCD01U50V2KX-L-GP VDDR1 PCIE_VDDC C8011 C8012 C8015 C8017 C8057
PX PX PX PX L12 L25 C8013 C8016
2

2
VDDR1 PCIE_VDDC SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC4D7U6D3V3KX-L-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC10U6D3V3MX-L-GP SC1U10V2KX-L1-GP
L13 L26
VDDR1 PCIE_VDDC
L20 M22 PX PX PX PX PX PX PX

2
VDDR1 PCIE_VDDC
L21 N22
VDDR1 PCIE_VDDC
L22 N23
VDDR1 PCIE_VDDC
N24
1

1
C8034 C8031 C8032 C8033 PCIE_VDDC
R22
SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP PCIE_VDDC
T22
LEVEL PCIE_VDDC
PX PX PX PX U22
2

2
TRANSLATION PCIE_VDDC 1V_VGACORE_S0
13mA PCIE_VDDC
V22 AMD ORB 10U x 6 LF145M 4.7U x 6
1D8V_VGA_S0 AA20
VDD_CT 2.2U x 16 1U x 20
AA21

1
C8018 VDD_CT
AB20 AA15

1
SC1U10V2KX-L1-GP VDD_CT CORE VDDC C8019 C8035 C8020 C8021 C8022 C8023
AB21 N15
VDD_CT VDDC SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC10U6D3V3MX-L-GP
PX N17

2
VDDC
R13 PX PX PX PX PX PX

2
I/O VDDC
25mA AA17
VDDC
R16
R18
3D3V_VGA_S0 VDDR3 VDDC
AA18 Y21
VDDR3 VDDC
AB17 T12
VDDR3 VDDC 1V_VGACORE_S0
AB18
VDDR3 VDDC
T15 NC on JET
T17

1
VDDC AB13 U10 W9 Y9 W10 T10 AC14 AB12 AB11 AC11 AC13
Memory phase lock loop power: Dedicated C8024
V12
NC_VDDR4#V12 VDDC
T20
Y12 U13

1
analogue power in for memory PLLs SC1U10V2KX-L1-GP NC_VDDR4#Y12 VDDC C8025 C8026 C8027 C8028 C8029 C8030
U12 U16

2
1D8V_VGA_S0 MPV18 NC_VDDR4#U12 VDDC SC10U6D3V3MX-L-GP SC1U10V2KX-L1-GP SC10U6D3V3MX-L-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP
L8001 PX VDDC
U18
V21 PX PX PX PX PX PX

2
VDDC 20141117_7" to 13"
1 2 MMZ1005S241C-GP V15
VDDC 1V_VGACORE_S0
PX V17
KAMUS
1

C8043 C8044 C8045 VDDC

V20
VDDC

POWER
SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC1U10V2KX-L1-GP Y13
VDDC
PX PX PX Y16
2

1
VDDC C8059 C8036 C8037 C8038 C8039 C8040 C8041 C8063 C8064
Y18
VDDC SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP
20141117_7" to 13" AA12
VDDC
M11 PX PX PX PX PX PX PX PX PX

2
VDDC
KAMUS VDDC
N12
U11
VDDC 1V_VGACORE_S0
Engine phase loop power: Dedicated analogue
C power pin for engine PLL PLL C
1D8V_VGA_S0 BLM15BD121SN1D-GP SPV18

1
L8002 0D95V_VGA_S0 C8058 C8066 C8060 C8061 C8062
PX SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP
1 2
R21
1.4A PX PX PX PX PX

2
1

C8053 C8054 MPV18 BIF_VDDC

U21

1
SC10U6D3V3MX-L-GP SC1U10V2KX-L1-GP BIF_VDDC C8065
PX
90mA AMD ORB 10U x 2 SC10U6D3V3MX-L-GP LF145M 4.7U x 2
PX L8
2

MPLL_PVDD
PX

2
ISOLATED 1U x 3 1U x 3 1V_VGACORE_S0
SPV18 CORE I/O
M13
5A 0.1U x2 0.1U x 2
Engine phase loop power: Dedicated digital
75mA H7
VDDCI
M15

1
0D95V_VGA_S0 SPLL_PVDD VDDCI C8046 C8047 C8048 C8049 C8050 C8051 C8052
M16
power pin for engine PLL VDDCI

SC4D7U6D3V3KX-L-GP
M17 SCD1U16V2KX-L-GP SCD1U16V2KX-L-GP SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SC10U6D3V3MX-L-GP SC10U6D3V3MX-L-GP
BLM15BD121SN1D-GP SPV10 SPV10 VDDCI
M18 PX PX PX PX PX
PX PX

2
L8003 VDDCI
PX 100mA VDDCI
M20
1 2 H8 M21
SPLL_VDDC VDDCI
N20
1

C8055 C8056 VDDCI

J7
SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP SPLL_PVSS

PX PX
2

JET-XT-S3-GP
PX

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU (5/5) PWR/GND

Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 80 of 102
5 4 3 2 1
 5 4 3 2 1

Channel 0 DATA0:15 Channel 0 DATA16:31

1D5V_VGA_S0 1D5V_VGA_S0
VRAM1 VRAM2
DQA0_[31..0] 78 DQA0_[31..0] 78
B2 E3 DQA0_14 B2 E3 DQA0_18
VDD DQ0 DQA0_10 VDD DQ0 DQA0_19
D9 F7 D9 F7
VDD DQ1 DQA0_15 VDD DQ1 DQA0_17
G7 F2 G7 F2
VDD DQ2 DQA0_11 VDD DQ2 DQA0_22
K2
VDD DQ3
F8 K2
VDD DQ3
F8 DATA GROUP 2
D K8 H3 DQA0_13 DATA GROUP 1 K8 H3 DQA0_20 D
VDD DQ4 DQA0_8 VDD DQ4 DQA0_21
N1 H8 N1 H8
VDD DQ5 DQA0_12 VDD DQ5 DQA0_16
N9 G2 N9 G2
VDD DQ6 DQA0_9 VDD DQ6 DQA0_23
R1 H7 R1 H7
VDD DQ7 DQA0_3 VDD DQ7 DQA0_31
R9 D7 R9 D7
VDD DQ8 DQA0_7 VDD DQ8 DQA0_27
C3 C3
DQ9 DQA0_1 DQ9 DQA0_30
A1 C8 A1 C8
VDDQ DQ10 DQA0_6 VDDQ DQ10 DQA0_25
A8 C2 A8 C2
VDDQ DQ11 DQA0_0 VDDQ DQ11 DQA0_28
C1
VDDQ DQ12
A7 DATA GROUP 0 C1
VDDQ DQ12
A7 DATA GROUP 3
C9 A2 DQA0_5 C9 A2 DQA0_24
VDDQ DQ13 DQA0_2 VDDQ DQ13 DQA0_29
D2 B8 D2 B8
VDDQ DQ14 DQA0_4 VDDQ DQ14 DQA0_26
E9 A3 E9 A3
VDDQ DQ15 VDDQ DQ15
F1 F1
VDDQ VDDQ
H2 F3 QSAP_1 78 H2 F3 QSAP_2 78
VDDQ LDQS VDDQ LDQS
H9
VDDQ LDQS#
G3 QSAN_1 78 DQS1 H9
VDDQ LDQS#
G3 QSAN_2 78 DQS2
C7 QSAP_0 78 C7 QSAP_3 78
FBA_VREF_1 UDQS FBA_VREF_2 UDQS
H1
VREFDQ UDQS#
B7 QSAN_0 78 DQS0 H1
VREFDQ UDQS#
B7 QSAN_3 78 DQS3
FBA_VREF_1_CA M8 FBA_VREF_2_CA M8
243R2F-2-GP VRAM_CH_A_ZQ_1 VREFCA VRAM_CH_A_ZQ_2 VREFCA
2 1 R8101 L8 K1 ODTA0 78 243R2F-2-GP 2 1 R8102 L8 K1 ODTA0 78
ZQ ODT ZQ ODT
VRAM_CH0 VRAM_CH0
L2 CSA0#_0 78 L2 CSA0#_0 78
CS# CS#
78,83 MAA0 N3 T2 DRAM_RST 78,83 78,83 MAA0 N3 T2 DRAM_RST 78,83
A0 RESET# A0 RESET#
78,83 MAA1 P7 78,83 MAA1 P7
A1 A1
78,83 MAA2 P3 J1 78,83 MAA2 P3 J1
A2 NC#J1 A2 NC#J1
78,83 MAA3 N2 J9 78,83 MAA3 N2 J9
A3 NC#J9 A3 NC#J9
78,83 MAA4 P8 L1 78,83 MAA4 P8 L1
A4 NC#L1 A4 NC#L1
78,83 MAA5 P2 L9 78,83 MAA5 P2 L9
A5 NC#L9 A5 NC#L9
78,83 MAA6 R8 M7 MAA15 78,83 78,83 MAA6 R8 M7 MAA15 78,83
A6 NC#M7 A6 NC#M7
78,83 MAA7 R2 T3 MAA13 78,83 78,83 MAA7 R2 T3 MAA13 78,83
A7 NC#T3 A7 NC#T3
78,83 MAA8 T8 T7 MAA14 78,83 78,83 MAA8 T8 T7 MAA14 78,83
A8 NC#T7 A8 NC#T7
78,83 MAA9 R3 78,83 MAA9 R3
A9 A9
78,83 MAA10 L7 78,83 MAA10 L7
A10/AP A10/AP
78,83 MAA11 R7 A9 78,83 MAA11 R7 A9
A11 VSS A11 VSS
78,83 MAA12 N7 B3 78,83 MAA12 N7 B3
A12/BC# VSS A12/BC# VSS
E1 E1
VSS VSS
G8 G8
VSS VSS
78,83 MAA_BA0 M2 J2 78,83 MAA_BA0 M2 J2
BA0 VSS BA0 VSS
78,83 MAA_BA1 N8 J8 78,83 MAA_BA1 N8 J8
BA1 VSS BA1 VSS
78,83 MAA_BA2 M3 M1 78,83 MAA_BA2 M3 M1
BA2 VSS BA2 VSS
M9 M9
VSS VSS DRAM_RST
C P1 P1 C
VSS VSS
Data Mask 1 78 DQMA1 E7
LDM VSS
P9 Data Mask 2 78 DQMA2 E7
LDM VSS
P9
D3 T1 D3 T1
Data Mask 0 78 DQMA0 UDM VSS
VSS
T9
Data Mask 3 78 DQMA3 UDM VSS
VSS
T9 For VRAM1,VRAM2
78 CLKA0 J7 B1 78 CLKA0 J7 B1
CK VSSQ CK VSSQ
78 CLKA0# K7 B9 78 CLKA0# K7 B9
CK# VSSQ CK# VSSQ
D1 D1

1
VSSQ VSSQ
78 CKEA0 K9 D8 78 CKEA0 K9 D8
CKE VSSQ CKE VSSQ

ED8101

ED8102
E2 E2

PESD5V0U1BL-GP-U1

PESD5V0U1BL-GP-U1
VSSQ VSSQ
VSSQ
E8
VSSQ
E8 VRAM_CH0 VRAM_CH0
78 WEA0# L3 F9 78 WEA0# L3 F9
WE# VSSQ WE# VSSQ
78 CASA0# K3 G1 78 CASA0# K3 G1

2
CAS# VSSQ CAS# VSSQ
78 RASA0# J3 G9 78 RASA0# J3 G9
RAS# VSSQ RAS# VSSQ

MT41K256M16HA-107G-E-GP MT41K256M16HA-107G-E-GP
VRAM_CH0_BOM_CTRL VRAM_CH0_BOM_CTRL

1D5V_VGA_S0 1D5V_VGA_S0 1D5V_VGA_S0 1D5V_VGA_S0

R8105 R8106 R8301 R8302

1

1
R8103 R8109 R8107 R8111 Single Rank, 40.2 Ohm 64.40R25.6DL
4K99R2F-L-GP 4K99R2F-L-GP 4K99R2F-L-GP 4K99R2F-L-GP
VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 Dual Rank, 80.6 Ohm 64.80R65.6DL
2

2
CLKA0 CLKA0#
FBA_VREF_1 FBA_VREF_1_CA FBA_VREF_2 FBA_VREF_2_CA

1
SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP
B R8105 R8106 B
40D2R2F-GP 40D2R2F-GP
1

1
VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0
1

2
R8104 C8113 R8110 C8118 R8108 C8117 R8112 C8119 CLKA0_CLKA0#
4K99R2F-L-GP 4K99R2F-L-GP 4K99R2F-L-GP 4K99R2F-L-GP
2

1
VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0
2

2
C8116
SCD01U50V2KX-L-GP

2
VRAM_CH0

Close to VRAM1 Close to VRAM2

1D5V_VGA_S0 1D5V_VGA_S0
0.1uF(X7R) 0.1uF(X7R)
K0402 ×4 K0402 ×4
SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0

1

C8101 C8102 C8103 C8104 C8127 C8121 C8124 C8109

2

10uF(X5R) 10uF(X5R)
1.0uF(X7R) M0805 ×2 1.0uF(X7R) M0805 ×2
K0603 ×8 K0603 ×8
A A
SC10U10V5KX-L1-GP

SC10U10V5KX-L1-GP
SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP
SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0
1

1
1

1
C8115 C8114 C8126 C8122
C8105 C8106 C8107 C8108 C8110 C8111 C8112 DY C8128 C8123 C8129 C8131 C8130 C8120 C8125 DY <Core Design>
2

2
2

2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VRAM1,2 (1/4)
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 81 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VRAM3,4 (2/4)
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 82 of 102
5 4 3 2 1
 5 4 3 2 1

Channel 1 DATA16:31 Channel 1 DATA0:15

1D5V_VGA_S0 1D5V_VGA_S0
VRAM5 VRAM6
DQA1_[31..0] 78 DQA1_[31..0] 78
B2 E3 DQA1_30 B2 E3 DQA1_0
VDD DQ0 DQA1_27 VDD DQ0 DQA1_4
D9 F7 D9 F7
VDD DQ1 DQA1_29 VDD DQ1 DQA1_2
G7 F2 G7 F2
VDD DQ2 DQA1_25 VDD DQ2 DQA1_7
K2
VDD DQ3
F8 DATA GROUP 7 K2
VDD DQ3
F8 DATA GROUP 4
K8 H3 DQA1_28 K8 H3 DQA1_3
VDD DQ4 DQA1_24 VDD DQ4 DQA1_5
N1 H8 N1 H8
VDD DQ5 DQA1_31 VDD DQ5 DQA1_1
N9 G2 N9 G2
VDD DQ6 DQA1_26 VDD DQ6 DQA1_6
R1 H7 R1 H7
VDD DQ7 DQA1_19 VDD DQ7 DQA1_12
R9 D7 R9 D7
VDD DQ8 DQA1_22 VDD DQ8 DQA1_11
C3 C3
DQ9 DQA1_18 DQ9 DQA1_15
A1 C8 A1 C8
VDDQ DQ10 DQA1_21 VDDQ DQ10 DQA1_10
A8
VDDQ DQ11
C2 A8
VDDQ DQ11
C2 DATA GROUP 5
D C1 A7 DQA1_17 DATA GROUP 6 C1 A7 DQA1_13 D
VDDQ DQ12 DQA1_23 VDDQ DQ12 DQA1_8
C9 A2 C9 A2
VDDQ DQ13 DQA1_16 VDDQ DQ13 DQA1_14
D2 B8 D2 B8
VDDQ DQ14 DQA1_20 VDDQ DQ14 DQA1_9
E9 A3 E9 A3
VDDQ DQ15 VDDQ DQ15
F1 F1
VDDQ VDDQ
H2 F3 QSAP_7 78 H2 F3 QSAP_4 78
VDDQ LDQS VDDQ LDQS
H9
VDDQ LDQS#
G3 QSAN_7 78 DQS7 H9
VDDQ LDQS#
G3 QSAN_4 78 DQS4
C7 QSAP_6 78 C7 QSAP_5 78
FBA_VREF_5 UDQS FBA_VREF_6 UDQS
H1
VREFDQ UDQS#
B7 QSAN_6 78 DQS6 H1
VREFDQ UDQS#
B7 QSAN_5 78 DQS5
FBA_VREF_5_CA M8 FBA_VREF_6_CA M8
243R2F-2-GP R8308 VRAM_CH_A_ZQ_5 VREFCA 243R2F-2-GP VRAM_CH_A_ZQ_6 VREFCA
2 1 L8 K1 ODTA1 78 2 1 R8309 L8 K1 ODTA1 78
ZQ ODT ZQ ODT
VRAM_CH1 VRAM_CH1
L2 CSA1#_0 78 L2 CSA1#_0 78
CS# CS#
78,81 MAA0 N3 T2 DRAM_RST 78,81 78,81 MAA0 N3 T2 DRAM_RST 78,81
A0 RESET# A0 RESET#
78,81 MAA1 P7 78,81 MAA1 P7
A1 A1
78,81 MAA2 P3 J1 78,81 MAA2 P3 J1
A2 NC#J1 A2 NC#J1
78,81 MAA3 N2 J9 78,81 MAA3 N2 J9
A3 NC#J9 A3 NC#J9
78,81 MAA4 P8 L1 78,81 MAA4 P8 L1
A4 NC#L1 A4 NC#L1
78,81 MAA5 P2 L9 78,81 MAA5 P2 L9
A5 NC#L9 A5 NC#L9
78,81 MAA6 R8 M7 MAA15 78,81 78,81 MAA6 R8 M7 MAA15 78,81
A6 NC#M7 A6 NC#M7
78,81 MAA7 R2 T3 MAA13 78,81 78,81 MAA7 R2 T3 MAA13 78,81
A7 NC#T3 A7 NC#T3
78,81 MAA8 T8 T7 MAA14 78,81 78,81 MAA8 T8 T7 MAA14 78,81
A8 NC#T7 A8 NC#T7
78,81 MAA9 R3 78,81 MAA9 R3
A9 A9
78,81 MAA10 L7 78,81 MAA10 L7
A10/AP A10/AP
78,81 MAA11 R7 A9 78,81 MAA11 R7 A9
A11 VSS A11 VSS
78,81 MAA12 N7 B3 78,81 MAA12 N7 B3
A12/BC# VSS A12/BC# VSS
E1 E1
VSS VSS
G8 G8
VSS VSS
78,81 MAA_BA0 M2 J2 78,81 MAA_BA0 M2 J2
BA0 VSS BA0 VSS
78,81 MAA_BA1 N8 J8 78,81 MAA_BA1 N8 J8
BA1 VSS BA1 VSS
78,81 MAA_BA2 M3 M1 78,81 MAA_BA2 M3 M1
BA2 VSS BA2 VSS
M9 M9
VSS VSS
P1 P1
VSS VSS
Data Mask 7 78 DQMA7 E7
LDM VSS
P9 Data Mask 4 78 DQMA4 E7
LDM VSS
P9
Data Mask 6 78 DQMA6 D3 T1 Data Mask 5 78 DQMA5 D3 T1
UDM VSS UDM VSS DRAM_RST
T9 T9
VSS VSS
J7 B1 J7 B1
78
78
CLKA1
CLKA1# K7
CK
CK#
VSSQ
VSSQ
B9
78
78
CLKA1
CLKA1# K7
CK
CK#
VSSQ
VSSQ
B9 For VRAM5,VRAM6
D1 D1
VSSQ VSSQ
C 78 CKEA1 K9 D8 78 CKEA1 K9 D8 C
CKE VSSQ CKE VSSQ
E2 E2
VSSQ VSSQ
E8 E8

1
VSSQ VSSQ
78 WEA1# L3 F9 78 WEA1# L3 F9
WE# VSSQ WE# VSSQ

ED8301

ED8302
78 CASA1# K3 G1 78 CASA1# K3 G1

PESD5V0U1BL-GP-U1

PESD5V0U1BL-GP-U1
CAS# VSSQ CAS# VSSQ
78 RASA1# J3
RAS# VSSQ
G9 78 RASA1# J3
RAS# VSSQ
G9 VRAM_CH0 VRAM_CH0

2
MT41K256M16HA-107G-E-GP MT41K256M16HA-107G-E-GP
VRAM_CH1_BOM_CTRL VRAM_CH1_BOM_CTRL

1D5V_VGA_S0 1D5V_VGA_S0
R8105 R8106 R8301 R8302 1D5V_VGA_S0 1D5V_VGA_S0

Single Rank, 40.2 Ohm

1

1
R8305 R8376 Dual Rank, 80.6 Ohm
4K99R2F-L-GP 4K99R2F-L-GP R8374 R8378
VRAM_CH1 VRAM_CH1 CLKA1 CLKA1# 4K99R2F-L-GP 4K99R2F-L-GP
VRAM_CH1 VRAM_CH1
2

2
R8301 R8302
FBA_VREF_5 FBA_VREF_5_CA 40D2R2F-GP 40D2R2F-GP
VRAM_CH1 VRAM_CH1 FBA_VREF_6 FBA_VREF_6_CA
2

CLKA1_CLKA1#
1

VRAM_CH1 VRAM_CH1
1

1
R8306 R8375 VRAM_CH1 VRAM_CH1

1
4K99R2F-L-GP C8324 4K99R2F-L-GP C8330 C8301 R8373 R8377
VRAM_CH1 VRAM_CH1 SCD01U50V2KX-L-GP 4K99R2F-L-GP C8329 4K99R2F-L-GP C8331
2

B VRAM_CH1 VRAM_CH1 VRAM_CH1 B

2

2
SCD1U16V2KX-L-GP SCD1U16V2KX-L-GP

2
SCD1U16V2KX-L-GP SCD1U16V2KX-L-GP

Close to VRAM5 Close to VRAM6

1D5V_VGA_S0 1D5V_VGA_S0
0.1uF(X7R) 0.1uF(X7R)
K0402 ×4 K0402 ×4
SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

SCD1U16V2KX-L-GP

VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1

1

C8319 C8326 C8318 C8322 C8334 C8336 C8335 C8341

2

10uF(X5R) 10uF(X5R)
1.0uF(X7R) M0805 ×2 1.0uF(X7R) M0805 ×2
K0603 ×8 K0603 ×8
SC10U10V5KX-L1-GP

SC10U10V5KX-L1-GP
SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP
SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1
1

1
A C8328 C8327 C8337 C8333 A
C8314 C8315 C8317 C8316 C8323 C8321 C8320 C8325 DY C8339 C8332 C8340 C8344 C8342 C8338 C8345 C8343 DY
2

2
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VRAM5,6 (3/4)
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 83 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VRAM7,8 (4/4)
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 84 of 102
5 4 3 2 1
 5 4 3 2 1

AMD EXO pro DCBATOUT

PG8503
PWR_VGA_CORE_DCBATOUT_2 DCBATOUT

PG8501
PWR_VGA_CORE_DCBATOUT_1

1
1 2 1 2
PR8501 PR8502
10KR2J-3-GP 10KR2J-3-GP GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PX PX PG8504 PG8502

2
1 2 1 2

PWR_VGA_CORE_UGATE_LX_NB
PR8503 1 2 10KR2F-2-GP PX EN/DEM_VGA GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP PWR_VGA_CORE_DCBATOUT_1
3D3V_VGA_S0 TP8503

PWR_VGA_CORE_LGATE_NB
PC8502 2 1 SCD1U16V2KX-L-GP PX
PG8506 PG8505
1 2 1 2
3D3V_VGA_S0 PR8550 1 2 0R2J-2-GP PX_JET

1
D GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP D
PWR_VGA_CORE_VDDIO
1D8V_VGA_S0
PR8505 1 2 0R2J-2-GP PX_TOPAZ
PC8503 1 2 SC1KP50V2KX-L-1-GP PX

PU8504 PU8501

PU8201_36
2 2

PU8201_39
5V_S5 3 3

1
1 4 1 4 PC8504 PC8505 PC8506

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
10 10 PX PX PX
PWR_VGA_CORE_VDDIO 9 9

2
PR8504 7 7
PWR_VGA_CORE_VR_HOT# 1 2 8 6 8 6

40

39

38

37

36

35

34

33

32

31
5 5
PX_TOPAZ 10KR2F-2-GP PU8502

ISUMP_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB
5V_S5 FDMS3600-02-RJK0215-COLAY-GP FDMS3600-02-RJK0215-COLAY-GP
ZZ PX PWR Change 84.08S36.037

PR8507
2 100KR2F-L1-GP PWR_VGA_CORE_NTC_NB PWR_VGA_CORE_BOOT21 1st = 84.08S36.037
PR8506 1 PX 1
NTC_NB BOOT2
30 PX 2PWR_VGA_CORE__BOOT2_1
2D2R3-1-U-GP
1 2 PC8507 PR8510
TDC=36A
1R2F-GP 2nd = 075.06992.0073

1
PR8508 1 PX 2 100KR2F-L1-GP PWR_VGA_CORE_IMON_NB 2 29 PWR_VGA_CORE_UGATE2 SCD22U25V3KX-GP
IMON_NB UGATE2
PX PX OCP<54A
PR8509 1 2 0R0402-PAD PWR_VGA_CORE_SVC 3 28 PWR_VGA_CORE_PHASE2
79 VGA_SVC SVC PHASE2 PWR_VGA_CORE_UGATE1 1V_VGACORE_S0
PL8502
PR8511 1 2 0R0402-PAD PWR_VGA_CORE_VR_HOT# PWR_VGA_CORE_LGATE2
4 27 1ST = 68.R3610.20X

2
79 TOPAZ_OCP VR_HOT# LGATE2
PWR_VGA_CORE_SVD PWR_VGA_CORE_PHASE1
2ND = 068.R3610.1001
PR8512 1 2 0R0402-PAD 5 26 1 2 COIL-D36UH-6-GP
79 VGA_SVD SVD ISL62771HRTZ-GP-U VDDP

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
PWR_VGA_CORE_VDD
PWR_VGA_CORE_VDDIO 6
VDDIO VDD
25
PWR_VGA_CORE_LGATE1
PX
PR8513 1 2 0R2J-2-GP PWR_VGA_CORE_SVT 7 24 PWR_VGA_CORE_LGATE1
79 VGA_SVT

2
SVT LGATE1

PG8507
PX_TOPAZ PC8509 PC8508

PG8508
PR8514 1 2 PWR_VGA_CORE_ENABLE 8 23 PWR_VGA_CORE_PHASE1 SC1U10V2KX-L1-GP SC1U10V2KX-L1-GP
0R0402-PAD ENABLE PHASE1 PT8501
PX PX PX

1
2

2
PWR_VGA_CORE_PWROK 9 22 PWR_VGA_CORE_UGATE1

1
PWROK UGATE1

SE330U2VDM-L-GP
PR8515 PC8510 79.33719.L01
PWR_VGA_CORE_BOOT1
PD8501 10 21 1 PX2PWR_VGA_CORE__BOOT1_11 2

2
PWR_VGA_CORE_IMON IMON BOOT1
AEN/DEM_VGA

PWR_VGA_CORE_PH1
K 2D2R3-1-U-GP 1ST = 79.33719.L01

PWR_VGA_CORE_VO1
20,86 PE_GPIO1
1

RB551VM-30TE-17-GP 41 SCD22U25V3KX-GP
GND 3D3V_VGA_S0 PR8517
PX 2ND = 79.33719.20C
1

PGOOD
C PX PR8516 PWR_VGA_CORE_ISUMP 1 PX 2 C

ISUMN
ISUMP

COMP
ISEN2

ISEN1

VSEN
133KR2F-GP PC8511 3K65R2F-1-GP

1
NTC

RTN
PE_GPIO1 is for 83.R5003.N8F PX

FB
SC1KP50V2KX-L-1-GP
2

PR8518
PX PR8519
turning off PWR IC 1ST = 83.R5003.N8F PX PX 1KR2J-L2-GP PWR_VGA_CORE_ISEN1 1 PX2
11

12

13

14

15

16

17

18

19

20
10KR2F-2-GP

2
2nd = 83.55130.08F PWR_VGA_CORE_PGOOD
PWR_VGA_CORE_NTC

PWR_VGA_CORE_ISEN2

PWR_VGA_CORE_ISEN1

PWR_VGA_CORE_ISUMP

PWR_VGA_CORE_ISUMN

PWR_VGA_CORE_VSEN

PWR_VGA_CORE_RTN
PR8520 1 2 0R0402-PAD DGPU_PWROK 19,24,76
PX

1
PC8512 PWR_VGA_CORE_VSUM- PR8521 1 2 1R2F-GP
SC100P50V2JN-L-GP
PX

2
PWR_VGA_CORE_ISEN2
PX
PR8522 1 2 10KR2J-3-GP
PR8523
PWR_VGA_CORE_FB 2 PX 1 PWR_VGA_CORE_FB_R 2 1 PC8513
301R2F-GP SC1KP50V2KX-L-1-GP
2

20141208_KAMUS PX
PR8524
100KR2F-L1-GP
PX PR8525
PX PWR_VGA_CORE_COMP PC8514 2 1 SC100P50V2JN-L-GP 1 2 PWR_VGA_CORE_VSEN PWR_VGA_CORE_DCBATOUT_2
1

1K2R2F-1-GP
PX
PR8527 PC8516
PR8526
PC8515 2 1PWR_VGA_CORE_FB2_R2 1 1 PX 2 PWR_VGA_CORE_COMP_1 1 PX 2
2KR2F-3-GP
47KR2F-GP
1

PX SC390P50V2KX-GP-U SC330P50V2KX-3GP
PR8528 PX
PC8517 PC8518 32K4R2F-1-GP DY
1

1
SCD22U10V2KX-L1-GP

SCD22U10V2KX-L1-GP

PX PX PC8519 PC8520 PC8521

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
PU8505 PU8503 PX PX PX
2

2 2
2

2
3 3
1 4 1 4
10 10
1

9 9
PR8529 PX PX 7 7
2K61R2F-1-GP PR8530 1 2 0R0402-PAD PR8531 1 2 10R2J-L-GP 8 6 8 6
20141124_KAMUS 5 5
1VGA_VSUM-_1
2

B PR8532 PC8523 VGA_VDD_RUN_FB_L 1 TP8501 B

1

SCD22U10V2KX-L1-GP

PC8522 PX PX FDMS3600-02-RJK0215-COLAY-GP FDMS3600-02-RJK0215-COLAY-GP

11KR2F-L-GP

PX PX PC8501 2 1 SCD01U50V2KX-L-GP ZZ PX PWR Change 84.08S36.037

2

PC8524
1st = 84.08S36.037
2

SCD022U25V2KX-GP

1DY 2
PR8533 2nd = 075.06992.0073
NTC-10K-29-GP-U SC330P50V2KX-3GP VGA_VDD_RUN_FB_H 1 TP8502
PX PR8534 1 2 0R0402-PAD 2 1 1V_VGACORE_S0 1V_VGACORE_S0
PWR_VGA_CORE_UGATE2
PR8535
PL8501 1ST = 68.R3610.20X
SC
2

PWR_VGA_CORE_VSUM- PX 10R2J-L-GP
1 2
PWR_VGA_CORE_PHASE2
2ND = 068.R3610.1001
PR8536 1 2 COIL-D36UH-6-GP 1
69.60011.201 806R2F-GP
AFTP8501
PX
1

PC8525 PWR_VGA_CORE_LGATE2
1ST = 69.60011.201
SCD1U25V2KX-L-GP
PX

2
2nd = 69.60037.011 PX PG8509 PG8510
2

2
GAP-CLOSE-PWR-3-GP
20141208_KAMUS

GAP-CLOSE-PWR-3-GP
PX PT8503

1
1

SE330U2VDM-L-GP
79.33719.L01

2
PWR_VGA_CORE_PH2
LT415:PR8536=604R 1ST = 79.33719.L01

PWR_VGA_CORE_VO2
2ND = 79.33719.20C
PR8537
PWR_VGA_CORE_ISUMP 1
PX2
3K65R2F-1-GP

PR8538
PWR_VGA_CORE_ISEN2 1
PX
10KR2F-2-GP
2

PWR_VGA_CORE_PWROK PR8544 1 2 0R0402-PAD PWR_VGA_CORE_VSUM- PR8540 1 PX 2

PWR_VGA_CORE_PGOOD 1R2F-GP
A PWR_VGA_CORE_ISEN1 PR8543
PX A
1 2 10KR2J-3-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU CORE
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 85 of 102
5 4 3 2 1
 5 4 3 2 1

20151106 need Add MOS to Control 1D35V_EN# IN SB version

3D3V_VGA_S0
3D3V_S0 to 3D3V_VGA_S0 Transfer Discharge circuit 1V_VGACORE_S0 1D8V_VGA_S0 GPU PWR Sequencing
Peak current: 25mA 3D3V_VGAS0
1D5V_VGA_S0

1
1

1
R8606
Q8601
AO3413L-GP
R8603 R8604 75R2F-2-GP => 0D95V_VGA_S0/1D8V_VGA_S0

1
24R2J-GP 24R2J-GP
3D3V_S0 S D R8605
PX
DY DY

2
DIS_1D8V_NV_L
75R2F-2-GP

2
PX Q8307_D => 1D35V_VGA_S0
1
PX

G
R8607

2
84.03413.B31

D
100KR2J-1-GP
PX => VGA_CORE

Notice:ZZ.2N702.J3101
DIS_FBVDD_L
Q8602

1D35V_EN#
2

3.3V_ALW_1 2N7002K-2-GP
3D3V_VGA discharge 0D95V_VGA_S0 84.2N702.J31
2ND = 84.2N702.031 All the ASIC supplies must reach their respective
nominal voltages withing 20ms of the start of the
6

2
D Q8603 D
3rd = 84.2N702.W31
2N7002KDW-GP R8608

S
84.2N702.A3F 75R2F-2-GP DY ramp-up sequence, though a shorter ramp-up

4
Q8604 1D35V_EN#

1
2nd = 075.063D1.007C PX PX duration is preferred. The maximum slew rate on

D
2N7002KDW-GP
R8609
1

1
84.2N702.A3F

Notice:ZZ.2N702.J3101
75R2F-2-GP Q8605
2nd = 075.063D1.007C PX PX 2N7002K-2-GP
all rails is 50mV/us.
3.3V_RUN_VGA_1

3
Different To Intel, AMD Is High Active 84.2N702.J31

2
20,85 PE_GPIO1 It is recommended
2ND = 84.2N702.031 that the 3.3V rail ramp up first.

DIS_0D95V_NV_L
3rd = 84.2N702.W31
1

S
R8601 PX
It is recommended that the 0.95V rail reach at least

1D35V_EN#
1D35V_EN#
1

10KR2J-L-GP

PX C8602 90% of its normal value no later than 2ms from the
SCD1U25V2KX-L-GP
2

start of VDDC ramping up.

2

SB: DY
Follow BDW pull down to GDN

1D8V_S5 1D8V_S5 to 1D8V_VGA_S0 Transfer Peak current: 311mA

1
R8620
2 3D3V_VGA_S0
1D0V_S5 to 0D95V_VGA_S0 Transfer 1D8V_VGA_S0
1D8_0D95VGA_EN

0R0402-PAD
U8601
1

C8603
SC1U10V2KX-L1-GP 15
GND

1
PX 1 14 C8607
2

VIN1#1 VOUT1#14 SCD1U16V2KX-L-GP

2 13
VIN1#2 VOUT1#13
R8610 1 2 1D8VGA_EN 1D8VGA_EN 3 12 VTT_CT_1D8VG PX

2
0R0402-PAD 1D0V_S5 EN1 SS1
5V_S0
1D0VGA_EN
4
BIAS PX GND
11
VTT_CT_0D95VG 0D95V_VGA_S0
5 10
EN2 SS2
6 9
7
VIN2#6 VOUT2#9
8
Peak current: 2A
VIN2#7 VOUT2#8
1

C8611

1
R8612 1 2 1D0VGA_EN SC1U10V2KX-L1-GP C8608 C8609
0R0402-PAD PX APL3523AQBI-TRG-GP SC1KP50V2KX-1GP SC1KP50V2KX-1GP
2
1

1
PX PX C8614

2
C8604 C8605 SCD1U16V2KX-L-GP
SCD1U25V2KX-L-GP SCD1U25V2KX-L-GP PX
2

2
DY DY

C
NN30331A for VGA_1D5V(For VRAM DDR3) C

Reference OSLO 1D5V_VGA_S0

DCBATOUT PWR_VGA_DCBATOUT_1D5V

PG8601
1 2 GAP-CLOSE-PWR-3-GP

PG8602 5V_S5
1 2 GAP-CLOSE-PWR-3-GP

1D5V_VGA_S0
1

PC8632
SC1U10V2KX-L1-GP
MAG. 7 x 7 x 3.0 mm
PX DCR: 9m~10mOhm
TDC : 6A
2

Idc : 10 A , Isat : 22A

1
1D5V_VGA_S0

SC22U6D3V5MX-L3-GP
U8603 PC8623
PX DY

2
PWR_VGA_DCBATOUT_1D5V 21 18 PWR_1D5V_PH PL8603 1 2 PC8613 PC8614 PC8615 PC8617
VCC LX#18
17
LX#17 IND-1UH-129-GP-U
16
LX#16 68.1R010.20D
11
LX#11

2
7
IN LX#10
10 PX PX PX DY

2
8 PC8612
IN

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP
PWR_1D5V_BT SCD1U25V2KX-L-GP

SCD1U25V2KX-GP
9 20 1 2

1
PR8623 IN BST PG8609
95K3R2F-GP
PX
PWR_1D5V_VFB GAP-CLOSE-PWR-6-GP
5

1
FB
1

PC8619 PC8621 PC8628 PC8629 1 2 PWR_1D5V_TON 6

TON
SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

PC8618 PX PX PX PX
SCD1U50V3KX-L-GP PX PWR_1D5V_PG 1 4
2

PGOOD AGND PWR_1D5V_VFB_A

DY PWR_1D5V_EN 2 19
EN PGND
14
PWR_1D5V_PFM PGND
3 13
PFM# PGND
12
PGND
1

PWR_1D5V_SS 22
SS PGND
15 1
R8623 PC8624
R1
1

66K5R2F-GP SC220P50V2KX-3GP
2

PR8626 AOZ2260QI-10-GP PX DY
1

100KR2F-L1-GP PX
2

PX PC8627
SCD01U50V2KX-L-GP
2

B B
PX
1

R8622
75KR2F-GP R2 Vo=0.8x(1+R1/R2)
PX
=0.8x(66.5+75/75)
2

Add For Discharge Circuit 20151123 3D3V_S0 =1.509

1

PX Q8606 PR8622
3D3V_VGA_S0 R8624 1 2 10KR2J-3-GP PWR_1D5V_EN G 10KR2J-3-GP
PX
2
1

D 1D35V_EN#
SC1KP50V2KX-1GP

C8620 PC8631
SCD22U10V2KX-L1-GP DY S PX
2

Notice:ZZ.2N702.J3101
PX 2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.2N702.W31

3D3V_S5
1

PR8624
100KR2J-1-GP
PX
2

PWR_1D5V_PG

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU Discrete Power

Size Document Number Rev
A1
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 86 of 102

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 87 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 88 of 102
5 4 3 2 1
 5 4 3 2 1

D D
H1 H2 H3 H4 H5
STF237R128H42-7-GP STF237R128H42-7-GP STF237R128H42-7-GP STF237R128H42-7-GP STF237R128H42-7-GP
SP1 SP2
H6 SPRING-43-GP-U SPRING-43-GP-U
STF236R128H93-GP 34.4WZ01.001 34.4WZ01.001 34.4WZ01.001 34.4WZ01.001 34.4WZ01.001

1
34.4LY03.201 34.15J03.001 34.15J03.001
PX PX
1

1
1ST = 34.4LY03.201
1ST = 34.4WZ01.001 1ST = 34.4WZ01.001 1ST = 34.4WZ01.001 1ST = 34.4WZ01.001 1ST = 34.4WZ01.001
2ND = 34.4LY03.101
2ND = 34.4WZ01.101 2ND = 34.4WZ01.101 2ND = 34.4WZ01.101 2ND = 34.4WZ01.101 2ND = 34.4WZ01.101

H18
HT6BE75R26-U-45-GP

ZZ.00PAD.EH1
H11
H8 H12 H13 H14 H15
HOLE237R103-GP HT9X9B9X9R31-S-GP HT9X9B9X9R31-S-GP HT9X9B9X9R31-S-GP HT9X9B9X9R31-S-GP H16 H19
ZZ.00PAD.EJ1 ZZ.00PAD.GG1 ZZ.00PAD.GG1 ZZ.00PAD.GG1 ZZ.00PAD.GG1 HOLE237R103-GP HOLE237R103-GP

1
ZZ.00PAD.EJ1 ZZ.00PAD.EJ1

1
1

1
ZZ.00PAD.571

HOLE355X355R111-S1-GP

C C
DCBATOUT

DCBATOUT
1

EC8601 EC8602 EC8603 EC8607 EC8608 EC8612 EC8621 EC8622

2

1
SCD1U50V3KX-L-GP

SCD1U50V3KX-L-GP

SCD1U50V3KX-L-GP

SCD1U50V3KX-L-GP

SCD1U50V3KX-L-GP

SCD1U50V3KX-L-GP

SCD1U50V3KX-L-GP

SCD1U50V3KX-L-GP

EC8604 EC8605 EC8606 EC8609 EC8610 EC8611

SC1U50V5ZY-1-GP-U

SC1U50V5ZY-1-GP-U

SC1U50V5ZY-1-GP-U

SC1U50V5ZY-1-GP-U

SC1U50V5ZY-1-GP-U
2

2
SCD1U50V3KX-L-GP
3D3V_S0
3D3V_S5 5V_S5 1D0V_S5 +VCCSA
1

EC8616 EC8617
SCD1U25V2KX-L-GP

SCD1U25V2KX-L-GP

DY DY RFC8923 RFC8924 RFC8925 RFC8926 RFC8928

2

DY DY DY DY DY
1

1
SC8P50V2DN-1GP

SC8P50V2DN-1GP

SC8P50V2DN-1GP

SC8P50V2DN-1GP

SC8P50V2DN-1GP
B EC8613 C8601 EC8614 EC8615 EC8618 EC8619 EC8620 B
SCD1U25V2KX-L-GP

SC1U10V2KX-1GP

SCD1U25V2KX-L-GP

SCD1U25V2KX-L-GP

SCD1U25V2KX-L-GP

SCD1U25V2KX-L-GP

SCD1U25V2KX-L-GP

DY DY DY DY DY DY
2

2
CL7 CL8
SPRING-166-GP SPRING-166-GP

34.41L50.001 34.41L50.001

1
A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 89 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

NFC (Reserved)
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 90 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPM
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 91 of 102
5 4 3 2 1
 5 4 3 2 1

SSID = Finger Print

D D

C C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Finger Print
Size Document Number Rev
A4
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 92 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 93 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 94 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 95 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 96 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 97 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LAN SWITCH
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 98 of 102
5 4 3 2 1
 5 4 3 2 1

D D

1 TP9911
16 XDP_PREQ# TPAD14-OP-GP
16 XDP_PRDY# 1 TP9901
TPAD14-OP-GP

1 TP9915
6 CFG3 TPAD14-OP-GP

1 TP9938
6 ITP_PMODE TPAD14-OP-GP

1 TP9904
TPAD14-OP-GP
4 PROC_TCK 1 TP9902
TPAD14-OP-GP

1 TP9908
TPAD14-OP-GP
4 PROC_TDI 1 TP9903
TPAD14-OP-GP

1 TP9937
TPAD14-OP-GP
4 PROC_TMS 1 TP9905
TPAD14-OP-GP
1 TP9939
TPAD14-OP-GP
4 PROC_TRST# 1 TP9906
TPAD14-OP-GP
1 TP9940
TPAD14-OP-GP
1 TP9936
4 PCH_JTAG_TDO TPAD14-OP-GP

4 PCH_JTAG_TCK 1 TP9907
TPAD14-OP-GP
C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 99 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 100 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 101 of 102
5 4 3 2 1
 5 4 3 2 1

SKL-U/Y Timing Diagram for G3 to S0/M0 [Non Deep Sx Platform]

[#543016 Rev0.9]
(DC mode) Red Words: Controlled by EC GPIO Skylake POWER UP SEQUENCE DIAGRAM
Red: Power Rail
+RTC_VCC t01 >9ms
Orange: Output from KBC
1D0V_S5 5V_S5
RTC_RST# Light Blue: Output from CPU

DCBATOUT
Vin VDD
3D3V_AUX_S5 DC AON7403
BT+ Page43
Battery EN SW +V1.00U_CPU(VCCST)
a Page43 Page43
Sense the power button status Press Power button SLG59M1470VTR
KBC_PWRBTN# Platform to KBC PSL_IN2
c Page40
PSL_OUT#(GPIO71) keep low AC +DC_IN AON7403
3D3V_AUX_KBC a Adapter in S5_ENABLE 3D3V_S5
KBC GPIO34 control power on by 3V_5V_EN Page43
Page43
S5_ENABLE
AD+ 3D3V_S5
5V_S5 IN 1D5V_S0
5V_S5 & 3D3V_S5 need meet 0.7V difference Out
V5REF_Sus must be powered up before EN1 EN2
VccSus3_3, or after VccSus3_3 within 3D3V_S5 3D3V_S5
D
0.7 V. Also, V5REF_Sus must power 5V_S5 & 3D3V_S5 need meet 0.7V difference TLV70215DBVR D
down after VccSus3_3, or before Charger EN Vin +VCCIO_VR
VccSus3_3 within 0.7 V. +5VA_PCH_VCC5REFSUS Ta DCBATOUT TPS51275CRUKR Lx
BQ24780RUYR VIN
KBC GPIO43 to PCH DC/DC Page54
4 PM_SLP_S3# RT8068AZQWID
PM_RSMRST#(RSMRST#_RST) t05 >10ms (3.3V/5V) 5V_S5 EN VCCIO_PWRGD
t07 >100ms ACOK Page44 PGOOD
In case of a non-Deep S4/S5 Platform PCH to KBC GPIO00
timing t42 should be added to t07 PCH_SUSCLK_KBC Page45 Page52 5
which will make it 100mS minimum.

KBC GPIO20 to PCH 3D3V_AUX_S5 d PM_SLP_S4# S5 1D35V_S3

PM_PWRBTN#
3

PM_SLP_S4#

PM_SLP_S3#
3V_5V_POK TPS51716RUKR
DDR_VTT_PG_CTRL 0D675V_S0
S3

1D35V_VTT_PWRGD
2N7002 3D3V_AUX_KBC PM_SLP_SUS# PGOOD

PM_PWRBTN# g Page51
DC
After Power Button
3 4 4 5
SLP_S4# SLP_S3# DDR_PG_CTL
PCH to KBC GPIO44
PM_SLP_S4# GPIO71 GPIO05 H_VR_ENABLE
t10 PCH to KBC GPIO01 VR_EN
KBC_PWRBTN#
PM_SLP_S3# >30us PSL_IN2# S5_ENABLE DPWROK 7
KBC GPIO47 to LAN GPIO34
1
PM_LAN_ENABLE c
Enable by PM_SLP_S4# The DSW rails must be stable for at least
1D5V_S3 10 ms before DSW_PWROK is asserted to PCH.
KBC_DPWROK
GPIO66 DSW_PWROK
DDR_VREF_S3(0.75V)
5V_S0 & 3D3V_S0 need meet 0.7V difference f

TBD
5V_S0 AC_IN# b PM_PWRBTN# Skylake-U MCP
PSL_IN1# GPIO20 PWRBTN#
V5REF must be powered up before 3D3V_S0 RSMRST_PWRGD#
TBD KBC 2
Vcc3_3, or after Vcc3_3 within 0.7 j ALL_SYS_PWRGD and VR_RDY assert,
3D3V_S5

Delay 10ms
V. Also, V5REF must power down
after Vcc3_3, or before Vcc3_3
within 0.7 V.
+5VS_PCH_VCC5REF Tb MEC1404 delay 10ms; PCH_PWROK assert.
RSMRST#_KBC: Delay 10 ms after receive 8 PCH_PWROK
1D5V_S0 RSMRST_PWRGD# and PM_SLP_SUS#. AND APWROK 4 PM_SLP_S3#

AND
Vcc
RSMRST#_KBC k AND Gate
1D8V_S0 PCH_PWROK PM_SLP_S0# VCCSTG_EN
GPIO36 GPIO93 PCH_PWROK SLP_S0# U74LVC1G08G-AL5 Y

0D75V_S0 VR_RDY 6
1D8V_S0 & 1D5V_S3 power ready 7 TBD PM_SUSWARN# 5
GPIO02 SUSWARN# PROCPWRGD
RUNPWROK
ALL_SYS_PWRGD l
6 GPIO26 9 1D0V_S5 5V_S5
1D05V_PCH PM_SUSACK#
GPIO81 SUSACK#
PLTRST# 11 PCI_PLTRST#
VCCP_CPU m AND VIN VDD
It is recommended that SYS_PWROK be asserted after RSMRST#_KBC VCCSTG_EN
both PWROK assertion and processor core VR PWRGD assertion. RSMRST# EN +V1.00DX(VCCSTG)
1D05_VTT_PWRGD VOUT
k
0D85V_S0 SY6288C10CAC
PM_SLP_S4#
GPIO44 Page41
3

Delay 100ms
PM_SLP_S3#
4 GPIO01 H_VCCST_PWRGD ALL_SYS_PWRGD
0D85V_S0 6 Level Shifter
D85V_PWRGD 10 74LVC1G07GW Page17
C SYS_PWROK C
GPIO77 SYS_PWROK
CPU SVID BUS SetVID ACK 50us< t36 <2000us EXT_PWR_GATE#
Page24 1D35VTT_PWRGD
VCC_CORE EXT_PWR_GATE# 5
ALL_SYS_PWRGD assert, SLP_SUS#
g ALL_SYS_PWRGD
VCC_GFXCORE delay 100ms; SYS_PWROK assert. VCCIO_PWRGD
t37
3D3V_S5 5 6
<5ms
g
IMVP_PWRGD
VIN

PM_SLP_SUS# 3D3V_S5_PCH
PCH_CLOCK_OUT SVID Transanctions EN SW

ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH

SY6288C10CAC
This signal represents the Power
Good for all the non-CORE and PWROK(S0_PWR_GOOD) Page41
non-graphics power rails.
t18
D85V_PWRGD >0us PCH to CPU
DRAMPWROK(VDDPWRGOOD) 2ms<t17 <650ms IMVP8 3D3V_S5
>1ms
CPU SVID Rails
t19
6 ALL_SYS_PWRGD SA/Core/GT/GTx
VR_ON
1D8V_S0
t20 >2ms
5ms<t13 <650ms VR_RDY VR_READY VIN
PCH to CPU PM_SLP_SUS#
UNCOREPWRGOOD(H_CPUPWRGD) 7 VCCPRIM_CORE
EN LX

SYS_PWROK t21+t22 >1ms+60us RT8068AZQWID VCCPRIMCORE_PWROK

PGOOD

1ms< t25 <100ms PCH to all system 1D0V_S5 5V_S5 Page52 h

PLT_RST#
t39 <200us
3D3V_S5 5V_S5
DMI
Vin VDD

+VCCMPHYGTAON_1P0_LS_SIP
EXT_PWR_GATE# EN SW
Vin VCNTL
g PM_SLP_SUS#
SLG59M1470VTR 1D8V_S5
EN Vout
Page17
APL5930KAI 1D8V_S5_PWROK
PGOOD

Page54 h

3V_5V_POK
e 0R 0402
PWR_DCBATOUT_1D0V
VCCPRIMCORE_PWROK RSMRST_PWRGD#
h 0R 0402

1D8V_S5_PWROK
j VIN
h 0R 0402
1D0V_S5
LX
1D0V_S5_PWRGD VCCPRIMCORE_PWROK EN
i
0R 0402
SY8208DQNC 1D0V_S5_PWRGD
h PGOOD

[dGPU] N16x Power-Up/Down Sequence Page53 i

B B

[DG-07158-001_v03]

a b c d e f g h i j k l m

1 2 3a 4 4a 4b 5 6 7 8 9 10 11 12

A A

<Core Des ign>

Wistron Corporation
21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.

Title

POWER SEQUENCE
Size Docum ent Num ber Rev
A0
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 102 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram

Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 103 of 102
5 4 3 2 1
 A B C D E

PCH SMBus Block Diagram KBC SMBus Block Diagram

3D3V_S5_PCH 3D3V_S0
TP_VDD
‧ ‧
3D3V_S0 ‧
SRN2K2J-1-GP SRN10KJ-5-GP
‧
DIMM 1 SRN10KJ-5-GP

1 SMBCLK SMB_CLK
‧ ‧PCH_SMBCLK 1

SMBDATA SMB_DATA
‧ ‧ PCH_SMBDATA
SCL

SDA
TouchPad Conn.
PSDAT1 TPDATA
‧ TPDATA TPDATA

SMBus Address:0xA0/0xA1 PSCLK1 TPCLK

‧ TPCLK TPCLK
2N7002SPT
3D3V_AUX_KBC

TPAD
PCH_SMBCLK
SCL
‧
PCH_SMBDATA
3D3V_S5_PCH SDA
SRN4K7J-8-GP
SMBus Address:0x58/0x59
‧
SRN33J-7-GP Battery Conn.
GPIO17/SCL1 ‧‧BAT_SCL PBAT_SMBCLK1 CLK_SMB
SRN2K2J-1-GP PTN3355 GPIO22/SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB SMBus address:16
PCH_SMBCLK
VDDA33_DP
‧ ‧
PCH_SMBDATA
TMS (Janus Only)
SML0CLK SML0_CLK

SML0DATA SML0_DATA SMBus Address:0xC0H/0x40H HPA02224RGRR

SCL
KBC SDA SMBus address:12
NPCE285P
2 2

GPIO73/SCL2

GPIO74/SDA2

PCH 3D3V_S0 SMBus Address:

3D3V_S5_PCH 0x94/0x95/0x96/0x97
‧
3D3V_S0
SRN2K2J-8-GP

‧ SRN2K2J-8-GP

SML1CLK ‧ ‧ SML1_CLK
‧ THM_SML1_CLK
SCL Thermal
‧ ‧ SML1_DATA
‧ THM_SML1_DATA
SML1DATA SDL
NCT7718W
SMBus Address:0x82/0x83 SMBus Address:0x98/0x99
2N7002SPT
3D3V_VGA_S0

‧SRN4K7J-8-GP
3D3V_VGA_S0

‧
dGPU
3 3

SMBC_Therm_NV I2CS_SCL
‧
SMBD_Therm_NV I2CS_SDA
‧
SMBus Address:0x9E/0x9F

3D3V_S0 5V_S0

0R2J-2-GP
‧ ‧ DY
3D3V_S0
SRN2K2J-1-GP SRN2K2J-1-GP GPIO47/SCL4A PROCHOT_EC
‧ ‧ H_PROCHOT_EC
GPIO53/SDA4A LCD_TST_EN LCD_TST_EN
‧ ‧
0R2J-2-GP
DDPB_CTRLCLK ‧PCH_HDMI_CLK DDC_CLK_HDMI ‧ LCD_TST
DDPB_CTRLDATA
‧ PCH_HDMI_DATA ‧‧ DDC_DATA_HDMI ‧ HDMI CONN
2N7002DW-1-GP

4 4

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SMBUS BLOCK DIAGRAM

Size Document Number Rev
A2
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 104 of 102
A B C D E
 A B C D E

Thermal Block Diagram Audio Block Diagram

1 1

3D3V_S5_PCH 3D3V_S0
PAGE28 D+ NCT7718_DXP
PCH MMBT3904-3-GP
SPKR_L+
SPKR_L-

D- NCT7718_DXN
SC2200P50V2KX-2GP SPKR_R-
SPKR_R+ SPEAKER
Thermal Place near CPU
SML1_DATA THM_SML1_DATA
NCT7718 PWM CORE
Codec
SML1DATA/GPIO74 ‧ ‧‧ 2N7002 ‧ SDA

SML1CLK/GPIO75 SML1_CLK
‧‧ ‧ THM_SML1_CLK
‧ SCL
MMBT3904-3-GP
ALC3223
T8 AUD_HP1_JACK_L HP MIC
SML1_DATA

AUD_HP1_JACK_R
SML1_CLK

PAGE20
3D3V_S0
T_CRIT# THERM_SYS_SHDN#
2N7002
S
D
PURE_HW_SHUTDOWN#

PCH_PWROK
EN 3V/5V SLEEVE COMBO
G RING2
2 2
‧ Put under CPU(T8 HW shutdown)

PAGE27 GPIO74 PAGE86

KBC GPIO73
R2714
Digital
NPCE285P 2N7002
SMBD_THERM_NV I2CS_SCL
VGA GPIO0/DMIC_DATA
DMIC_DATA_R
0R2J-2-GP
DMIC_DATA
MIC
SMBC_THERM_NV I2CS_SDA DMIC_CLK_R R2716 DMIC_CLK
GPIO1/DMIC_CLK
0R2J-2-GP

GPIO4
N15V-GM-S-A2
GPIO94 GPIO56
GB2-64 (23x23)
FAN_TACH1
FAN1_DAC_1

3 3
TACH

FAN
VIN
FAN_VCC1

5V

VIN VSET VOUT

FAN CONTROL
APL5606AKI
PAGE28

4 4
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
THERMAL/AUDIO BLOCK DIAGRAM
Size Document Number Rev
Custom
ODYSSEY SKL-U -1
Date: Monday, April 25, 2016 Sheet 105 of 102
A B C D E