lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
Simple single-port AXI memory interface
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
BaseJump STL: A Standard Template Library for SystemVerilog
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
RISC-V Debug Support for our PULP RISC-V Cores
[UNRELEASED] FP div/sqrt unit for transprecision
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
Common SystemVerilog components