102struct MachineVerifier {
106 ReportedErrs(AbortOnError) {}
109 bool AbortOnError =
true)
111 ReportedErrs(AbortOnError) {}
116 bool AbortOnError =
true)
117 :
OS(
OS ? *
OS :
nulls()), Banner(
b), LiveVars(LiveVars),
118 LiveInts(LiveInts), LiveStks(LiveStks), Indexes(Indexes),
119 ReportedErrs(AbortOnError) {}
125 Pass *
const PASS =
nullptr;
136 bool isFunctionRegBankSelected =
false;
137 bool isFunctionSelected =
false;
138 bool isFunctionTracksDebugUserValues =
false;
148 BlockSet FunctionBlocks;
152 RegVector regsDefined, regsDead, regsKilled;
153 RegMaskVector regMasks;
158 void addRegWithSubRegs(RegVector &RV,
Register Reg) {
160 if (
Reg.isPhysical())
166 bool reachable =
false;
187 RegSet vregsRequired;
190 BlockSet Preds, Succs;
197 if (!
Reg.isVirtual())
199 if (regsLiveOut.count(Reg))
201 return vregsRequired.insert(Reg).second;
205 bool addRequired(
const RegSet &RS) {
206 bool Changed =
false;
208 Changed |= addRequired(Reg);
213 bool addRequired(
const RegMap &RM) {
214 bool Changed =
false;
215 for (
const auto &
I : RM)
216 Changed |= addRequired(
I.first);
222 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
230 return Reg.id() < regsReserved.
size() && regsReserved.
test(
Reg.id());
233 bool isAllocatable(
Register Reg)
const {
234 return Reg.id() <
TRI->getNumRegs() &&
TRI->isInAllocatableClass(Reg) &&
246 class ReportedErrors {
247 unsigned NumReported = 0;
252 ReportedErrors(
bool AbortOnError) : AbortOnError(AbortOnError) {}
259 " machine code errors.");
262 ReportedErrorsLock->unlock();
272 ReportedErrorsLock->lock();
274 return NumReported == 1;
278 bool hasError() {
return NumReported; }
280 ReportedErrors ReportedErrs;
287 void visitMachineFunctionBefore();
303 void visitMachineOperand(
const MachineOperand *MO,
unsigned MONum);
306 void visitMachineFunctionAfter();
311 void report(
const char *msg,
const MachineOperand *MO,
unsigned MONum,
319 void report_context(
const VNInfo &VNI)
const;
320 void report_context(
SlotIndex Pos)
const;
321 void report_context(
MCPhysReg PhysReg)
const;
322 void report_context_liverange(
const LiveRange &LR)
const;
323 void report_context_lanemask(
LaneBitmask LaneMask)
const;
324 void report_context_vreg(
Register VReg)
const;
325 void report_context_vreg_regunit(
VirtRegOrUnit VRegOrUnit)
const;
340 void calcRegsPassed();
343 void calcRegsRequired();
344 void verifyLiveVariables();
345 void verifyLiveIntervals();
349 void verifyLiveRangeSegment(
const LiveRange &,
355 void verifyStackFrame();
357 void verifyStackProtector();
359 void verifySlotIndexes()
const;
366 const std::string Banner;
368 MachineVerifierLegacyPass(std::string banner = std::string())
387 MachineFunctionProperties::Property::FailsVerification))
390 MachineVerifier(
this, Banner.c_str(), &
errs()).verify(MF);
406 MachineVerifier(MFAM, Banner.c_str(), &
errs()).verify(MF);
410char MachineVerifierLegacyPass::ID = 0;
413 "Verify generated machine code",
false,
false)
416 return new MachineVerifierLegacyPass(Banner);
426 MachineVerifier(
nullptr, Banner.c_str(), &
errs()).verify(MF);
430 bool AbortOnError)
const {
431 return MachineVerifier(p, Banner,
OS, AbortOnError).verify(*
this);
436 bool AbortOnError)
const {
437 return MachineVerifier(Banner,
nullptr, LiveInts,
438 nullptr, Indexes,
OS, AbortOnError)
442void MachineVerifier::verifySlotIndexes()
const {
443 if (Indexes ==
nullptr)
461 MRI->getNumVirtRegs())
462 report(
"Function has NoVRegs property but there are VReg operands", &MF);
479 if (isFunctionFailedISel)
491 LiveInts = LISWrapper ? &LISWrapper->getLIS() :
nullptr;
495 LiveVars = LVWrapper ? &LVWrapper->getLV() :
nullptr;
497 LiveStks = LSWrapper ? &LSWrapper->getLS() :
nullptr;
499 Indexes = SIWrapper ? &SIWrapper->getSI() :
nullptr;
512 verifyProperties(MF);
514 visitMachineFunctionBefore();
516 visitMachineBasicBlockBefore(&
MBB);
520 bool InBundle =
false;
523 if (
MI.getParent() != &
MBB) {
524 report(
"Bad instruction parent pointer", &
MBB);
525 OS <<
"Instruction: " <<
MI;
530 if (InBundle && !
MI.isBundledWithPred())
531 report(
"Missing BundledPred flag, "
532 "BundledSucc was set on predecessor",
534 if (!InBundle &&
MI.isBundledWithPred())
535 report(
"BundledPred flag is set, "
536 "but BundledSucc not set on predecessor",
540 if (!
MI.isInsideBundle()) {
542 visitMachineBundleAfter(CurBundle);
544 visitMachineBundleBefore(CurBundle);
545 }
else if (!CurBundle)
546 report(
"No bundle header", &
MI);
547 visitMachineInstrBefore(&
MI);
548 for (
unsigned I = 0, E =
MI.getNumOperands();
I != E; ++
I) {
550 if (
Op.getParent() != &
MI) {
553 report(
"Instruction has operand with wrong parent set", &
MI);
556 visitMachineOperand(&
Op,
I);
560 InBundle =
MI.isBundledWithSucc();
563 visitMachineBundleAfter(CurBundle);
565 report(
"BundledSucc flag set on last instruction in block", &
MBB.
back());
566 visitMachineBasicBlockAfter(&
MBB);
568 visitMachineFunctionAfter();
578 return !ReportedErrs.hasError();
581void MachineVerifier::report(
const char *msg,
const MachineFunction *MF) {
584 if (ReportedErrs.increment()) {
586 OS <<
"# " << Banner <<
'\n';
588 if (LiveInts !=
nullptr)
594 OS <<
"*** Bad machine code: " << msg <<
" ***\n"
595 <<
"- function: " << MF->
getName() <<
'\n';
602 <<
" (" << (
const void *)
MBB <<
')';
604 OS <<
" [" << Indexes->getMBBStartIdx(
MBB) <<
';'
605 << Indexes->getMBBEndIdx(
MBB) <<
')';
609void MachineVerifier::report(
const char *msg,
const MachineInstr *
MI) {
611 report(msg,
MI->getParent());
612 OS <<
"- instruction: ";
613 if (Indexes && Indexes->hasIndex(*
MI))
614 OS << Indexes->getInstructionIndex(*
MI) <<
'\t';
618void MachineVerifier::report(
const char *msg,
const MachineOperand *MO,
619 unsigned MONum,
LLT MOVRegType) {
622 OS <<
"- operand " << MONum <<
": ";
628 report(Msg.
str().c_str(),
MI);
631void MachineVerifier::report_context(
SlotIndex Pos)
const {
632 OS <<
"- at: " << Pos <<
'\n';
635void MachineVerifier::report_context(
const LiveInterval &LI)
const {
636 OS <<
"- interval: " << LI <<
'\n';
639void MachineVerifier::report_context(
const LiveRange &LR,
642 report_context_liverange(LR);
643 report_context_vreg_regunit(VRegOrUnit);
645 report_context_lanemask(LaneMask);
649 OS <<
"- segment: " << S <<
'\n';
652void MachineVerifier::report_context(
const VNInfo &VNI)
const {
653 OS <<
"- ValNo: " << VNI.
id <<
" (def " << VNI.
def <<
")\n";
656void MachineVerifier::report_context_liverange(
const LiveRange &LR)
const {
657 OS <<
"- liverange: " << LR <<
'\n';
660void MachineVerifier::report_context(
MCPhysReg PReg)
const {
664void MachineVerifier::report_context_vreg(
Register VReg)
const {
668void MachineVerifier::report_context_vreg_regunit(
678void MachineVerifier::report_context_lanemask(
LaneBitmask LaneMask)
const {
683 BBInfo &MInfo = MBBInfoMap[
MBB];
684 if (!MInfo.reachable) {
685 MInfo.reachable =
true;
691void MachineVerifier::visitMachineFunctionBefore() {
693 regsReserved =
MRI->reservedRegsFrozen() ?
MRI->getReservedRegs()
694 :
TRI->getReservedRegs(*MF);
697 markReachable(&MF->
front());
700 FunctionBlocks.clear();
701 for (
const auto &
MBB : *MF) {
702 FunctionBlocks.insert(&
MBB);
703 BBInfo &MInfo = MBBInfoMap[&
MBB];
707 report(
"MBB has duplicate entries in its predecessor list.", &
MBB);
711 report(
"MBB has duplicate entries in its successor list.", &
MBB);
715 MRI->verifyUseLists();
719 verifyStackProtector();
725 FirstTerminator =
nullptr;
726 FirstNonPHI =
nullptr;
728 if (!MF->getProperties().hasProperty(
733 if (isAllocatable(LI.PhysReg) && !
MBB->
isEHPad() &&
736 report(
"MBB has allocatable live-in, but isn't entry, landing-pad, or "
737 "inlineasm-br-indirect-target.",
739 report_context(LI.PhysReg);
746 report(
"ir-block-address-taken is associated with basic block not used by "
755 LandingPadSuccs.
insert(succ);
756 if (!FunctionBlocks.count(succ))
757 report(
"MBB has successor that isn't part of the function.",
MBB);
758 if (!MBBInfoMap[succ].Preds.count(
MBB)) {
759 report(
"Inconsistent CFG",
MBB);
760 OS <<
"MBB is not in the predecessor list of the successor "
767 if (!FunctionBlocks.count(Pred))
768 report(
"MBB has predecessor that isn't part of the function.",
MBB);
769 if (!MBBInfoMap[Pred].Succs.count(
MBB)) {
770 report(
"Inconsistent CFG",
MBB);
771 OS <<
"MBB is not in the successor list of the predecessor "
779 if (LandingPadSuccs.
size() > 1 &&
784 report(
"MBB has more than one landing pad successor",
MBB);
797 report(
"MBB exits via unconditional fall-through but ends with a "
798 "barrier instruction!",
MBB);
801 report(
"MBB exits via unconditional fall-through but has a condition!",
804 }
else if (
TBB && !FBB &&
Cond.empty()) {
807 report(
"MBB exits via unconditional branch but doesn't contain "
808 "any instructions!",
MBB);
810 report(
"MBB exits via unconditional branch but doesn't end with a "
811 "barrier instruction!",
MBB);
813 report(
"MBB exits via unconditional branch but the branch isn't a "
814 "terminator instruction!",
MBB);
816 }
else if (
TBB && !FBB && !
Cond.empty()) {
819 report(
"MBB exits via conditional branch/fall-through but doesn't "
820 "contain any instructions!",
MBB);
822 report(
"MBB exits via conditional branch/fall-through but ends with a "
823 "barrier instruction!",
MBB);
825 report(
"MBB exits via conditional branch/fall-through but the branch "
826 "isn't a terminator instruction!",
MBB);
828 }
else if (
TBB && FBB) {
832 report(
"MBB exits via conditional branch/branch but doesn't "
833 "contain any instructions!",
MBB);
835 report(
"MBB exits via conditional branch/branch but doesn't end with a "
836 "barrier instruction!",
MBB);
838 report(
"MBB exits via conditional branch/branch but the branch "
839 "isn't a terminator instruction!",
MBB);
842 report(
"MBB exits via conditional branch/branch but there's no "
846 report(
"analyzeBranch returned invalid data!",
MBB);
852 report(
"MBB exits via jump or conditional branch, but its target isn't a "
856 report(
"MBB exits via conditional branch, but its target isn't a CFG "
863 bool Fallthrough = !
TBB || (!
Cond.empty() && !FBB);
868 if (!
Cond.empty() && !FBB) {
871 report(
"MBB conditionally falls through out of function!",
MBB);
873 report(
"MBB exits via conditional branch/fall-through but the CFG "
874 "successors don't match the actual successors!",
881 if (SuccMBB ==
TBB || SuccMBB == FBB)
889 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
891 report(
"MBB has unexpected successors which are not branch targets, "
892 "fallthrough, EHPads, or inlineasm_br targets.",
898 if (
MRI->tracksLiveness()) {
900 if (!LI.PhysReg.isPhysical()) {
901 report(
"MBB live-in list contains non-physical register",
MBB);
920 lastIndex = Indexes->getMBBStartIdx(
MBB);
925void MachineVerifier::visitMachineBundleBefore(
const MachineInstr *
MI) {
926 if (Indexes && Indexes->hasIndex(*
MI)) {
928 if (!(idx > lastIndex)) {
929 report(
"Instruction index out of order",
MI);
930 OS <<
"Last instruction was at " << lastIndex <<
'\n';
936 if (
MI->isTerminator()) {
937 if (!FirstTerminator)
938 FirstTerminator =
MI;
939 }
else if (FirstTerminator) {
942 if (FirstTerminator->
getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
943 report(
"Non-terminator instruction after the first terminator",
MI);
944 OS <<
"First terminator was:\t" << *FirstTerminator;
953 if (
MI->getNumOperands() < 2) {
954 report(
"Too few operands on inline asm",
MI);
957 if (!
MI->getOperand(0).isSymbol())
958 report(
"Asm string must be an external symbol",
MI);
959 if (!
MI->getOperand(1).isImm())
960 report(
"Asm flags must be an immediate",
MI);
964 if (!isUInt<6>(
MI->getOperand(1).getImm()))
965 report(
"Unknown asm flags", &
MI->getOperand(1), 1);
971 for (
unsigned e =
MI->getNumOperands(); OpNo <
e; OpNo += NumOps) {
977 NumOps = 1 +
F.getNumOperandRegisters();
980 if (OpNo >
MI->getNumOperands())
981 report(
"Missing operands in last group",
MI);
984 if (OpNo < MI->getNumOperands() &&
MI->getOperand(OpNo).isMetadata())
988 for (
unsigned e =
MI->getNumOperands(); OpNo < e; ++OpNo) {
991 report(
"Expected implicit register after groups", &MO, OpNo);
994 if (
MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
1007 if (!IndirectTargetMBB) {
1008 report(
"INLINEASM_BR indirect target does not exist", &MO, i);
1013 report(
"INLINEASM_BR indirect target missing from successor list", &MO,
1017 report(
"INLINEASM_BR indirect target predecessor list missing parent",
1023bool MachineVerifier::verifyAllRegOpsScalar(
const MachineInstr &
MI,
1028 const auto Reg = Op.getReg();
1029 if (Reg.isPhysical())
1031 return !MRI.getType(Reg).isScalar();
1034 report(
"All register operands must have scalar types", &
MI);
1041bool MachineVerifier::verifyVectorElementMatch(
LLT Ty0,
LLT Ty1,
1044 report(
"operand types must be all-vector or all-scalar",
MI);
1054 report(
"operand types must preserve number of vector elements",
MI);
1061bool MachineVerifier::verifyGIntrinsicSideEffects(
const MachineInstr *
MI) {
1062 auto Opcode =
MI->getOpcode();
1063 bool NoSideEffects = Opcode == TargetOpcode::G_INTRINSIC ||
1064 Opcode == TargetOpcode::G_INTRINSIC_CONVERGENT;
1065 unsigned IntrID = cast<GIntrinsic>(
MI)->getIntrinsicID();
1066 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1068 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
1069 bool DeclHasSideEffects = !
Attrs.getMemoryEffects().doesNotAccessMemory();
1070 if (NoSideEffects && DeclHasSideEffects) {
1072 " used with intrinsic that accesses memory"),
1076 if (!NoSideEffects && !DeclHasSideEffects) {
1077 report(
Twine(
TII->getName(Opcode),
" used with readnone intrinsic"),
MI);
1085bool MachineVerifier::verifyGIntrinsicConvergence(
const MachineInstr *
MI) {
1086 auto Opcode =
MI->getOpcode();
1087 bool NotConvergent = Opcode == TargetOpcode::G_INTRINSIC ||
1088 Opcode == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
1089 unsigned IntrID = cast<GIntrinsic>(
MI)->getIntrinsicID();
1090 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1092 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
1093 bool DeclIsConvergent =
Attrs.hasFnAttr(Attribute::Convergent);
1094 if (NotConvergent && DeclIsConvergent) {
1095 report(
Twine(
TII->getName(Opcode),
" used with a convergent intrinsic"),
1099 if (!NotConvergent && !DeclIsConvergent) {
1101 Twine(
TII->getName(Opcode),
" used with a non-convergent intrinsic"),
1110void MachineVerifier::verifyPreISelGenericInstruction(
const MachineInstr *
MI) {
1111 if (isFunctionSelected)
1112 report(
"Unexpected generic instruction in a Selected function",
MI);
1115 unsigned NumOps =
MI->getNumOperands();
1118 if (
MI->isBranch() && !
MI->isIndirectBranch()) {
1119 bool HasMBB =
false;
1128 report(
"Branch instruction is missing a basic block operand or "
1129 "isIndirectBranch property",
1138 if (!MCID.
operands()[
I].isGenericType())
1142 size_t TypeIdx = MCID.
operands()[
I].getGenericTypeIndex();
1143 Types.resize(std::max(TypeIdx + 1,
Types.size()));
1147 report(
"generic instruction must use register operands",
MI);
1157 if (!Types[TypeIdx].
isValid())
1158 Types[TypeIdx] = OpTy;
1159 else if (Types[TypeIdx] != OpTy)
1160 report(
"Type mismatch in generic instruction", MO,
I, OpTy);
1163 report(
"Generic instruction is missing a virtual register type", MO,
I);
1168 for (
unsigned I = 0;
I <
MI->getNumOperands(); ++
I) {
1171 report(
"Generic instruction cannot have physical register", MO,
I);
1183 unsigned Opc =
MI->getOpcode();
1185 case TargetOpcode::G_ASSERT_SEXT:
1186 case TargetOpcode::G_ASSERT_ZEXT: {
1187 std::string OpcName =
1188 Opc == TargetOpcode::G_ASSERT_ZEXT ?
"G_ASSERT_ZEXT" :
"G_ASSERT_SEXT";
1189 if (!
MI->getOperand(2).isImm()) {
1190 report(
Twine(OpcName,
" expects an immediate operand #2"),
MI);
1196 LLT SrcTy =
MRI->getType(Src);
1197 int64_t
Imm =
MI->getOperand(2).getImm();
1199 report(
Twine(OpcName,
" size must be >= 1"),
MI);
1204 report(
Twine(OpcName,
" size must be less than source bit width"),
MI);
1212 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1213 report(
Twine(OpcName,
" cannot change register bank"),
MI);
1219 if (DstRC && DstRC !=
MRI->getRegClassOrNull(Src)) {
1221 Twine(OpcName,
" source and destination register classes must match"),
1229 case TargetOpcode::G_CONSTANT:
1230 case TargetOpcode::G_FCONSTANT: {
1231 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1233 report(
"Instruction cannot use a vector result type",
MI);
1235 if (
MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1236 if (!
MI->getOperand(1).isCImm()) {
1237 report(
"G_CONSTANT operand must be cimm",
MI);
1243 report(
"inconsistent constant size",
MI);
1245 if (!
MI->getOperand(1).isFPImm()) {
1246 report(
"G_FCONSTANT operand must be fpimm",
MI);
1253 report(
"inconsistent constant size",
MI);
1259 case TargetOpcode::G_LOAD:
1260 case TargetOpcode::G_STORE:
1261 case TargetOpcode::G_ZEXTLOAD:
1262 case TargetOpcode::G_SEXTLOAD: {
1263 LLT ValTy =
MRI->getType(
MI->getOperand(0).getReg());
1264 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1266 report(
"Generic memory instruction must access a pointer",
MI);
1270 if (!
MI->hasOneMemOperand()) {
1271 report(
"Generic instruction accessing memory must have one mem operand",
1275 if (
MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1276 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1279 report(
"Generic extload must have a narrower memory type",
MI);
1280 }
else if (
MI->getOpcode() == TargetOpcode::G_LOAD) {
1283 report(
"load memory size cannot exceed result size",
MI);
1290 report(
"range is incompatible with the result type",
MI);
1293 }
else if (
MI->getOpcode() == TargetOpcode::G_STORE) {
1296 report(
"store memory size cannot exceed value size",
MI);
1300 if (Opc == TargetOpcode::G_STORE) {
1303 report(
"atomic store cannot use acquire ordering",
MI);
1308 report(
"atomic load cannot use release ordering",
MI);
1314 case TargetOpcode::G_PHI: {
1315 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1320 LLT Ty = MRI->getType(MO.getReg());
1321 if (!Ty.isValid() || (Ty != DstTy))
1325 report(
"Generic Instruction G_PHI has operands with incompatible/missing "
1330 case TargetOpcode::G_BITCAST: {
1331 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1332 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1337 report(
"bitcast cannot convert between pointers and other types",
MI);
1340 report(
"bitcast sizes must match",
MI);
1343 report(
"bitcast must change the type",
MI);
1347 case TargetOpcode::G_INTTOPTR:
1348 case TargetOpcode::G_PTRTOINT:
1349 case TargetOpcode::G_ADDRSPACE_CAST: {
1350 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1351 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1355 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1360 if (
MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1362 report(
"inttoptr result type must be a pointer",
MI);
1364 report(
"inttoptr source type must not be a pointer",
MI);
1365 }
else if (
MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1367 report(
"ptrtoint source type must be a pointer",
MI);
1369 report(
"ptrtoint result type must not be a pointer",
MI);
1371 assert(
MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1373 report(
"addrspacecast types must be pointers",
MI);
1376 report(
"addrspacecast must convert different address spaces",
MI);
1382 case TargetOpcode::G_PTR_ADD: {
1383 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1384 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1385 LLT OffsetTy =
MRI->getType(
MI->getOperand(2).getReg());
1390 report(
"gep first operand must be a pointer",
MI);
1393 report(
"gep offset operand must not be a pointer",
MI);
1398 unsigned IndexSizeInBits =
DL.getIndexSize(AS) * 8;
1400 report(
"gep offset operand must match index size for address space",
1408 case TargetOpcode::G_PTRMASK: {
1409 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1410 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1411 LLT MaskTy =
MRI->getType(
MI->getOperand(2).getReg());
1416 report(
"ptrmask result type must be a pointer",
MI);
1419 report(
"ptrmask mask type must be an integer",
MI);
1421 verifyVectorElementMatch(DstTy, MaskTy,
MI);
1424 case TargetOpcode::G_SEXT:
1425 case TargetOpcode::G_ZEXT:
1426 case TargetOpcode::G_ANYEXT:
1427 case TargetOpcode::G_TRUNC:
1428 case TargetOpcode::G_FPEXT:
1429 case TargetOpcode::G_FPTRUNC: {
1436 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1437 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1442 report(
"Generic extend/truncate can not operate on pointers",
MI);
1444 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1448 switch (
MI->getOpcode()) {
1450 if (DstSize <= SrcSize)
1451 report(
"Generic extend has destination type no larger than source",
MI);
1453 case TargetOpcode::G_TRUNC:
1454 case TargetOpcode::G_FPTRUNC:
1455 if (DstSize >= SrcSize)
1456 report(
"Generic truncate has destination type no smaller than source",
1462 case TargetOpcode::G_SELECT: {
1463 LLT SelTy =
MRI->getType(
MI->getOperand(0).getReg());
1464 LLT CondTy =
MRI->getType(
MI->getOperand(1).getReg());
1470 verifyVectorElementMatch(SelTy, CondTy,
MI);
1473 case TargetOpcode::G_MERGE_VALUES: {
1478 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1479 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1481 report(
"G_MERGE_VALUES cannot operate on vectors",
MI);
1483 const unsigned NumOps =
MI->getNumOperands();
1485 report(
"G_MERGE_VALUES result size is inconsistent",
MI);
1487 for (
unsigned I = 2;
I != NumOps; ++
I) {
1488 if (
MRI->getType(
MI->getOperand(
I).getReg()) != SrcTy)
1489 report(
"G_MERGE_VALUES source types do not match",
MI);
1494 case TargetOpcode::G_UNMERGE_VALUES: {
1495 unsigned NumDsts =
MI->getNumOperands() - 1;
1496 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1497 for (
unsigned i = 1; i < NumDsts; ++i) {
1498 if (
MRI->getType(
MI->getOperand(i).getReg()) != DstTy) {
1499 report(
"G_UNMERGE_VALUES destination types do not match",
MI);
1504 LLT SrcTy =
MRI->getType(
MI->getOperand(NumDsts).getReg());
1512 report(
"G_UNMERGE_VALUES source operand does not match vector "
1513 "destination operands",
1520 report(
"G_UNMERGE_VALUES vector source operand does not match scalar "
1521 "destination operands",
1526 report(
"G_UNMERGE_VALUES scalar source operand does not match scalar "
1527 "destination operands",
1533 case TargetOpcode::G_BUILD_VECTOR: {
1536 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1537 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1539 report(
"G_BUILD_VECTOR must produce a vector from scalar operands",
MI);
1544 report(
"G_BUILD_VECTOR result element type must match source type",
MI);
1547 report(
"G_BUILD_VECTOR must have an operand for each elemement",
MI);
1550 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1551 report(
"G_BUILD_VECTOR source operand types are not homogeneous",
MI);
1555 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1558 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1559 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1561 report(
"G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1564 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1565 report(
"G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1568 report(
"G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1573 case TargetOpcode::G_CONCAT_VECTORS: {
1576 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1577 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1579 report(
"G_CONCAT_VECTOR requires vector source and destination operands",
1582 if (
MI->getNumOperands() < 3)
1583 report(
"G_CONCAT_VECTOR requires at least 2 source operands",
MI);
1586 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1587 report(
"G_CONCAT_VECTOR source operand types are not homogeneous",
MI);
1590 report(
"G_CONCAT_VECTOR num dest and source elements should match",
MI);
1593 case TargetOpcode::G_ICMP:
1594 case TargetOpcode::G_FCMP: {
1595 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1596 LLT SrcTy =
MRI->getType(
MI->getOperand(2).getReg());
1601 report(
"Generic vector icmp/fcmp must preserve number of lanes",
MI);
1605 case TargetOpcode::G_SCMP:
1606 case TargetOpcode::G_UCMP: {
1607 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1608 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1611 report(
"Generic scmp/ucmp does not support pointers as operands",
MI);
1616 report(
"Generic scmp/ucmp does not support pointers as a result",
MI);
1621 report(
"Result type must be at least 2 bits wide",
MI);
1628 report(
"Generic vector scmp/ucmp must preserve number of lanes",
MI);
1634 case TargetOpcode::G_EXTRACT: {
1636 if (!
SrcOp.isReg()) {
1637 report(
"extract source must be a register",
MI);
1642 if (!OffsetOp.
isImm()) {
1643 report(
"extract offset must be a constant",
MI);
1647 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1649 if (SrcSize == DstSize)
1650 report(
"extract source must be larger than result",
MI);
1652 if (DstSize + OffsetOp.
getImm() > SrcSize)
1653 report(
"extract reads past end of register",
MI);
1656 case TargetOpcode::G_INSERT: {
1658 if (!
SrcOp.isReg()) {
1659 report(
"insert source must be a register",
MI);
1664 if (!OffsetOp.
isImm()) {
1665 report(
"insert offset must be a constant",
MI);
1669 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1672 if (DstSize <= SrcSize)
1673 report(
"inserted size must be smaller than total register",
MI);
1675 if (SrcSize + OffsetOp.
getImm() > DstSize)
1676 report(
"insert writes past end of register",
MI);
1680 case TargetOpcode::G_JUMP_TABLE: {
1681 if (!
MI->getOperand(1).isJTI())
1682 report(
"G_JUMP_TABLE source operand must be a jump table index",
MI);
1683 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1685 report(
"G_JUMP_TABLE dest operand must have a pointer type",
MI);
1688 case TargetOpcode::G_BRJT: {
1689 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
1690 report(
"G_BRJT src operand 0 must be a pointer type",
MI);
1692 if (!
MI->getOperand(1).isJTI())
1693 report(
"G_BRJT src operand 1 must be a jump table index",
MI);
1695 const auto &IdxOp =
MI->getOperand(2);
1696 if (!IdxOp.isReg() ||
MRI->getType(IdxOp.getReg()).isPointer())
1697 report(
"G_BRJT src operand 2 must be a scalar reg type",
MI);
1700 case TargetOpcode::G_INTRINSIC:
1701 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
1702 case TargetOpcode::G_INTRINSIC_CONVERGENT:
1703 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: {
1708 report(
"G_INTRINSIC first src operand must be an intrinsic ID",
MI);
1712 if (!verifyGIntrinsicSideEffects(
MI))
1714 if (!verifyGIntrinsicConvergence(
MI))
1719 case TargetOpcode::G_SEXT_INREG: {
1720 if (!
MI->getOperand(2).isImm()) {
1721 report(
"G_SEXT_INREG expects an immediate operand #2",
MI);
1725 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1726 int64_t
Imm =
MI->getOperand(2).getImm();
1728 report(
"G_SEXT_INREG size must be >= 1",
MI);
1730 report(
"G_SEXT_INREG size must be less than source bit width",
MI);
1733 case TargetOpcode::G_BSWAP: {
1734 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1736 report(
"G_BSWAP size must be a multiple of 16 bits",
MI);
1739 case TargetOpcode::G_VSCALE: {
1740 if (!
MI->getOperand(1).isCImm()) {
1741 report(
"G_VSCALE operand must be cimm",
MI);
1744 if (
MI->getOperand(1).getCImm()->isZero()) {
1745 report(
"G_VSCALE immediate cannot be zero",
MI);
1750 case TargetOpcode::G_STEP_VECTOR: {
1751 if (!
MI->getOperand(1).isCImm()) {
1752 report(
"operand must be cimm",
MI);
1756 if (!
MI->getOperand(1).getCImm()->getValue().isStrictlyPositive()) {
1757 report(
"step must be > 0",
MI);
1761 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1763 report(
"Destination type must be a scalable vector",
MI);
1769 report(
"Destination element type must be scalar",
MI);
1773 if (
MI->getOperand(1).getCImm()->getBitWidth() !=
1775 report(
"step bitwidth differs from result type element bitwidth",
MI);
1780 case TargetOpcode::G_INSERT_SUBVECTOR: {
1782 if (!Src0Op.
isReg()) {
1783 report(
"G_INSERT_SUBVECTOR first source must be a register",
MI);
1788 if (!Src1Op.
isReg()) {
1789 report(
"G_INSERT_SUBVECTOR second source must be a register",
MI);
1794 if (!IndexOp.
isImm()) {
1795 report(
"G_INSERT_SUBVECTOR index must be an immediate",
MI);
1799 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1803 report(
"Destination type must be a vector",
MI);
1808 report(
"Second source must be a vector",
MI);
1813 report(
"Element type of vectors must be the same",
MI);
1818 report(
"Vector types must both be fixed or both be scalable",
MI);
1824 report(
"Second source must be smaller than destination vector",
MI);
1830 if (IndexOp.
getImm() % Src1MinLen != 0) {
1831 report(
"Index must be a multiple of the second source vector's "
1832 "minimum vector length",
1838 if (
Idx >= DstMinLen ||
Idx + Src1MinLen > DstMinLen) {
1839 report(
"Subvector type and index must not cause insert to overrun the "
1840 "vector being inserted into",
1847 case TargetOpcode::G_EXTRACT_SUBVECTOR: {
1849 if (!
SrcOp.isReg()) {
1850 report(
"G_EXTRACT_SUBVECTOR first source must be a register",
MI);
1855 if (!IndexOp.
isImm()) {
1856 report(
"G_EXTRACT_SUBVECTOR index must be an immediate",
MI);
1860 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1864 report(
"Destination type must be a vector",
MI);
1869 report(
"Source must be a vector",
MI);
1874 report(
"Element type of vectors must be the same",
MI);
1879 report(
"Vector types must both be fixed or both be scalable",
MI);
1885 report(
"Destination vector must be smaller than source vector",
MI);
1891 if (
Idx % DstMinLen != 0) {
1892 report(
"Index must be a multiple of the destination vector's minimum "
1899 if (
Idx >= SrcMinLen ||
Idx + DstMinLen > SrcMinLen) {
1900 report(
"Destination type and index must not cause extract to overrun the "
1908 case TargetOpcode::G_SHUFFLE_VECTOR: {
1911 report(
"Incorrect mask operand type for G_SHUFFLE_VECTOR",
MI);
1915 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1916 LLT Src0Ty =
MRI->getType(
MI->getOperand(1).getReg());
1917 LLT Src1Ty =
MRI->getType(
MI->getOperand(2).getReg());
1919 if (Src0Ty != Src1Ty)
1920 report(
"Source operands must be the same type",
MI);
1923 report(
"G_SHUFFLE_VECTOR cannot change element type",
MI);
1932 if (
static_cast<int>(MaskIdxes.
size()) != DstNumElts)
1933 report(
"Wrong result type for shufflemask",
MI);
1935 for (
int Idx : MaskIdxes) {
1939 if (
Idx >= 2 * SrcNumElts)
1940 report(
"Out of bounds shuffle index",
MI);
1946 case TargetOpcode::G_SPLAT_VECTOR: {
1947 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1948 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1951 report(
"Destination type must be a scalable vector",
MI);
1956 report(
"Source type must be a scalar or pointer",
MI);
1962 report(
"Element type of the destination must be the same size or smaller "
1963 "than the source type",
1970 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1971 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1972 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1973 LLT IdxTy =
MRI->getType(
MI->getOperand(2).getReg());
1976 report(
"Destination type must be a scalar or pointer",
MI);
1981 report(
"First source must be a vector",
MI);
1985 auto TLI = MF->getSubtarget().getTargetLowering();
1987 TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) {
1988 report(
"Index type must match VectorIdxTy",
MI);
1994 case TargetOpcode::G_INSERT_VECTOR_ELT: {
1995 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1996 LLT VecTy =
MRI->getType(
MI->getOperand(1).getReg());
1997 LLT ScaTy =
MRI->getType(
MI->getOperand(2).getReg());
1998 LLT IdxTy =
MRI->getType(
MI->getOperand(3).getReg());
2001 report(
"Destination type must be a vector",
MI);
2005 if (VecTy != DstTy) {
2006 report(
"Destination type and vector type must match",
MI);
2011 report(
"Inserted element must be a scalar or pointer",
MI);
2015 auto TLI = MF->getSubtarget().getTargetLowering();
2017 TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) {
2018 report(
"Index type must match VectorIdxTy",
MI);
2024 case TargetOpcode::G_DYN_STACKALLOC: {
2030 report(
"dst operand 0 must be a pointer type",
MI);
2034 if (!AllocOp.
isReg() || !
MRI->getType(AllocOp.
getReg()).isScalar()) {
2035 report(
"src operand 1 must be a scalar reg type",
MI);
2039 if (!AlignOp.
isImm()) {
2040 report(
"src operand 2 must be an immediate type",
MI);
2045 case TargetOpcode::G_MEMCPY_INLINE:
2046 case TargetOpcode::G_MEMCPY:
2047 case TargetOpcode::G_MEMMOVE: {
2049 if (MMOs.
size() != 2) {
2050 report(
"memcpy/memmove must have 2 memory operands",
MI);
2056 report(
"wrong memory operand types",
MI);
2061 report(
"inconsistent memory operand sizes",
MI);
2063 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
2064 LLT SrcPtrTy =
MRI->getType(
MI->getOperand(1).getReg());
2067 report(
"memory instruction operand must be a pointer",
MI);
2072 report(
"inconsistent store address space",
MI);
2074 report(
"inconsistent load address space",
MI);
2076 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
2077 if (!
MI->getOperand(3).isImm() || (
MI->getOperand(3).getImm() & ~1LL))
2078 report(
"'tail' flag (operand 3) must be an immediate 0 or 1",
MI);
2082 case TargetOpcode::G_BZERO:
2083 case TargetOpcode::G_MEMSET: {
2085 std::string
Name = Opc == TargetOpcode::G_MEMSET ?
"memset" :
"bzero";
2086 if (MMOs.
size() != 1) {
2087 report(
Twine(
Name,
" must have 1 memory operand"),
MI);
2092 report(
Twine(
Name,
" memory operand must be a store"),
MI);
2096 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
2098 report(
Twine(
Name,
" operand must be a pointer"),
MI);
2103 report(
"inconsistent " +
Twine(
Name,
" address space"),
MI);
2105 if (!
MI->getOperand(
MI->getNumOperands() - 1).isImm() ||
2106 (
MI->getOperand(
MI->getNumOperands() - 1).getImm() & ~1LL))
2107 report(
"'tail' flag (last operand) must be an immediate 0 or 1",
MI);
2111 case TargetOpcode::G_UBSANTRAP: {
2113 if (!
MI->getOperand(0).isImm()) {
2114 report(
"Crash kind must be an immediate", &KindOp, 0);
2117 int64_t
Kind =
MI->getOperand(0).getImm();
2118 if (!isInt<8>(Kind))
2119 report(
"Crash kind must be 8 bit wide", &KindOp, 0);
2122 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
2123 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
2124 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
2125 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
2126 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
2128 report(
"Vector reduction requires a scalar destination type",
MI);
2130 report(
"Sequential FADD/FMUL vector reduction requires a scalar 1st operand",
MI);
2132 report(
"Sequential FADD/FMUL vector reduction must have a vector 2nd operand",
MI);
2135 case TargetOpcode::G_VECREDUCE_FADD:
2136 case TargetOpcode::G_VECREDUCE_FMUL:
2137 case TargetOpcode::G_VECREDUCE_FMAX:
2138 case TargetOpcode::G_VECREDUCE_FMIN:
2139 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
2140 case TargetOpcode::G_VECREDUCE_FMINIMUM:
2141 case TargetOpcode::G_VECREDUCE_ADD:
2142 case TargetOpcode::G_VECREDUCE_MUL:
2143 case TargetOpcode::G_VECREDUCE_AND:
2144 case TargetOpcode::G_VECREDUCE_OR:
2145 case TargetOpcode::G_VECREDUCE_XOR:
2146 case TargetOpcode::G_VECREDUCE_SMAX:
2147 case TargetOpcode::G_VECREDUCE_SMIN:
2148 case TargetOpcode::G_VECREDUCE_UMAX:
2149 case TargetOpcode::G_VECREDUCE_UMIN: {
2150 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
2152 report(
"Vector reduction requires a scalar destination type",
MI);
2156 case TargetOpcode::G_SBFX:
2157 case TargetOpcode::G_UBFX: {
2158 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
2160 report(
"Bitfield extraction is not supported on vectors",
MI);
2165 case TargetOpcode::G_SHL:
2166 case TargetOpcode::G_LSHR:
2167 case TargetOpcode::G_ASHR:
2168 case TargetOpcode::G_ROTR:
2169 case TargetOpcode::G_ROTL: {
2170 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
2171 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
2173 report(
"Shifts and rotates require operands to be either all scalars or "
2180 case TargetOpcode::G_LLROUND:
2181 case TargetOpcode::G_LROUND: {
2182 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
2183 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
2188 report(
Twine(
Op,
" operand must not be a pointer type"),
MI);
2190 verifyAllRegOpsScalar(*
MI, *
MRI);
2193 verifyVectorElementMatch(SrcTy, DstTy,
MI);
2198 case TargetOpcode::G_IS_FPCLASS: {
2199 LLT DestTy =
MRI->getType(
MI->getOperand(0).getReg());
2202 report(
"Destination must be a scalar or vector of scalars",
MI);
2205 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
2208 report(
"Source must be a scalar or vector of scalars",
MI);
2211 if (!verifyVectorElementMatch(DestTy, SrcTy,
MI))
2214 if (!TestMO.
isImm()) {
2215 report(
"floating-point class set (operand 2) must be an immediate",
MI);
2220 report(
"Incorrect floating-point class set (operand 2)",
MI);
2225 case TargetOpcode::G_PREFETCH: {
2227 if (!AddrOp.
isReg() || !
MRI->getType(AddrOp.
getReg()).isPointer()) {
2228 report(
"addr operand must be a pointer", &AddrOp, 0);
2233 report(
"rw operand must be an immediate 0-1", &RWOp, 1);
2238 report(
"locality operand must be an immediate 0-3", &LocalityOp, 2);
2243 report(
"cache type operand must be an immediate 0-1", &CacheTypeOp, 3);
2248 case TargetOpcode::G_ASSERT_ALIGN: {
2249 if (
MI->getOperand(2).getImm() < 1)
2250 report(
"alignment immediate must be >= 1",
MI);
2253 case TargetOpcode::G_CONSTANT_POOL: {
2254 if (!
MI->getOperand(1).isCPI())
2255 report(
"Src operand 1 must be a constant pool index",
MI);
2256 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
2257 report(
"Dst operand 0 must be a pointer",
MI);
2260 case TargetOpcode::G_PTRAUTH_GLOBAL_VALUE: {
2262 if (!AddrOp.
isReg() || !
MRI->getType(AddrOp.
getReg()).isPointer())
2263 report(
"addr operand must be a pointer", &AddrOp, 1);
2271void MachineVerifier::visitMachineInstrBefore(
const MachineInstr *
MI) {
2274 report(
"Too few operands",
MI);
2276 <<
MI->getNumOperands() <<
" given.\n";
2280 report(
"NoConvergent flag expected only on convergent instructions.",
MI);
2283 if (MF->getProperties().hasProperty(
2285 report(
"Found PHI instruction with NoPHIs property set",
MI);
2288 report(
"Found PHI instruction after non-PHI",
MI);
2289 }
else if (FirstNonPHI ==
nullptr)
2293 if (
MI->isInlineAsm())
2294 verifyInlineAsm(
MI);
2297 if (
TII->isUnspillableTerminator(
MI)) {
2298 if (!
MI->getOperand(0).isReg() || !
MI->getOperand(0).isDef())
2299 report(
"Unspillable Terminator does not define a reg",
MI);
2301 if (
Def.isVirtual() &&
2302 !MF->getProperties().hasProperty(
2304 std::distance(
MRI->use_nodbg_begin(Def),
MRI->use_nodbg_end()) > 1)
2305 report(
"Unspillable Terminator expected to have at most one use!",
MI);
2311 if (
MI->isDebugValue() &&
MI->getNumOperands() == 4)
2312 if (!
MI->getDebugLoc())
2313 report(
"Missing DebugLoc for debug instruction",
MI);
2317 if (
MI->isMetaInstruction() &&
MI->peekDebugInstrNum())
2318 report(
"Metadata instruction should not have a value tracking number",
MI);
2322 if (
Op->isLoad() && !
MI->mayLoad())
2323 report(
"Missing mayLoad flag",
MI);
2324 if (
Op->isStore() && !
MI->mayStore())
2325 report(
"Missing mayStore flag",
MI);
2331 bool mapped = !LiveInts->isNotInMIMap(*
MI);
2332 if (
MI->isDebugOrPseudoInstr()) {
2334 report(
"Debug instruction has a slot index",
MI);
2335 }
else if (
MI->isInsideBundle()) {
2337 report(
"Instruction inside bundle has a slot index",
MI);
2340 report(
"Missing slot index",
MI);
2346 verifyPreISelGenericInstruction(
MI);
2355 switch (
MI->getOpcode()) {
2356 case TargetOpcode::COPY: {
2362 LLT DstTy =
MRI->getType(DstReg);
2363 LLT SrcTy =
MRI->getType(SrcReg);
2366 if (SrcTy != DstTy) {
2367 report(
"Copy Instruction is illegal with mismatching types",
MI);
2368 OS <<
"Def = " << DstTy <<
", Src = " << SrcTy <<
'\n';
2383 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
2385 SrcSize =
TRI->getRegSizeInBits(*SrcRC);
2390 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
2392 DstSize =
TRI->getRegSizeInBits(*DstRC);
2410 if (!
DstOp.getSubReg() && !
SrcOp.getSubReg()) {
2411 report(
"Copy Instruction is illegal with mismatching sizes",
MI);
2412 OS <<
"Def Size = " << DstSize <<
", Src Size = " << SrcSize <<
'\n';
2417 case TargetOpcode::STATEPOINT: {
2419 if (!
MI->getOperand(SO.getIDPos()).isImm() ||
2420 !
MI->getOperand(SO.getNBytesPos()).isImm() ||
2421 !
MI->getOperand(SO.getNCallArgsPos()).isImm()) {
2422 report(
"meta operands to STATEPOINT not constant!",
MI);
2426 auto VerifyStackMapConstant = [&](
unsigned Offset) {
2427 if (
Offset >=
MI->getNumOperands()) {
2428 report(
"stack map constant to STATEPOINT is out of range!",
MI);
2431 if (!
MI->getOperand(
Offset - 1).isImm() ||
2432 MI->getOperand(
Offset - 1).getImm() != StackMaps::ConstantOp ||
2434 report(
"stack map constant to STATEPOINT not well formed!",
MI);
2436 VerifyStackMapConstant(SO.getCCIdx());
2437 VerifyStackMapConstant(SO.getFlagsIdx());
2438 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
2439 VerifyStackMapConstant(SO.getNumGCPtrIdx());
2440 VerifyStackMapConstant(SO.getNumAllocaIdx());
2441 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
2445 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
2446 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
2447 for (
unsigned Idx = 0;
Idx <
MI->getNumDefs();
Idx++) {
2449 if (!
MI->isRegTiedToUseOperand(
Idx, &UseOpIdx)) {
2450 report(
"STATEPOINT defs expected to be tied",
MI);
2453 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
2454 report(
"STATEPOINT def tied to non-gc operand",
MI);
2461 case TargetOpcode::INSERT_SUBREG: {
2462 unsigned InsertedSize;
2463 if (
unsigned SubIdx =
MI->getOperand(2).getSubReg())
2464 InsertedSize =
TRI->getSubRegIdxSize(SubIdx);
2466 InsertedSize =
TRI->getRegSizeInBits(
MI->getOperand(2).getReg(), *
MRI);
2467 unsigned SubRegSize =
TRI->getSubRegIdxSize(
MI->getOperand(3).getImm());
2468 if (SubRegSize < InsertedSize) {
2469 report(
"INSERT_SUBREG expected inserted value to have equal or lesser "
2470 "size than the subreg it was inserted into",
MI);
2474 case TargetOpcode::REG_SEQUENCE: {
2475 unsigned NumOps =
MI->getNumOperands();
2476 if (!(NumOps & 1)) {
2477 report(
"Invalid number of operands for REG_SEQUENCE",
MI);
2481 for (
unsigned I = 1;
I != NumOps;
I += 2) {
2486 report(
"Invalid register operand for REG_SEQUENCE", &RegOp,
I);
2488 if (!SubRegOp.
isImm() || SubRegOp.
getImm() == 0 ||
2489 SubRegOp.
getImm() >=
TRI->getNumSubRegIndices()) {
2490 report(
"Invalid subregister index operand for REG_SEQUENCE",
2495 Register DstReg =
MI->getOperand(0).getReg();
2497 report(
"REG_SEQUENCE does not support physical register results",
MI);
2499 if (
MI->getOperand(0).getSubReg())
2500 report(
"Invalid subreg result for REG_SEQUENCE",
MI);
2508MachineVerifier::visitMachineOperand(
const MachineOperand *MO,
unsigned MONum) {
2512 if (MCID.
getOpcode() == TargetOpcode::PATCHPOINT)
2513 NumDefs = (MONum == 0 && MO->
isReg()) ? NumDefs : 0;
2516 if (MONum < NumDefs) {
2519 report(
"Explicit definition must be a register", MO, MONum);
2521 report(
"Explicit definition marked as use", MO, MONum);
2523 report(
"Explicit definition marked as implicit", MO, MONum);
2532 report(
"Explicit operand marked as def", MO, MONum);
2534 report(
"Explicit operand marked as implicit", MO, MONum);
2540 report(
"Expected a register operand.", MO, MONum);
2544 !
TII->isPCRelRegisterOperandLegal(*MO)))
2545 report(
"Expected a non-register operand.", MO, MONum);
2552 report(
"Tied use must be a register", MO, MONum);
2554 report(
"Operand should be tied", MO, MONum);
2555 else if (
unsigned(TiedTo) !=
MI->findTiedOperandIdx(MONum))
2556 report(
"Tied def doesn't match MCInstrDesc", MO, MONum);
2559 if (!MOTied.
isReg())
2560 report(
"Tied counterpart must be a register", &MOTied, TiedTo);
2563 report(
"Tied physical registers must match.", &MOTied, TiedTo);
2566 report(
"Explicit operand should not be tied", MO, MONum);
2567 }
else if (!
MI->isVariadic()) {
2570 report(
"Extra explicit operand on non-variadic instruction", MO, MONum);
2577 if (
MI->isDebugInstr() && MO->
isUse()) {
2579 report(
"Register operand must be marked debug", MO, MONum);
2581 report(
"Register operand must not be marked debug", MO, MONum);
2587 if (
MRI->tracksLiveness() && !
MI->isDebugInstr())
2588 checkLiveness(MO, MONum);
2592 report(
"Undef virtual register def operands require a subregister", MO, MONum);
2596 unsigned OtherIdx =
MI->findTiedOperandIdx(MONum);
2598 if (!OtherMO.
isReg())
2599 report(
"Must be tied to a register", MO, MONum);
2601 report(
"Missing tie flags on tied operand", MO, MONum);
2602 if (
MI->findTiedOperandIdx(OtherIdx) != MONum)
2603 report(
"Inconsistent tie links", MO, MONum);
2607 report(
"Explicit def tied to explicit use without tie constraint",
2611 report(
"Explicit def should be tied to implicit use", MO, MONum);
2624 if (MF->getProperties().hasProperty(
2626 MO->
isUse() &&
MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2627 Reg !=
MI->getOperand(DefIdx).getReg())
2628 report(
"Two-address instruction operands must be identical", MO, MONum);
2633 if (
Reg.isPhysical()) {
2635 report(
"Illegal subregister index for physical register", MO, MONum);
2640 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2641 if (!DRC->contains(Reg)) {
2642 report(
"Illegal physical register for instruction", MO, MONum);
2644 <<
TRI->getRegClassName(DRC) <<
" register.\n";
2649 if (
MRI->isReserved(Reg)) {
2650 report(
"isRenamable set on reserved register", MO, MONum);
2667 report(
"Generic virtual register use cannot be undef", MO, MONum);
2674 if (isFunctionTracksDebugUserValues || !MO->
isUse() ||
2675 !
MI->isDebugValue() || !
MRI->def_empty(Reg)) {
2677 if (isFunctionSelected) {
2678 report(
"Generic virtual register invalid in a Selected function",
2684 LLT Ty =
MRI->getType(Reg);
2686 report(
"Generic virtual register must have a valid type", MO,
2695 if (!RegBank && isFunctionRegBankSelected) {
2696 report(
"Generic virtual register must have a bank in a "
2697 "RegBankSelected function",
2705 report(
"Register bank is too small for virtual register", MO,
2707 OS <<
"Register bank " << RegBank->
getName() <<
" too small("
2715 report(
"Generic virtual register does not allow subregister index", MO,
2725 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2726 report(
"Virtual register does not match instruction constraint", MO,
2728 OS <<
"Expect register class "
2729 <<
TRI->getRegClassName(
TII->getRegClass(MCID, MONum,
TRI, *MF))
2730 <<
" but got nothing\n";
2738 TRI->getSubClassWithSubReg(RC, SubIdx);
2740 report(
"Invalid subregister index for virtual register", MO, MONum);
2741 OS <<
"Register class " <<
TRI->getRegClassName(RC)
2742 <<
" does not support subreg index " << SubIdx <<
'\n';
2746 report(
"Invalid register class for subregister index", MO, MONum);
2747 OS <<
"Register class " <<
TRI->getRegClassName(RC)
2748 <<
" does not fully support subreg index " << SubIdx <<
'\n';
2754 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2757 TRI->getLargestLegalSuperClass(RC, *MF);
2759 report(
"No largest legal super class exists.", MO, MONum);
2762 DRC =
TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2764 report(
"No matching super-reg register class.", MO, MONum);
2769 report(
"Illegal virtual register for instruction", MO, MONum);
2770 OS <<
"Expected a " <<
TRI->getRegClassName(DRC)
2771 <<
" register, but got a " <<
TRI->getRegClassName(RC)
2786 report(
"PHI operand is not in the CFG", MO, MONum);
2790 if (LiveStks && LiveStks->hasInterval(MO->
getIndex()) &&
2791 LiveInts && !LiveInts->isNotInMIMap(*
MI)) {
2802 for (
auto *MMO :
MI->memoperands()) {
2804 if (PSV ==
nullptr)
continue;
2806 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2807 if (
Value ==
nullptr)
continue;
2808 if (
Value->getFrameIndex() != FI)
continue;
2817 report(
"Missing fixed stack memoperand.",
MI);
2820 report(
"Instruction loads from dead spill slot", MO, MONum);
2821 OS <<
"Live stack: " << LI <<
'\n';
2824 report(
"Instruction stores to dead spill slot", MO, MONum);
2825 OS <<
"Live stack: " << LI <<
'\n';
2831 if (MO->
getCFIIndex() >= MF->getFrameInstructions().size())
2832 report(
"CFI instruction has invalid index", MO, MONum);
2840void MachineVerifier::checkLivenessAtUse(
const MachineOperand *MO,
2848 report(
"invalid live range", MO, MONum);
2849 report_context_liverange(LR);
2850 report_context_vreg_regunit(VRegOrUnit);
2851 report_context(UseIdx);
2860 report(
"No live segment at use", MO, MONum);
2861 report_context_liverange(LR);
2862 report_context_vreg_regunit(VRegOrUnit);
2863 report_context(UseIdx);
2866 report(
"Live range continues after kill flag", MO, MONum);
2867 report_context_liverange(LR);
2868 report_context_vreg_regunit(VRegOrUnit);
2870 report_context_lanemask(LaneMask);
2871 report_context(UseIdx);
2875void MachineVerifier::checkLivenessAtDef(
const MachineOperand *MO,
2882 report(
"invalid live range", MO, MONum);
2883 report_context_liverange(LR);
2884 report_context_vreg_regunit(VRegOrUnit);
2886 report_context_lanemask(LaneMask);
2887 report_context(DefIdx);
2899 if (((SubRangeCheck || MO->
getSubReg() == 0) && VNI->def != DefIdx) ||
2901 (VNI->def != DefIdx &&
2902 (!VNI->def.isEarlyClobber() || !DefIdx.
isRegister()))) {
2903 report(
"Inconsistent valno->def", MO, MONum);
2904 report_context_liverange(LR);
2905 report_context_vreg_regunit(VRegOrUnit);
2907 report_context_lanemask(LaneMask);
2908 report_context(*VNI);
2909 report_context(DefIdx);
2912 report(
"No live segment at def", MO, MONum);
2913 report_context_liverange(LR);
2914 report_context_vreg_regunit(VRegOrUnit);
2916 report_context_lanemask(LaneMask);
2917 report_context(DefIdx);
2929 if (SubRangeCheck || MO->
getSubReg() == 0) {
2930 report(
"Live range continues after dead def flag", MO, MONum);
2931 report_context_liverange(LR);
2932 report_context_vreg_regunit(VRegOrUnit);
2934 report_context_lanemask(LaneMask);
2940void MachineVerifier::checkLiveness(
const MachineOperand *MO,
unsigned MONum) {
2943 const unsigned SubRegIdx = MO->
getSubReg();
2946 if (LiveInts &&
Reg.isVirtual()) {
2947 if (LiveInts->hasInterval(Reg)) {
2948 LI = &LiveInts->getInterval(Reg);
2951 report(
"Live interval for subreg operand has no subranges", MO, MONum);
2953 report(
"Virtual register has no live interval", MO, MONum);
2960 addRegWithSubRegs(regsKilled, Reg);
2965 if (LiveVars &&
Reg.isVirtual() && MO->
isKill() &&
2966 !
MI->isBundledWithPred()) {
2969 report(
"Kill missing from LiveVariables", MO, MONum);
2973 if (LiveInts && !LiveInts->isNotInMIMap(*
MI)) {
2977 UseIdx = LiveInts->getMBBEndIdx(
2978 MI->getOperand(MONum + 1).getMBB()).getPrevSlot();
2980 UseIdx = LiveInts->getInstructionIndex(*
MI);
2983 if (
Reg.isPhysical() && !isReserved(Reg)) {
2985 if (
MRI->isReservedRegUnit(Unit))
2987 if (
const LiveRange *LR = LiveInts->getCachedRegUnit(Unit))
2988 checkLivenessAtUse(MO, MONum, UseIdx, *LR,
VirtRegOrUnit(Unit));
2992 if (
Reg.isVirtual()) {
2994 checkLivenessAtUse(MO, MONum, UseIdx, *LI,
VirtRegOrUnit(Reg));
2998 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2999 :
MRI->getMaxLaneMaskForVReg(Reg);
3002 if ((MOMask & SR.LaneMask).none())
3004 checkLivenessAtUse(MO, MONum, UseIdx, SR,
VirtRegOrUnit(Reg),
3008 LiveInMask |= SR.LaneMask;
3011 if ((LiveInMask & MOMask).
none()) {
3012 report(
"No live subrange at use", MO, MONum);
3013 report_context(*LI);
3014 report_context(UseIdx);
3017 if (
MI->isPHI() && LiveInMask != MOMask) {
3018 report(
"Not all lanes of PHI source live at use", MO, MONum);
3019 report_context(*LI);
3020 report_context(UseIdx);
3027 if (!regsLive.count(Reg)) {
3028 if (
Reg.isPhysical()) {
3030 bool Bad = !isReserved(Reg);
3035 if (regsLive.count(
SubReg)) {
3047 if (!MOP.isReg() || !MOP.isImplicit())
3050 if (!MOP.getReg().isPhysical())
3053 if (MOP.getReg() != Reg &&
3055 return llvm::is_contained(TRI->regunits(MOP.getReg()),
3062 report(
"Using an undefined physical register", MO, MONum);
3063 }
else if (
MRI->def_empty(Reg)) {
3064 report(
"Reading virtual register without a def", MO, MONum);
3066 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
3070 if (MInfo.regsKilled.count(Reg))
3071 report(
"Using a killed virtual register", MO, MONum);
3072 else if (!
MI->isPHI())
3073 MInfo.vregsLiveIn.insert(std::make_pair(Reg,
MI));
3082 addRegWithSubRegs(regsDead, Reg);
3084 addRegWithSubRegs(regsDefined, Reg);
3087 if (
MRI->isSSA() &&
Reg.isVirtual() &&
3088 std::next(
MRI->def_begin(Reg)) !=
MRI->def_end())
3089 report(
"Multiple virtual register defs in SSA form", MO, MONum);
3092 if (LiveInts && !LiveInts->isNotInMIMap(*
MI)) {
3093 SlotIndex DefIdx = LiveInts->getInstructionIndex(*
MI);
3096 if (
Reg.isVirtual()) {
3097 checkLivenessAtDef(MO, MONum, DefIdx, *LI,
VirtRegOrUnit(Reg));
3101 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
3102 :
MRI->getMaxLaneMaskForVReg(Reg);
3104 if ((SR.LaneMask & MOMask).none())
3106 checkLivenessAtDef(MO, MONum, DefIdx, SR,
VirtRegOrUnit(Reg),
true,
3119void MachineVerifier::visitMachineBundleAfter(
const MachineInstr *
MI) {
3120 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
3121 set_union(MInfo.regsKilled, regsKilled);
3122 set_subtract(regsLive, regsKilled); regsKilled.clear();
3124 while (!regMasks.empty()) {
3127 if (
Reg.isPhysical() &&
3129 regsDead.push_back(Reg);
3132 set_union(regsLive, regsDefined); regsDefined.clear();
3137 MBBInfoMap[
MBB].regsLiveOut = regsLive;
3142 if (!(stop > lastIndex)) {
3143 report(
"Block ends before last instruction index",
MBB);
3144 OS <<
"Block ends at " << stop <<
" last instruction was at " << lastIndex
3160 template <
typename RegSetT>
void add(
const RegSetT &FromRegSet) {
3162 filterAndAdd(FromRegSet, VRegsBuffer);
3167 template <
typename RegSetT>
3168 bool filterAndAdd(
const RegSetT &FromRegSet,
3170 unsigned SparseUniverse = Sparse.size();
3171 unsigned NewSparseUniverse = SparseUniverse;
3172 unsigned NewDenseSize =
Dense.size();
3173 size_t Begin = ToVRegs.
size();
3175 if (!
Reg.isVirtual())
3178 if (
Index < SparseUniverseMax) {
3179 if (
Index < SparseUniverse && Sparse.test(
Index))
3181 NewSparseUniverse = std::max(NewSparseUniverse,
Index + 1);
3196 Sparse.resize(NewSparseUniverse);
3197 Dense.reserve(NewDenseSize);
3198 for (
unsigned I = Begin;
I <
End; ++
I) {
3201 if (
Index < SparseUniverseMax)
3210 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
3230class FilteringVRegSet {
3237 template <
typename RegSetT>
void addToFilter(
const RegSetT &RS) {
3242 template <
typename RegSetT>
bool add(
const RegSetT &RS) {
3245 return Filter.filterAndAdd(RS, VRegs);
3250 size_t size()
const {
return VRegs.
size(); }
3257void MachineVerifier::calcRegsPassed() {
3264 FilteringVRegSet VRegs;
3265 BBInfo &
Info = MBBInfoMap[MB];
3268 VRegs.addToFilter(
Info.regsKilled);
3269 VRegs.addToFilter(
Info.regsLiveOut);
3271 const BBInfo &PredInfo = MBBInfoMap[Pred];
3272 if (!PredInfo.reachable)
3275 VRegs.add(PredInfo.regsLiveOut);
3276 VRegs.add(PredInfo.vregsPassed);
3278 Info.vregsPassed.reserve(VRegs.size());
3279 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
3286void MachineVerifier::calcRegsRequired() {
3289 for (
const auto &
MBB : *MF) {
3290 BBInfo &MInfo = MBBInfoMap[&
MBB];
3292 BBInfo &PInfo = MBBInfoMap[Pred];
3293 if (PInfo.addRequired(MInfo.vregsLiveIn))
3299 for (
unsigned i = 1, e =
MI.getNumOperands(); i != e; i += 2) {
3301 if (!
MI.getOperand(i).isReg() || !
MI.getOperand(i).readsReg())
3308 BBInfo &PInfo = MBBInfoMap[Pred];
3309 if (PInfo.addRequired(Reg))
3317 while (!todo.
empty()) {
3320 BBInfo &MInfo = MBBInfoMap[
MBB];
3324 BBInfo &SInfo = MBBInfoMap[Pred];
3325 if (SInfo.addRequired(MInfo.vregsRequired))
3334 BBInfo &MInfo = MBBInfoMap[&
MBB];
3344 report(
"Expected first PHI operand to be a register def", &MODef, 0);
3349 report(
"Unexpected flag on PHI operand", &MODef, 0);
3352 report(
"Expected first PHI operand to be a virtual register", &MODef, 0);
3354 for (
unsigned I = 1, E =
Phi.getNumOperands();
I != E;
I += 2) {
3357 report(
"Expected PHI operand to be a register", &MO0,
I);
3362 report(
"Unexpected flag on PHI operand", &MO0,
I);
3366 report(
"Expected PHI operand to be a basic block", &MO1,
I + 1);
3372 report(
"PHI input is not a predecessor block", &MO1,
I + 1);
3376 if (MInfo.reachable) {
3378 BBInfo &PrInfo = MBBInfoMap[&Pre];
3379 if (!MO0.
isUndef() && PrInfo.reachable &&
3380 !PrInfo.isLiveOut(MO0.
getReg()))
3381 report(
"PHI operand is not live-out from predecessor", &MO0,
I);
3386 if (MInfo.reachable) {
3388 if (!seen.
count(Pred)) {
3389 report(
"Missing PHI operand", &Phi);
3391 <<
" is a predecessor according to the CFG.\n";
3400 std::function<
void(
const Twine &Message)> FailureCB,
3405 for (
const auto &
MBB : MF) {
3417void MachineVerifier::visitMachineFunctionAfter() {
3418 auto FailureCB = [
this](
const Twine &Message) {
3419 report(Message.str().c_str(), MF);
3432 for (
const auto &
MBB : *MF) {
3433 BBInfo &MInfo = MBBInfoMap[&
MBB];
3434 for (
Register VReg : MInfo.vregsRequired)
3435 if (MInfo.regsKilled.count(VReg)) {
3436 report(
"Virtual register killed in block, but needed live out.", &
MBB);
3438 <<
" is used after the block.\n";
3443 BBInfo &MInfo = MBBInfoMap[&MF->front()];
3444 for (
Register VReg : MInfo.vregsRequired) {
3445 report(
"Virtual register defs don't dominate all uses.", MF);
3446 report_context_vreg(VReg);
3451 verifyLiveVariables();
3453 verifyLiveIntervals();
3462 if (
MRI->tracksLiveness())
3463 for (
const auto &
MBB : *MF)
3467 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
3470 BBInfo &PInfo = MBBInfoMap[Pred];
3471 if (!PInfo.regsLiveOut.count(LiveInReg)) {
3472 report(
"Live in register not found to be live out from predecessor.",
3474 OS <<
TRI->getName(LiveInReg) <<
" not found to be live out from "
3480 for (
auto CSInfo : MF->getCallSitesInfo())
3481 if (!CSInfo.first->isCall())
3482 report(
"Call site info referencing instruction that is not call", MF);
3486 if (MF->getFunction().getSubprogram()) {
3488 for (
const auto &
MBB : *MF) {
3489 for (
const auto &
MI :
MBB) {
3490 if (
auto Num =
MI.peekDebugInstrNum()) {
3493 report(
"Instruction has a duplicated value tracking number", &
MI);
3500void MachineVerifier::verifyLiveVariables() {
3501 assert(LiveVars &&
"Don't call verifyLiveVariables without LiveVars");
3502 for (
unsigned I = 0, E =
MRI->getNumVirtRegs();
I != E; ++
I) {
3505 for (
const auto &
MBB : *MF) {
3506 BBInfo &MInfo = MBBInfoMap[&
MBB];
3509 if (MInfo.vregsRequired.count(Reg)) {
3511 report(
"LiveVariables: Block missing from AliveBlocks", &
MBB);
3513 <<
" must be live through the block.\n";
3517 report(
"LiveVariables: Block should not be in AliveBlocks", &
MBB);
3519 <<
" is not needed live through the block.\n";
3526void MachineVerifier::verifyLiveIntervals() {
3527 assert(LiveInts &&
"Don't call verifyLiveIntervals without LiveInts");
3528 for (
unsigned I = 0, E =
MRI->getNumVirtRegs();
I != E; ++
I) {
3532 if (
MRI->reg_nodbg_empty(Reg))
3535 if (!LiveInts->hasInterval(Reg)) {
3536 report(
"Missing live interval for virtual register", MF);
3542 assert(Reg == LI.
reg() &&
"Invalid reg to interval mapping");
3543 verifyLiveInterval(LI);
3547 for (
unsigned i = 0, e =
TRI->getNumRegUnits(); i != e; ++i)
3548 if (
const LiveRange *LR = LiveInts->getCachedRegUnit(i))
3552void MachineVerifier::verifyLiveRangeValue(
const LiveRange &LR,
3562 report(
"Value not live at VNInfo def and not marked unused", MF);
3563 report_context(LR, VRegOrUnit, LaneMask);
3564 report_context(*VNI);
3568 if (DefVNI != VNI) {
3569 report(
"Live segment at def has different VNInfo", MF);
3570 report_context(LR, VRegOrUnit, LaneMask);
3571 report_context(*VNI);
3577 report(
"Invalid VNInfo definition index", MF);
3578 report_context(LR, VRegOrUnit, LaneMask);
3579 report_context(*VNI);
3584 if (VNI->
def != LiveInts->getMBBStartIdx(
MBB)) {
3585 report(
"PHIDef VNInfo is not defined at MBB start",
MBB);
3586 report_context(LR, VRegOrUnit, LaneMask);
3587 report_context(*VNI);
3595 report(
"No instruction at VNInfo def index",
MBB);
3596 report_context(LR, VRegOrUnit, LaneMask);
3597 report_context(*VNI);
3601 bool hasDef =
false;
3602 bool isEarlyClobber =
false;
3604 if (!MOI->isReg() || !MOI->isDef())
3610 if (!MOI->getReg().isPhysical() ||
3614 if (LaneMask.
any() &&
3615 (
TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3618 if (MOI->isEarlyClobber())
3619 isEarlyClobber =
true;
3623 report(
"Defining instruction does not modify register",
MI);
3624 report_context(LR, VRegOrUnit, LaneMask);
3625 report_context(*VNI);
3630 if (isEarlyClobber) {
3632 report(
"Early clobber def must be at an early-clobber slot",
MBB);
3633 report_context(LR, VRegOrUnit, LaneMask);
3634 report_context(*VNI);
3637 report(
"Non-PHI, non-early clobber def must be at a register slot",
MBB);
3638 report_context(LR, VRegOrUnit, LaneMask);
3639 report_context(*VNI);
3643void MachineVerifier::verifyLiveRangeSegment(
const LiveRange &LR,
3649 assert(VNI &&
"Live segment has no valno");
3652 report(
"Foreign valno in live segment", MF);
3653 report_context(LR, VRegOrUnit, LaneMask);
3655 report_context(*VNI);
3659 report(
"Live segment valno is marked unused", MF);
3660 report_context(LR, VRegOrUnit, LaneMask);
3666 report(
"Bad start of live segment, no basic block", MF);
3667 report_context(LR, VRegOrUnit, LaneMask);
3673 report(
"Live segment must begin at MBB entry or valno def",
MBB);
3674 report_context(LR, VRegOrUnit, LaneMask);
3681 report(
"Bad end of live segment, no basic block", MF);
3682 report_context(LR, VRegOrUnit, LaneMask);
3688 if (S.
end != LiveInts->getMBBEndIdx(EndMBB)) {
3698 report(
"Live segment doesn't end at a valid instruction", EndMBB);
3699 report_context(LR, VRegOrUnit, LaneMask);
3706 report(
"Live segment ends at B slot of an instruction", EndMBB);
3707 report_context(LR, VRegOrUnit, LaneMask);
3715 report(
"Live segment ending at dead slot spans instructions", EndMBB);
3716 report_context(LR, VRegOrUnit, LaneMask);
3725 if (MF->getProperties().hasProperty(
3728 if (
I + 1 == LR.
end() || (
I + 1)->start != S.
end) {
3729 report(
"Live segment ending at early clobber slot must be "
3730 "redefined by an EC def in the same instruction",
3732 report_context(LR, VRegOrUnit, LaneMask);
3742 bool hasRead =
false;
3743 bool hasSubRegDef =
false;
3744 bool hasDeadDef =
false;
3746 if (!MOI->isReg() || MOI->getReg() != VRegOrUnit.
asVirtualReg())
3748 unsigned Sub = MOI->getSubReg();
3753 hasSubRegDef =
true;
3762 if (LaneMask.
any() && (LaneMask & SLM).none())
3764 if (MOI->readsReg())
3771 if (LaneMask.
none() && !hasDeadDef) {
3773 "Instruction ending live segment on dead slot has no dead flag",
3775 report_context(LR, VRegOrUnit, LaneMask);
3783 LaneMask.
any() || !hasSubRegDef) {
3784 report(
"Instruction ending live segment doesn't read the register",
3786 report_context(LR, VRegOrUnit, LaneMask);
3806 if (LaneMask.
any()) {
3812 assert(LiveInts->isLiveInToMBB(LR, &*MFI));
3815 if (&*MFI == EndMBB)
3823 VNI->
def == LiveInts->getMBBStartIdx(&*MFI);
3827 SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
3829 if (MFI->isEHPad()) {
3832 PEnd = Indexes->getInstructionIndex(
MI).getBoundaryIndex();
3843 if (!PVNI && (LaneMask.
none() || !IsPHI)) {
3846 report(
"Register not marked live out of predecessor", Pred);
3847 report_context(LR, VRegOrUnit, LaneMask);
3848 report_context(*VNI);
3850 << LiveInts->getMBBStartIdx(&*MFI) <<
", not live before " << PEnd
3856 if (!IsPHI && PVNI != VNI) {
3857 report(
"Different value live out of predecessor", Pred);
3858 report_context(LR, VRegOrUnit, LaneMask);
3859 OS <<
"Valno #" << PVNI->
id <<
" live out of "
3862 << LiveInts->getMBBStartIdx(&*MFI) <<
'\n';
3865 if (&*MFI == EndMBB)
3871void MachineVerifier::verifyLiveRange(
const LiveRange &LR,
3875 verifyLiveRangeValue(LR, VNI, VRegOrUnit, LaneMask);
3878 verifyLiveRangeSegment(LR,
I, VRegOrUnit, LaneMask);
3881void MachineVerifier::verifyLiveInterval(
const LiveInterval &LI) {
3890 if ((Mask & SR.LaneMask).any()) {
3891 report(
"Lane masks of sub ranges overlap in live interval", MF);
3894 if ((SR.LaneMask & ~MaxMask).any()) {
3895 report(
"Subrange lanemask is invalid", MF);
3899 report(
"Subrange must not be empty", MF);
3902 Mask |= SR.LaneMask;
3905 report(
"A Subrange is not covered by the main range", MF);
3913 unsigned NumComp = ConEQ.Classify(LI);
3915 report(
"Multiple connected components in live interval", MF);
3917 for (
unsigned comp = 0; comp != NumComp; ++comp) {
3918 OS << comp <<
": valnos";
3920 if (comp == ConEQ.getEqClass(
I))
3933struct StackStateOfBB {
3934 StackStateOfBB() =
default;
3935 StackStateOfBB(
int EntryVal,
int ExitVal,
bool EntrySetup,
bool ExitSetup)
3936 : EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3937 ExitIsSetup(ExitSetup) {}
3942 bool EntryIsSetup =
false;
3943 bool ExitIsSetup =
false;
3951void MachineVerifier::verifyStackFrame() {
3952 unsigned FrameSetupOpcode =
TII->getCallFrameSetupOpcode();
3953 unsigned FrameDestroyOpcode =
TII->getCallFrameDestroyOpcode();
3954 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3958 SPState.
resize(MF->getNumBlockIDs());
3965 DFI != DFE; ++DFI) {
3968 StackStateOfBB BBState;
3970 if (DFI.getPathLength() >= 2) {
3973 "DFS stack predecessor is already visited.\n");
3974 BBState.EntryValue = SPState[StackPred->
getNumber()].ExitValue;
3975 BBState.EntryIsSetup = SPState[StackPred->
getNumber()].ExitIsSetup;
3976 BBState.ExitValue = BBState.EntryValue;
3977 BBState.ExitIsSetup = BBState.EntryIsSetup;
3981 report(
"Call frame size on entry does not match value computed from "
3985 <<
" does not match value computed from predecessor "
3986 << -BBState.EntryValue <<
'\n';
3990 for (
const auto &
I : *
MBB) {
3991 if (
I.getOpcode() == FrameSetupOpcode) {
3992 if (BBState.ExitIsSetup)
3993 report(
"FrameSetup is after another FrameSetup", &
I);
3994 if (!
MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
3995 report(
"AdjustsStack not set in presence of a frame pseudo "
3996 "instruction.", &
I);
3997 BBState.ExitValue -=
TII->getFrameTotalSize(
I);
3998 BBState.ExitIsSetup =
true;
4001 if (
I.getOpcode() == FrameDestroyOpcode) {
4002 int Size =
TII->getFrameTotalSize(
I);
4003 if (!BBState.ExitIsSetup)
4004 report(
"FrameDestroy is not after a FrameSetup", &
I);
4005 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
4007 if (BBState.ExitIsSetup && AbsSPAdj !=
Size) {
4008 report(
"FrameDestroy <n> is after FrameSetup <m>", &
I);
4009 OS <<
"FrameDestroy <" <<
Size <<
"> is after FrameSetup <"
4010 << AbsSPAdj <<
">.\n";
4012 if (!
MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
4013 report(
"AdjustsStack not set in presence of a frame pseudo "
4014 "instruction.", &
I);
4015 BBState.ExitValue +=
Size;
4016 BBState.ExitIsSetup =
false;
4024 if (Reachable.
count(Pred) &&
4025 (SPState[Pred->
getNumber()].ExitValue != BBState.EntryValue ||
4026 SPState[Pred->
getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
4027 report(
"The exit stack state of a predecessor is inconsistent.",
MBB);
4029 << SPState[Pred->
getNumber()].ExitValue <<
", "
4030 << SPState[Pred->
getNumber()].ExitIsSetup <<
"), while "
4032 << BBState.EntryValue <<
", " << BBState.EntryIsSetup <<
").\n";
4039 if (Reachable.
count(Succ) &&
4040 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
4041 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
4042 report(
"The entry stack state of a successor is inconsistent.",
MBB);
4044 << SPState[Succ->getNumber()].EntryValue <<
", "
4045 << SPState[Succ->getNumber()].EntryIsSetup <<
"), while "
4047 << BBState.ExitValue <<
", " << BBState.ExitIsSetup <<
").\n";
4053 if (BBState.ExitIsSetup)
4054 report(
"A return block ends with a FrameSetup.",
MBB);
4055 if (BBState.ExitValue)
4056 report(
"A return block ends with a nonzero stack adjustment.",
MBB);
4061void MachineVerifier::verifyStackProtector() {
4070 bool StackGrowsDown =
4097 if (SPStart < ObjEnd && ObjStart < SPEnd) {
4098 report(
"Stack protector overlaps with another stack object", MF);
4101 if ((StackGrowsDown && SPStart <= ObjStart) ||
4102 (!StackGrowsDown && SPStart >= ObjStart)) {
4103 report(
"Stack protector is not the top-most object on the stack", MF);
unsigned const MachineRegisterInfo * MRI
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
This file implements the BitVector class.
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
global merge Global merge function pass
const HexagonInstrInfo * TII
hexagon widen Hexagon Store false hexagon widen loads
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
This file declares the MIR specialization of the GenericConvergenceVerifier template.
unsigned const TargetRegisterInfo * TRI
static void verifyConvergenceControl(const MachineFunction &MF, MachineDominatorTree &DT, std::function< void(const Twine &Message)> FailureCB, raw_ostream &OS)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
This file defines generic set operations that may be used on set's of different types,...
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file describes how to lower LLVM code to machine code.
static unsigned getSize(unsigned Kind)
const fltSemantics & getSemantics() const
A container for analyses that lazily runs them and caches their results.
PassT::Result * getCachedResult(IRUnitT &IR) const
Get the cached result of an analysis pass for a given IR unit.
Represent the analysis usage information of a pass.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches,...
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
bool test(unsigned Idx) const
void clear()
clear - Removes all bits from the bitvector.
iterator_range< const_set_bits_iterator > set_bits() const
size_type size() const
size - Returns the number of bits in this bitvector.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
IntegerType * getIntegerType() const
Variant of the getType() method to always return an IntegerType, which reduces the amount of casting ...
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Implements a dense probed hash-table based set.
void recalculate(ParentType &Func)
recalculate - compute a dominator tree for the given function
Base class for user error types.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
FunctionPass class - This class is used to implement most global optimizations.
void initialize(raw_ostream *OS, function_ref< void(const Twine &Message)> FailureCB, const FunctionT &F)
void verify(const DominatorTreeT &DT)
void visit(const BlockT &BB)
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
constexpr bool isPointerVector() const
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr bool isScalable() const
Returns true if the LLT is a scalable vector.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
constexpr unsigned getAddressSpace() const
constexpr bool isPointerOrPointerVector() const
constexpr LLT getScalarType() const
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Result of a LiveRange query.
bool isDeadDef() const
Return true if this instruction has a dead def.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
VNInfo * valueOut() const
Return the value leaving the instruction, if any.
bool isKill() const
Return true if the live-in value is killed by this instruction.
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
This class represents the liveness of a register, stack slot, etc.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
bool liveAt(SlotIndex index) const
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarily including Idx,...
bool verify() const
Walk the range and assert if any invariants fail to hold.
unsigned getNumValNums() const
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
TypeSize getValue() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
ExceptionHandling getExceptionHandlingType() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
bool isConvergent() const
Return true if this instruction is convergent.
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getOpcode() const
Return the opcode number for this descriptor.
This holds information about one operand of a machine instruction, indicating the register class for ...
bool isOptionalDef() const
Set if this operand is a optional def.
uint8_t OperandType
Information about the type of the operand.
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.
const MDOperand & getOperand(unsigned I) const
bool isValid() const
isValid - Returns true until all the operands have been visited.
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
succ_iterator succ_begin()
bool isIRBlockAddressTaken() const
Test whether this block is the target of an IR BlockAddress.
unsigned succ_size() const
BasicBlock * getAddressTakenIRBlock() const
Retrieves the BasicBlock which corresponds to this MachineBasicBlock.
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
pred_iterator pred_begin()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned getCallFrameSize() const
Return the call frame size on entry to this basic block.
iterator_range< succ_iterator > successors()
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int getStackProtectorIndex() const
Return the index for the stack protector object.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
bool isVariableSizedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a variable sized object.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
bool hasStackProtectorIndex() const
uint8_t getStackID(int ObjectIdx) const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool verify(Pass *p=nullptr, const char *Banner=nullptr, raw_ostream *OS=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
BasicBlockListType::const_iterator const_iterator
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isReturn(QueryType Type=AnyInBundle) const
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const PseudoSourceValue * getPseudoValue() const
const MDNode * getRanges() const
Return the range tag for the memory reference.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
LocationSize getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isIntrinsicID() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isValidExcessOperand() const
Return true if this operand can validly be appended to an arbitrary operand list.
bool isShuffleMask() const
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
ManagedStatic - This transparently changes the behavior of global statics to be lazily constructed on...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
A set of analyses that are preserved following a run of a transformation pass.
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
This class implements the register bank concept.
const char * getName() const
Get a user friendly name of this register bank.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
bool erase(PtrType Ptr)
Remove pointer from the set.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
Information about stack frame layout on the target.
StackDirection getStackGrowthDirection() const
getStackGrowthDirection - Return the direction the stack grows
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
std::string str() const
Return the twine contents as a std::string.
VNInfo - Value Number Information.
bool isUnused() const
Returns true if this value is unused.
unsigned id
The ID number of this value.
SlotIndex def
The index of the defining instruction.
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
LLVM Value Representation.
Wrapper class representing a virtual register or register unit.
constexpr bool isVirtualReg() const
constexpr MCRegUnit asMCRegUnit() const
constexpr Register asVirtualReg() const
std::pair< iterator, bool > insert(const ValueT &V)
constexpr bool isNonZero() const
static constexpr bool isKnownLT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
static constexpr bool isKnownGT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
static constexpr bool isKnownGE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
self_iterator getIterator()
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
This class implements an extremely fast bulk output stream that can only output to a stream.
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< PhiNode * > Phi
NodeAddr< DefNode * > Def
NodeAddr< FuncNode * > Func
const_iterator begin(StringRef path LLVM_LIFETIME_BOUND, Style style=Style::native)
Get begin iterator over path.
const_iterator end(StringRef path LLVM_LIFETIME_BOUND)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
void initializeMachineVerifierLegacyPassPass(PassRegistry &)
@ SjLj
setjmp/longjmp based exceptions
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
void verifyMachineFunction(const std::string &Banner, const MachineFunction &MF)
auto reverse(ContainerTy &&C)
detail::ValueMatchesPoly< M > HasValue(M Matcher)
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_ostream & nulls()
This returns a reference to a raw_ostream which simply discards output.
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
Implement std::hash so that hash_code can be used in STL containers.
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
static constexpr LaneBitmask getAll()
constexpr bool none() const
constexpr bool any() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
Pair of physical register and lane mask.