Open Source Assembly Assemblers for Mac

This is a student project designed to compete in the 2010 IEEE Computer Society Student Competition: http://www.computer.org/portal/web/competition/2010competition The Code Red architecture is designed for extremely lower power environments, like distributed sensor networks. Included is a design of that architecture, a Java-based simulator, an implementation (without vector instructions) designed as a Logisim circuit (http://ozark.hendrix.edu/~burch/logisim/), and more. The name "Code Red" comes from our team name, the Red Team. Since the competition dictated a small team size, our professor split the class and gave each group a color. We liked the name "Code Red" and chose it to represent our team and school's color (UMass' official color is Maroon.) Only later did we realize that "Code Red" was the name of an unrelated computer worm from 2001.

MEDDAC is the seeding point for designing a new approach to Operating System design itself. It is an Open Source project with roots in mainframe design and development the author began in 1979. Monitor Editor Disassembler Decompiler Assembler Compiler

UniSIMD assembler is a high-level C/C++ macro assembler framework unified across ARM, MIPS, POWER and x86 architectures. It establishes a subset of both BASE and SIMD instruction sets with clearly defined common API, so that application logic can be written and maintained in one place without code replication. The assembler itself isn't a separate tool, but rather a collection of C/C++ header files, which applications need to include directly in order to use. At present, Intel SSE/SSE2/SSE4 and AVX/AVX2/AVX-512 (32/64-bit x86 ISAs), ARMv7 NEON/NEONv2, ARMv8 AArch32 and AArch64 NEON, SVE (32/64-bit ARM ISAs), MIPS 32/64-bit r5/r6 MSA and POWER 32/64-bit VMX/VSX (little/big-endian ISAs) are mostly implemented (/w horizontal reductions) although scalar improvements, wider SIMD vectors with zeroing/merging predicates in 3/4-operand instructions are planned as extensions to current 2/3-operand SPMD-driven vertical SIMD ISA. See README file.