Download
XLS is an open-source toolkit for building high-level hardware with a modern compiler stack that spans from a functional DSL to optimized IR and hardware generation. At the front end, DSLX lets you describe algorithms with strong typing and familiar control flow while remaining synthesis-friendly. The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA/ASIC flows. A key idea is “software-style” iteration: fast, deterministic simulation via the JIT encourages test-driven development and property checking before committing to RTL. XLS also provides tooling for pipelining, state insertion, and formal equivalence checks between different stages, giving developers confidence as designs evolve. The result is a productive path from high-level specification to real hardware, without giving up control over latency, throughput, and area trade-offs.
Features
- DSLX front end for clear, strongly typed hardware descriptions
- Optimizing compiler and IR with scheduling and transformation passes
- Dual back ends for JIT simulation and Verilog code generation
- Pipelinining and state-insertion tools to meet timing goals
- Property testing and equivalence checking across compiler stages
- Python/C++ tooling for analysis, visualization, and CI integration
Project Samples
