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Post-Layout Simulation Guide

The parasitic capacitances extracted from a layout can impact circuit performance, so post-layout simulation is important. This involves setting the simulation environment to use the extracted netlist rather than the schematic netlist. The steps are otherwise the same as schematic simulation. Comparing the schematic and post-layout simulation results reveals any differences caused by layout issues.

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John Leons
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231 views2 pages

Post-Layout Simulation Guide

The parasitic capacitances extracted from a layout can impact circuit performance, so post-layout simulation is important. This involves setting the simulation environment to use the extracted netlist rather than the schematic netlist. The steps are otherwise the same as schematic simulation. Comparing the schematic and post-layout simulation results reveals any differences caused by layout issues.

Uploaded by

John Leons
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd

Post Layout Simulation

The parasitic capacitances extracted according to how your layout is designed might be critical in
affecting the actual performance of your design. In order to get an idea of how the design would work
from your layout, you should perform a post-layout simulation from the extracted view. The procedure
is identical to that for simulating from the schematic view.
Open the test schematic for the inverter you used in schematic view simulation.

Open the Analog Design Environment to simulate the circuit


For post layout simulation, an only different thing, compared with schematic view simulation, is that
we need to change some set-up in environment as follows. In Analog Design Environment, choose
Setup -> environment. If then, Environment Options will pop-up.
Type in extracted on Switch View List in the Environment Options. It means that when simulating
your circuit, the simulator will use extracted views net-list, not net-list from schematic view. The
other steps are same as that of the schematic simulation.
To compare both results of schematic view and extracted view, we need to overlap both results in a
same window. Here is one example for this.
Use Plotting mode options. After you display your result from schematic simulation, simulate again
with extracted view, and then switch to Append mode in Plotting mode as shown in figure below.

Display again.

Finally, we will see two overlapped signals in a same window. If your layout is bad, the results show
big differences between schematic and extracted view.

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