Sequential Circuit Analysis

Objectives
This

section introduces synchronous sequential circuits with

the following goals:
Give a precise definition of synchronous sequential circuits.
Introduce several structural and behavioral models for synchronous

sequential circuits.
Demonstrate by example how to analyze synchronous sequential
circuits by deriving their behavior from a structural description.
Demonstrate how to represent the behavior of a synchronous
sequential circuit with Verilog.

Reading assignment
Section

3.4
Sections 4.4, 4,5, and 4.6

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Sequential Circuit Analysis

Topics

Sequential Circuit Models

Mealy and Moore Models

Blocking and Non-blocking Assignment statements

Verilog representation of sequential circuits

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Sequential Circuit Analysis

10.1. Synchronous Sequential Circuits

Definition. A sequential circuit is said to be a
synchronous sequential circuit if it satisfies the
following conditions:

There is at least one flip-flop in every loop

All flip-flops have the same type of dynamic clock
All clock inputs of all the flip-flops are driven by the same
clock signal.

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Sequential Circuit Analysis

Sequential Circuit Canonical Form

Input
Signals

Combinational
Logic
Network

Output
Signals

FF
Current
State
Signals

Next
State
Signals

FF
CLK

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Any synchronous sequential circuit can be drawn in this

form by pulling the flip-flops to the bottom of the figure
(think of the lines as elastic). Since all loops have a flipflop in them, this will leave the remaining circuit without
loops, and hence combinational.

Sequential Circuit Analysis

1. Synchronous Sequential Circuits

Definition. A sequential circuit is said to be a
synchronous sequential circuit if it satisfies the
following conditions:

There is at least one flip-flop in every loop

All flip-flops have the same type of dynamic clock
All clock inputs of all the flip-flops are driven by the same
clock signal.

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Sequential Circuit Analysis

Sequential Circuit Canonical Form

Input
Signals

Combinational
Logic
Network

Output
Signals

FF
Current
State
Signals

Next
State
Signals

FF
CLK

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Any synchronous sequential circuit can be drawn in this

form by pulling the flip-flops to the bottom of the figure
(think of the lines as elastic). Since all loops have a flipflop in them, this will leave the remaining circuit without
loops, and hence combinational.

Sequential Circuit Analysis

There are two versions of this model called the Mealy

Model and the Moore model. The only difference is in the
way the output signals are generated.
Mealy Model: Outputs depend on current state and inputs
Moore Model: Outputs only depend on current state.

Mealy Model
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Moore Model
5

Sequential Circuit Analysis

2. Synchronous Sequential Circuit Models

Structural

Logic diagram
Excitation Equations
Output equations

Behavioral

Transition and output equations

Transition table
State table
State diagram (graph)

SSC Analysis: Derive one of the behavioral models

from an instance of a structural model
SSC Synthesis: Derive a structural model from one of
the behavioral models
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Sequential Circuit Analysis

10.3. Analysis Examples

Example # 1
X
1

Q0

Q1

CK

Derive the excitation and output equations:

J0 = X' + Q1'
J1 = Q0

K0 = 1
K1 = X + Q0

Y = XQ0'Q1 + X'Q0Q1
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Sequential Circuit Analysis

Derive the transition equations from the excitation

equations:
Use the characteristic equation for JK flip-flops:

Q* = JQ' + K'Q
The resulting transition equations are:
Q0* = J0Q0' + K0'Q0 = (X'+ Q1')Q0' + 0Q0
= X'Q0' + Q0'Q1'
Q1* = J1Q1' + K1'Q1 = Q0Q1' + (X+ Q0)'Q1
= Q0Q1' + X'Q0'Q1

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Construct the transition table from the transition equations:

Q1, Q0

X=0 X=1

00
01
10
11

01 01
10 10
11 00
00 00
Q1* Q0*

X=0 X=1
0
0
0
1

0
0
1
0
Y

Sequential Circuit Analysis

Construct the state table and state diagram from the

transition table:
Assign 0 to 00, 1 to 01, 2 to 10, and 3 to 11 giving the following

state table and diagram

Q1, Q0
0
0
1
1

0
1
0
1

X=0

X=1

X=0

X=1

0
0
0
1

0
0
1
0

01
01
10
10
11
00
00
00
Q1* Q0*

Q X=0 X=1 X=0 X=1

0
1
2
3

1
2
3
0

1
2
0
0
Q*

Transition Table

0
0
0
1

0
0
1
0
Y

State Table

State Diagram
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Sequential Circuit Analysis

Example #2

Derive the excitation and output equations:

D2 =
D1 =
D0 =
Y =

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X Q2 Q0
Q2
Q1
X Q2 Q0

10

Sequential Circuit Analysis

Construct the excitation/transition table from the

excitation/transition equations:
Note that since D flip-flops are used, the sets of excitation and

transition equations are the same. Therefore the transition table is

obtained by plotting the excitation equations.
Q2* = Y = XQ2 Q0; Q1* = Q2; Q0* = Q1;

Q2 Q1 Q0
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

X=0

X=1

X=0

X=1

000
100
001
101
110
010
111
011

100
000
101
001
010
110
011
111

0
1
0
1
1
0
1
0

1
0
1
0
0
1
0
1

0
1
0
1
0
1
0
1

Q2* Q1* Q0*

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Sequential Circuit Analysis

Construct the state table from the transition table

Let 000 = A, 001 = B, 010 = C, 011 = D, 100 = E, 101 = F,

110 = G, 111 = H
Q2 Q1 Q0
0
0
0
0
1
1
1
1

Transition Table:

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

X=0

X=1

X=0

X=1

000
100
001
101
110
010
111
011

100
000
101
001
010
110
011
111

0
1
0
1
1
0
1
0

1
0
1
0
0
1
0
1

Q2* Q1* Q0*

State Table:

X=0

X=1

X=0

X=1

A
B
C
D
E
F
G
H

A
E
B
F
G
C
H
D

E
A
F
B
C
G
D
H

0
1
0
1
0
1
1
0

1
0
1
0
1
0
0
1

Q*
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12

Y
Sequential Circuit Analysis

Construct the state diagram from the state table

State Table:

X=0

X=1

X=0

X=1

A
B
C
D
E
F
G
H

A
E
B
F
G
C
H
D

E
A
F
B
C
G
D
H

0
1
0
1
0
1
1
0

1
0
1
0
1
0
0
1

Q*

State Diagram:

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13

Sequential Circuit Analysis

Example #3 (Problem 7.18)

EN
J
K

Q0

MAX
Q1

CLK

Derive the excitation and output equations:

J0 = K0 = EN
J1 = K1 = ENQ0
MAX = ENQ0Q1

Derive the transition equations from the excitation equations:

Q0* = J0Q0' + K0'Q0 = ENQ0' + EN'Q0
Q1* = J1Q1' + K1'Q1 = ENQ0Q1' +(ENQ0)'Q1

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Sequential Circuit Analysis

Construct the transition table from the transition equations:

Transition Equations: Q0* = ENQ0' + EN'Q0

Q1* = ENQ0Q1' + EN' Q1 +Q0'Q1

Q1 Q0 EN=0 EN=1 EN=0 EN=1

00
0 0 0 1
0
0
01
0 1 1 0
0
0
10
1 0 1 1
0
0
11
1 1 0 0
0
1
Q1* Q0*
MAX

Construct the state table from the transition table:

Q
0
1
2
3

EN=0
0
1
2
3
Q*

EN=1
1
2
3
0

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15

Sequential Circuit Analysis

Construct the state diagram from the state table:

State Table:

Q
0
1
2
3

EN=0
0
1
2
3
Q*

EN=1
1
2
3
0

EN/0
0

State Diagram:

EN=0 EN=1
0
0
0
0
0
0
0
1
MAX

EN/0

EN/0

1
EN/0

EN/1
EN/0

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EN=0 EN=1
0
0
0
0
0
0
0
1
MAX

16

EN/0

2
EN/0

Sequential Circuit Analysis

Example #4

Logic Diagram
J

Q0
K

Q1
K

X
CLK

Derive the excitation equations

J0 = XQ1'Q0'
J1 = XQ0
K0 = XQ1
K1 = XQ1Q0'

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Derive the transition equations from the excitation

equations:
Q0*

= J0Q0' + K0'Q0
= (XQ1'Q0')Q0' + (XQ1)'Q0
= XQ1'Q0' + X'Q0 + Q1'Q0

Q1*

= J1Q1' + K1'Q1
= (XQ0)Q1' + (XQ1Q0')'Q1
= (XQ0Q1' + (X' + Q1' + Q0)Q1
= XQ0Q1' + X'Q1 + Q0Q1

Derive the transition table from the transition equations:

Q1 Q0
00
01
10
11

X=0
00
01
10
11
Q1* Q0*

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Sequential Circuit Analysis

18

X=1
01
1 1
00
10

0
0
1
1
Z
Sequential Circuit Analysis

Derive the state table from the transition table:

Where 00 = A, 01 = B, 10 = C, 11 = D

Q
A
B
C
D

X=0
A
B
C
D

X=1
B
D
A
C
Q*

0
0
1
1
Z

Derive the state diagram from the state table:

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Sequential Circuit Analysis

4. Synchronous Sequential Circuits & Verilog

Blocking vs. non-blocking assignment statements

Write code for the following circuit (a 2-bit shift register)

D

D Q
Q

Q1

D Q

Q2

Ck

First try
module bexample (D, Ck, Q1, Q2);
input D, Ck;
output Q1, Q2;
reg Q1, Q2;
always @(posedge Ck)
begin
Q1 = D;
Q2 = Q1;
end

D
Ck

D Q

Q1

D Q

Q2

endmodule

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Sequential Circuit Analysis

10

The assignment statements in the previous example are

called blocking. They have the following properties:
The assignment symbol is the equal sign (=).
Multiple assignment statements in the same always block are

executed in the order written.

z
z

In other words a blocking assignment statement will block until the

assignment is complete before going to the next statement.
Hence Q1 first gets D and then Q2 gets the new value of Q1 in the previous
example.

What we need is an assignment that does not change the

state variables until the inputs of all of them have been
computed. This is called a non-blocking assignment and
has the following properties:
The assignment symbol is <=
All statements are evaluated using the values the variables have

when the always block is entered.

Only when the always block terminates are the variables updated

with their new values.

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Sequential Circuit Analysis

The following module using blocking assignments will

realize the circuit in the previous example:
module nbexample (D, Ck, Q1, Q2);
input D, Ck;
output Q1, Q2;
reg Q1, Q2;
D

always @(posedge Ck)

begin
Q1 <= D;
Q2 <= Q1;
end

D Q
Q

Q1

D Q

Q2

Ck

endmodule

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As a general rule, it is best to use non-blocking assignments

for the state variables of a sequential circuit and use
blocking assignments in combinational logic modules.

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Sequential Circuit Analysis

11

Verilog description of example #1

module example1 (Ck, X, Q, Y);
input Ck, X;
output Y;
output [1:0] Q;
reg [1:0] Q;
always @(posedge Ck)
case (Q)
0: Q <= 1;
1: Q <= 2;
2: if (X) Q <= 0;
else Q <= 3;
3: Q <= 0;
default: Q <= 2'bxx;
endcase
assign Y = ((Q == 2) & X) | ((Q == 3) & ~X);
endmodule

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23

Sequential Circuit Analysis

Alternate description of example 1

module example1a (Ck, X, Q, Y);
input Ck, X;
output Y;
output [1:0] Q;
reg [1:0] Q, NXST;
reg Y;
always @(posedge Ck)
Q <= NXST;
always @(Q or X)
case (Q)
0: begin NXST = 2'b01; Y = 0; end
1: begin NXST = 2; Y = 0; end
2: if (~X) begin NXST = 3; Y = 0; end
else begin NXST = 0; Y = 1; end
3: begin NXST = 0; if (~X) Y = 1; else Y = 0; end
endcase
endmodule

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24

Sequential Circuit Analysis

12

Another Example
module simple (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
always @(w or y) // Define the next state combinational logic
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase
always @(negedge Resetn or posedge Clock) // Define the flip-flops
if (Resetn == 0) y <= A;
else y <= Y;
assign z = (y == C); // Define output logic
endmodule

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25

Sequential Circuit Analysis

Alternate description of previous example:

module simple (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg [2:1] y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
always @(negedge Resetn or posedge Clock) // Define the sequential block
if (Resetn == 0) y <= A;
else
case (y)
A: if (w) y <= B;
else
y <= A;
B: if (w) y <= C;
else
y <= A;
C: if (w) y <= C;
else
y <= A;
default: y <= 2'bxx;
endcase
assign z = (y == C); // Define output
endmodule
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Sequential Circuit Analysis

13

5. Review
Sequential circuit models:

Canonical form
Mealy vs. Moore models

Excitation & output equations

Transition equations & transition table

State table and state diagram

Verilog models

Blocking vs. non-blocking assignment statements

The treatment of clocks in all the models.

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Sequential Circuit Analysis

14