OVERVIEW OF 3D VERTICAL NAND FLASH MEMORY

USING CHARGE TRAP FLASH TECHNOLOGY

Seminar Report
Submitted by
MUNEER K (M130440EC)
In partial fulfillment for the award of the Degree of
MASTER OF TECHNOLOGY
IN
ELECTRONICS & COMMUNICATION ENGINEERING
(Electronic Design and Technology)

Department of Electronics and Communication Engineering

NATIONAL INSTITUTE OF TECHNOLOGY CALICUT
NIT Campus P.O., Calicut, Kerala - 673601
April 2014

Department of Electronics & Communication Engineering

NATIONAL INSTITUTE OF TECHNOLOGY, CALICUT

CERTIFICATE
This is to certify that the report entitled OVERVIEW OF 3D VERTICAL NAND
FLASH MEMORY USING CHARGE TRAP FLASH TECHNOLOGY is a
bonafide record of the Seminar presented by MUNEER K (M130440EC), in partial
fulfillment of the requirements for the award of the degree of Master of Technology
in Electronic Design and Technology from National Institute of Technology
Calicut.

Faculty-in-charge

Head of Department

(EC6108 - Seminar)

Dept. of ECE

Dept. of ECE
Place: NIT Calicut
Date:

ABSTRACT
The existing standstill in memory scaling was resolved by the recent
development in 3D vertical NAND flash memory.
Three-dimensional NAND takes today's flash, which is built on a horizontal
plane, and turns it sideways. Then, like microscopic memory skyscrapers, it stacks
them side-by-side to create a vastly more dense chip with twice the write performance
and 10 times the reliability of today's 2D, or planar, NAND.
NAND flash uses transistors or a charge to trap (also known as Charge Trap
Flash) to store a bit of data in a silicon cell. By making this CTF layer threedimensional, the reliability and speed of the NAND memory have improved sharply.
The new 3D V-NAND shows not only an increase of a minimum of 2X to a
maximum 10X higher reliability, but also twice the write performance over
conventional 10nm-class floating gate NAND flash memory.

CONTENTS
List of Figures
1 Introduction
2 Flash Memory

ii
1
2

2.1
2.2

Principle Of Operation
NAND Flash
3 Limitations of NAND Flash
3.1
Cell to Cell Interference
3.2
Oxide Defects
4 Charge Trap Flash
4.1
Charge Trapping Operation
5 3D Vertical NAND Flash Memory

3
4
6
6
7
8
8
12

5.1
Structure
5.2
Construction
5.3
Performance
6 Conclusion & Future Works

12

References

15

13
13

14

LIST OF FIGURES

Fig No
1

Flash memory cell

Floating gate operation

NAND Flash

Cell to cell interference

Charge Trapping vs Floating Gate mechanisms

Multi Bit Storage Mechanism

10

Planar NAND flash to 3D NAND flash

12

Performance Comparisons

13

V-NAND Structure Innovation Timeline

14

1 CHAPTER 1
2 INTRODUCTION
3
4

Within a few years, we will likely be carrying a

smartphone, tablet or laptop with hundreds of gigabytes or even terabytes

of hyper fast, non-volatile memory, thanks to the developments unveiled,
the three-dimensional (3D) Vertical NAND (V-NAND) flash memory
which breaks through the current scaling limit and opens new dimensions
for the existing standstill technologies.
5

They can be used for a wide range of consumer electronics

and enterprise applications, including embedded NAND storage and solid

state drives (SSDs) achieving gains in performance and area ratio. NAND
flash is similar to other secondary data storage devices, such as hard disks
and optical media, and is thus very suitable for use in mass-storage
devices, such as memory cards. Vertical structures are seen as a logical
next step for NAND flash, once further horizontal scaling becomes
inviable. Samsung has announced the mass production of its 3D vertical
NAND flash chips. And it has successfully included 128 Gbytes of
memory on a single chip.
6

Now let us have a close look at how these new

developments will lead us to our next generation storage level.

7
8
9
10
11
12

13 CHAPTER 2
14 FLASH MEMORY
16

Flash memory is an electronic non-volatile computer storage

medium that can be electrically erased and reprogrammed. Flash memory was
developed from EEPROM

(electrically erasable programmable read-only

memory).
17

There are two main types of flash memory, which are named after

the NAND and NOR logic gates. The internal characteristics of the individual
flash memory cells exhibit characteristics similar to those of the corresponding
gates. Whereas EPROMs had to be completely erased before being rewritten,
NAND type flash memory may be written and read in blocks (or pages) which are
generally much smaller than the entire device. The NOR type allows a single
machine word (byte) to be written or read independently.
18

Although flash memory is technically a type of EEPROM, the term

"EEPROM" is generally used to refer specifically to non-flash EEPROM which is

erasable in small blocks, typically bytes. Because erase cycles are slow, the large
block sizes used in flash memory erasing give it a significant speed advantage
over old-style EEPROM when writing large amounts of data.
19

As of 2013 flash memory costs much less than byte-programmable

EEPROM and has become the dominant memory type wherever a system requires
a significant amount of non-volatile, solid state storage. NOR-based flash has long
erase and write times, but provides full address and data buses, allowing random
access to any memory location. This makes it a suitable replacement for older
read-only memory (ROM) chips, which are used to store program code that rarely
needs to be updated, such as a computer's BIOS or the firmware of set-top boxes.
NAND flash has reduced erase and write times, and requires less chip area per
cell, thus allowing greater storage density and lower cost per bit than NOR flash;

20 it also has up to ten times the endurance of NOR flash. However, the I/O
interface of NAND flash does not provide a random-access external address
bus. Rather, data must be read on a block-wise basis, with typical block sizes
of hundreds to thousands of bits. This makes NAND flash unsuitable as a
drop-in replacement for program ROM, since most microprocessors and
microcontrollers required byte-level random access.
21

In this regard, NAND flash is similar to other secondary data

storage devices, such as hard disks and optical media, and is thus very suitable for
use in mass-storage devices, such as memory cards.
2.1 Principle of Operation

22
24

23 Fig 1: Flash Memory Cell

25
26
Flash memory stores information in an array of memory cells made from
floating-gate transistors.
27

The floating gate may be conductive (typically polysilicon in most kinds

of flash memory) or non-conductive (as in SONOS flash memory).

28 Floating-gate transistor
29

In flash memory, each memory cell resembles a standard MOSFET, except

the transistor has two gates instead of one. On top is the control gate (CG), as
in other MOS transistors, but below this there is a floating gate (FG) insulated

all around by an oxide layer. The FG is interposed between the CG and the
MOSFET channel.
30

Because the FG is electrically isolated by its insulating layer, any electrons

placed on it are trapped there and, under normal conditions, will not discharge
for many years. When the FG holds a charge, it screens (partially cancels) the
electric field from the CG, which modifies the threshold voltage (VT) of the
cell (more voltage has to be applied to the CG to make the channel conduct).

31

32

Fig 2: Floating Gate Operation

33
34

For read-out, a voltage intermediate between the possible threshold

voltages is applied to the CG, and the MOSFET channel's conductivity tested (if
it's conducting or insulating), which is influenced by the FG. That is when the
earlier threshold is applied if current flows through channel then no charges are
trapped. The trapped charges can be decided to be of any logic state.
35

The current flow through the MOSFET channel is sensed and forms a
binary code, reproducing the stored data. In a multi-level cell device, which
stores more than one bit per cell, the amount of current flow is sensed (rather
than simply its presence or absence), in order to determine more precisely the
level of charge on the FG.

2.2 NAND FLASH

36

NAND flash also uses floating-gate transistors, but they are

connected in a way that resembles a NAND gate: several transistors are connected
in series, and only if all word lines are pulled high (above the transistors' VT) is
the bit line pulled low.
37

Fig 3: NAND flash

38
39
40

To read, first the desired group is selected (in the same way that a

single transistor is selected from a NOR array). Next, most of the word lines are
pulled up above the VT of a programmed bit, while one of them is pulled up to
just over the VT of an erased bit. The series group will conduct (and pull the bit
line low) if the selected bit has not been programmed.

41
42
43
44
45
46
47
5

48
49
50
51
52

53 CHAPTER 3
54 LIMITATIONS OF NAND FLASH
55 The main reasons why we had to switch from the existing NAND flash was
due to cell to cell interference and oxide defects.
57 3.1 CELL TO CELL INTERFERENCE
58

NAND flash has been scaling very aggressively. As processes

migrate, the width of the interface of the control gate and the floating gate shrinks
in proportion to the square of the shrink, and the spacing between floating gates
shrinks in proportion to the process shrink, but the floating gates thickness
remains the same. (The thinner the floating gate is made the less tolerant the cell
becomes to electron loss.) This means that the coupling between adjacent floating
gates becomes larger than the coupling between the control gate and the floating
gate, leading to data corruption between adjacent bits.

59

60

Fig 4: Cell To Cell Interference

61 As we can see that till about 20nm we can adjust and continue scaling without
having the interference problem. Beyond that pattering will form. This is why
further scaling couldn't be done.
62 3.2 OXIDE DEFECTS
63

High write loads in a flash memory cause stress on the tunnel oxide

layer creating small disruptions in the crystal lattice called oxide defects. If a
large number of such disruptions are created a short circuit develops between the
floating gate and the transistors channel and the floating gate can no longer hold a
charge. This is the root cause of flash wear-out, which is specified as the chips
endurance. In order to reduce the occurrence of such short circuits, floating gate
flash is manufactured using a thick tunnel oxide (~100), but this slows erase
when Fowler-Nordheim tunneling is used and forces the design to use a higher
tunneling voltage, which puts new burdens on other parts of the chip.

64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79

80 CHAPTER 4
81 CHARGE TRAP FLASH
83

To overcome the above problems charge trap flash technology was

introduced instead of floating gate.

84 The technology differs from the more conventional floating-gate MOSFET
technology in that it uses a silicon nitride film to store electrons rather than the
doped polycrystalline silicon typical of a floating gate structure. This approach
allows memory manufacturers to reduce manufacturing costs five ways:
85 1. Fewer process steps are required to form a charge storage node
86

2.

Smaller process geometries can be used (therefore reducing chip

size and

cost)

87 3. Multiple bits can be stored on a single flash memory cell.

88 4. Improved reliability
89

5.

Higher yield since the charge trap is less susceptible to point

defects in the tunneloxide layer

90
91 4.1 CHARGE TRAPPING OPERATION

92

Like the floating gate memory cell, a charge trapping cell uses a

variable charge between the control gate and the channel to change the threshold
voltage of the transistor. The mechanisms to modify this charge are relatively
similar between the floating gate and the charge trap, and the read mechanisms are
also very similar.
Charge Trapping vs Floating Gate Mechanisms
93

In a charge trapping flash electrons are stored in a trapping layer

just as they are stored in the floating gate in a standard flash memory, EEPROM,
or EPROM. The key difference is that the charge trapping layer is an insulator,
while the floating gate is a conductor.

10

94
95 Fig 5: Charge Trapping vs Floating Gate mechanisms
Getting the charge onto the charge trapping layer
96
97

Electrons are moved onto the charge trapping layer similarly to the

way that floating gate NOR flash is programmed, through channel hot electron
(CHE) injection mechanism also known as Hot-carrier injection. In brief, a high
voltage is placed between the control gate while a medium-high voltage is applied
on the source and the drain while a current is induced from the source to the drain.
Those electrons that have gained sufficient energy in traversing through the highfield region near the drain will boil off from the channel to be injected into the
charge trapping layer where they come to rest.
Removing a charge from the charge trapping layer
98
Charge trapping flash is erased via hot hole injection (See Hotcarrier injection) as opposed to the FowlerNordheim tunneling approach used in
both NAND and NOR flash for erasure. This process uses a field, rather than the
current used in FN, to move holes toward the charge trapping layer to remove the
charge.
99

It uses a charge trapping layer not only as a substitute for a conventional

floating gate, but it also takes advantage of the non-conducting nature of the
charge storage nitride to allow two bits to share the same memory cell. As
shown the bits reside at opposite ends of the cell and can be read by running a
current through the channel in different directions.

11

100
101
102

Fig 6: Multi bit storage mechanism

Products have been successfully made to combine this approach with

multilevel cell technology to contain four bits on a [Link] cell is read by
using forward and reverse currents through the channel to read either side of
the charge trap.

Getting 2 bits onto the cell

103
During CHE programming the hot electrons are injected from the
channel into the charge trapping layer toward the biased drain end of the channel,
but not from the floating source end of the channel. By allowing the transistor's
source and drain to switch from one end of the channel to the other, charges can
be injected and stored into the charge trapping layer over either end of the
channel. In a similar way, one end of the charge trapping cell can be erased by
placing the erasing field at one end or the other of the channel, allowing the other
end to float. Band-to-band Hot Hole Erase creates holes that are trapped locally
some of which recombine with electrons to remove the charge from that end of the
charge trap.
Reading 2 bits from the cell
104
The read is performed very simply by reversing the source and
drain contacts. The junction depletion region extending from the drain side shields
the channel from the charge on the side of the charge trapping cell that overlies the
drain. The net result of this is that the drain-side charge has little effect on the

12

current running through the channel, while the source-side charge determines the
threshold of the transistor.
105

When source and drain are reversed, the opposite side's charge

determines the transistor's threshold. This way two different charge levels at either
end of the charge trapping cell will cause two different currents to flow through
the cell, depending on the direction of the current flow.
106

Thus a charge trapping cell is relatively immune to earlier

mentioned difficulties in floating gate, since the charge trapping layer is an

insulator. A short circuit created by an oxide defect between the charge trapping
layer and the channel will drain off only the electrons in immediate contact with
the short, leaving the other electrons in place to continue to control the threshold
voltage of the transistor. Since short circuits are less of a concern, a thinner tunnel
oxide layer can be used (50-70) increasing the trapping layers coupling to the
channel and leading to a faster program speed (with localized trapped charges)
and erasing with lower tunneling voltages. The lower tunneling voltages, in turn,
place less stress on the tunnel oxide layer, leading to fewer lattice disruptions.
Another important benefit of using a charge trapping cell is that the thin
charge trapping layer reduces capacitive coupling between neighboring cells to
improve performance and scalability.
107
108

109
110
111
112
113
114
115
116

13

117
118
119

CHAPTER 5

3D VERTICAL NAND FLASH MEMORY

Vertical structures are seen as a logical next step for NAND flash,

once further horizontal scaling becomes inviable. Since vertical features cannot be
etched sideways, a charge trapping layer becomes a very interesting way to build a
vertical NAND flash string.
120

Vertical NAND (V-NAND) memory stacks memory cells vertically

and uses a charge trap flash architecture. The vertical layers allow larger areal bit
densities without requiring smaller individual cells.
121

5.1 STRUCTURE
122

V-NAND uses a charge trap flash geometry that stores charge on

an embedded silicon nitride film. Such a film is more robust against point defects
and can be made thicker to hold larger numbers of electrons. V-NAND wraps a
planar charge trap cell into a cylindrical form as shown.

123
124
125

Fig 7: Planar NAND flash to 3D NAND flash

An individual memory cell is made up of one planar polysilicon layer

containing a hole filled by multiple concentric vertical cylinders. The hole's

14

polysilicon surface acts as the gate electrode. The outermost silicon dioxide
cylinder acts as the gate

15

126

dielectric, enclosing a silicon nitride cylinder that stores charge, in turn

enclosing a silicon dioxide cylinder as the tunnel dielectric that surrounds a
central rod of conducting polysilicon which acts as the conducting channel.
Memory cells in different vertical layers do not interfere with each other, as
the charges cannot move vertically through the silicon nitride storage medium,
and the electric fields associated with the gates are closely confined within
each layer. The vertical collection is electrically identical to the serial-linked
groups in which conventional NAND flash memory is configured.

127

5.2 CONSTRUCTION
128

Growth of a group of V-NAND cells begins with an alternating

stack of conducting (doped) polysilicon layers and insulating silicon dioxide

layers. The next step is to form a cylindrical hole through these layers. In practice,
a 128 Gbit V-NAND chip with 24 layers of memory cells requires about 2.9
billion such holes. Next the hole's inner surface receives multiple coatings, first
silicon dioxide, then silicon nitride, then a second layer of silicon dioxide. Finally,
the hole is filled with conducting (doped) polysilicon.
129

5.3 PERFORMANCE
130

As of 2013 V-NAND flash reads and writes twice as fast as

conventional NAND. It lasts 10 times longer. V-NAND consumes 50 percent less

power. As of 2013 they offer comparable physical bit density, using 10-nm
lithography, but potentially offer as much as two orders of magnitude of increased
density.
131
132
133
134
135

136

Fig 8: Performance comparisons

16

137
138

CHAPTER 6

CONCLUSION AND FUTURE WORKS

139
140

Thus since 40 years of standstill at the NAND flash technology,

we have finally come up with a solution to our problem. Memory devices which
are nowadays the main parts that determine the lions share of cost to the whole
product. But by our advancement we can now generate cost effective, high
capacity super-fast memories in addition to their small size feature.

141
142
Fig 9: 3D V-NAND structure innovation timeline
At present successful stacking of 24 layers have been done and a scaling of
10-19nm has been achieved. Samsung has announced the mass production of
its 3D vertical NAND flash chips. And it has successfully included 128 Gbytes
of memory on a single chip.

143

144

Thus we can hope that in near future all the present trends will
change and so let us step into the new era of storage.

17

145
[1]

REFERENCES

Hang-Ting Lue, Shih-Hung Chen, Yen-Hao Shih, Kuang-Yeu

Hsieh, and Chih-Yuan Lu, Overview of 3D NAND Flash and
Progress of Vertical Gate (VG) Architecture, in Solid-State
and Integrated Circuit Technology (ICSICT) , ISSN: 1556-

[2]

6013,pp. 1-4 .2012

Saied Tehrani, James Pak, Mark Randolph, Yu Sun, Sameer
Haddad, Eduardo Maayan, Yoram Betser,Advancement in
Charge-Trap Flash Memory Technology, in Memory
Workshop (IMW), 2013 5th IEEE International , pp. 9-

[3]

12,2013
Charge trap flash-

[4]
[5]

[Link]
Flash memory- [Link]
"Press Release: Samsung Announces 3D NAND Flash With
Revolutionary Charge Trap Technology"

146

18