INTRODUCTION TO

RF CMOS IC DESIGN
FOR WIRELESS APPLICATIONS
Mohammed Ismail
Analog VLSI Lab
Web: [Link]/VLSI

Analog VLSI Lab.

Outline
Introduction
Wireless Standards and migration to 3G
CMOS technology for RF
CMOS radio Challenges
Bluetooth as an example for a wireless system
Radio Architectures
CMOS Circuit Design
Conclusions
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The Wireless Revolution

Mobile Meets the Internet
An electronic postcard and a
video conference display are just
two of the multimedia possibilities
illustrated by a pair of computergenerated concept cell phones

A triple-band GSM phone

capable of working in the 900-,
1800-, and 1900-MHz bands. It
is Bluetooth enabled, which
means among other things that it
can connect to the headset
without needing wires

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Wireless Systems
Communication
Theory
Math and more Math (Greek!)
Algorithms

CAD support
Testing
(Tools and Toys!)

Product
Implementation
Circuit Designers
Layout Engineers
Microwave/DSP..etc

Tremendous growth in Wireless Applications

Demands expertise from different areas (more integration of people)
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Third Generation Wireless Applications

Bit Rate
KB/Sec

In-door

WLAN
1000 Bluetooth
100

DECT
PHS
CT1/CT2

10

Cordless
1
10m

100m

3G directions

GPS

GSM
IS-54/IS-95
PDC
Cellular

1000m

Satellite

Paging
10Km

100Km

1000Km

Cell Size

Many Wireless Applications and Gadgets (Multi-dimensional)

More Functional Integration in 3G
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Wireless Standards and Migration

1G

Push to 3G caused by:

1- Demand for Higher Data Rates
3- Global Roaming

2G

3G

2- Capacity

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3G Cellular Standards and Harmonization

3G
IS-95

Multi Carrier
CDMA2000

3GPP2
Direct Sequence

3GPP

OHG
(Operators Harmonization
Group)

ETSI
ARIB

GSM

TDD

3GPP for the similar ETSI and ARIB WCDMA proposals (TDD)
3GPP2 for CDMA2000 and similar WCDMA proposals (FDD)

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Third Generation Cell Phones

3G demands

More Capacity
Higher data rates
More Functions

WCDMA (5MHz)

Backward Compatibility
Global Roaming

Multi-Standard
(Programmable)

Lower Cost
Small Size
Long Battery
lifetime
Low Power
CMOS solution

Programmable CMOS Integrated Wireless Transceivers

Multi-dimensional applications and Multi-standard support

Analog VLSI Lab.

Summary of Cellular Phone, Cordless Phone, LAN and PCS Standards

Wireless
Standard

Access
Scheme

Frequency
Specturm
(MHz)
824849(Tx)
869894(Rx)
17101785(Tx)
18051850(Rx)
890915(Tx)
935960(Rx)

Channel
Spacing

Frequency
Accuracy

Modulation
Technique

Data Rate

Peak
Power

AMPS

FDD

30kHz

2.5ppm

FM

N/A

3W

DCS-1800

TDMA

200kHz

90Hz

GMSK

270.8kbs

200kHz

90Hz

GMSK

270.8kbs

0.8,2,
5,8W
0.8,2,
5,8W

GSM

EGSM

TDMA/
FDMA/
FDD
TDMA

880915(Tx)
925960(Rx)
18801910(Tx)
19301930(Rx)
824849(Tx)
869894(Rx)

200kHz

90Hz

GMSK

270.8kbs

PCS-1900

TDMA

200kHz

90Hz

GMSK

270.8kbs

IS-54
(IS-136)
(D-AMPS)
DECT

TDMA/
FDD

30kHz

200Hz

/4QPSK

48kbs

TDMA
TDD
CDMA

18811897

1.728MHz

50kHz

GFSK

1.152Mbs

250mW

24002483

N/A

25ppm

QPSK

1,211Mbs

1W

CDMA

1920~1980(Tx)
2110~2170(Rx)

5MHz

+/- 0.1ppm

QPSK

3.84Mbs

IS-95

CDMA

1.25MHz

N/A

OQPSK

1.2288Mbs

Bluetooth
(802.11FH)

CDMA/
FH

824-849(Tx)
869-894(Rx)
2400-2483

0.125,
0.25,0.5
2W
N/A

1MHz

20ppm

GFSK

1Mbs

0-20dBm

802.11
(DSSS)
WCDMA
(UMTS)

0.8,2,
5,8W
0.8,2,
5,8W
0.8,1,
2,3 W

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A single handset to support all wireless environments

Global
Satellite

Suburban

Macrocell

Urban

In-building

Microcell

Picocell

Terminals

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Frequencies: A limited natural resource

Companies pay billions for licenses to use these bands!

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Short-Range Wireless Standards

Frequency
Range

Multiple
Access

Modulation

Data Rate

IEEE
802.11

2.4GHz DSSS

2.4GHz

DSSS

DBPSK
DQPSK

WLAN
Standards

2.4GHz FHSS

2.4GHz

FHSS

2GFSK
4GFSK

1Mbps
2Mbps
1Mbps
2Mbps

2.4GHz DSSS
High Data Rate

2.4GHz

DSSS

CCK

Standards

5GHz OFDM

HIPERLAN/2

Spec. 2.0 (5MHz)

5.250GHz
5.775GHz
5.250GHz
5.600GHz

OFDM
OFDM

BPSK/QPSK
16/64 QAM
BPSK/QPSK
16/64 QAM

5.5Mbps
11Mbps
6,9,12,18
24,36,48,54
6,9,12,18
27,36,54Mbps

2.4GHz

FHSS

2GFSK

1Mbps

2.4GHz

FHSS

2GFSK
4GFSK

5Mbps
10Mbps

Analog VLSI Lab.

2.4GHz Standards
IEEE 802.11 DSSS
CDMA, 1-2Mbps
DBPSK, DQPSK
-80dBm sensitivity
11bit Barker Code
Date rate can be increased.(HR/DSSS)

IEEE 802.11 FHSS

CDMA, 1-2Mbps
2GFSK, 4GFSK
-80dBm/-75dBm sensitivity
Simple demodulator
good immunity

Spec 1.0

IEEE 802.11 FHSS

1-2Mbps, 2-4GFSK
1MHz BW
-80/-75dBm sensitivity
hopping rate by the
regulatory authorities

1Mbps, 2GFSK
1MHz BW
-70dBm sensitivity
1600hops/s
smaller size, lower cost

1-2Mbps, 2-4GFSK
1MHz BW
-80/-70dBm sensitivity
50hops/s
Mainly for home networking

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Multistandard operation

WLAN 5G (IEEE802.11a , HIPERLAN2), WLAN 2.4G (IEE802.11b,

IEEE802.11g), WCDMA
Reconfigurable hardware to choose from above
Seperate Bluetooth transceiver
Coordination required if Bluetooth and 2.4G band operate simultaneously
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Multistandard operation

WLAN 5G (IEEE802.11a , HIPERLAN2)

WLAN 2.4G (IEE802.11b, IEEE802.11g)
WCDMA
Seperate Bluetooth transceiver
Reconfigurable radio to choose one of the standards

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Integration in Wireless Systems

Objective:
Low Cost/Low Power/High volume implementation of radio
functions that are formally implemented using bulky,
expensive and power hungry hybrid components.
Multi-mode/Multi-band operation
Service Integration

Optimum Technology Choice

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CMOS technology for RF

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CMOS Technology RF Capabilities

*
Year
Technology
node

1999
180nm

Min. Digital
Supply (V)

2000

2001

1.8-1.5

Min. Analog
Supply (V)

3.32.5

RF
Frequency
(GHz)

0.92.5

2002
130nm

2003

2004

1.5-1.2

2005
100nm
1.2-0.9

2008
70nm

2011
50nm

2014
35nm

0.90.6

0.60.5

0.50.3

2.5-1.8

1.8-1.5

1.5

0.9-10

0.9-100

fmax (GHz)

25

28

32

35

40

45

50

60

150

175

ft (GHz)

20

20

25

30

30

35

40

50

120

140

<1

<1

<1

Noise
Figure (dB)

1.5

1.2

Performance

Time-market

CMOS is a good candidate for RF

Circuits.
Wafer cost

integration

Integration, and packaging rather

than the technology are the limiting
factors

* International Technology Roadmap for semiconductor, 1999edition

Analog VLSI Lab.

Smaller transistors and faster CMOS

200

FT 1 / LG

150

FT = gm / 2 CIN
/L

125

FT (GHz)

6.0

5
O
2
Ta

7.0

2
Si O

)
x
a
(m

100

T OX

5.0
4.0

V DD

75

3.0

50

FT 1 / LG
2

25
0
0.01

LG

2.0
1.0

0.10

0.20

0.30

0.40

0.50

0.60

Maximum Supply Voltage (V)

175

8.0

0.0
0.70

Effective Gate Length (um)

Ft is no problem in CMOS
Analog VLSI Lab.

CMOS Vs Bipolar
CMOS
Symmetric behaviour
Better Linearity (higher signal
swing)
Higher ft at submicron feature
size
Better scaling properties
Low static power (no DC gate
current)

Bipolar
Higher gm for same bias
High ft
Low thermal and 1/f noise, but
produces input current noise
Lower DC offset
No body effect
Lower overdrive (VCEsat)

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CMOS Interconnect Reverse Scaling

Top metal layers larger pitches thicker lines : for power handling and
reduce losses
Interconnect dielectric thickness is twice the metal thickness : minimize
interlevel shorts and minimize capacitance
Hence top metal layers are far from the silicon substrate thus minimizing
substrate losses
Analog VLSI Lab.

CMOS Interconnect Reverse Scaling

Distance between top metal layer and silicon substrate currently about
1.5um per metal layer
10 metal layer technology by the end of the decade
* Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design, [Link],
[Link] etal., JSSC, Oct 2001

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CMOS Interconnect Reverse Scaling

This feature allows use of

Coplanar transmission lines using top metals

Distributed amplifier design
Distributed Oscillator design
can use CMOS for > 10GHz operation !!!

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Passives
Inductors

technolgy advances result in top metal layers that thicker

(low resistance) and further away from the silicon substrate (lower
substrate losses)
Capacitors
meteal-metal capacitors ahave better performance than polypoly capacitors and have less paracitic capacitance to substrate
Varactors
Capacitance between the gate and the bulk can be made used
of to achieve tunable capacitance

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Inductors

Top metal layers provide low loss

moderate Q values can be achieved
provides gain while consuming minimum voltage headroom

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Inductors

Large inductor values possible with mutli layer inductors in

modern processes due to mutual coupling
Interlayer capacitance reduced by using alternate metal layers
Advanced CMOS processes using Cu technology can achieve Q
values upto 20
Same concept can be used to build onchip transformers

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Inductor model

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Capacitors

Capacitance between two metal layers

Low resistance metal layers reduced loss

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RF capacitor model

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Varactors

Variable capacitance between gate and bulk connection

typically used to achieve wide tuning range in VCOs

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RF Layout Techniques
RF and analog layout completely different from digital layout

Digital layouts focus on minimizing area. They use standard cells

with emphasis on minimizing the interconnect area
RF and analog layouts concerned with matching accuracy and noise
immunity rather than minimizing area
Layout involves optimizing individual transistor layouts
Techniques such as interdigitized layouts and common centroid
layouts adopted to improve matching
Substrate taps and wells are used to improve noise immunity
Symmetry critical for differential paths

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Transistor Layout
Multiple finger layout to minimize gate resistance
Poly contacted at both ends to reduce gate resistance
Dummy gates at the ends to minimize effects of boundary
dependent etching
Interdigitized layouts where matching is critical
Common centroid layout where matching is critical
Guard bands surrounding the layout to reduce noise
Transistors to be matched should have same orientation

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Transistor Layout

Poor Layout

Equivalent circuit

Proper Layout

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Transistor Layout

Higher gate resistance

Reduced gate resistance

Gate folds used with relatively wide devices

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Resistor Layout
R = 2Rcontact + (W/L)Rsh
Rsh sheet resistance of poly

Contact resistance should be taken into account

Dummy resistors at the ends to minimize effects of boundary
dependent etching
Interdigitized layouts where resister matching is critical
Guard bands surrounding the resistor layout to reduce noise
Noise isolation by placing resistors over a well
Matched resistors should have same orientation

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Resistor Layout

dummy

Guard band

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Capacitor Layout
Ceff = Aeff (o r/ tox)
Aeff = (W-2x)(L-2x) WL 2(W+L)x
Effective area smaller than designed due to etching effects
Since Aeff proportional to perimeter, keep area-perimeter ratio
constant for better matching
Dummy capacitors at the ends to minimize effects of boundary
dependent etching
Common centroid layouts where matching is critical
Guard bands surrounding the layout to reduce noise
Noise isolation by placing capacitors over a well

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Capacitor Layout

Guard band

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Matching Issues
Second order size effects minimized by constructing large devices
based on unit cells
Boundary conditions for all devices should be matched

C1

C2

C2

C1

M1 M2 M2 M1 M1 M2

Interdigitized

Common centroid

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CMOS Circuit Techniques

Advanced considerably over the last decade
Offset Cancellation (chopping), self calibration and trimming
Low voltage switched capacitor, Sample-and-Hold
Nosie shaping (- technique)
Class AB biasing and adaptive biasing
Low voltage CMOS bandgaps
Gain boosting
Current division
Statistical modeling and yield enhancement

Analog VLSI Lab.

Recent Examples of CMOS Transceivers

Power amplifier
is included

Author

Architecture

Operating
Band
DECT

Techn,
0.6 m

Power
consumption
198mW

J. Rudell et al.
(ISSCC97)
Abidi et al.
(ISSCC97)
M. Steyaert et
al. (ISSCC98)
D. Schaeffer
at al.
(ISSCC98)
S. Wu at al.
(ISSCC98)
D. McNalley
(ISSCC99)
Rasavi
(JSSC, March
99)
HUT
(ISSCC99)
T. Melly et al.
(CICC00)

Wideband IF

ISM (800900MHz)
DCS 1800

1.0 m

177mW

0.35 m

190mW

Low-IF /
Weaver

GPS

0.5 m

115mW

Weaver

GSM/DCS180
0
ISM

0.6 m

72mW-75mW

0.6 m

450mW

Zero-IF

IEEE802.11
WLAN

0.6 m

80mW

Zero-IF

WCDMA
@2GHz
WISNET
@433MHz

0.35Bi0MOS

128mW

0.5 m

100mW

Zero_IF
Low-IF

Zero-IF

Zero_IF

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CMOS Radio Challenges

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CMOS radio challenges : circuits

Good RF characterization and modeling is
needed scalable models, passives, varactors
Process technology with better substrate
isolation
Good modeling of substrate coupling effects,
fully incorporated in the design process
Better design kits for RF design

Analog VLSI Lab.

CMOS radio challenges : System

Adopt system partitioning and mixed-signal strategy
that lend themselves naturally to deep-submicron CMOS
Maximize digital content
requires high speed ADCs/DACs with good DR
Incorporate antenna and front-end passives (RF filters,
Balun, switches) very early in the design process
Adopt pragmatic SOC and SOP (System On Package)
strategies

Analog VLSI Lab.

CMOS radio challenges : System

Good package models, fully incorporated in the design
porcess
Mapping strategy for system to block specifications that
is amenable to CMOS design capability
Complete understanding of the wireless system standards
to optimize the system and avoid unnecessary over design
Test verification, qualification and certification

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BluetoothTM Technology Creating a world without

wires
The BLUETOOTH trademarks are owned by Ericsson.

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The Bluetooth SIG

! Bluetooth was introduced in 1998

by Ericsson, IBM, Intel, Nokia and

Toshiba.
! Currently, more than 2000 adopters
! Bluetooth enabled devices have started
to appear on the market (2001)
! Visit [Link]

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Bluetooth chipsets in m units

Source: Cahner in stat

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Bluetooth in 3G
Bluetooth Technology
Radio interface, operating in the
2.45 GHz "free" ISM band.
Transmitting power less than 1 mW, typical operating range up to
10 meters (30 ft)
Up to 730 kbit/s user data rates, both circuit and packet switched
connection
Very cost effective design! Integration into computer and phone chipsets
is foreseen

The initial creator group consists of these companies

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Bluetooth Is

...

Major joint computing and

telecomm industry initiative
Revolutionary radio technology
solution
Cable replacement, no line of
sight restrictions
Open specification
Perfect for mobile devices
Small, low power, and low cost

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The technology

Short range wireless technology

Range up to 100 meters
Operate at the unlicensed 2.4 ISM band
Form small ad hoc networks called piconets
One master and 7 active slaves
1 Mb/s rate
Robust and reliable transmission using frequency hop spectrum
Support link level security including authentication and encryption
Plug-and-play service discovery
Supports legacy applications
Enable cheap single chip implementation at low power

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Bluetooth usage scenarios 1(3)

Cable replacement

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Bluetooth usage scenarios 2(3)

Access point to networks

GSM/GPRS
Modem

Servers

LAN Access Point

Internet
Cordless
phone

ADSL Modem

ADSL mux

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Bluetooth usage scenarios 3(3)

Personal Area Networking building small local IP subnets

Bluetooth
bridge

Internet
Router/
bridge

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Protocol architecture

Audio

SDP

IP
BNE RFCOMM

Co
n tr
ol

Applications

L2CAP
Link Manager
Baseband
RF

Bluetooth core consists of Link Manager, Baseband and

RF
L2CAP, SDP, RFCOMM, BNE constitute the host stack
Analog VLSI Lab.

Bluetooth radio
1Mhz

. . .
79

12 3

83.5 Mhz

frequency hopping spread spectrum

2.402 GHz + k MHz, k=0, , 78
1,600 hops per second
GFSK modulation
1 Mb/s symbol rate
transmit power
0 dbm (up to 20dbm with power control)

Audio

IP

SDP

BNE RFCOMM

Co
ntr
ol

Applications

L2CAP
Link Manager
Baseband
RF

Analog VLSI Lab.

Audio

Form Piconets and Scatternets

Use paging and inquiry procedures to synchronize
transmission hop frequency and clock of the devices
Implement channel access control based on Time Division
Duplex (TDD)
Support data and voice links
Applications
Provide flow and error control
IP
Voice coding including the error
SDP
BNE RFCOMM
resistant voice coding scheme CVSD
L2CAP
(Continuous Variable Slope Delta)

Co
ntr
ol

Baseband

Link Manager
Baseband
RF

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Link Manager
! Establish links between devices
! Piconet management
! Security support including authentication, encryption and key

management
! Link commands configuration and information

IP

Audio

SDP

BNE RFCOMM

Co
ntr
ol

Applications

L2CAP
Link Manager
Baseband
RF

Analog VLSI Lab.

L2CAP
! Link Layer and Connection Adaptation Protocol (L2CAP)
! Adapt upper layers protocols over the Baseband
! Set up both connectionless and connection-oriented logical channels
! Provide quality of service as well as packet segmentation and

reassembly

IP

Audio

SDP

BNE RFCOMM

Co
ntr
ol

Applications

L2CAP
Link Manager
Baseband
RF

Analog VLSI Lab.

Other protocols
! RFCOMM
! Emulate serial lines used by many legacy applications (e.g. dial-

up networking, LAN access)

! Provide reliable and in sequence delivery of byte stream
! Support multiple concurrent connections to one or more BT
devices
! SDP (Service Discovery Protocol)

! Bluetooth Network Encapsulation (BNE)

! Encapsulate Ethernet over

the transport of IP

SDP
Audio

attributes
! supports service browsing

IP
BNE RFCOMM

Co
ntr
ol

Applications
class
or

! searches for services by service

L2CAP
Link Manager
Baseband

Bluetooth for
RF

Analog VLSI Lab.

!
!
!
!
!

Profiles
Main tool for interoperability between BT devices for a specific
usage model (application and devices)
Define the set of procedures (from different protocols) and the
messages required
Specify the order in which the procedures are combined
Define the roles of involved devices
Four general profiles have been specified
" Generic Access profile
" Serial Port Profile
" Service Discovery Application Profile
" Generic Object Exchange Profile
A number of application profiles has been specified e.g. LAN
Access, Dial-up Networking, File Transfer, Headset.

Analog VLSI Lab.

The profile tree

Dial-up networking

File Transfer

Cordless Telephony
Headset

LAN Access

Synchronization

Intercom
Fax

Networking Profiles

Telephony Profiles

Object Push

Object Exchange
Profiles

Generic Object
Exchange

Serial Port

Generic access

Transport
Profiles

Service discovery
application

Generic Bluetooth Access Profiles

Analog VLSI Lab.

Embedded Bluetooth solutions

Courtesy of Spirea AB, Stockholm

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The flexible solution strategy

Courtesy of Spirea AB, Stockholm

Analog VLSI Lab.

Bluetooth HW

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Bluetooth radio
Ericsson Bipolar radio

One fully tested unit-easy to use

Radio IC, filters and baluns are matched together
Ideal for embedded applications and applications requiring a flexible form
factor

Smallest size
RF IC flipchip mounted-No package
Filter,impedance matched baluns and switch integrated into LTCC
substrate
Lowest height
Self shielding design!
Output power/receiver sensitivity
Class 2 ("10m"), -70dBm at BER 0.1%
Analog VLSI Lab.

Modules
Ericsson Bluetooth Module
Radio, Baseband and Flash memory
Firmware: Supports all Bluetooth protocol layers up to
HCI
UART and USB interfaces for high speed data transfer
rates
PCM and USB interfaces for voice
Low energy consumption
Point to multi-point operation
Built-in shield
FCC and ETSI type approved

Analog VLSI Lab.

Bluetooth radio and baseband architectures

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Radio Architectures

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Super Heterodyne Receivers

Discrete IR and IF filters not amenable for Integration

Channel selection done at IF
Low dynamic range baseband circuits
Multi-Standard programmability in IF stage is difficult to achieve
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Integrated Receivers

Eliminates the need for discrete IR and IF filters

Signal + Blockers are translated to baseband
Channel selection done at baseband
High dynamic range baseband circuits required
Multi-standard programmability in baseband circuits

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Direct Conversion Receiver

Digital servo loop implementation using DSP (for offset cancellation)

Baseband Filter programmability for multi-standard support
Digitally programmable variable gain amplifiers
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WCDMA/GSM/DECT Multi-standard Receiver

DCS1800
Band Filter

Antenna

DCS1800
LNA

I Mixer

DC Offset
Cancellation

Channel/Antialiasing Filter

VGA
Multi-standard
ADC

WCDMA
GSM

Duplexer

DECT
Band Filter

DECT
LNA

DAC

DECT

Multi-band
Frequency Synth.

Transmitter
Signal

WCDMA
Band Filter

WCDMA
LNA

Baseband
Signal

Multi-standard
ADC
Q Mixer

DAC

90 o

DC Offset Channel/AntiCancellation aliasing Filter

Processor

VGA

Zero-IF receiver architecture

Multiple narrow-band LNAs are used to get the high gain and low noise figure
with low power.
I/Q Mixers, low-pass analog filters, analog-to-digital converters are shared for all
the standards
Advanced Offset cancellation algorithm is needed to solve the DC offset problem

Analog VLSI Lab.

WCDMA/GSM/DECT Multi-standard Receiver

Standardswitching Signal

I
DCS1800

1710~1785M Hz

DECT
TDD and
Band Switch

1880~1897M Hz

90 o

M ulti-band
Frequency
Synthesizer

WCDMA
From
Transmitter

Q
1900~1920MHz

Single-pole-four-throw switch controlled by Standard-switching Signal.

(MURATA Filter and Switch)
Only one LNA of the three works to save power controlled by the Standardswitching signal
Two I/Q mixers are shared by all.

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FSK low-IF Receiver

Bluetooth, HomeRF, IEEE 802.11b(FHSS)

Image Rejection by Hartley Method
Quadrature Detector for Demodulator

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RF CMOS Circuit Design

Analog VLSI Lab.

LNA
First stage in the receiver chain
sensitivity of the system
determines the overall NF of the system
Input matching
Provide enough gain to overcome the noise of subsequent
stages (Sensitivity)
Add as little noise as possible
Accomodate a large dynamic range without distortion

Analog VLSI Lab.

LNA
Ld

Lg
Cgs

Ls

Typical single ended CMOS LNA

Analog VLSI Lab.

LNA Design
Common Source
Amplifying device must be large and biased at high current to
reduce noise
Large input device => large input capacitance thereby attenuating
the input signal thus magnifyinging noise.
Hence NF is minimized by proper choice of transistor size and bias
current at the operating frequency of interest.
Min. NF is achieved varies with bias current and device size
NFmin 1+2.3(/T)
optimum device width Wopt 1/(3LsCoxRs)

Analog VLSI Lab.

LNA Design
Zin = ([Link] /Ls) + s(Lg+Ls) + 1/([Link])

Input matched with proper choice of gm,Cgs, Ls and Lg

Power constraints and minimum noise figure determine the
transistor size and hence gm and Cgs.
Choose Ls to achieve 50 Ohm match
Design Lg to tune out the additional capacitance at the
operating frequency
Gain depends on the parasitics of Q1 and load.
Cascode device improves reverse isolation.
Additional stage may be needed to drive a 50 Ohm load
(heterodyne architectures).

Analog VLSI Lab.

LNA

Common Gate
Input matching is simpler
Zin = 1/ (gm+sCgs)
Higher linearity.

Vbias

Vin

Better reverse isolation.

However, higher NF due to limitations on the choice of gm.

Analog VLSI Lab.

Mixer
Frequency translation by multiplying two signals
cos(ct). cos(st) = cos(c+ s)t

upconversion

cos(c- s)t

downconversion

Is NOT Linear Time Invariant (LTI)

LTI systems cannot produce spectral components that are not in the input
To MIX, system has to be Non-Linear or Time Variant
Important properties
Conversion Gain
Noise Figure SSB vs DSB
Linearity
Port Isolation

Analog VLSI Lab.

Mixer
Nonlinearity based Mixers provide frequency translation through
indirect multiplication.
Assuming the nonlinearity is characterized by,
Vout = An (Vin)n
If

Vin = Vc cos(ct) + Vs cos(st)

Second order nonlinearity would result in a cross modulation component,

Vout(cross) = A2 Vc Vs [cos(c- s)t + cos(c+ s)t ]

VS cos(wSt)

VC cos(wCt)

Analog VLSI Lab.

Mixer
Gilbert multiplier based mixers

Switching transistors => multiply by square wave

VIF

VLO
VRF

Analog VLSI Lab.

Basic Oscillator Theory

Analog VLSI Lab.

Oscillator Circuits
RC Oscillators
- easy to realise
- low, medium frequency
- poor phase noise performance
LC Oscillators
- high frequency
- good phase noise performance
- suited for RF wireless applications

Analog VLSI Lab.

Voltage Controlled Oscillators (VCO)

Wireless applications require that oscillators be tunable by a
control signal
Control signal is usually in the form of a voltage

Vcont

VCO

o
1

V1

V2

Vcont

Analog VLSI Lab.

VCO Design Parameters

Analog VLSI Lab.

LC VCO Design

Analog VLSI Lab.

Multi Band VCO

Multi-band operation is accomplished by tuning LC VCO with two control lines,

one for continuous tuning and the other for digital band selection. The
continuous tuning is used for PLL control and channel select. The digital tuning
is used for RF band selection using MOSFET varactors.
Examples:
1. A synthesizer for 900MHz/1800MHz GSM transceiver using wide-band IF
double conversion architecture with a fixed IF of 300MHz. A multi-band VCO
can be designed to operate in the bands of 1200MHz and 1500MHz. Fig. (a)
2. The VCO can be shared between 1800MHz frequency band (GSM, PCS,
WCDMA) and the GPS band 1600MHz. Fig. (b)
VCO band 1 VCO band 2
300MHz
300MHz

200MHz

f
IF 300MHz

900MHz
GSM band

1200MHz

1500MHz
(a)

1800MHz

1600MHz

1800MHz

GSM band

GPS

GSM/PCS/CDMA

(b)

Analog VLSI Lab.

A Dual-Mode Frequency Synthesizer for 3G

A fully integrated dual mode frequency synthesizer for GSM and WCDMA with
maximum hardware sharing:

Analog VLSI Lab.

A Dual-Mode Frequency Synthesizer for 3G

(cont)
Shared components

Non-shared
components

VCO

Integer frequency
divider

PFD, CP,
loop filter

Crystal
oscillator

GSM

15801630MHz

Divided by
246-254

Loop filter
3dB ~
320kHz

80MHz

WCDMA

17851845MHz

Divided by
357-369

/2 output divider,
/32 input divider,
2nd modulator
/25 input divider

Frequency divider:
Integer frequency divider for GSM
Fractional frequency divider for WCDMA

Dual band VCO:

NMOS accumulation mode varactor for band-to-band switching
PN junction varactor for in-band tuning

Shared components:
PFD, CP, integer frequency divider, loop filter, VCO, reference signal, 70% of total die area

Analog VLSI Lab.

Performance Specifications of
Frequency synthesizers
Frequency range
Frequency resolution
Lock time
Spectral purity
phase noise
harmonics
spur

Analog VLSI Lab.

Power Amplifiers
Tuned
load

Vin

Tee/Pi
Matching
network

RL

Challenging because
Most power hungry block in the transceiver
discrete or hybrid implementation is favoured
Large current in output device and matching network packaging
problem
Parasitic effects introduce instability Layout considerations
Analog VLSI Lab.

Power Amplifiers - classification

Classified according to
biasing (A, B, AB, C)
ciruit topology (D, E, F, G, H, S)

Class A

=50 %

Class A
biasing

Class B

=78.6 %

Class B
biasing

Analog VLSI Lab.

Power Amplifiers classification

Class E
Switching power amplifier
Can achieve =100% (theoretical)
Efficiency and output power can be optimized simulataneously
The transistor operates as a switch
It requires a transistor with large breakdown voltage
Class F
Nonlinear amplifier + harmonic distortion
The main idea is to use different termination impedance for different
harmonics to make the drain voltage approach a square wave
Efficiency between 85% to 88%

Analog VLSI Lab.

Power Amplifiers Linearization

Mainly used in basestations
Spectrally efficient modulation schemes to minimize spectral regrowth
In multi-carrier systems, amplifiers should be linear to avoid crossmodulation
Having both linear+efficient PA requires use of non-linear PA (high
efficiency) and the application of linearization techniques
Linearization techniques such as
Feedforward
Feedback
Envelope elimination and restoration
predistortion

Analog VLSI Lab.

RF Measurement Techniques
Example - Phase noise measurements
Measurement at primary frequency of source is not
possible (dynamic ranges of 160dB and 1Hz bandwidths
in the GHz region would be required for the spectrum
analyzer!)
Alternate methods
Direct RF spectrum measurement after
downconversion
Frequency discrimination
Quadrature phase detection

Analog VLSI Lab.

Direct RF Spectrum Measurement

fo

fD
fo+fD

The signal is downconverted to the range of a spectrum analyzer

with desired IF bandwidth
Noise floor of spectrum analyzer is better at lower frequencies
Good approximation when sidebands are symmetrical (AM noise
not present)
Phase noise sidebands from reference frequency at the mixer are
also translated down so reference source must have much better phase
noise performance than oscillator under test

Analog VLSI Lab.

Frequency discrimination
Frequency
discriminator

Selective
Analyzer
Sv(f)=(1/Kf2)Sv(f)
Where Kf = discriminator sensitivity (volt/Hz)

If the noise level is beyond the dynamic range of the spectrum

analyzer, the carrier needs to be eliminated
This is the case for measurements at high offset frequencies
High linearity is required by the discriminating device

Analog VLSI Lab.

Quadrature phase detection

Optional
Preamp

Selective
Analyzer

oscilloscope

Use a double balanced mixer with the unknown source and

reference source set in phase quadrature (90o) at the input (this
eliminates the carrier)
For phase fluctuations << 1 radian the voltage fluctuations at the
mixer output are v=K where K is the calibration factor
If the phase noise of reference is > 10dB below the noise of the
oscillator then the measured noise would be that of the oscillator
Analog VLSI Lab.

Analog Baseband Chains

Analog VLSI Lab.

Goals/Motivation
Develop baseband chains for 3G Integrated Wireless
receivers
Tailored for Integrated Cellular,cordless and Indoor applications
Based on regular modules for short design time

Investigate and propose new CMOS circuits and

techniques suitable for integrated receivers
Low Power Consumption
Digitally Programmable
Simple and Robust Filter/VGA/OTA circuit structures

Analog VLSI Lab.

WCDMA/GSM/DECT Multi-standard Receiver

Anti-aliasing
Filter

Filter
Section 1

VGA1

Filter
Section 2

VGA2

Output
Signal

Two exactly same branches are needed for I/Q channels

Filtering specifications are set as a WCDMA channel filter
Automatic gain control range is set for all the three standards
Anti-aliasing filter is used to filter out the noise and blockers
outside of the sampling frequency of the analog-to-digital
converter.
Proper interleaving order of amplifying and filtering should be
optimized to satisfy both the noise performance and the
nonlinearity performance

Analog VLSI Lab.

Example
Digitally programmable baseband chain for a GSM/DECT
multistandard receiver
900 MHz
RF
Filter

LNA
Mixer

1.8 GHz
RF
Filter

ADC
LNA

2.4 GHz
RF
Filter

Mixer
I

LNA

Mixer
I

DSP
Carrier Tracking
Symbol Timing
Recovery
Frame Recovery
Symbol Decode
Sequence Control
AGC Control
Equalization
DC offset Control
Dout

Enables cell phones to be used as a cordless phone by supporting both

GSM/DECT modes of operation
Utilizes wide band double conversion technique to allow integration
Focus set to develop the baseband section of the receiver chain
Analog VLSI Lab.

GSM/DECT multi-standard receiver

DC offset cancellation in DSP

DC offset fed back to baseband section to be subtracted from signal
VGA with digital offset correction capability is preferred

Channel selection to be performed using DSP

Relaxes filtering requirements (only AAF is necessary)

Software programmable FIR filters for multistandard operation
Requires the use of high dynamic range sigma delta converter
Baseband VGA to reduce the ADC dynamic range

Analog VLSI Lab.

Programmable AAF Filter

Vi

R1

R2

R3
K

C1

Vo

Capacitor array for digitally programmable bandwidth

Based on Sallen Key topology

Few Active elements (better Linearity + Less Noise!+ Simple to design)
Based on unity gain buffer (Simple + High frequency)
Low power Class AB CMOS buffer necessary for low power consumption
Analog VLSI Lab.

The digitally controlled VGA section

Digital offset control
Ib
CDN
R

R
R/2

R1

R2

Vi

Vo
+

R/4
R/8

R4

2R

R5
COARSE

R3

FINE

Two stage VGA sections to achieve wide gain control with fine gain steps
Digital offset trimming using current division network (6 bit)

Analog VLSI Lab.

The digitally controlled VGA section

Digitally controlled Norton VGA die photo

Analog VLSI Lab.

The digitally controlled baseband chain

Programmable bandwidth that covers 100KHz GSM band, 700KHz DECT and
Support for 2.1MHz WCDMA also tested
30dB gain control range with 1dB gain step and gain error < 0.4dB

Analog VLSI Lab.

The digitally controlled baseband chain for receiver

Block

parameter

measurement

Filter

IIP3 (In Band)

IIP3 (Out of Band)
Input referred Noise
In band ripple
Stop band attenuation
Current consumption

29dBm
41dBm
26nV/sqrt(Hz)
0.1dB
70dB
0.58mA

VGA

[Link]
Min Gain
Gain step
Gain error
IIP3
Input referred noise
Bandwidth (Cl=20pF)
Current Consumption

24dB
-6dB
1dB
0.4dB
27dB
16.5nV/sqrt(Hz)
4.1MHz
0.82mA

Analog VLSI Lab.

Digitally Programmable CMOS Filter/VGA

for wireless base stations
Specifications
Signal of Interest

: 12MHz - 23MHz

Pass Band of Filter

: 12MHz - 23MHz (-0.5dB corner points)

Pass Band Ripple

: < 0.5dB

Stop Band

: 0MHz - 5MHz and after 40MHz

Stop Band Attenuation

: > 25dB

Programmable Gain

: -10 dB to 30 dB in steps of 1 dB

Linearity (IMD)

: > 53 dBc

Signal to Noise Ratio

: > 57 dB (noise integrated over 5MHz Bandwidth)

Analog VLSI Lab.

Proposed Filter/VGA Chain

*LPF: Low pass filter
*HPF: High pass filter
2nd order
LPF

6dB step

1st order
HPF

3dB step

2nd order
LPF

6dB step

(-12~0) dB
attenuator

+6 dB

(-12~0) dB

Vin+

Vin+6 dB

1dB step

(-12~0) dB
attenuator
2nd order
LPF

+6 dB

2nd order
HPF

6dB step

attenuator
2nd order
LPF

2nd order
HPF

Vout+

Vout-

(-4~0) dB
attenuator

+6 dB

0 dB

(-12~0) dB
attenuator

+6 dB

6 dB gain buffers in 5 filter stages provide fixed 30 dB gain.

Use filter stages with voltage gain to eliminate the need for VGA stages.
5 digitally programmable attenuators attenuate 30 dB gain in 1 dB steps of gain
Analog VLSI Lab.

Vin+

C1

Vin+

+
+

C2

Vout+

Buffer

Vout+

Buffer

C2

Vout-

Vout-

Vin-

C1

Vin-

Use the buffer circuit to implement fully

differential Sallen-Key filter sections.

Use resistive chain to attenuate the gain

In 1/3/6 dB steps.

Filter tuning is achieved by 4 bit binary

weighted capacitor array.

Programmable gain variation: -10 30 dB

5 bit digital control
Analog VLSI Lab.

The frequency response of VGA/Filter chain

Analog VLSI Lab.

Conclusion
Design Techniques achieving maximum hardware share at
minimum power consumption (configurable radio, programmable
analog baseband)
Improvement in technology, characterization, packaging techniques
are needed
Migration to future wireless standards for higher data rates and
multimedia applications
Eventual convergence of LAN, WAN, PAN infrastructures for
seamless wireless communication
Need for higher levels of integration, available only in CMOS
technologies
Technology scaling favors multi GHz RFCMOS
New challenges, careful system partitioning, good mixed signal
strategy, maximize digital content

Analog VLSI Lab.

No one likes
to be wired!
Analog VLSI Lab.