Lecture: Cache Hierarchies
Topics: cache innovations (Sections B.1-B.3, 2.1)
1
Types of Cache Misses
Compulsory misses: happens the first time a memory
word is accessed the misses for an infinite cache
Capacity misses: happens because the program touched
many other words before re-touching the same word the
misses for a fully-associative cache
Conflict misses: happens because two words map to the
same location in the cache the misses generated while
moving from a fully-associative to a direct-mapped cache
Sidenote: can a fully-associative cache have more misses
than a direct-mapped cache of the same size?
2
Reducing Miss Rate
Large block size reduces compulsory misses, reduces
miss penalty in case of spatial locality increases traffic
between different levels, space waste, and conflict misses
Large cache reduces capacity/conflict misses access
time penalty
High associativity reduces conflict misses rule of thumb:
2-way cache of capacity N/2 has the same miss rate as
1-way cache of capacity N more energy
3
More Cache Basics
L1 caches are split as instruction and data; L2 and L3
are unified
The L1/L2 hierarchy can be inclusive, exclusive, or
non-inclusive
On a write, you can do write-allocate or write-no-allocate
On a write, you can do writeback or write-through;
write-back reduces traffic, write-through simplifies coherence
Reads get higher priority; writes are usually buffered
L1 does parallel tag/data access; L2/L3 does serial tag/data
4
Techniques to Reduce Cache Misses
Victim caches
Better replacement policies pseudo-LRU, NRU, DRRIP
Cache compression
5
Victim Caches
A direct-mapped cache suffers from misses because
multiple pieces of data map to the same location
The processor often tries to access data that it recently
discarded all discards are placed in a small victim cache
(4 or 8 entries) the victim cache is checked before going
to L2
Can be viewed as additional associativity for a few sets
that tend to have the most conflicts
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Replacement Policies
Pseudo-LRU: maintain a tree and keep track of which
side of the tree was touched more recently; simple bit ops
NRU: every block in a set has a bit; the bit is made zero
when the block is touched; if all are zero, make all one;
a block with bit set to 1 is evicted
DRRIP: use multiple (say, 3) NRU bits; incoming blocks
are set to a high number (say 6), so they are close to
being evicted; similar to placing an incoming block near
the head of the LRU list instead of near the tail
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Tolerating Miss Penalty
Out of order execution: can do other useful work while
waiting for the miss can have multiple cache misses
-- cache controller has to keep track of multiple
outstanding misses (non-blocking cache)
Hardware and software prefetching into prefetch buffers
aggressive prefetching can increase contention for buses
8
Stream Buffers
Simplest form of prefetch: on every miss, bring in
multiple cache lines
When you read the top of the queue, bring in the next line
Sequential lines
L1
Stream buffer
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Stride-Based Prefetching
For each load, keep track of the last address accessed
by the load and a possibly consistent stride
FSM detects consistent stride and issues prefetches
incorrect
init steady
correct
correct
incorrect
(update stride) PC tag prev_addr stride state
correct
correct
trans no-pred
incorrect
(update stride) incorrect
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(update stride)
Prefetching
Hardware prefetching can be employed for any of the
cache levels
It can introduce cache pollution prefetched data is
often placed in a separate prefetch buffer to avoid
pollution this buffer must be looked up in parallel
with the cache access
Aggressive prefetching increases coverage, but leads
to a reduction in accuracy wasted memory bandwidth
Prefetches must be timely: they must be issued sufficiently
in advance to hide the latency, but not too early (to avoid
pollution and eviction before use) 11
Intel Montecito Cache
Two cores, each
with a private
12 MB L3 cache
and 1 MB L2
Naffziger et al., Journal of Solid-State Circuits, 2006
12
Intel 80-Core Prototype Polaris
Prototype chip with an entire
die of SRAM cache stacked
upon the cores
13
Example Intel Studies
C C C C C C C C
Memory interface
L1 L1 L1 L1 L1 L1 L1 L1
L2 L2 L2 L2
Interconnect
L3
From Zhao et al.,
IO interface CMP-MSI Workshop 2007
L3 Cache sizes up to 32 MB
14
Shared Vs. Private Caches in Multi-Core
What are the pros/cons to a shared L2 cache?
P1 P2 P3 P4 P1 P2 P3 P4
L1 L1 L1 L1 L1 L1 L1 L1
L2 L2 L2 L2
L2
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Shared Vs. Private Caches in Multi-Core
Advantages of a shared cache:
Space is dynamically allocated among cores
No waste of space because of replication
Potentially faster cache coherence (and easier to
locate data on a miss)
Advantages of a private cache:
small L2 faster access time
private bus to L2 less contention
16
UCA and NUCA
The small-sized caches so far have all been uniform cache
access: the latency for any access is a constant, no matter
where data is found
For a large multi-megabyte cache, it is expensive to limit
access time by the worst case delay: hence, non-uniform
cache architecture
17
Large NUCA
Issues to be addressed for
Non-Uniform Cache Access:
Mapping
CPU Migration
Search
Replication
18
Shared NUCA Cache
A single tile composed
of a core, L1 caches, and
Core 0 Core 1 Core 2 Core 3
a bank (slice) of the
L1 L1 L1 L1 L1 L1 L1 L1 shared L2 cache
D$ I$ D$ I$ D$ I$ D$ I$
L2 $ L2 $ L2 $ L2 $
Core 4 Core 5 Core 6 Core 7
The cache controller
L1 L1 L1 L1 L1 L1 L1 L1 forwards address requests
D$ I$ D$ I$ D$ I$ D$ I$ to the appropriate L2 bank
L2 $ L2 $ L2 $ L2 $ and handles coherence
operations
Memory Controller for off-chip access
Title
Bullet
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