9/23/13
CPU Data Path
Professor Michael McGarry
Data Path
§ Functional units used to operate on or hold data within a
processor
§ Memories
§ Register file
§ ALU
§ Multiplexers
CPU Data Path Design
§ We will look at the implementation of a very basic MIPS
processor
§ Load/Store instructions
§ lw, sw
§ Arithmetic-Logical instructions
§ add, sub, and, or
§ Branch instruction
§ beq
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Instruction Memory
Instr[31:0]
Instruction Word
Arithmetic/Logical Instructions
Data Path
§ op rd, rs, rt (op = {add, sub, and, or})
§ Reg[rd] = Reg[rs] op Reg[rt]
Reg[rd] = Reg[rs] op Reg[rt]
Reg[…]
Arithmetic/Logical Instructions
Data Path
§ op rd, rs, rt (op = {add, sub, and, or})
§ Reg[rd] = Reg[rs] op Reg[rt]
§ Multiplexers to select rd, rs, and rt
§ ALU to perform operation, control signal driven by funct
§ Control signal to select register write
rs funct
Reg[rs]
rt
rd Reg[rd]
Reg[rt]
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Data Transfer Instructions Data
Path
§ lw rt, Offset(rs)
§ Reg[rt] = Mem[Reg[rs] + Offset]
§ sw rt, Offset(rs)
§ Mem[Reg[rs] + Offset] = Reg[rt]
Reg[…]
MemAddr
MemAddr = Reg[rs] + Offset
Mem[…]
Load Word Data Path
§ lw rt, Offset(rs)
§ Reg[rt] = Mem[Reg[rs] + Offset]
§ Memory address =Reg[rs] + Offset (16-bit address in I format,
sign extended to 32 bits)
§ ALU computes memory address (op1 = Reg[rs], op2 = Offset)
§ Control signal to select memory read and register write
rs add
Reg[rs]
rt
Offset* Reg[rt]
Offset Offset*
Store Word Data Path
§ sw rt, Offset(rs)
§ Mem[Reg[rs] + Offset] = Reg[rt]
§ Memory address = Reg[rs] + Offset (16-bit address in I format,
sign extended to 32 bits)
§ ALU computes memory address (op1 = Reg[rs], op2 = Offset)
§ Control signal to select memory write
rs add
Reg[rs]
rt
Offset*
Offset
Offset*
Reg[rt]
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Branch Instruction Data Path
§ beq rs, rt, Offset
§ If Reg[rs] == Reg[rt] (i.e., Reg[rs] – Reg[rt] = 0)
§ then PC = PC + Offset (16-bit address in I format, sign
extended to 32 bits) << 2
rs
Reg[rs] sub
rt
Reg[rt]
Offset Offset*
Arithmetic/Logical Instructions
opcode (6) rs (5) rt (5) rd (5) sh (5) function (6)
Indicates type of instruction,
determines control signal settings
Data Transfer Instructions
opcode (6) rs (5) rt (5) constant or address (16)
Store
Indicates type of instruction,
determines control signal settings
Load
Multiplexer selects which field in
Instr Word drives Write register
RegDst (either rd or rt)
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Conditional Branch Instructions
opcode (6) rs (5) rt (5) constant or address (16)
Indicates type of instruction,
determines control signal settings
Five Stages of Execution
§ Fetch (IF)
§ fetch instruction from memory
§ Decode (ID)
§ instruction word is in IR
§ use bits in instruction word to drive control signals
§ Execute (EX)
§ Operation for Arithmetic/Logical instruction
§ Address computation for Data transfer instruction
§ Equality check for Branch instruction
§ Memory Access (MEM)
§ Memory read - load instruction
§ Memory write – store instruction
§ Write Result/Back (WB)
§ Register write – arithmetic/logical instruction
§ Register write – load instruction
Instruction Fetch (IF)
§ Using Program Counter (PC), fetch next instruction from memory
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Instruction Decode (ID)
§ Decode instruction word (RegDst)
§ Use opcode to determine instruction format
§ Will determine details of the next three stages
§ Will determine control signals required for next three stages
Instruction Execute (EX)
§ Execute instruction using ALU (ALUSrc, ALUOp)
§ arithmetic/logical instructions
§ load/store instructions (compute address)
§ branch instruction (check branch condition)
Instruction Execute (EX)
§ Branch address addition done in parallel by an
adder (PCSrc) (PCSrc = 1 if branch taken)
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Memory Access (MEM)
§ Load/Store Instructions (MemWrite, MemRead)
§ Read/Write memory access (only lw and sw)
Write Result (WB)
§ Write result to register (MemToReg,
RegWrite) (only lw and A/L instrs)
Five Data Path Stages
IF ID EX MEM WB
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Five Stages of Execution
§ Fetch (IF)
§ hard-coded
§ Decode (ID)
§ RegDst – 0 : rs field drives Write Reg (lw instr); 1 : rd field drives Write Reg
§ Execute (EX)
§ ALUSrc – 1 : 16-bit from instruction word (I-format); 0 : Read Register 2
§ ALUOp – Add; Sub; And; Or
§ PCSrc – 1 : Branch target (if beq and branch taken); 0 : PC + 4
§ Memory Access (MEM)
§ MemWrite – positive edge triggers write (sw instr)
§ MemRead – positive edge triggers read (lw instr)
§ Write Result/Back (WB)
§ MemToReg – 0 : ALU Out; 1 : Mem Out (lw instr)
§ RegWrite – positive edge triggers write
Recap
§ Instruction Execution Stages
§ Instruction Fetch (IF)
§ Instruction Decode (ID)
§ Execute (EX)
§ Memory Access (MEM)
§ Write Result (WB)
§ Next: CPU Architecture - Control Path
