Ex.No.

1 Implementation of Half adder & Full Adder

a) Half Adder

Truth Table

Input Output

A B S(Sum) C(Carry)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 1 1

Circuit Diagram Graphical

Notation

Equations

S (Sum) =A^B

C (Carry) =AB
Verilog code for Half adder

module hadd(a,b,s,c);

input a;

input b;

output s;

output c;

assign s = a ^ b;

assign c = a & b;

endmodule

b)Full Adder

Truth Table

Input Output

A B C SUM Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1
 1 1 0 0 1

1 1 1 1 1

K- Map for sum K-map for Carry

SUM = A’B’C + A’BC’ + AB’C’ + ABC Cout = A’BC + AB’C + ABC’

+ABC

SUM= A^B^C Cout= (A^B)C+AB

Circuit Diagram

Verilog code for Full adder

module fadd(a,b,c,s,cout);

input a;

input b;
input i;

output s;

outputcout;

assign s = (a ^ b) ^ c;

assigncout = (a & b)|( b & c)|(c & a);

endmodule

C) Full Adder Using Two Half Adders and one OR gate

Circuit Diagram

Verilog code for Full adder using half adder

module fadd(a,b,ci,s,co);

input a;

input b;

output s;

outputcout;

wire c1,c2,s1

HA 1(s1,c1,a,b);
 HA 2(s,cout,c1,s1)

endmodule

module HA(s,c,a,b);

inputa,b;

outputs,c;

s=a^b;

c=ab;

endmodule

Ex.no:2(a) RIPPLE CARRY ADDER

Multiple full adder circuits can be cascaded in parallel to add an

N-bit number. For an N- bit parallel adder, there must be N number of
full adder circuits. A ripple carry adder is a logic circuit in which the
carry-out of each full adder is the carry in of the succeeding next most
significant full adder. It is called a ripple carry adder because each
carry bit gets rippled into the next stage. In a ripple carry adder the
sum and carry out bits of any half adder stage is not valid until the
carry in of that stage occurs.Propagation delays inside the logic
circuitry is the reason behind this. Propagation delay is time elapsed
between the application of an input and occurance of the
corresponding output. Consider a NOT gate, When the input is “0″
the output will be “1″ and vice versa. The time taken for the NOT
gate’s output to become “0″ after the application of logic “1″ to the
NOT gate’s input is the propagation delay here. Similarly the carry
propagation delay is the time elapsed between the application of the
carry in signal and the occurance of the carry out (Cout) signal.
Circuit diagram of a 4-bit ripple carry adder is shown below.
//4 Bit Ripple Carry Adder in Verilog

//Structural Model : Half Adder

module half_adder(output S,C,input A,B);

xor(S,A,B);
and(C,A,B);
endmodule

//Structural Model : Full Adder

module full_adder(output S,Cout,inputA,B,Cin);

wire s1,c1,c2;
half_adder HA1(s1,c1,A,B);
half_adder HA2(S,c2,s1,Cin);
or OG1(Cout,c1,c2);
endmodule
//Structural Model : 4 Bit Ripple Carry Adder

module ripple_adder_4bit(output [3:0] Sum,outputCout,input [3:0]

A,B,inputCin);
wire c1,c2,c3;
full_adder FA1(Sum[0],c1,A[0],B[0],Cin),
FA2(Sum[1],c2,A[1],B[1],c1),
FA3(Sum[2],c3,A[2],B[2],c2),
FA4(Sum[3],Cout,A[3],B[3],c3);
endmodule

// 4 Bit Ripple Carry Adder Test Bench:

module test_ripple_adder_4bit;
// Inputs
reg [3:0] A;
reg [3:0] B;
regCin;
// Outputs
wire [3:0] Sum;
wire Cout;
// Instantiate the Unit Under Test (UUT)
ripple_adder_4bit uut (.Sum(Sum), .Cout(Cout), .A(A), .B(B), .Cin(Cin));
initial begin
// Initialize Inputs
A = 0;
B = 0;
Cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A=4'b0001;B=4'b0000;Cin=1'b0;
#10 A=4'b1010;B=4'b0011;Cin=1'b0;
#10 A=4'b1101;B=4'b1010;Cin=1'b1;
end
initial begin
$monitor("time=",$time,, "A=%b B=%b Cin=%b : Sum=%b
Cout=%b",A,B,Cin,Sum,Cout);
end
endmodule

Ex.No:2(b) CARRY LOOKAHEAD ADDER

The corresponding boolean expressions are given here to construct a carry

lookaheadadder. In the carry-lookahead circuit we ned to generate the two
signals carry propagator(P) and carry generator(G),
Pi = Ai ⊕ Bi
Gi = Ai · Bi

The output sum and carry can be expressed as

Sumi = Pi ⊕ CiCi+1 = Gi + ( Pi · Ci)
Having these we could design the circuit. We can now write the Boolean
function for the carry output of each stage and substitute for each Ci its
value from the previous equations:

C1 = G0 + P0 · C0
C2 = G1 + P1 · C1 = G1 + P1 · G0 + P1 · P0 · C0
C3 = G2 + P2 · C2 = G2 P2 · G1 + P2 · P1 · G0 + P2 · P1 · P0 · C0
C4 = G3 + P3 · C3 = G3 P3 · G2 P3 · P2 · G1 + P3 · P2 · P1 · G0 + P3 · P2 · P1 ·
P0 · C0

//4 bit Carry Look Ahead Adder verilog

module CLA_Adder(a,b,cin,sum,cout);
input[3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire p0,p1,p2,p3,g0,g1,g2,g3,c1,c2,c3,c4;
assign p0=(a[0]^b[0]),
p1=(a[1]^b[1]),
p2=(a[2]^b[2]),
p3=(a[3]^b[3]);
 assign g0=(a[0]&b[0]),
g1=(a[1]&b[1]),
g2=(a[2]&b[2]),
g3=(a[3]&b[3]);
assign c0=cin,
c1=g0|(p0&cin),
c2=g1|(p1&g0)|(p1&p0&cin),
c3=g2|(p2&g1)|(p2&p1&g0)|(p1&p1&p0&cin),

c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&cin);
assign sum[0]=p0^c0,
sum[1]=p1^c1,
sum[2]=p2^c2,
sum[3]=p3^c3;
assign cout=c4;

endmodule

//TESTBENCH CODE- Carry Look Ahead Adder

module TestModule;

// Inputs
reg [3:0] a;
reg [3:0] b;
regcin;

// Outputs
wire [3:0] sum;
wire cout;

// Instantiate the Unit Under Test (UUT)

CLA_Adderuut (.a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));

initial begin
// Initialize Inputs
a = 0;
b = 0;
 cin = 0;

// Wait 100 ns for global reset to finish

#100;

a = 5;
b = 6;
cin = 1;

// Wait 100 ns for global reset to finish

#100;
end

endmodule

Ex.No:3(a) CARRY SAVE ADDER

//4 bit carry save adder Verilog code:

module fulladder(input a,b,cin,outputsum,carry);

assign sum=a^b^cin;
assign carry=(a&b)|(cin&b)|(a&cin);
endmodule
module carrysave(input[3:0] x,y,z, output[4:0] s,outputcout);
wire[3:0] c1,s1,c2;
fulladder fa_inst10(x[0],y[0],z[0],s1[0],c1[0]),
fa_inst11(x[1],y[1],z[1],s1[1],c1[1]),
 fa_inst12(x[2],y[2],z[2],s1[2],c1[2]),
fa_inst13(x[3],y[3],z[3],s1[3],c1[3]);
fulladder fa_inst20(s1[1],c1[0],1'b0,s[1],c2[1]),
fa_inst21(s1[2],c1[1],c2[1],s[2],c2[2]),
fa_inst22(s1[3],c1[2],c2[2],s[3],c2[3]),
fa_inst23(1'b0,c1[3],c2[3],s[4],cout);
assign s[0]=s1[0];
endmodule

//4 bit carry save adderverilog: test bench:

module carrysave_test;
reg[3:0] x,y,z;
wire[4:0] s;
wire cout;
integer i,j,k,error;
carrysaveuut(x,y,z,s,cout);
initial begin
x=0;
y=0;
z=0;
error=0;
for(i=0;i<16;i=i+1)
begin
for(j=0;j<16;j=j+1)
begin
for(k=0;k<16;k=k+1)
begin
x=i;y=j;z=k;
#10;
if({cout,s}|(i+j+k))
error<=error+1;
end
end
end
end
endmodule

Ex.No:3(b) CARRY SELECT ADDER

Above is the basic building block of a carry-select adder, where the block
size is 4. Two 4-bit ripple carry adders are multiplexed together, where the
resulting carryand sum bits are selected by the carry-in.
//4 bit Carry select Adder using Verilog

module carry_select(a,b,cin,sum,co);
input [3:0]a;
input [3:0]b;
input cin;
output [3:0]sum;
output co;
wire [3:0]sum;
wire co;
wire s1,c1,s2,c2,s3,c3,s4,s11,s44,c4,c11,s22,c22,s33,c33,c44;
//assuming carryin 0
fa x1(a[0],b[0],0,s1,c1);
fa x2(a[1],b[1],c1,s2,c2);
fa x3(a[2],b[2],c2,s3,c3);
fa x4(a[3],b[3],c3,s4,c4);
//assuming carryin 1
fa x5(a[0],b[0],1,s11,c11);
fa x6(a[1],b[1],c11,s22,c22);
fa x7(a[2],b[2],c22,s33,c33);
fa x8(a[3],b[3],c33,s44,c44);
//select either carry 1 or 0 using carry out of FA
//mux for sum select
mux x9(s1,s11,cin,sum[0]);
mux x10(s2,s22,cin,sum[1]);
mux x11(s3,s33,cin,sum[2]);
mux x12(s4,s44,cin,sum[3]);
//mux for carry select
mux x13(c4,c44,cin,co);
endmodule

module fa(a, b, c, sum, carry);

input a;
input b;
input c;
output sum;
output carry;
wire d,e,f;
xor(sum,a,b,c);
and(d,a,b);
and(e,b,c);
and(f,a,c);
or(carry,d,e,f);
endmodule
module mux(a, b, s, q );
input a;
input b;
input s;
output q;
wire q;
assign q=s?b:a;
endmodule

//4 bit Carry select Adder test bench

module test_csa;
// Inputs
reg [3:0] a;
reg [3:0] b;
regcin;
// Outputs
wire [3:0] sum;
wire co;

// Instantiate the Unit Under Test (UUT)

carry_selectuut (.a(a), .b(b), .cin(cin), .sum(sum), .co(co));
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
#100;

a = 4'd5;
b = 4'd10;
cin = 0;
#100;

a = 4'd5;
b = 4'd10;
cin = 1;
#100;

a = 4'd15;
b = 4'd10;
cin = 0;
#100;

a = 4'd15;
b = 4'd11;
cin = 1;
#100;

// Add stimulus here

end
endmodule

Ex.No:4(a) BOOTH MULTIPLIER

Booth's multiplication algorithm is an algorithm which multiplies 2 signed

integers in 2's complement. The algorithm is depicted in the following figure
with a brief description. This approach uses fewer additions and
subtractions than more straightforward algorithms.

//8 bit booth multiplier verilog

module multiplier(prod, busy, mc, mp, clk, start);
output [15:0] prod;
output busy;
input [7:0] mc, mp;
input clk, start;
reg [7:0] A, Q, M;
reg Q_1;
reg [3:0] count;

wire [7:0] sum, difference;

always @(posedgeclk)
begin
if (start) begin
A <= 8'b0;
M <= mc;
Q <= mp;
Q_1 <= 1'b0;
count <= 4'b0;
end
else begin
case ({Q[0], Q_1})
2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};
2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};
default: {A, Q, Q_1} <= {A[7], A, Q};
endcase
count <= count + 1'b1;
end
end

alu adder (sum, A, M, 1'b0);

alusubtracter (difference, A, ~M, 1'b1);

assign prod = {A, Q};

assign busy = (count < 8);

endmodule

/*The following is an alu. It is an adder, but capable of subtraction:Recall

that subtraction means adding the two's complement--
a - b = a + (-b) = a + (inverted b + 1).The 1 will be coming in as cin (carry-
in)*/
module alu(out, a, b, cin);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;

assign out = a + b + cin;

endmodule

//8 bit booth multiplier verilog: test bench:

module testbench;

regclk, start;
reg [7:0] a, b;

wire [15:0] ab;

wire busy;

multiplier multiplier1(ab, busy, a, b, clk, start);

initial begin
clk = 0;
$display("first example: a = 3 b = 17");
a = 3; b = 17; start = 1; #50 start = 0;
#80 $display("first example done");
$display("second example: a = 7 b = 7");
a = 7; b = 7; start = 1; #50 start = 0;
#80 $display("second example done");
$finish;
end

always #5 clk = !clk;

always @(posedgeclk)

$strobe("ab: %d busy: %d at time=%t", ab, busy, $stime);

Endmodule

Output:

first example: a = 3 b = 17
ab: 17 busy: 1 at time= 5
ab: 17 busy: 1 at time= 15
ab: 17 busy: 1 at time= 25
ab: 17 busy: 1 at time= 35
ab: 17 busy: 1 at time= 45
ab: 65160 busy: 1 at time= 55
ab: 196 busy: 1 at time= 65
ab: 98 busy: 1 at time= 75
ab: 49 busy: 1 at time= 85
ab: 65176 busy: 1 at time= 95
ab: 204 busy: 1 at time= 105
ab: 102 busy: 1 at time= 115
ab: 51 busy: 0 at time= 125
first example done
second example: a = 7 b = 7
ab: 7 busy: 1 at time= 135
ab: 7 busy: 1 at time= 145
ab: 7 busy: 1 at time= 155
ab: 7 busy: 1 at time= 165
ab: 7 busy: 1 at time= 175
ab: 64643 busy: 1 at time= 185
ab: 65089 busy: 1 at time= 195
ab: 65312 busy: 1 at time= 205
ab: 784 busy: 1 at time= 215
ab: 392 busy: 1 at time= 225
ab: 196 busy: 1 at time= 235
ab: 98 busy: 1 at time= 245
ab: 49 busy: 0 at time= 255
second example done
Ex.No:4(b) SIGNED BOOTH MULTIPLIER

//4 bit signed booth multiplier verilog:

module BoothMulti(X, Y, Z);

input signed [3:0] X, Y;

output signed [7:0] Z;
reg signed [7:0] Z;
reg [1:0] temp;
integer i;
reg E1;
reg [3:0] Y1;
always @ (X, Y)
begin
Z = 8'd0;
E1 = 1'd0;
for (i = 0; i < 4; i = i + 1)
begin
temp = {X[i], E1};
Y1 = - Y;
case (temp)
2'd2 : Z [7 : 4] = Z [7 : 4] + Y1;
2'd1 : Z [7 : 4] = Z [7 : 4] + Y;
default : begin end
endcase
Z = Z >> 1;

Z[7] = Z[6];

E1 = X[i];
end
if (Y == 4'd8)

begin
Z = - Z;
 end

end

endmodule

//Booth multiplier Testbench code:

module BoothTB;

// Inputs
reg [3:0] X;
reg [3:0] Y;

// Outputs
wire [7:0] Z;

// Instantiate the Unit Under Test (UUT)

BoothMultiuut (
.X(X),
.Y(Y),
.Z(Z)
);

initial begin
// Initialize Inputs
X = 0;
Y = 0;

// Wait 100 ns for global reset to finish

#100;
X=-5;
Y=7;
// Add stimulus here

end

endmodule
Ex.No:5 WALLACE TREE MULTIPLIER
//4 bit Wallace tree multiplier verilog:
//Half Adder Code:

module half_add( input a, input b, output s, output c );

assign s = a ^ b;
assign c = a & b;
endmodule

//Full Adder Code:

module full_add( input a, input b, input ci, output s, output co );

assign s = (a ^ b) ^ ci;
assign co = (a & b) ^ (ci & (a ^ b));
endmodule

//Wallace 4 bit multiplier verilog Code:

module wallace4(input [3:0] A, input [3:0] B, output [7:0] P);

integer i;
wire s11,s12,s13,s14,s15,s22,s23,s24,s25,s26,s32,s34,s35,s36,s37;
wire c11,c12,c13,c14,c15,c22,c23,c24,c25,c26,c32,c34,c35,c36,c37;
reg [3:0] pp0,pp1,pp2,pp3 ;
//Calculation of Partial Product
always @(A or B)
begin
for(i=0;i<4;i=i+1) begin
pp0[i] <= A[i] & B[0];
pp1[i] <= A[i] & B[1];
pp2[i] <= A[i] & B[2];
pp3[i] <= A[i] & B[3];
end
end

assign P[0] = pp0[0];

assign P[1] = s11;
assign P[2] = s22;
assign P[3] = s32;
assign P[4] = s34;
assign P[5] = s35;
assign P[6] = s36;
assign P[7] = s37;

//first stage
half_add ha11 (pp0[1],pp1[0],s11,c11);
full_add fa12 (pp0[2],pp1[1],pp2[0],s12,c12);
full_add fa13 (pp0[3],pp1[2],pp2[1],s13,c13);
full_add fa14 (pp1[3],pp2[2],pp3[1],s14,c14);
half_add ha15 (pp2[3],pp3[2],s15,c15);

//second stage
half_add ha21 (c11,s12,s22,c22);
full_add fa22 (pp3[0],c12,s13,s23,c23);
full_add fa23 (c13,c23,s14,s24,c24);
full_add fa24 (c14,c24,s15,s25,c25);
full_add fa25 (c15,c25,pp3[3],s26,c26);

//third stage
half_add ha31 (c22,s23,s32,c32);
half_add ha32 (c32,s24,s34,c34);
half_add ha33 (c34,s25,s35,c35);
half_add ha34 (c35,s26,s36,c36);
half_add ha35 (c36,c26,s37,c37);
endmodule

//wallace tree multiplier Testbench code:

module tb;
// Inputs
reg [3:0] A;
reg [3:0] B;
// Outputs
 wire [7:0] P;
integer i,j,error;

// Instantiate the Unit Under Test (UUT)

wallaceuut (.A(A), .B(B), .P(P));
initial begin
// Apply inputs for the whole range of A and B.16*16 = 256 inputs.
error = 0;
for(i=0;i <=15;i = i+1)
for(j=0;j <=15;j = j+1)
begin
A <= i;
B <= j;
#1;
if(P != A*B) //if the result isnt correct increment "error".
error = error + 1;
end
end
endmodule

Ex.No:6(a) RS – FlipFlop
 Block Diagram:- Truth Table:-

//RS Flip Flop Verilog code:

module rsflip(rs, clock, q, qb);

input [1:0] rs;
input clock;
output reg q, qb;
always @ (posedge clock)
begin
case (rs)
2'b00 : q = q ;
2'b01 : q = 1'b1 ;
2'b10 : q = 1'b0 ;
2'b11 : q = 1'dZ ;
endcase
qb =~ q;
end
endmodule

//RS Flip Flop Verilog testbench code:

module rsflip_tb();
// Inputs
reg [1:0] rs; reg clock;

// Outputs
wire q; wire qb;

// Instantiate the Unit Under Test (UUT)

rsflipuut ( .rs(rs), .clock(clock), .q(q), .qb(qb) );

initial
clock=1'b1;
always #5 clock=~clock;
initial
begin
rs=2'b00;
#20;
rs =2'b01;
#20;
rs =2'b10;
 #20;
rs =2'b11;
#50;
end
initial
$monitor ($time, "rs=%b q=%b qb=%b ", rs, q, qb);
endmodule

Ex.No:6(b) D – FlipFlop

Circuit Diagram

Block Diagram:- Truth Table:-

//D Flip Flop Verilog code:

module dflip(reset, clock, d, q, qb);

input reset, clock, d;
output q, qb;
reg q;
wire qb;
always @ (posedge clock)
begin
if (reset)
q<=1'b0;
else
q<=d;
end
assign qb=~q;
endmodule

//D Flip Flop Verilog TestBench code:

module dflip_tb();
reg reset;
reg clock;
reg d;
wire q;
wire qb;

dflip uut(.reset(reset),.clock(clock),.d(d),.q(q),.qb(qb));
initial begin
clock=1'b1;
reset=1'b0;
end
always #5 clock=~clock;
always #40 reset=~reset;

initial
begin
#20 d =1'b1;
#20 d =1'b0;
#30 d =1'b1;
#30 d =1'b0;
end

initial
begin
$monitor ($time, "reset=%b clock=%b d=%b q=%b qb=%b", reset, clock, d,
q, qb);
end
endmodule
Ex.No:6(c) JK – Flip Flop

Circuit Diagram

Block Diagram:- Truth Table:-

//JK Flip Flop Verilog code:

module jkflip(JK, clock, q, qb);

input [1:0] JK;
input clock;
output reg q, qb;
always @ (posedge clock)
begin
case (JK)
2'b00 : q = q;
2'b01 : q = 1'b0;
2'b10 : q = 1'b1;
2'b11 : q =~ q;
endcase
qb =~ q;
end
endmodule

//JK Flip Flop Verilog Testbench code:

module jkflip_tb();
reg [1:0] JK;
reg clock;
wire q;
wire qb;
jkflip uut (.JK(JK),.clock(clock), .q(q), .qb(qb));
initial
clock=1'b1;
always #5 clock=~clock;
initial
begin
 JK=2'b00; #20;
JK=2'b01; #20;
JK=2'b10; #20;
JK=2'b11; #50;
end
initial
$monitor ($time, "JK=%b q=%b qb=%b ", JK, q, qb);
endmodule

Ex.No:7(a) 4-BIT BINARY RIPPLE COUNTER

Function Table

Output(count 0-15)

A B C D

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1
 1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

//4 bit binary Ripple Counter verilog code:

module ripplecounter(q,clk,reset);
output [3:0]q;
input clk,reset;
T_FF tff0(q[0],clk,reset);
T_FF tff1(q[1],q[0],reset);
T_FF tff2(q[2],q[1],reset);
T_FF tff3(q[3],q[2],reset);
endmodule
module T_FF(q,clk,reset);
output q;
input clk,reset;
wire d;
D_FF dff0(q,d,clk,reset);
not n1(d,q);
endmodule

module D_FF(q,d,clk,reset);
output q;
input d,clk,reset;
reg q;
always@(posedge reset or negedgeclk)
if(reset)
q=1'b0;
else
q=d;
endmodule

//4 bit binary Ripple Counter verilog testbench code:

module ripplecounter_tb();
regclk;
reg reset;
wire [3:0] q;
ripplecounter UUT(q,clk,reset);
initial clk=1'b0;
always
#5 clk=~clk;
initial begin
reset=1'b1;
#15 reset=1'b0;
#180 reset=1'b1;
#10 reset=1'b0;
end
initial
$monitor($time,"output q= %d",q);
endmodule

Ex.No:7(b) JOHNSON COUNTER

 outputs

Vcc QA QB QC QD CLK1

14 13 12 11 10 9 8

74LS95

1 2 3 4 5 6 7

A B C D

A1A

2 1

//Johnson Counter verilog code:

module johnsoncounter(rst,clk,q);
input rst,clk;
output[3:0]q;
reg[3:0]q;
always@(negedgerst or posedgeclk)
if(!rst)
q<=0;
else
q<={{q[2:0]},{~q[3]}};
endmodule

//Johnson Counter Verilog testbench code:

module johnsoncounter_tb();
regrst;
regclk;
wire [3:0] q;
johnsoncounter uut (.rst(rst), .clk(clk), .q(q));
initial
begin
rst = 0;
clk = 0;
#10;
#10 rst=1;
#5 clk=1;
#5 clk=0; #5 clk=1; #5 clk=0;
#5 clk=1; #5 clk=0; #5 clk=1;
#5 clk=0; #5 clk=1; #5 clk=0;
#5 clk=1; #5 clk=0; #5 clk=1;
 #5 clk=0; #5 clk=1; #5 clk=0;
#5 $stop;
end
endmodule

Ex.No:7(c) UP DOWN COUNTER

Count Table

Output(count Output(count up)

down)

Q0 Q1 Q2 Q3 Q1 Q2 Q3
Q0

1 1 1 1 0 0 0 0

1 1 1 0 0 0 0 1

1 1 0 1 0 0 1 0

1 1 0 0 0 0 1 1

1 0 1 1 0 1 0 0

1 0 1 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 0 0 0 1 1 1

0 1 1 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 0 1 1 0 1 0

0 1 0 0 1 0 1 1

0 0 1 1 1 1 0 0
0 0 1 0 1 1 0 1

0 0 0 1 1 1 1 0

0 0 0 0 1 1 1 1

//4 bit binary UpDown Counter verilog code:

module updowncounter(clk, clear, updown, q);

input clk;
input clear;
input updown;
output [3:0] q;
reg [3:0] q;
always@(posedge clear or posedgeclk)
begin
 if(clear)
q <=4'b0000;
else if(updown)
q <= q+1'b1;
else
q <= q-1'b1;
end
endmodule

//4 bit binary UpDown Counter verilogtestbench code:

module updowncounter_tb();
regclk;
reg clear;
regupdown;
wire [3:0] q;
updowncounter uut(.clk(clk),.clear(clear),.updown(updown),.q(q));
initial
begin
clk = 0;
clear = 0;
updown = 0;
#5 clear=1'b1;
#5 clear=1'b0;
#5 updown=1'b1;
 #170 updown = 0;
end
always #5 clk=~clk;
initial
#400 $stop;
endmodule

Ex.No:8(a) DECODER

A decoder is a device which does the reverse operation of

an encoder, undoing the encoding so that the original information can be
retrieved. The same method used to encode is usually just reversed in
order to decode. It is a combinational circuit that converts binary
information from n input lines to a maximum of 2n unique output lines.
Function Table

Input Output

C B A D7 D6 D5 D4 D3 D2 D1 D0

x x x 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0
Block Diagram 3-8 Decoder

A0
Z6
A1
A2 Z5
Z4
Z3
Z2
3 to 8 decoder Z1
Enable
Z0

Circuit Diagram 3-8 Decoder

//3 to 8 decoder Verilog code:

module decoder3to8(Data_in,Data_out);
input [2:0] Data_in;
output [7:0] Data_out;
reg [7:0] Data_out;
always @(Data_in)
case (Data_in) //case statement. Check all the 8 combinations.
3'b000 : Data_out = 8'b00000001;
3'b001 : Data_out = 8'b00000010;
3'b010 : Data_out = 8'b00000100;
3'b011 : Data_out = 8'b00001000;
3'b100 : Data_out = 8'b00010000;
3'b101 : Data_out = 8'b00100000;
3'b110 : Data_out = 8'b01000000;
3'b111 : Data_out = 8'b10000000;
default : Data_out = 8'b00000000;
endcase
endmodule

//3 to 8 decoder Verilog testbench code:

module decoder3to8_tb();
reg [2:0] Data_in;
wire [7:0] Data_out;
decoder3to8 uut(.Data_in(Data_in),.Data_out(Data_out));

initial begin
Data_in = 3'b000; #100;
Data_in = 3'b001; #100;
Data_in = 3'b010; #100;
 Data_in = 3'b011; #100;
Data_in = 3'b100; #100;
Data_in = 3'b101; #100;
Data_in = 3'b110; #100;
Data_in = 3'b111; #100;
end
endmodule

Ex.No:8(b) ENCODER

Input Output
D0 D1 D2 D3 D4 D5 D6 D7 C B A
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

Block Diagram 8:3 encoder

Z7
A0
Z6

Z5 A1

Z4
Z3 A2
Z2
Z1
8 to 3 encoder
Z0
//8 to 3 encoder Verilog code:

module encoder8to3(d, a, b, c);

input [0:7] d;
output a;
output b;
output c;
or(a,d[4],d[5],d[6],d[7]);
or(b,d[3],d[2],d[6],d[7]);
or(c,d[1],d[3],d[5],d[7]);
endmodule

//8 to 3 encoder Verilog testbench code:

module encoder8to3_tb();
reg [0:7] d;
wire a;
wire b;
wire c;
encoder8to3 uut (.d(d),.a(a),.b(b),.c(c));
initial begin
#10 d=8'b10000000;
#10 d=8'b01000000;
#10 d=8'b00100000;
#10 d=8'b00010000;
#10 d=8'b00001000;
#10 d=8'b00000100;
#10 d=8'b00000010;
#10 d=8'b00000001;
#10$stop;
end
endmodule

Ex.No:9 MULTIPLEXER

In electronics, a multiplexer (or mux) is a device that selects one of

several analog or digital input signals and forwards the selected input into a
single line. A multiplexer of 2n inputs has n select lines, which are used to
select which input line to send to the output. Multiplexers are mainly used
to increase the amount of data that can be sent over the network within a
certain amount of time and bandwidth. A multiplexer is also called a data
selector.

DEMULTIPLEXER

Data Select
Outputs
Input Inputs
D X Y Z h G F e d C b A
D 0 0 0 0 0 0 0 0 0 0 D
D 0 0 1 0 0 0 0 0 0 D 0
D 0 1 0 0 0 0 0 0 D 0 0
D 0 1 1 0 0 0 0 D 0 0 0
D 1 0 0 0 0 0 D 0 0 0 0
D 1 0 1 0 0 D 0 0 0 0 0
D 1 1 0 0 D 0 0 0 0 0 0
D 1 1 1 D 0 0 0 0 0 0 0
//1:8 Demultiplexer Verilog code:

module demultiplexer1to8(din,x,y,z,a,b,c,d,e,f,g,h);
output a,b,c,d,e,f,g,h;
input din,x,y,z;
assign a=din&(~x)&(~y)&(~z);
assign b=din&(~x)&(~y)&(z);
assign c=din&(~x)&(y)&(~z);
assign d=din&(~x)&(y)&(z);
assign e=din&(x)&(~y)&(~z);
assign f=din&(x)&(~y)&(z);
assign g=din&(x)&(y)&(~z);
assign h=din&(x)&(y)&(z);
endmodule

//1:8 demultiplexer Verilog testbench code:

module demultiplexer1to8_tb();
regdin;regx;regy;reg z;
wire a;wireb;wirec;wired;wiree;wiref;wireg;wire h;
demultiplexer1to8 uut (.din(din),.x(x),.y(y),.z(z),.a(a),
.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h));
initial begin
 din = 0;x = 0;y = 0;z = 0;#100;
din = 1;x = 0;y = 0;z= 0;#100;
din =1;x = 0;y = 0;z= 1;#100;
din = 1;x = 0;y = 1;z=0;#100;
din = 1;x = 0;y = 1;z=1;#100;
din = 1;x = 1;y = 0;z=0;#100;
din = 1;x = 1;y = 0;z=1;#100;
din = 1;x = 1;y = 1;z=0;#100;
din = 1;x = 1;y = 1;z=1;
end
endmodule