Efficient Wall Adapter

A Major Qualifying Project Report

Submitted to the Faculty
of the

WORCESTER POLYTECHNIC INSTITUTE

in partial fulfillment of the requirements for the

Degree of Bachelor of Science
in
Electrical and Computer Engineering
by

__________________________
Brendan D. Barschdorf

__________________________
Russell R. Kernan

Project Number: JKM-3A07

Date: 3/10/2008

Sponsoring Organization:
NECAMSID

Project Advisors:

____________________________
Professor John McNeill, Major Advisor

____________________________
Professor Alexander Wyglinski, Co-Advisor
Abstract
 
 
This  report  presents  a  design  for  an  efficient  AC  adapter  that  uses  85%  less  power  than 
conventional adapters when idle, for an additional  cost of only $1.21.  The design exceeds the team’s 
initial targets of 75% increased power efficiency at a cost of $1.30.  The team logically derived the final 
polling  design  from  three  initially  proposed  solutions.    This  project  addresses  the  inefficiencies  of 
modern AC adapters, whose increased utilization has become an increasing detriment to both economy 
and environment. 

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Acknowledgements

We would like to acknowledge the many people and organizations that made this project possible:

New England Center for Analog and Mixed-Signal IC Design

Allegro Microsystems
Analog Devices
BAE Systems
Texas Instruments

Worcester Polytechnic Institute 

Professor John A. McNeill
Professor Alexander M. Wyglinski
Tom Angelotti

Component Samples
Coilcraft A9619-C Flyback Transformer
RFB0807-102L EMI Inductor
ON Semiconductor NCP1011 Monolithic Switcher
Vishay SFH-615A-4 Optocoupler

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Executive Summary
The world today faces many challenges regarding the use of energy and its conservation since 
the shortage of fossil fuels is becoming an increasing reality.  As mobile devices have woven themselves 
into the fabric of society, the collective energy wasted in powering handheld electronics has become a 
global issue.  Most of the energy wasted while charging a mobile device occurs within the charger, which 
is also known as an AC adapter.   
  AC  adapters  are  devices  that  transform  high‐voltage,  alternating  current  energy  from  a  wall 
socket into a low‐voltage, direct current form that is usable for several appliances at home and in the 
office.  Larger appliances, such as television sets, dishwashers, and refrigerators are designed with this 
device internally.  Small electronics, such as mobile communication devices and compact appliances, are 
designed to use external adapters to minimize product size and allow for mobility.  Adapters alone have 
evolved greatly throughout their existence.  Original, linear designs of an adapter were highly inefficient 
with regards to power consumption.  Therefore, most modern adapters utilize a switching application to 
transform the high voltage with a high frequency to the DC output.  Switch‐mode power supplies (SMPS) 
are able to use smaller transformers for power conversion as a result.  Moreover, smaller transformers 
operate at a higher efficiency than linear transformers. 
  While  much  progress  has  been  made  to  improve  the  design  and  efficiency  of  modern  power 
adapters,  one  critical  drawback  remains  inherent  within  the  circuit.    Normally,  mobile  devices  are 
connected to adapters for only a matter hours before they are disconnected.  When a mobile device is 
disconnected  from  the  charger,  it  may  be  assumed  that  the  adapter  deactivates  itself  until  later  use.  
However, this is not the true behavior of an AC adapter.  In reality, the adapter remains active, supplying 
power to most of the circuit.  Although smaller, high‐efficiency transformers are being used in modern 
adapters,  they  continuously  consume  a  majority  of  the  power  when  no  devices  are  connected  to  the 
adapter.    Unless  an  adapter  is  disconnected  from  the  wall  socket,  internal  components  draw  and 
dissipate power. 
  On  an  individual  adapter  basis,  the  amount  of  energy  wasted  per  year  is  negligible  ($0.64  of 
energy per year).  However, there are hundreds of millions of adapters in use today, mainly attributed to 
the increase of cell phones and PDAs across the globe.  In effect, millions of dollars are spent on wasted 
energy every year.  Therefore, a demand exists for an efficient  wall adapter that limits the amount of 

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energy wasted during no‐load conditions.  The large‐scale incorporation of such a device would benefit 
the planet both economically and environmentally. 
  This  project  focuses  on  improving  the  design  of  the  modern  adapter  in  order  to  create  an 
efficient  model.    In  the  early  stages  of  the  product,  a  list  of  specifications  was  created  for  the  new 
efficient AC adapter to follow in order to be a viable alternative: 
• Negligible increase in adapter sizes  with little additional circuitry 
• A  target energy efficiency improvement of 75% 
• Additional cost to consumer no greater than two‐year cost for wasted energy (i.e., $1.30) 
• Fully‐integrated solution (not to be marketed as separate device) 
  After  performing  research  on  the  product’s  prospective  demand  on  the  market,  the  team 
researched existing adapter designs.  Once an adapter model had been chosen from ON Semiconductor, 
the team designed a test bed according to the model's specifications.   Next, three possible approaches 
to  designing  an  efficient  wall  adapter  were  formulated:    Polling  Timer,  Jump  Start,  and  Hijack.    After 
further review, the team decided that neither the Jump Start idea nor the Hijack idea would be pursued 
as a general design approach for the project.  The Polling Timer involves the use of timing circuitry to 
periodically re‐enable adapter functionality during standby conditions so the system may check for the 
presence of a load.  A high‐level functional diagram of the Polling Timer is shown in Figure ES‐1. 
 

 
Figure ES‐1: Polling Timer Functional Diagram 
5 

 
  
The  low‐current  detection  measures  the  output  current  level  while  the  adapter  is  activated.  
Accordingly,  the  timer  triggers  the  interrupt  switch  to  disconnect  the  input  of  the  adapter  from  the 
transformer.   
  Within  this  approach,  the  team  developed  two  methods  to  achieve  a  polling  function  in  the 
circuit: 555 timer and a capacitor.  The capacitive‐polling technique was investigated, but was deemed 
too expensive as well as inefficient.  Therefore, the team began to implement a 555‐based polling timer. 
Once  a  working  design  was  achieved,  the  team  collected  power  measurements  to  compare  the  new 
design  with  the  original  adapter  test  bed.    While  only  marginally  increasing  power  during  charging 
mode, the efficient adapter design improved standby power consumption by 85% for an additional cost 
of $1.21.  Since the solution is also compact in size and fully‐integrated into the original adapter, all the 
necessary design requirements were met for the project.   
  In  future  efforts  to  improve  adapter  design,  the  team  hopes  that  one  not  only  improves  the 
efficiency of the proposed adapter, but also makes it more cost effective.   It is critical that the additional 
cost to the consumer be as small as possible in order to encourage either separate purchase or to entice 
electronic  manufacturers  to  include  an  efficient  adapter  design  in  their  chargers.      On  another  note, 
future teams should further investigate the possibility of passive polling using a storage component such 
as  an  inductor  or  capacitor.    If  passive  polling  can  be  realized,  it  would  further  decrease  the  standby 
power  consumption  over  time,  since  no  active  devices  would  be  in  use.    However,  the  team's  overall 
hopes  are  to  further  increase  the  awareness  of  wasted  energy  in  electronic  devices’  standby  power 
consumption,  so  the  world  can  pursue  alternative  fuel  sources  and  mitigate  its  dependency  on  fossil 
fuels. 
  The outcome of this project is an efficient wall adapter that meets the following specifications: 
• 85% reduction of standby power consumption over original design 
• $1.21 additional component cost which fell within the project's budget of $1.30 
Fully‐integrated, compact design that negligibly affects spatial dimensions of adapter 

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Table of Contents
 

1 Introduction 14
1.1 The Problem 15
1.2 The Economics 16
1.3 Specification Goals 18
2 The Modern Power Adapter 22
2.1 Switch-Mode Supply Development 22
2.2 Specific Example 25
2.3 Simulation 28
2.4 Test Bed 39
2.5 Measured Waveforms of Test Bed 52
3 Approach 69
3.1 Initial Proposals 69
3.2 Evaluation 76
3.3 Consolidation 89
4 Detailed Design 96
4.1 Low-Current Sensing Circuit 96
4.2 Adapter Cutoff and Reactivation Circuit 105
5 Results 120
5.1 Capacitive Polling 120
5.2 555 Timer Polling 124
6 Future Work 137
7 Conclusion 145

References 147
Appendix A – Final Schematic and Parts List 152
Appendix B – Common Mode Effect Derivation 155
Appendix C – PSpice Simulation Code 160
Appendix D – Related Patent 166
Appendix E – Datasheets 175

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Table of Figures
Figure ES‐1: Polling Timer Functional Diagram .......................................................................................................................................................... 5 
Figure 1‐1: Wireless Subscribers in United States in the years 1995, 2000, 2005, and 2006 [11]. .......................................................................... 16 
Figure 1‐2: Energy Consumption Breakdown in the United States for 2005 [13]. ................................................................................................... 17 
Figure 1‐3: Adapter output current (left) and the current‐sensing logic output voltage (right) versus time.  The load is disconnected from adapter 
at tDISCONNECT, causing the output current to drop, and the current‐sensing alert to rise. ......................................................................................... 21 
Figure 2‐1: Shown is a top‐level diagram of a linear power supply.  The input, with series resistance, is directly connected to the primary winding 
of the transformer.  The transformer attenuates the input voltage to a low‐amplitude voltage on its secondary winding.  Finally, the output 
rectifier with capacitive peak detection converts the AC signal into the DC output. .............................................................................................. 23 
Figure 2‐2: Functional diagram of a Flyback converter, representing the 5 principle qualities of modern power adapters; input rectification, high 
speed switching, step‐down transforming, output rectification, and built‐in overload current sensing [26]. ......................................................... 24 
Figure 2‐3: Efficient, Low Cost, Low Standby Power (<100mW), 2.5W Cell Phone Charger from ON Semiconductor Design Note DN06017/D [27].
 ................................................................................................................................................................................................................................ 25 
Figure 2‐4: The simplified block diagram of the NCP1011’s functionality portrays each of the three operating conditions.  During normal 
operation, the power MOSFET driver is controlled by a flip‐flop coupled with the 100‐kHz clock, periodically reset by the VCC capacitor when the 
voltage at pin 1 equals VOVERLOAD.  If pin 4 is grounded, signifying a high‐current output condition, the Flip‐Flop is reset.  Lastly, the chip operates 
in latch‐off mode when the charge/discharge cycle of CVCC is extended during no‐load conditions [28]. ............................................................... 27 
Figure 2‐5: Schematic of adapter test bed from Figure 2‐3; netlist used to perform PSpice simulation on entire system. ..................................... 29 
Figure 2‐6: PSpice simulation results; output voltage of adapter versus time, prior to activation of switching IC.  Output voltage increases 
linearly by 3µV, likely as a result of energy transferred by the input rectifier ripple through the transformer. ...................................................... 30 
Figure 2‐7: PSpice simulation results; input voltage at primary winding and Vcc pin on switching IC versus time, prior to activation of switching 
IC.  Primary winding voltage remains close to rectified mains voltage, while the IC’s power capacitor charges toward its activation trigger of 
8.5V. ........................................................................................................................................................................................................................ 30 
Figure 2‐8: PSpice simulation results; voltage at Vcc pin on switching IC versus time.  Voltage hits its activation trigger of 8.5V and begins 
oscillations.  The VCC pin is located on pin 1 of the NCP1011 block diagram. .......................................................................................................... 31 
Figure 2‐9: PSpice simulation results; output voltage of NCP1011 versus time.  Switching begins when the voltage at the Vcc pin reaches 8.5V 
(Figure 2‐8).  The output of the NCP1011 is equivalent to pin 5 on the block diagram. .......................................................................................... 32 
Figure 2‐10: PSpice simulation results; voltage outputted by switching IC versus time.  Same as Figure 2‐9, but with a smaller time scale to show 
IC’s oscillation pattern.  The output of the NCP1011 is equivalent to pin 5 on the block diagram. ......................................................................... 32 
Figure 2‐11: PSpice simulation results; voltage at the DC output of the adapter versus time.  Again, switching IC activates at 17.2ms, causing the 
output to increase toward its eventual 5V level. ..................................................................................................................................................... 33 
Figure 2‐12: Simplified schematic of adapter test bed from Figure 2‐3 used for netlist of simplified system, which was created for faster 
simulation runtimes. ............................................................................................................................................................................................... 34 
Figure 2‐13: PSpice (simplified) simulation results; mains input voltage and rectified mains voltage versus time.  Input voltage is rectified before 
being switched to 100kHz by switching IC. .............................................................................................................................................................. 35 
Figure 2‐14: PSpice simulation results; voltage at the DC output of the simplified adapter versus time.  Voltage converges at 6V DC within half of 
a second. ................................................................................................................................................................................................................. 35 
Figure 2‐15: PSpice simulation results; voltage at the DC output of the simplified adapter versus time.  Output filter capacitors were simulated 
with an initial condition of 1V, to shorten the time required to observe 5V at the output of the adapter. ............................................................ 36 
Figure 2‐16: PSpice transformer models, original noisy model (right) was replaced with an improved magnetically coupled model (left) [30]. ... 38 
Figure 2‐17: PSpice (simplified) simulation results; voltage at the DC output of the adapter versus time.  This noise is likely the result of the 
simulation model of the circuit’s transformer having an exaggerated reaction to the high speed switching of the IC. .......................................... 38 
Figure 2‐18: Rendition of isolated circuit hazard; floating circuits will readily seek an introduced ground, such as a human being in close 
proximity [33]. ......................................................................................................................................................................................................... 42 
Figure 2‐19: Input rectifier of test bed, circuit diagram (top) and soldered circuit (bottom). ................................................................................. 43 

8 

 
Figure 2‐20:  Input test wave from function generator; 10V sinusoid. .................................................................................................................... 44 
Figure 2‐21: Rectifier/filter stage output resulting from application of input test wave in Figure 2‐20; 10VDC. ...................................................... 44 
Figure 2‐22: Magnification of rectifier/filter stage output from Figure 2‐21.  The lack of visible ripple demonstrates the functionality of the tank 
filter comprised of capacitors C1 and C2 and inductor L1. ...................................................................................................................................... 45 
Figure 2‐23: AC side of test bed, circuit diagram (top) and soldered circuit (bottom), (11/20/2007). .................................................................... 46 
Figure 2‐24: Diagram depicting the delivery of AC power, from the utility transformer to the outlet and the eventual device’s interface with it.  
Note that line is represented as a white wire while neutral is black [34]. ............................................................................................................... 47 
Figure 2‐25:  Top view of first prototype of adapter test bed implemented on perfboards (11/21/2007).  Major circuit stages are labeled with 
arrows and descriptions. ......................................................................................................................................................................................... 48 
Figure 2‐26: Bottom view of the first prototype of the adapter test bed implemented on perfboards (11/21/2007).  Connections between both 
perfboards have been labeled with arrows and descriptions in addition to input and output connections. .......................................................... 49 
Figure 2‐27: 5.6V DC output of first adapter prototype. ......................................................................................................................................... 49 
Figure 2‐28: Close‐up probe capture of noise observed at the DC output of the first test bed implementation.  The level of noise varies slightly 
relative to the DC bias, so the effect of these oscillations on the battery load is negligible. ................................................................................... 50 
Figure 2‐29: First revision of adapter PCB design (11/29/2007).  Green traces represent top‐level copper connections while red traces represent 
bottom copper connections.  The top silkscreen is shown as light blue to outline component footprints and pin holes.  The bottom copper area 
on the AC portion of the PCB is connected to AC ground via a jumper [27]. ........................................................................................................... 51 
Figure 2‐30: Test bed schematic from ON Semiconductor’s DN06017/D Design Note. .......................................................................................... 53 
Figure 2‐31: Oscilloscope capture of DC output voltage with 200Ω load using the first test bed implementation.  The mean voltage was observed 
to be slightly above 5V. ........................................................................................................................................................................................... 53 
Figure 2‐32: IC output with 200Ω load (left), Voltage across primary winding with 200Ω load (right) using first test bed implementation. .......... 54 
Figure 2‐33: The simplified block diagram of the NCP1011.  Pin 1 is the VCC pin, and pins 3, 7, and 8 are connected to AC ground.  Pin 4 is the 
feedback pin from optocoupler U2 and pin 5 is the output of the switcher.  Pins 2 and 6 are not connected, and are therefore absent from the 
diagram [28]. ........................................................................................................................................................................................................... 55 
Figure 2‐34: The left waveform shows the voltage on the NCP1011’s Vcc pin with 200Ω load, while the right waveform shows a 10X 
magnification of the left waveform using the first implementation of the test bed. .............................................................................................. 56 
Figure 2‐35: IC output with 200Ω load (left), no load (right) using first test bed implementation. ......................................................................... 56 
Figure 2‐36: IC output with 200Ω load (left), shorted load (right) using the first test bed implementation. ........................................................... 57 
Figure 2‐37: Using the first test bed implementation, IC output is shown with pin 4 of the NCP1011 shorted to AC ground, simulating a high‐
current condition.  Switching behavior is completely ceased under this condition. ................................................................................................ 58 
Figure 2‐38: Using the first test bed implementation, IC output is shown with 587mA flowing through the current‐sensing resistor R4, simulating 
a high‐current condition.  Switching behavior is completely ceased under this condition. ..................................................................................... 58 
Figure 2‐39: Voltage across C4, 50mA load (left), open (no) load (right) using first test bed implementation. ....................................................... 59 
Figure 2‐40: Initial input power measurement setup for adapter test bed.  The ammeter is placed in series, separating the live, 120VRMS input 
from the adapter input. ........................................................................................................................................................................................... 60 
Figure 2‐41: Example of a typical rectifier with smoothing capacitor, and its output waveform.  Current is only drawn during the periods in 
which the capacitor’s voltage is charging, so the current waveform will not be sinusoidal [35]. ............................................................................ 61 
Figure 2‐42: The second arrangement used in test bed power measurements.  Input voltage is measured by scope A, while a voltage directly 
related to the input current is measured by probe B. ............................................................................................................................................. 61 
Figure 2‐43: Test setup for measuring the power efficiency of the original test bed configuration. ....................................................................... 62 
Figure 2‐44: Configuration of oscilloscope probes for input current measurement of initial adapter test bed. ..................................................... 62 
Figure 2‐45: Oscilloscope capture of input power measurement using 1Ω sensing resistor (left) for the initial adapter test bed.  The adapter is 
connected to AC power via a surge protector.  The observed noise was attributed to the three‐phase to single‐phase power conversion.  The 
right‐hand signal shows the noise produced while the surge protector is switched off. ......................................................................................... 63 
Figure 2‐46: Efficiency measurement with 100 Ω sensing resistor – 51 Ω load. ...................................................................................................... 64 
Figure 2‐47: Plot of efficiency percentage versus load resistance. .......................................................................................................................... 65 

9 

 
Figure 2‐48: Plot of power drawn by the adapter versus power delivered to output. ............................................................................................ 66 
Figure 2‐49: Original test bed power measurement with 100Ω sensing resistor under a shorted load condition. ................................................. 67 
Figure 2‐50: Original test bed power measurement with 100Ω sensing resistor under a no‐load condition. ......................................................... 67 
Figure 3‐1: Simplified functional diagram of a modern switch mode power supply. .............................................................................................. 69 
Figure 3‐2: Top‐level schematic of Polling Timer implementation.  Using some form of current sensing at the output of the adapter, the Low‐
Current Detection stage alerts the Interrupt Switch, which disconnects the input to the adapter.  The Timing circuitry periodically deactivates 
the Interrupt Switch, allowing the Low‐Current Detection to re‐evaluate the adapter’s current state. ................................................................. 71 
Figure 3‐3: Top‐level schematic of Jump Start implementation.  Using some form of current sensing at the output of the adapter, the Low‐
Current Detection stage alerts the Interrupt Switch, which disconnects the input to the adapter.  The Reverse‐Current Activation deactivates the 
Interrupt Switch using residual power in a reconnected load device. ..................................................................................................................... 73 
Figure 3‐4: Top‐level schematic of hijack implementation.  Using some form of current sense at the output of the adapter, the Low‐Current 
Detection stage triggers pre‐existing reduced power state in the switching IC, typically reserved for high‐current protection. ............................ 75 
Figure 3‐5: Active switching IC output (left), low power switching IC output (right).  Note that even in low power mode, there is still a significant 
amount of 100kHz activity produced by the IC.  Since the Hijack idea relies on this mode, it would not be able to reduce power consumption 
much below 300mW. .............................................................................................................................................................................................. 77 
Figure 3‐6: NIST Representation of Hall Effect [37]. ................................................................................................................................................ 78 
Figure 3‐7: Schematic of an ideal transformer [39]. ................................................................................................................................................ 80 
Figure 3‐8: ADM4073 Low Cost, Voltage Output, High‐Side, Current‐Sense Amplifier Internal Schematic [40]. ..................................................... 81 
Figure 3‐9: Current‐sensing amplifier outputs a voltage proportional to the load current [40]. ............................................................................. 83 
Figure 3‐10: Transistor‐Based Current Detection Schematic [27]............................................................................................................................ 84 
Figure 3‐11: First‐order RC circuit. ........................................................................................................................................................................... 89 
Figure 3‐12: Example polling duty cycle of 50% for capacitive‐based polling method. ........................................................................................... 90 
Figure 3‐13: Example polling duty cycle much less than 50% for capacitive‐based polling method. ....................................................................... 91 
Figure 3‐14: Functional block diagram of efficient wall adapter with capacitive‐based polling. ............................................................................. 91 
Figure 3‐15:  Schematic for adapter reactivation.  The TLC555 subcircuit periodically reactivates the P‐Channel MOSFET to re‐enable connection 
between the top voltage rail to the transformer.  The Zener‐based voltage regulator provides the necessary voltage level to the TLC555 
subcircuit. ................................................................................................................................................................................................................ 92 
Figure 3‐16: Example polling cycle of monostable multivibrator [44]. .................................................................................................................... 94 
Figure 3‐17: Schematic showing monostable configuration of the TS555 timer [44]. ............................................................................................. 94 
Figure 3‐18: Functional Block Diagram of Adapter with Monostable Multivibrator Polling. ................................................................................... 95 
Figure 4‐1: Processing diagram for current sense stage of proposed solution, from sensing resistor to flag output. ............................................. 97 
Figure 4‐2: Inverting open loop comparator configuration used in low‐current sensing for proposed solution; used to raise a flag high if sensing 
resistor’s voltage is low, and vice‐versa.  Also sets the cutoff level with VREF. ......................................................................................................... 99 
Figure 4‐3: Theoretical arrangement of inverting comparator and LED of optoisolator.  However, current and voltage limitations must be 
overcome. ............................................................................................................................................................................................................. 100 
Figure 4‐4: Inverting comparator with current amplifier on output to drive LED.  This circuit should light properly and on command. .............. 101 
Figure 4‐5: Preliminary schematic of low‐current sense stage prior to calculation of component values............................................................. 102 
Figure 4‐6: First schematic of low‐current sense stage of proposed solution, with component values. ............................................................... 104 
Figure 4‐7:  Processing diagram for power cutoff stage of proposed solution, including low‐current flag reaction. ............................................ 106 
Figure 4‐8:  PSpice schematic and netlist of Zener‐based voltage converter for supplying power to 555 timer; created to determine the viability 
of using the 170V adapter input to run a low power IC and associated circuitry [50]. .......................................................................................... 109 
Figure 4‐9:  PSpice simulation results; voltage and current plots for Zener‐based voltage converter configuration shown in Figure 4‐8 schematic.  
Circuit appears to function as expected, creating a relatively small voltage drop across the Zener. .................................................................... 109 
Figure 4‐10:  PSpice simulation results; current and power plots for Zener‐based voltage converter configuration shown in Figure 4‐8 schematic.  
Resistor and Zener values may need modification to save power and increase load voltage, but this step‐down application appears to work. . 110 

10 

 
Figure 4‐11: Branching the input path for dual controls would allow for the current‐sensing circuitry to directly control the functionality of the 
adapter while the 555 can still reactivate it from the opposite side of the isolation barrier. ................................................................................ 111 
Figure 4‐12:  First top‐level drawing of the adapter polling circuit layout.  The TLC555 subcircuit periodically activates the P‐Channel MOSFET, 
which impedes the top voltage rail from reaching the transformer’s primary winding.  The Zener‐based voltage regulator supplies the TLC555 
subcircuit with an appropriate voltage. ................................................................................................................................................................. 112 
Figure 4‐13: 555 timer configured for monostable operation; pulse time is determined by RC combination [44]. .............................................. 113 
Figure 4‐14: Final low‐current sensing schematic with added polling capacitor CP.  Capacitor will hold the low‐current flag voltage, keeping the 
adapter deactivated until it discharges. ................................................................................................................................................................ 115 
Figure 4‐15:  Polling capacitor implementation; transistor QP prevents the capacitor from discharging through ground, allowing it to stay 
charged for longer, thereby increasing the time between polls. ........................................................................................................................... 117 
Figure 4‐16:  Adapter cutoff schematic; disconnection circuitry was redesigned to allow an active TRIAC to disable the adapter, which is 
opposite to its foreseen function.  Resistive voltage divider keeps MOSFET’s gate‐source voltage from exceeding component limits, while 
simultaneously keeping TRIAC current below active holding level [51]. ............................................................................................................... 118 
Figure 5‐1: Initial test setup of capacitive‐polling adapter using an external DC source and test LED. ................................................................. 121 
Figure 5‐2: Capacitive polling solution schematic; 10mF capacitor charges when low‐current alert is activated, and holds the TRIAC’s LED on (and 
thereby the adapter off) until it discharges. .......................................................................................................................................................... 122 
Figure 5‐3: Oscilloscope capture of output voltage for capacitive‐based polling timer configuration.  The polling period was limited to around 1s.
 .............................................................................................................................................................................................................................. 123 
Figure 5‐4: Final schematic; adapter with monostable multivibrator timing. ........................................................................................................ 124 
Figure 5‐5: Shown is a close‐up view of the adapter test bed configuration used for 555 timer‐based polling adapter tests.  The red and black 
wires on the right are attached to the DC output and the orange and yellow wires above the DC output are connected across the current‐
sensing resistor R4.  In addition, two more wires were connected across output filter capacitor C4 to provide a 5V supply for low‐current sense 
circuitry.  The purple and leftmost orange wires were attached to the 170VDC rail and AC ground respectively to provide power for the 555 timer 
subcircuit.  The rightmost wire provided the drain of the p‐channel power MOSFET with a connection to the primary winding of the 
transformer. .......................................................................................................................................................................................................... 125 
Figure 5‐6:  Shown is the interconnections between the original adapter test bed and the additional low‐current sensing and polling circuitry.  
The right‐hand breadboard in the figure holds all circuitry for the low‐current sense, while the left‐hand breadboard holds the 555 timer polling 
subcircuit.  The green and yellow wires provide the feedback connection between the TRIAC output of the MOC3023 and the 555 timer.  The 
white and yellow alligator clips were use to connect DC output to a resistive load.  Moreover, oscilloscope probes were connected to the 
alligator clips to measure the DC output voltage during testing. .......................................................................................................................... 126 
Figure 5‐7: Output waveform of adapter; 555 Timer polling intervals are shown to be around 62s. .................................................................... 126 
Figure 5‐8: Power measurement setup; input voltage measured by Scope B, input current related to voltage on Scope B. ................................ 127 
Figure 5‐9: Input voltage (CH2) and amplified Input Current (CH1) waveforms of initial 555 timer‐based polling adapter with 200Ω load. ........ 128 
Figure 5‐10: Noise observed on CH1 when surge protector is switched to off position.  The noise is attributed to three‐phase to single‐phase 
power conversion. ................................................................................................................................................................................................. 128 
Figure 5‐11: Input voltage (CH2) and amplified Input Current (CH1) waveforms of initial 555 timer‐based polling adapter during standby (no 
load). ..................................................................................................................................................................................................................... 129 
Figure 5‐12: Noisy current measurement (left) and true current measurement with noise subtracted (right). ................................................... 130 
Figure 5‐13: Power consumption comparison of modified adapter and original test bed over time.  Load is disconnected after 50 seconds. .... 132 
Figure 5‐14: Plot of power consumption for both the modified and the unmodified adapter versus the inverse of the attached load resistance.
 .............................................................................................................................................................................................................................. 133 
Figure 5‐15:  PCB layout of the 555 timer‐based polling adapter.  Original test bed circuitry is located on the lower half of the PCB while 
additional circuitry such as the low‐current sense and the 555 timer subcircuit are located on the upper half of the board. ............................. 134 
Figure 5‐16: Final schematic; adapter with monostable multivibrator timing. ...................................................................................................... 135 
Figure 6‐1: Basic adapter functionality.  When the adapter is activated, storage device is filled to full capacity with electrical or magnetic energy.  
During this time, the load is charged.  When the load is disconnected, energy is discharged from the storage device until the energy drops below 
a particular threshold.  When this occurs, the adapter is reactivated.  Notice the charge cycle when the adapter is activated and the discharge 
cycle when the adapter is deactivated. ................................................................................................................................................................. 137 

11 

 
Figure 6‐2: The output stage of the power adapter, showing two filter capacitors. ............................................................................................. 138 
Figure 6‐3: Output stage of an adapter.  Rectifier diode is forward biased, capacitor is charging. ....................................................................... 139 
Figure 6‐4: Output stage of an adapter.  Rectifier diode is reverse biased, capacitor is discharging. .................................................................... 139 
Figure 6‐5: Current‐voltage relationship for a capacitor; the voltage across an adapter drops as the integral of the current being drawn from it.  
Therefore, by monitoring how low the capacitor’s voltage gets between recharges, the current that was being drawn from it can be 
determined. .......................................................................................................................................................................................................... 140 
Figure 6‐6: Voltage across adapter’s output capacitor; with 50mA load (left), open load (right).  The discharging voltage drop is relatively very 
small, due to the fast 100 kHz charge‐discharge cycles.  The capacitive voltage drop is further confused by a large overall voltage drop when no 
load is applied and the NCP1011 switcher enters power saving mode. ................................................................................................................ 141 
Figure 6‐7: Schematic of modeled DC output of adapter.  V represents the DC output voltage, and the capacitance C1 represents the total 
capacitance at the output of the adapter. ............................................................................................................................................................. 142 
Figure 6‐8: Segment of the DC output stage of the efficient wall adapter. ........................................................................................................... 143 
Figure 6‐9: Top‐level design of efficient wall adapter with passive polling. .......................................................................................................... 144 

 
 
 
   

12 

 
Table of Tables
Table 2‐1: The final revision of a parts list for the adapter test bed.  To fit the table in this document, the manufacturer part number field has 
been excluded.  The final cost of the adapter assumes that each part in the list is purchased in a bulk of at least 1000.  The table is sorted by the 
total price of each component [27]. ........................................................................................................................................................................ 40 
Table 2‐2: Original Test Bed Adapter ‐ Efficiency Measurements and Calculations................................................................................................. 64 
Table 3‐1: Qualitative Analysis of Current‐Sensing Devices. .................................................................................................................................... 85 
Table 3‐2: Qualitative Analysis on Power Interrupt Devices. ................................................................................................................................... 88 
Table 3‐3: Pin Descriptions of 555 Timer [43]. ........................................................................................................................................................ 93 
Table 4‐1: Input/output characteristic of inverting comparator (Figure 4‐2) for three possible input scenarios.  A flag voltage sufficient to 
activate the disconnect stage should be raised in any of the cases......................................................................................................................... 99 
Table 5‐1:  Initial procedure followed to record polling period of capacitive‐polling adapter. .............................................................................. 121 
Table 5‐2: Input power measurements of the modified and original adapter with 200Ω load. ............................................................................ 130 
Table 5‐3: Input power measurements of the modified and original adapter with no load. ................................................................................. 131 

   

13 

 
 Introduction  1 

  Today’s  world  faces  a  widespread  problem  regarding  the  conservation  of  energy  resources.  
Global warming and the increasing scarcity of fossil fuels have highlighted the importance of this issue 
and  its  impact  on  humanity  [1].    Possible  future  repercussions  of  a  fossil  fuel  shortage  have  lead  to 
initiatives  to  develop  energy‐efficient  cars  and  appliances,  as  well  as  an  increase  in  renewable  energy 
utilization [2]. 
  Many  of  the  items  that  require  energy  from  fossil  fuels  are  modern  necessities  in  society.  
Automobiles  have  become  the  world's  primary  conveyance,  home  appliances  perform  everyday 
household functions, and artificial lights illuminate offices and homes everywhere.  In order to operate 
more efficiently, designers of these products are working constantly to minimize energy consumption of 
electronic  devices.    For  instance,  the  automotive  industry  is  in  the  process  of  designing  cars  that 
consume  less  gasoline  while  idle  [3].    The  U.S.  Government’s  ENERGY  STAR  program  stipulates  low‐
power  specifications  for  a  variety  of  household  appliances  [4].    In  addition,  several  countries  have 
legislation  in  place  to  ban  the  production  and  sale  of  incandescent  light  bulbs,  which  are  notoriously 
inefficient [5]. 
  Appliances in the home rely on electrical energy to perform specific tasks.  Many household and 
office appliances use power adapters to transform high‐voltage electrical energy into a workable form.  
Most  adapters  take  the  standardized  120V  alternating  current  (AC)  voltage  from  a  wall  socket  and 
convert  it  to  a  low,  direct  current  (DC)  voltage.    Larger  appliances  such  as  televisions  and  desktop 
computers have their power adapters located internally within the device.  Smaller electronics, such as 
cell  phones,  utilize  external  power  adapters  to  maintain  compactness  in  design.    Traditionally,  these 
external  adapters  are  called  AC  adapters,  and  serve  a  great  purpose  in  powering  commonly‐used 
devices around the globe.   
  The  market  for  consumer  electronics  is  rapidly  expanding  on  a  world‐wide  scale,  evolving 
toward a seemingly universal goal: portability.  What was once a stereo and record collection has been 
condensed to a handheld MP3 player.  Mainframes and personal computers have proliferated as laptops 
and PDAs.  In the 1980s, AT&T’s primary source of revenue was Plain Old Telephone Service (POTS) and 
their  budget  rivaled  that  of  the  fifth  largest  economy  in  the  world  [6].    Two  decades  later,  cellular 
phones have taken over the communications market with a total of 2.3 billion global subscribers in 2007 

14 

 
and an estimated 3.96 billion by 2011, over half of the world’s population [7].  However, portability of 
electronic devices heavily depends on the need for portable power.  Therefore, the use of AC adapters 
around  the  world  has  grown  significantly  in  the  past  10  years.    According  to  the  United  States 
Environmental Protection Agency, “as many as 1.5 billion power adapters are in use in the United States, 
about five for every American” in 2005 [8].  Each adapter supplies the power that drives the portable 
electronics world we live in today, but also provides an additional byproduct that adversely affects our 
planet. 
 

The Problem 1.1

   
  Due to escalating energy costs and the shortage of fossil fuels, a strong emphasis is being placed 
on  the  energy  efficiency  of  AC  adapters.    In  fact,  external  adapters  have  been  referred  to  as  energy 
vampires  because  they  constantly  consume  power,  regardless  of  load  connectivity  [9].    Granted,  the 
power  wasted  by  a  single  adapter  is  negligible,  but  AC  adapters  have  a  widespread  application  across 
the portable electronics market, posing a large‐scale issue. 
  Anytime  AC  power  is  transformed  into  DC  power,  energy  is  wasted  through  losses  by  internal 
components.  Not only does this occur while a load is connected to the adapter but also during no‐load 
conditions.  In fact, power is constantly drawn and dissipated by the adapter's internal circuitry as long 
as it is connected to an AC power source.  The transformer inside the adapter, which converts the high 
voltage  input  into  a  lower  voltage  signal,  consumes  a  majority  of  the  energy  during  standby.    The 
remaining  components  also  contribute  to  the  wasted  power  consumed  every  day  without  an  end 
purpose. 
Today’s  consumers  are  reminded  that  they  should  unplug  their  chargers  from  the  wall  when 
they are not in use [10].  However, even if one conscientiously practices this habit, it places too much 
burden on the consumer to conserve energy.  Turning off a light in an unoccupied room is an easy task, 
but adapters are often located in tight quarters and are not readily accessible (e.g., behind furniture).  
Common sense dictates the need for a practical solution involving an automatic control system for the 
modern AC adapter, making decisions regarding the system's power state according to the presence of a 
load.  It seems necessary to design an efficient wall adapter that will fit into a society of convenience.  A 
closer look into its marketability will show that the world demands the incorporation of such a device. 
 

15 

 
The Economics 1.2
 
The cell phone industry has boomed during the last decade by enormous proportions.  Between 
1995  and  2005,  wireless  subscribers  in  the  U.S.  have  increased  by  174.1  million  [11].    Figure  1‐1 
illustrates the rapidly increasing number of wireless subscribers in the United States. 
 

 
Figure 1‐1: Wireless Subscribers in United States in the years 1995, 2000, 2005, and 2006 [11]. 
 
According  to  the  Cellular Telecommunications Industry Association (CTIA),  76%  of  the  United 
States population owns a cell phone, translating to 233 million wireless subscribers in 2006 [11].  Since 
almost every cell phone has its own adapter, approximately 233 million mobile phone chargers are also 
in use across the country.  Assuming all of these adapters remain plugged in year‐round and their no‐
load power consumption follows the ENERGY STAR standard of 500mW [12] on average, the total power 
consumption of ordinary cell phone adapters is equal to:  
. .
  233,000,000   (1‐1) 

While  this  figure  may  seem  impressive,  it  is  only  a  small  percentage  of  the  total  U.S.  energy 
consumption,  which  equals  around  30000TWh  yearly  [13].    On  the  other  hand,  the  ENERGY  STAR 
website mentions that a total of 300TWh of energy flows through all external power adapters every year 
[14].    Figure  1‐2  shows  that  this  amount  accounts  for  1.01%  of  the  national  energy  consumption.  

16 

 
Therefore,  it  is  important  to  realize  that  despite  zero‐load  consumption  of  cell  phone  adapters 
constituting only a small fraction of total adapter consumption, the creation of an efficient wall adapter 
could  provide  long‐term  savings.    ENERGY  STAR  predicts  a  potential  energy  savings  of  5TWh  if  all 
adapters were designed to their idle power consumption standard [15].  This notion introduces the first 
potential market for efficient wall adapters: national governments.  
 

 
Figure 1‐2: Energy Consumption Breakdown in the United States for 2005 [13]. 
 
  In  the  United  States,  the  ENERGY  STAR  campaign  is  the  most  publicized  program  for  power 
efficiency.  In Europe, the European Commission (EC) Code of Conduct on Energy Efficiency of External 
Power Supplies provides guidelines for power‐saving adapters  [16].  The code specifies a plan to reduce 
zero‐load consumption for all external power supplies consuming fewer than 60W of output power to 
300mW.  The EC believes they can reduce zero‐load power losses by 5TWh per year if all adapters meet 
this requirement starting in 2010.  The prospective savings would be 500 million euro [16]. 
  National governments may also assist in developing potential markets.  For instance, the United 
States has environmental and energy agencies that would be compelled to recommend an efficient wall 
adapter to be used in cell phone charging applications (e.g., ENERGY STAR).  Moreover, if the product 
can  be  patented  or  approved,  governments  have  the  ability  to  pass  legislation  mandating  its 
distribution.  For example, on December 18, 2007, the United States Congress voted in a new energy bill 
that  will  reduce  the  country’s  dependency  on  oil  and  increase  the  utilization  of  alternative  energy 
sources  [17].    The  provisions  of  this  bill  call  for  automobile  and  lighting  products  to  become  more 

17 

 
energy‐efficient.  Automobiles will be required to consume an average of 35 miles per gallon by the year 
2020, and lighting products will be forced to meet ENERGY STAR standards by the year 2012 [17].  The 
downside  of  marketing  to  national  governments  is  the  delays  inherent  in  passing  the  necessary 
legislation.  However, there are several other potential markets that could be pursued concurrently. 
  As  mentioned  previously,  and  illustrated  in  Figure  1‐2,  power  adapters  do  not  occupy  a 
significant percentage of the total energy consumption in the United States [13].  These figures seem to 
imply that the consumer’s incentive will not be centered on short‐term economic savings, but on long‐
term economic and environmental benefits.  If the efficient wall adapter costs $2.00 more than present 
models, and if electricity costs equate to 14.6 cents per kWh [18], then it would take three to four years 
to  recover  the  difference  in  cost.    However,  since  energy  costs  continue  to  rise  due  to  the  increasing 
scarcity of resources, the economic savings will also increase.  If the adapter could be manufactured at a 
smaller  premium  (e.g.,  $1.00),  the  energy  savings  would  cover  the  additional  cost  within  one  or  two 
years,  which  is  the  typical  duration  of  a  cellular  phone  contract  [19].    Such  an  inexpensive,  efficient 
adapter could easily become a neutral value proposition to the consumer on a purely monetary basis. 
  Conversely, the corporate market’s incentive for a more efficient wall adapter differs from that 
of  the  everyday  consumer.    Cell  phone  manufacturers  such  as  Nokia  and  Motorola  look  to  entice 
customers  to  buy  their  products  using  different  marketing  schemes.    Many  of  these  manufacturers 
market  their  products  from  a  green  angle  (i.e.,  an  environmental  friendliness  standpoint),  in  order  to 
appeal to the consumers’ morality or concern for the environment [20].   
An overview of the economics landscape suggests that a more efficient wall adapter would be 
generally  welcomed.    Although  the  improved  design  may  not  be  particularly  attractive  to  the  average 
consumer,  corporations  involved  in  the  retail  of  small  electronics  would  invite  such  a  device.  
Furthermore,  the  marketability  of  a  low‐power  adapter  could  benefit  greatly  from  newfound  federal 
impetus  for  energy  legislation  [17].    Overall,  there  appears  to  be  global  demand  for  a  more  energy‐
efficient AC adapter from a variety of sources.   
 

Specification Goals 1.3

 
The  following  objectives  were  established  at  the  beginning  of  the  project  in  order  to  provide 
guidelines for the final product: 
 

18 

 
 
• Universal Application 
AC adapters have a wide variety of applications, so it follows logically that numerous variations 
have been designed.  Therefore, the project’s implementation should be universal so that it may apply 
to all external power adapters.  The fulfillment of this objective requires the product to consist of mostly 
basic components, such as resistors, capacitors, inductors, and transistors.  Using simple electrical parts 
minimizes complexity and possible incompatibilities with certain designs.  In addition, the utilization of 
basic components allows the product’s size to remain as compact as possible.  It should be noted that 
devices such as transformers and relays can considerably increase the size of an existing adapter.   
  Although the project’s aim is to develop a universal product, the scope of the project concerns 
adapters utilized in North America (120VRMS, 60Hz input). 

 
• Fully Integrated Solution 
The anticipated, high‐efficiency product could be based on two distinct implementations.  One 
design consists of an intermediary device that would placed in series between the wall and an external 
power adapter.  Another design involves an integrated modification within the adapter itself.  The first 
solution provides an easy way for the consumer to improve the efficiency of existing adapter models.  As 
a result, new, more efficient adapters would not have to be purchased.  However, this option has a few 
setbacks.  The overall cost of implementing such a device would be an expensive investment compared 
to  the  integrated  solution.    Moreover,  some  modern  wall  adapters  are  designed  with  physical  casings 
that  cling  to  the  wall  when  plugged  into  an  electrical  socket,  invoking  the  term  wall  warts  due  to  the 
way they bulge from the wall [9].  Consequently, adding a device between the wart and the wall would 
only  increase  the  bulk  of  the  implementation  and  reduce  aesthetics.    Furthermore,  it  is  likely  that 
modifying the adapter’s internal circuitry would provide more opportunities for increasing the efficiency 
of the system compared to its external counterpart.  These considerations were significant enough that 
an internal, fully‐integrated solution was chosen as the best implementation for the design. 
 

• Added Cost of $1.30 
Energy  Star‐endorsed  wall  adapters  consume  a  maximum  500mW  of  power,  equivalent  to 
approximately $0.64 over the course of a year.  The typical cell phone contract term, which frequently 
19 

 
represents the lifetime use of the associated cell phone, is two years [19].  Therefore, it can be assumed 
that the consumer would break even economically by the end of their contract if the additional cost of 
an  efficient  wall  adapter  is  less  than  $1.30.    Consequently,  a  neutral  cost  proposition  increases  the 
appeal of an efficient wall adapter. 
 

• Minimum Idle Power Reduction of 75% 
Ideally, the efficient wall adapter designed in this project will consume 0W of power during idle 
conditions.  However, the economic and spatial constraints established in previous specifications affect 
the plausibility of achieving ideal functionality.  Therefore, the team decided that the product should be 
designed to consume at least 75% less power than the efficient models currently on the market.  This 
reduction  will  be  maximized  if  passive  components  are  predominantly  used  throughout  the  solution, 
since a circuit containing mostly passive parts will consume less power during idle times compared to a 
configuration with several active devices.  The more the adapter reduces standby power consumption, 
the more the consumer benefits economically. 
 

• Maximum Output Threshold Current of 15mA 
In  order  to  determine  whether  a  load  is  connected  at  the  DC  output  of  the  adapter,  sensing 
circuitry  is  needed  to  measure  the  output  current  within  a  specified  range.    Therefore,  the  current 
detection circuit must be able to alert the necessary components when the output load is nonexistent.  
In order to achieve this functionality, the sensing circuitry must be designed around a threshold level of 
current.  The threshold must be signficantly less than the minimum current drawn by a connected load 
while  large  enough  for  the  low‐current  sense  to  measure.    The  minimum  level  of  current  drawn  by  a 
battery  load  to  maintain  a  full  amount  of  charge  is  called  trickle  current.    Although  adapter  trickle 
currents  vary,  the  smallest  trickle  current  rate  uncovered  during  research  was  3%  of  the  battery’s 
capacity  per  hour  [21].    If  a  small  cell  phone  battery  (900mAh)  is  connected  to  the  adapter,  then  the 
trickle  current  would  be  around  27mA.    Therefore,  the  team  chose  a  value  of  15mA  as  the  maximum 
threshold current, which is about half of the lowest observed trickle current.  Figure 1‐3 below shows 
the  relationship  between  the  output  current  and  the  output  voltage  of  the  sensing  circuit.    For  this 
particular cell phone, the trickle current is around 30 mA.  At tDISCONNECT, the phone is disconnected from 
the adapter.  Once the current decays past the threshold current of at least 15 mA, the output of the 
current sensing circuit will switch from logic low, or 0V, to logic high, or a 5V level.  It is important that 
20 

 
the  current  sensing  circuit  output  remains  low  when  the  phone  is  connected  so  the  battery  is  able  to 
maintain its charge.   
 

When device is disconnected,  …causing the current sensing 
output current drops…  circuit to raise its alert voltage 

 
Figure 1‐3: Adapter output current (left) and the current‐sensing logic output voltage (right) versus time.  The 
load is disconnected from adapter at tDISCONNECT, causing the output current to drop, and the current‐sensing alert 
to rise. 

Collectively, these specifications constitute the team’s efforts to design an efficient wall adapter 
that will enhance society  both economically and environmentally.  Over  the  course of this project  the 
team has designed an adapter that meets all of its goals.  It is a modular design that can be integrated 
into  any  AC  adapter,  and  deactivates  itself  when  the  adapter’s  output  current  drops  below  15mA.    In 
addition, the team bettered its cost goal with a final cost of $1.21 per 1000 units.  Most significantly, the 
adapter’s idle power consumption was reduced by 85% over the original adapter model, which is one of 
the most efficient adapter designs on the market today.  The remainder of this report explains how the 
team managed to achieve and exceed these goals. 
The ensuing chapter addresses the background of the project, including a summary of modern 
switch  mode  power  supply  design  as  well  as  the  assembly  and  analysis  of  the  adapter  test  bed.    The 
third  chapter  describes  the  team’s  three  top‐level  approaches  to  designing  an  efficient  wall  adapter.  
Three  proposed  solution  ideas  are  discussed  and  subsequently  narrowed  down  to  the  modified 
adapter’s  most  basic  stages:  current  detection  and  power  disconnection.    Chapter  4  describes  the 
specific circuitry used to implement the approaches specified in Chapter 3.  The fifth chapter discusses 
results of the adapter design in terms of power savings, cost, and relevant output waveforms.  Chapter 6 
discusses the team’s recommendations for future teams interested in improving this project’s adapter 
design, while the seventh chapter concludes the report. 
21 

 
 The Modern Power Adapter  2 
 
After  exploring  the  possible  economic  and  environmental  implications  of  an  efficient  wall 
adapter, the team became educated on the progression of power adapters over time.  Several questions 
were asked prior to conducting this research:   
1. How do modern AC adapters work? 
2. What previous efforts have been made in developing an efficient AC adapter?  
3. Which adapter design should be chosen for testing and experimentation? 
Before  designing  a  solution  for  an  existing  product,  it  is  only  customary  to  familiarize  oneself  with  its 
functionality  and  internal  components.    It  is  crucial  not  only  to  understand  the  purpose  of  particular 
stages in the circuit, but to also understand the function of each component in the design.  Secondly, the 
team  felt  it  was  necessary  to  investigate  whether  previous  efforts  had  been  made  in  developing  an 
efficient wall adapter.  For instance, it would be wise to analyze previous designs of AC adapters.  If an 
existing design can be altered to improve efficiency, then the team’s efforts would be a success.  Lastly, 
the team chose an efficient wall adapter design to use as a test bed.  Choosing an existing design with 
great efficiency allowed the team to manipulate and subsequently improve a present‐day adapter.   
 

Switch-Mode Supply Development 2.1

 
  The  need  for  transforming  AC  power  into  a  DC  signal  has  always  had  significance  in  electrical 
applications  since  Faraday  introduced  the  first  of  its  kind  in  1831  [22].    The  first  power  supplies  were 
designed in a linear arrangement.  A linear power supply takes the AC, high‐voltage input and attenuates 
the  signal  using  a  step‐down  transformer.    From  the  secondary  winding  of  the  transformer,  the 
attenuated signal is rectified into the DC output signal.  Figure 2‐1 shows a top‐level diagram of a linear 
power supply. 

22 

 
  
Figure 2‐1: Shown is a top‐level diagram of a linear power supply.  The input, with series resistance, is directly 
connected to the primary winding of the transformer.  The transformer attenuates the input voltage to a low‐
amplitude voltage on its secondary winding.  Finally, the output rectifier with capacitive peak detection converts 
the AC signal into the DC output. 

For  many  years,  linear  power  supplies  were  predominantly  used  to  operate  electrical 
appliances.    However,  the  significant  downside  in  using  a  linear  power  supply  is  its  poor  power 
efficiency.    Due  to  losses  experienced  in  the  transformer’s  primary  winding  and  iron  core,  power 
delivered at the output is much less than the power supplied to the input.  Therefore, large, expensive 
transformers are generally used in linear power supplies to cope with heat dissipated due to such losses 
[23].    For  instance,  large  transformers  are  used  on  power  lines  to  convert  high‐power  electricity  from 
the regional supplier to households across the United States.   
Since  the invention of the transistor in the  mid‐1940s, the power supply community has been 
investigating  ways  to  use  switching  applications  to  reduce  losses  and  minimize  the  size  of  adapters.  
Although the original theory was conceived in the 1950s, the switched‐mode power supply (SMPS) did 
not come to fruition until the late 1970s [24].  At this time, IC manufacturers began creating controller 
ICs that performed high‐frequency switching [24].  The inception of controller ICs in the SMPS allowed 
smaller  transformers  to  be  used  in  the  design,  effectively  allowing  the  SMPS  to  become  more 
marketable  and  cost‐effective.    Currently,  the  SMPS  is  now  widely  used  in  smaller‐sized  electronic 
applications, more so than its linear counterpart due to its compact design [24]. 
  In SMPS design, switching is conducted at high frequencies for a couple reasons.  As previously 
mentioned, the power losses in a SMPS are minimized if the frequency of the signal across the primary 
winding is high.  In addition, the typical range of human hearing includes frequencies between 20Hz and 
20kHz [25].  If switching occurred at a frequency within this range, there is a possibility of acoustic noise 
generation that would be irritating to the consumer.  Therefore, a switching frequency between 50kHz 
and 150kHz is generally used in SMPS applications [24]. 

23 

 
  There are a multitude of SMPS designs used in modern adapters today.  Figure 2‐2 shows a top‐
level diagram of a common Flyback converter [26].  Beginning with a standard AC input of 120VRMS, the 
input  rectifier  converts  the  high‐voltage  AC  into  a  high‐voltage  DC  signal.    Meanwhile,  the  monolithic 
switcher,  driven  by  an  internal  flip‐flop,  switches  the  bottom  node  of  transformer’s  primary  winding 
from AC ground to the potential seen at the top node.  The high‐frequency, high‐voltage signal on the 
primary  winding  is  translated  into  an  attenuated  version  on  the  secondary  winding.    At  this  point, 
operation  continues  in  line  with  a  linear  power  supply,  rectifying  the  high‐frequency  signal  into  a  DC 
voltage.   
  Often  employed  as  a  safety  measure,  switching  power  supplies  will  also  include  some  level  of 
current‐sensing  capability  near  the  output.    This  circuitry  sends  feedback  to  the  switching  IC  which  is 
capable of shutting down in case the load attached to the adapter attempts to draw more current than 
the adapter can supply.   
 

 
Figure 2‐2: Functional diagram  of  a Flyback  converter, representing the  5  principle  qualities of modern power 
adapters;  input  rectification,  high  speed  switching,  step‐down  transforming,  output  rectification,  and  built‐in 
overload current sensing [26]. 

    
 

24 

 
Specific Example 2.2
 
In  efforts  to  find  an  existing,  efficient  SMPS  adapter,  the  team  found  a  design  note  from  ON 
Semiconductor,  labeled  as  an  Efficient,  Low  Cost,  Low  Standby  Power  (<100  mW),  2.5  W  Cell  Phone 
Charger  [27].    Design  note  DN06017/D  is  filed  as  an  application  of  the  NCP1011  IC,  or  a  Self‐Supplied 
Monolithic Switcher for Low Standby‐Power Offline SMPS [28].  Like the monolithic switcher described in 
Figure  2‐2,  the  NCP1011  provides  idle‐state  recognition  for  enabling  a  low  standby  power  mode  in 
addition to switching at a frequency of 100kHz.  If the NCP1011 detects an idle condition at the output, 
the  adapter  transitions  into  a  skip‐cycle  mode,  reducing  the  duty  cycle  of  the  output  during  no‐load 
conditions.  Moreover, the adapter uses feedback from an output current‐sensing circuit to execute its 
latch‐off  mode  if  an  excessive  amount  of  current  is  detected.    During  latch‐off  mode,  the  NCP1011 
disables adapter operations for a period of time, after which the adapter is reactivated.  In effect, the 
NCP1011 protects against possible permanent damage to the load and internal circuitry.  The schematic 
for the adapter in design note DN06017/D is shown in Figure 2‐3 [27]. 
 

 
Figure 2‐3: Efficient, Low Cost, Low Standby Power (<100mW), 2.5W Cell Phone Charger from ON Semiconductor 
Design Note DN06017/D [27]. 

25 

 
  This  particular  SMPS  design  follows  the  top‐level  diagram  shown  in  Figure  2‐2,  with  an  input 
rectifier,  transformer,  output  rectifier,  high‐current  sense,  and  a  monolithic  switcher.    After  the  input 
has  been  connected,  AC  voltage  is  rectified  by  diode  D1,  and  filtered  by  the  tank  circuit  arranged  by 
inductor L1 and capacitors C1 and C2.  The high‐voltage DC signal of around 170V is then passed to the 
primary  winding  of  the  transformer.    The  NCP1011  uses  power  from  its  output  pin  (pin  5)  for  initial 
startup,  charging  capacitor  C3  on  its  Vcc  pin  (pin  1).    Once  the  charge  on  this  capacitor  reaches 
approximately 8.5V, the NCP1011 IC begins switching at 100kHz [28]. 
After the NCP1011 commences switching operation, pulses from 0V to 170V and 10µs apart are 
observed  across  the  transformer.    In  order  to  save  power,  a  transformer  with  an  auxiliary  winding  is 
used  to  power  the  NCP1011  once  switching  begins.    A  simple  diode  rectifier  (D4)  is  used  with  a  filter 
capacitor (C9) to convert the AC signal into a DC signal.  Resistor R8 and capacitor C3 constitute an RC 
timing circuit that controls the operation of the NCP1011.  Capacitor C6 and device U2 are connected in 
parallel with the feedback pin (pin 4) of the NCP1011.  U2 is an optocoupler used to provide feedback 
from the high‐current sense on the DC side of the isolation to the monolithic switcher.  During normal 
operation, the BJT in the optocoupler is in cutoff mode, applying a high resistance between pin 4 of the 
NCP1011 and AC ground.  Capacitor C6 contributes to the isolation between these two nodes as well.  If 
a  sufficiently‐high  amount  of  current  is  detected  at  the  output,  U2  activates  the  BJT  into  saturation, 
effectively shorting the feedback pin of the NCP1011 to AC ground.  If a ground fault is detected by the 
NCP1011 on its feedback pin, the chip transitions into latch‐off mode [28].  Figure 2‐4 shows a simplified 
block diagram of the NCP1011’s functionality. 

26 

 
  
Figure  2‐4:  The  simplified  block  diagram  of  the  NCP1011’s  functionality  portrays  each  of  the  three  operating 
conditions.  During normal operation, the power MOSFET driver is controlled by a flip‐flop coupled with the 100‐
kHz clock, periodically reset by the VCC capacitor when the voltage at pin 1 equals VOVERLOAD.  If pin 4 is grounded, 
signifying  a  high‐current  output  condition,  the  Flip‐Flop  is  reset.    Lastly,  the  chip  operates  in  latch‐off  mode 
when the charge/discharge cycle of CVCC is extended during no‐load conditions [28]. 

  Capacitor  C5,  resistor  R2,  and  diode  D3  are  arranged  in  what  is  known  as  a  snubber 
configuration  [29].    Snubbers  are  circuits  that  protect  electrical  components,  such  as  transformers, 
relays,  other  inductive  devices,  and  surrounding  components  from  transient  voltage  spikes  caused  by 
current interruptions.  When current to an inductive device is suddenly cut, the magnetic energy stored 
therein will naturally attempt to sustain current flow.  This current, now inhibited by an open circuit, has 
the  potential  to  build  up  brief,  high‐magnitude  voltages  that  could  stress  or  damage  nearby 
components.  For example, this effect can be seen in arching across relay contacts [29]. 
  Since the large voltage spike is created in a reversed direction of normal operation, one of the 
most basic snubber designs is simply a diode installed in reverse parallel with the target inductive coils.  
This gives the current a small, but closed path to follow, preventing high voltages from occurring.  There 
are  also  snubbers,  such  as  the  RC  snubber,  that  use  capacitors  to  control  the  voltage  across  the  coils 
directly,  rather  than  the  current  produced  by  them.    The  capacitor’s  transient  nature  performs  a 
controlled absorption of the energy spike and typically dissipates it through a resistor [29].   

27 

 
  The snubber in the NCP1011 power adapter model makes use of both the diode and capacitor 
snubber principles.  It performs a helpful role for the output of the switcher as well, absorbing most of 
the  output  current  upon  shutdown.    This  decreases  the  peak  power  dissipation  of  the  switcher  by 
dissipating power through the snubber instead, thus increasing the reliability of the IC.  Controlling the 
voltages  in  shutdown  circuit  operations  has  also  been  shown  to  lower  the  high‐frequency 
electromagnetic interference potentially created by uncontrolled switching. 
  The DC stage of the circuit is implemented according to the top‐level diagram shown in Figure 
2‐2.    Diode  D2  and  capacitor  C4  provide  the  output  rectification  required  for  AC‐to‐DC  conversion.  
Capacitor C7 is placed in parallel with the output to filter out remaining high‐frequency components in 
the signal.  On the other hand, resistor R4 is placed in series with the top rail to provide a measure of the 
output  current.    As  the  load  draws  power  from  the  adapter,  the  voltage  drop  across  R4  is  linearly 
proportional to the current.   The base and emitter of PNP BJT Q1 are placed across this voltage drop.  If 
the  voltage  drop  reaches  approximately  600mV,  the  output  current  level  has  eclipsed  the  500mA 
maximum.  At this point, Q1 is biased into the active region, sourcing current to the optocoupler U2.  U2 
notifies the switcher of the high‐current condition and the adapter is subsequently deactivated. 
  Finally, to ensure a consistent output voltage regardless of component imperfections, the Zener 
diode D5 is place in reverse bias with respect to the top DC voltage rail.   The  rating on  this particular 
Zener diode is 4.3V, so in order to achieve an output of 5V, resistor R3 of 200Ω is placed from the anode 
of  D5  to  DC  ground  to  serve  as  a  pull‐up  resistor.    Resistor  R6  is  placed  in  the  design  as  a  means  to 
further manipulate the output voltage, but is assigned a value of 0Ω to maintain a DC output of 5V [27]. 
  It  is  clear  that  the  SMPS  contains  a  significant  amount  of  additional  components  when 
compared  to  a  linear  power  supply.    In  addition  to  switching  controllers,  feedback  circuitry  and 
additional  diode  rectifiers  are  among  several  added  devices  to  the  SMPS  adapter  design.    Therefore, 
SMPS  are  marketable  today  because  the  cost  of  the  smaller  transformer  and  additional  parts  is  much 
less than the cost of the large, linear transformer overall. 
 

Simulation 2.3

Once  an  existing  adapter  model  was  chosen  as  the  project’s  test  bed,  it  was  necessary  to 
simulate the design in PSpice in order to confirm functionality of each stage.  Figure 2‐5 shows the node 
numbering used in the simulation netlist. 

28 

 
  
Figure 2‐5: Schematic of adapter test bed from Figure 2‐3; netlist used to perform PSpice simulation on entire 
system. 

  Due  to  the  unavailability  of  simulation  models  for  some  components  or  the  non‐existence 
thereof,  some  of  the  semiconductor  components  as  well  as  the  transformer  were  modeled  using 
different parameters.  The netlist of the full adapter simulation can be found in Appendix C.  All initial 
conditions  for  energy  storage  components  (e.g.,  capacitors  and  inductors)  were  set  to  0V  for  all 
simulations unless otherwise specified. 

 
Results 2.3.1
 
Simulation  results  of  the  full  adapter  simulation  were  accurate  for  some  measurements  while 
inaccurate for others.  Figure 2‐6 displays the output voltage behavior between 5ms and 15ms.  The DC 
output climbs steadily at a rate of 367nV per 1ms.  While this voltage increase is negligible compared to 
the expected output level, the behavior can be attributed to the voltage ripple produced by the input 
rectifier.  The slight voltage variation is translated from the primary winding to the secondary winding, 
causing a steady output current to charge the output filter capacitors C4 and C7.   

29 

 
 Figure 2‐7 shows the voltage at the Vcc pin of the IC climbing steadily toward 8.5V.  The voltage 
across  the  primary  winding  can  also  be  seen  to  be  at  a  level  of  169V,  with  the  previously‐mentioned 
voltage ripple produced by the rectifier affecting the stability of the signal. 

 
Figure 2‐6: PSpice simulation results; output voltage of adapter versus time, prior to activation of switching IC.  
Output  voltage  increases  linearly  by  3µV,  likely  as  a  result  of  energy  transferred  by  the  input  rectifier  ripple 
through the transformer. 

Primary winding input

Switcher VCC pin

 
Figure 2‐7: PSpice simulation results; input voltage at primary winding and Vcc pin on switching IC versus time, 
prior to activation of switching IC.  Primary winding voltage remains close to rectified mains voltage, while the 
IC’s power capacitor charges toward its activation trigger of 8.5V. 

30 

 
 In order to observe the system’s behavior while in normal operation, the simulation was altered 
to record data from 10ms to 20ms.  Figure 2‐8 shows the voltage at the VCC pin of the NCP1011.  After 
17.2ms, the voltage at pin 1 reaches a level of 8.5V.  The parabolic behavior between 17.2ms and 20ms 
of  pin  1  can  be  attributed  to  the  introduced  output  load  once  switching  begins.    However,  after  the 
startup time of 17.2ms has elapsed, the adapter begins internally switching, providing a high‐frequency 
signal across the primary winding of the transformer.  The voltage at pin 5 of the NCP1011, which is its 
output, is shown on the same timescale in Figure 2‐9 and Figure 2‐10.  When looking at these plots, the 
team  noticed  an  unusual  level  of  voltage  detected  at  the  output  of  the  NCP1011.    In  fact,  Figure  2‐9 
shows a signal with an amplitude of 700VPEAK.  The magnified plot shown in Figure 2‐10 shows that 700V 
is reached during switching transitions from low to high.  It was puzzling to understand why these spikes 
occurred,  since  a  snubber  is  used  in  parallel  with  the  primary  winding  of  the  transformer  to  mitigate 
voltage spikes.  The team was unsure whether this phenomenon was a product of simulation or a true 
representation  of  circuit  operation.    The  only  way  to  verify  either  case  was  to  conduct  physical 
measurement on the system. 
 
 
 
 

Activation triggered at 8.5V, 17.2ms 

 
Figure 2‐8: PSpice simulation results; voltage at Vcc pin on switching IC versus time.  Voltage hits its activation 
trigger of 8.5V and begins oscillations.  The VCC pin is located on pin 1 of the NCP1011 block diagram. 

 
31 

 
 Adapter activation at 17.2ms 
 
Figure  2‐9:  PSpice  simulation  results;  output  voltage  of  NCP1011  versus  time.    Switching  begins  when  the 
voltage at the Vcc pin reaches 8.5V (Figure 2‐8).  The output of the NCP1011 is equivalent to pin 5 on the block 
diagram. 

 
 
 
 
 
 
 

 
Figure 2‐10: PSpice simulation results; voltage outputted by switching IC versus time.  Same as Figure 2‐9, but 
with a smaller time scale to show IC’s oscillation pattern.  The output of the NCP1011 is equivalent to pin 5 on 
the block diagram. 
32 

 
 A plot of the adapter’s DC output versus time is shown in Figure 2‐11.  At the critical time when 
the  startup  period  ends  (17.2ms),  the  adapter’s  output  voltage  rate  increases  from  367nV  per  1ms  to 
50mV per 1ms.  The output  current is relatively  constant due  to a resistive load at  the  output, so the 
expected  time  the  output  voltage  reaches  5V  is  around  100ms  after  adapter  activation.    Since  a  full 
simulation of 20ms requires a significant amount of time to run, the notion of conducting a simulation 
for 100ms is not plausible.  Therefore, the team formulated a solution to provide an alternative way to 
simulate the adapter in a timely manner.   
 

Activation at 17.2ms 

 
Figure 2‐11: PSpice simulation results; voltage at the DC output of the adapter versus time.  Again, switching IC 
activates at 17.2ms, causing the output to increase toward its eventual 5V level. 

  The  team  dissected  the  netlist  in  efforts  to  locate  the  source  responsible  for  elongating 
simulation  runtime.    It  was  determined  that  the  model  of  the  NCP1011  IC  provided  by  ON 
Semiconductor performed several calculations during simulations, shortening the time step significantly.  
Therefore, the IC would need to be replaced with a subcircuit that imitated its functionality. 
In order to simulate the adapter in a more time‐effective way while preserving the integrity of 
system  functionality,  the  team  modeled  the  NCP1011  using  a  pair  of  controlled  switches.    A  voltage‐
controlled switch (S1) was used to switch the voltage through the transformer to ground at 100kHz.  The 
feedback  control  subsystem  was  replaced  by  a  current‐controlled  switch  (W1).    Since  an  auxiliary 
winding was not required to power the NCP1011 in the simplified model, the transformer was reduced 
33 

 
to a primary winding and  a secondary winding.  Figure 2‐12 represents the  configuration  used for the 
simplified simulation.  The PSpice netlist used in the simplified simulation can be found in Appendix C.   
  Initial  trials  of  the  simplified  model  of  the  adapter  yielded  promising  results.    Figure  2‐13 
displays the expected rectification of the AC input voltage, while Figure 2‐14 shows the output voltage 
of the adapter between 0ms and 400ms.  The voltage level converges at around 6V, which is 1V higher 
than the expected value.  It is possible that this discrepancy is due to the Zener diode model used for the 
simulation (1N4623).  It is noticeable that the simplified simulation was run much longer than the initial 
version.  However, the runtime of the simplified simulation was significantly less than the full simulation, 
proving  that  ON  Semiconductor’s  NCP1011  model  was  responsible  for  the  team’s  initial  simulation 
difficulties. 

 
Figure 2‐12: Simplified schematic of adapter test bed from Figure 2‐3 used for netlist of simplified system, which 
was created for faster simulation runtimes. 
 

34 

 
 Rectified input, now DC  

AC mains input

 
Figure 2‐13: PSpice (simplified) simulation results; mains input voltage and rectified mains voltage versus time.  
Input voltage is rectified before being switched to 100kHz by switching IC. 
 

 
Figure 2‐14: PSpice simulation results; voltage at the DC output of the simplified adapter versus time.  Voltage 
converges at 6V DC within half of a second. 

The  team  later  revisited  the  complete  adapter  model  in  efforts  to  obtain  results  while 
expediting simulation runtime.  In order to shorten simulation duration, initial conditions were applied 
to capacitors throughout the circuit.  If voltages across the capacitors were preset above 0V, the team 
believed the time required for the output voltage to reach 5V would be shortened.  Therefore, the input 
rectifier  capacitors  were  preset  to  169V,  since  the  169.7VPK  AC  signal  will  be  rectified  to  a  169V  DC 

35 

 
signal.    Output  filter  capacitors  were  set  to  maintain  a  level  of  around  5V,  since  this  is  the  expected 
output voltage level.   
However, some problems were experienced in the first trial with initial conditions applied to the 
various capacitors.  Specifically, an error was observed indicating overflow: convert.  In the second trial, 
the  initial  conditions  of  the  output  capacitors  C4  and  C7  were  reduced  to  1V  while  leaving  the  preset 
voltages of the input rectifier capacitors unchanged.  Figure 2‐15 shows the results of the second trial. 
 

 
Figure 2‐15: PSpice simulation results; voltage at the DC output of the simplified adapter versus time.  Output 
filter capacitors were simulated with an initial condition of 1V, to shorten the time required to observe 5V at the 
output of the adapter. 

 
  The voltage waveform shown in Figure 2‐15 is representative of the expected adapter output.  
The main takeaway from the team’s simulations is the time required to observe the rated 5V at the DC 
output.  Although the simulated time period may seem excessive, the large filter capacitor C4 explains 
why it may take a timescale of above 200ms to reach the appropriate value.  Moreover, a timescale of 
200ms is negligable to the user, so it is very plausible that the simulated timescale is representative of 
its actual value. 
 

36 

 
Simulation Challenges 2.3.2
In  addition  to  previous  difficulties,  the  team  experienced  several  other  complications  while 
running simulations.  One of the first problems encountered by the team in its full simulation trials was 
PSpice’s interpretation of isolated circuits.  It was discovered that circuit connectivity checks in PSpice 
require  paths  to  node  0  for  all  nodes.    Therefore,  isolated  circuits  such  as  AC  adapters  require  a 
connection  between  DC  ground  and  AC  ground.    However,  a  direct  connection  cannot  be  made  since 
isolation  between  both  stages  must  be  preserved.    The  team  found  that  placing  a  high  resistance 
between AC ground and DC ground was common practice in simulating isolated circuits [30].  The large 
resistor  RB  of  1TΩ  satisfies  PSpice’s  connectivity  requirements  while  preserving  isolation  between  the 
AC and DC stages of the adapter.   
Another complication of simulating the adapter was PSpice convergence issues.  In one of the 
initial  trials  of  the  full  simulation,  PSpice  reported  issues  in  calculating  voltages  within  the  subcircuit 
model of the optocoupler.  This problem was resolved by performing a transient analysis between 5ms 
and 15ms.  The time delay of 5ms eliminated the effect of startup transients on the simulation results, 
and allowed PSpice to record data without difficulty.   
Still another problem was found in the team’s original model of the transformer.  Initially, the 
transformer  was  modeled  using  a  combination  of  voltage‐dependent  voltage  sources  and  current‐
dependent voltage sources.  Figure 2‐16 shows both the modified transformer model and the original 
transformer  used  in  PSpice  simulations.    Although  voltage  ratios  were  set  according  to  specifications, 
the old transformer model failed to emulate true device operation since inductors were excluded from 
the subcircuit. 

37 

 
*New Transformer* *Old Transformer*
X3 6 4 12 13 7 0 XFMRAUX X3 6 4 12 13 7 0 XFMRAUX
.SUBCKT XFMRAUX 1 2 3 4 5 6 .SUBCKT XFMRAUX 1 2 3 4 10 11 PARAMS: RATIO1=0.1
RATIO2=0.05
*PRIMARY RP 1 2 1MEG
L1 1 2 2000 E1 5 4 VALUE = { V(1,2)*RATIO1 }
*SECONDARY G1 1 2 VALUE = { I(VM1)*RATIO1 }
L2 3 4 20 RS1 6 3 1U
L3 5 6 39.2 VM1 5 6
*MAGNETIC COUPLING E2 20 11 VALUE = { V(2,1)*RATIO2 }
K12 L1 L2 0.99999 G2 2 1 VALUE = { I(VM2)*RATIO2 }
K13 L1 L3 0.99999 RS2 21 10 1U
.ENDS VM2 20 21
.ENDS
Figure  2‐16:  PSpice  transformer  models,  original  noisy  model  (right)  was  replaced  with  an  improved 
magnetically coupled model (left) [30]. 

 
Figure  2‐17:  PSpice  (simplified)  simulation  results;  voltage  at  the  DC  output  of  the  adapter  versus  time.    This 
noise is likely the result of the simulation model of the circuit’s transformer having an exaggerated reaction to 
the high speed switching of the IC. 

  Figure 2‐17 shows the output voltage of the adapter when the old transformer model was used.  
It was clear that the high‐voltage, high‐frequency pulses experienced across the primary winding of the 

38 

 
transformer were not properly translated to the secondary winding.  It was determined that although 
the  old  transformer  model  may  be  useful  for  low‐frequency  or  low‐voltage  applications,  it  was  not 
operating appropriately for the adapter configuration. 
  Therefore, a modified subcircuit, shown alongside the old model in Figure 2‐16, was substituted 
in  for  the  transformer  [30].    The  new  model  uses  multiple  inductors  to  represent  the  windings  of  the 
transformer  and  mutual  inductance  to  emulate  the  magnetic  coupling  relationships  between  the 
windings.    Inductor  L1  is  used  as  the  primary  winding  in  the  subcircuit,  with  L2  functioning  as  the 
secondary winding and L3 as the auxiliary winding.  An inductance of 2000H was chosen for the primary 
winding to minimize the effect of series resistance on transformer operation.  The inductances of L2 and 
L3 were calculated using the following equation [31]: 

                      (2‐1) 

Since the turn ratio of the secondary winding to the primary winding is 0.1, the value of L2 is 100 times 
less  than  L1,  or  20H.    Similarly,  the  turn  ratio  of  the  auxiliary  winding  to  the  primary  winding  is  0.14, 
giving the value of 39.2H for L3.  The new model of the transformer allowed the team to observe the 
waveforms presented in the results portion of the simulation section. 
  Despite the many complications experienced running the various simulations of the adapter, the 
team was able to obtain waveforms that resembled accurate representation of system functionality.  In 
many electrical design projects, simulation is beneficial to determine behavioral irregularities within the 
circuit  so  troubleshooting  can  be  done  and  adjustments  can  be  made.    However,  the  design  of  an 
efficient wall adapter consists of low‐cost components, so physical measurements and adjustments can 
be made without spending a substantial amount financially.  Therefore, the team used a trial and error 
approach  to  building  the  adapter  test  bed  and  implementing  additional  circuitry,  using  the  results  of 
simulation trials to reinforce their findings. 
 

Test Bed 2.4

   
After running the full and simplified simulations, the team focused on purchasing the necessary 
parts to build an adapter prototype.  Assembling the adapter described in ON Semiconductor’s design 
note DN06017/D proved beneficial in several ways [27].  First, creating an adapter parts list allowed the 
team  to  see  the  total  cost  of  building  an  adapter,  in  addition  to  comparing  the  prices  of  the  various 
components.    Second,  the  team  discovered  the  physical  space  required  to  build  an  adapter  while 
39 

 
delicately  soldering  the  components  onto  a  perfboard.    Most  importantly,  the  physical  measurements 
conducted on the finished test bed helped verify as well as disprove preconceptions on system behavior.  
Therefore, this section is divided into the following three subsections: 
1. Preparing for adapter assembly by creating parts list and ordering necessary components 
2. Assembling the adapter test bed on a perfboard and later a printed circuit board (PCB) 
3. Recording measurements and waveforms from test bed to confirm overall behavior of circuit 

 
Preparations 2.4.1
 
Before  purchasing  parts  for  the  test  bed,  the  team  first  created  a  list  of  all  components  to 
compare cost, distributor, and quantity.  The parts list for the current, completed version of the test bed 
is given in Table 2‐1 [27]. 
 
Table  2‐1:  The  final  revision  of  a  parts  list  for  the  adapter  test  bed.    To  fit  the  table  in  this  document,  the 
manufacturer part number field has been excluded.  The final cost of the adapter assumes that each part in the 
list is purchased in a bulk of at least 1000.  The table is sorted by the total price of each component [27]. 
Unit 
Price  Total 
Quantity  Label  Part Type  Value  Distributor  Distributor Part #  (1000)  Price 
1  T1  Transformer  3.5 mH  Coilcraft  A9619‐C $1.680  $1.680 
1  U3  IEC AC PCB  Pin  Mouser  693‐GSP2.8101.13 $1.150  $1.150 
1  U1  Switcher IC  NCP1011ST  Mouser  863‐NCP1011AP100G $0.604  $0.604 
1  L1  Inductor  1mH  Mouser  652‐SDR1005‐102KL $0.310  $0.310 
1  R1  Resistor  20Ω, 2W  Mouser  71‐CPF2‐F‐20‐E3 $0.299  $0.299 
2  C1, C2  Capacitor  4.7uF, 400V  Mouser  647‐UVR2G4R7MPD $0.137  $0.274 
1  U2  Optocoupler  SFH‐615A‐4  Mouser  782‐SFH615A‐4 $0.250  $0.250 
2  C5, C6  Capacitor  1nF, 1kV  Mouser  81‐DEHR33A102KA2B $0.088  $0.176 
1  D2  Diode  MBR150  Mouser  863‐MBR150G $0.097  $0.097 
2  C3, C9  Capacitor  10uF  Mouser  647‐USR1E100MDD $0.048  $0.096 
1  Q1  BJT  2N2907  Mouser  610‐PN2907A $0.090  $0.090 
1  C8  Capacitor  4.7nF  Mouser  140‐500P5‐472K‐RC $0.080  $0.080 
1  D3  Diode  MUR160  Mouser  512‐UF4005 $0.059  $0.059 
1  C4  Capacitor  1mF  Mouser  647‐UVR0J102MPD1TA $0.059  $0.059 
1  R4  Resistor  1.2Ω, 0.5W  Mouser  660‐MF1/2LC1R2J $0.057  $0.057 
1  C7  Capacitor  100nF  Mouser  594‐K104K15X7RF53H5 $0.050  $0.050 
1  D1  Diode  1N4007  Mouser  863‐1N4007G $0.019  $0.019 
1  D5  Zener  1N5229B  Mouser  512‐1N5229B $0.015  $0.015 
1  R2  Resistor  150kΩ  Mouser  660‐CFS1/4CT52R154J $0.009  $0.009 

40 

 
 1  R7  Resistor  10Ω  Mouser  660‐CFS1/4CT52R100J $0.009  $0.009 
1  R8  Resistor  2kΩ  Mouser  660‐CFS1/4CT52R202J $0.009  $0.009 
1  R3  Resistor  200Ω  Mouser  660‐CFS1/4CT52R201J $0.009  $0.009 
1  D4  Diode  1N4148  Mouser  78‐1N4148 $0.008  $0.008 
1  R5  Resistor  100Ω  Mouser  660‐CFS1/4CT52R101J $0.008  $0.008 
1  R6  Jumper  0Ω  Mouser  660‐Z25YC $0.007  $0.007 
Total  $5.42 
Date:  11/28/2007 
   
Most  of  the  parts  in  Table  2‐1  were  available  from  Mouser  Electronics,  so  the  team  chose  to 
purchase a majority of the items from this particular distributor.   The one exception in the list was the 
transformer, since it was sold directly from its manufacturer  (Coilcraft) [32].  Overall, the total cost of 
the  adapter  test  bed’s  parts  was  $5.42.    The  team  believed  this  was  a  reasonable  price,  since  many 
adapters available at retail outlets are sold up to four times that amount. 
  Once  the  parts  were  ordered  from  Mouser  Electronics  and  Coilcraft,  respectively,  the  team 
debated on the type of board to be used for the test bed.  The two choices presented before the group 
were  a  solderless  breadboard  or  a  pre‐punched  perfboard.    Each  option  has  its  own  advantages  and 
drawbacks.   
  The  prominent  benefit  of  using  a  solderless  breadboard  is  the  ease  of  implementation.    Since 
the pinholes in each horizontal row are connected and each vertical column of connections is divided, 
the breadboard would allow the team to assemble the adapter  without  the  use of solder.  Moreover, 
circuit troubleshooting is very much simplified when using a breadboard since each component can be 
easily  replaced.    On  the  other  hand,  the  pre‐punched  perfboard  does  not  provide  the  same  ease  of 
implementation.    Each  pinhole  on  the  perfboard  is  completely  isolated  from  the  surrounding  pins, 
requiring  the  circuit  assembler  to  solder  leads  together.    If  the  design  contains  a  multitude  of 
components,  this  can  prove  to  be  an  arduous  process.    Therefore,  a  circuit  prototype  is  often 
implemented on a breadboard in the interest of time and troubleshooting. 
Although the breadboard seemed to be the logical choice, the team discovered a critical flaw in 
using a breadboard for the adapter test bed implementation.  The vertical columns on the breadboard 
are  separated  by  a  parasitic  capacitance  of  4pF  from  one  another.    This  characteristic  is  not  a  major 
issue  when  building  circuits  that  process  low‐frequency  signals.    However,  the  adapter  test  bed  uses 
100‐kHz  switching  from  the  NCP1011.    Therefore,  the  inter‐column  impedance  of  the  breadboard  is 
significantly  reduced  for  high‐frequency  applications.    Since  the  impedance  of  a  capacitor  follows  the 

41 

 
statement  (1/jωC),  the  isolation  between  select  vertical  columns  of  the  breadboard  would  be  a  mere 
400kΩ  for  the  adapter  test  bed.    There  are  many  hazardous  sideeffects  introduced  by  low‐impedance 
separation of nodes, including the possiblity of shorted nodes and leakage currents.   
Notwithstanding, the perfboard provides a very high‐impedance internode isolation.  As long as 
interconnections  are  soldered  properly,  the  adapter  test  bed  would  operate  without  the  possibility  of 
leakage currents or shorted nodes.  In the end, the team believed the perfboard was the right choice for 
implementing the adapter test bed. 
  Separate from ensuring proper curcuit functionality, there are many safety concerns associated 
with  testing  and  building  high‐voltage,  fast‐switching  circuitry.    In  particular,  high‐power  circuits  can 
have fatal consequences if not treated with caution.  According to the Electronic Library of Construction 
Occupational  Safety  and  Health  (eLCOSH),  120VRMS  at  currents  as  low  as  50mA  can  have  fatal 
implications on a human being [33].   

 
Figure 2‐18: Rendition of isolated circuit hazard; floating circuits will readily seek an introduced ground, such as 
a human being in close proximity [33]. 
 
  Constructing  an  AC  adapter  introduces  the  hazard  of  isolated  circuits.    An  IEEE  article  details 
how  isolated  circuits  have  subsections  that  have  no  direct  ground  [33].    In  Figure  2‐18,  circuitry 
connected to the secondary winding of the transformer has no return path to the original AC ground of 

42 

 
the  energy  source.    Therefore,  the  nodes  located  on  the  isolated  side  of  the  circuit  are  floating  with 
respect  to  earth  ground.    In  effect,  a  person  in  close  proximity  of  a  floating  node  can  be  in  danger  of 
electric shock.  For instance, the man’s feet in Figure 2‐18 are shown to be connected to earth ground.  
If  he  made  contact  with  a  node  on  the  floating  side  of  the  circuit,  a  path  to  earth  ground  would  be 
introduced, and he could be electrocuted provided a high level of current is allowed to run through his 
body.    In  addition,  he  could  experience  electric  shock  by  simultaneously  touching  one  node  of  the 
isolated  circuit  and  another  ground.    Although  the  isolated  nodes  on  the  DC  side  of  the  test  bed  are 
relatively  low‐power,  the  potential  danger  introduced  by  isolated  circuits  were  kept  in  mind  while 
building the adapter. 
 

Assembly 2.4.2
 
Once  all  of  the  necessary  parts  were  available,  the  team  began  building  the  test  bed  on  a 
perfboard.  In efforts to simplify circuit troubleshooting, the adapter was built and tested in stages from 
the AC input to the DC output.  The first subcircuit assembled on the perfboard was the input rectifier.  
The physical arrangement and circuit schematic are shown in Figure 2‐19. 

 
 

 
Figure 2‐19: Input rectifier of test bed, circuit diagram (top) and soldered circuit (bottom). 

43 

 
  Before  connecting  the  120VRMS  signal  to  the  rectifier,  the  team  setup  a  function  generator  to 
provide  the  circuit  with  a  sinusoidal  input  wave  of  approximately  10.5V  at  a  frequency  of  60Hz.    An 
oscilloscope probe was connected first to the input signal and then to the output of the rectifier, which 
recorded  the  voltage  across  capacitor  C2.    Figure  2‐20  shows  three  cycles  of  the  input  signal  to  the 
rectifier, and Figure 2‐21 shows the DC voltage recorded across C2.  The DC voltage was observed to be 
approximately  10V.    The  slight  attenuation  of  the  peak  voltage  of  the  input  to  the  DC  output  can  be 
attributed to the voltage drop across rectifier diode D1.   

 
Figure 2‐20:  Input test wave from function generator; 10V sinusoid. 
 

 
Figure 2‐21: Rectifier/filter stage output resulting from application of input test wave in Figure 2‐20; 10VDC. 
 

  In addition, the ripple voltage of the rectifier’s output waveform was also observed.  In an effort 
to observe the variation in the signal, the oscilloscope’s voltage precision was increased to 100mV per 

44 

 
division.  Although a small oscillation was observed on the oscilloscope plot shown in Figure 2‐22, the 
team was satisfied with the overall stability of the signal. 
 

 
Figure  2‐22:  Magnification  of  rectifier/filter  stage  output  from  Figure  2‐21.    The  lack  of  visible  ripple 
demonstrates the functionality of the tank filter comprised of capacitors C1 and C2 and inductor L1. 
   
After verifying the functionality of the input rectifier, the remaining circuitry located on the AC 
side  of  the  isolation  was  assembled  on  the  perfboard.    The  remaining  subcircuits  to  be  assembled 
included the snubber in parallel with the primary winding of the transformer, the transformer, and the 
NCP1011 IC.  Optocoupler U2 was not yet placed in the perfboard since feedback control functionality 
requires  the  current  sense  circuitry  located  on  the  DC  side  of  the  adapter.    Figure  2‐23  shows  the 
schematic  for  all  circuitry  located  on  the  AC  portion  of  the  adapter  as  well  as  the  physical 
implementation of the schematic on the perfboard.   
Testing of the present configuration required the standard 120VRMS, 60Hz input to the rectifier.  
In order to safely connect this high‐power signal to the perfboard, a three‐connection power cable was 
used.  The cable was stripped of its outer insulator so the three inner connections could be accessed.  
Since the individual copper wires in the power cable were too thick to connect directly to the perfboard, 
each  wire  gauge  was  adapted  by  soldering  a  segment  of  10‐gauge  wire.    The  three  connections  were 
each insulated using shrink tubes, heated to fit around the soldered wires.  The adapted 120VRMS wire 
(black) and the neutral wire (white) are shown in Figure 2‐23.  The earth ground connection (green) was 
fastened to the metal backing of a test bench. 
  Once  the  adapted  power  connections  were  soldered  to  the  perfboard,  the  half‐constructed 
adapter was plugged into a wall socket.  No adverse effects or phenomena were experienced after one 

45 

 
minute of 120VRMS running through the AC side of the adapter.  The team proceeded to disconnect the 
power  connection  and  connected  an  oscilloscope  probe  across  capacitor  C2  to  measure  the  output 
voltage of the rectifier.  When power was reconnected, the oscilloscope showed a 0V potential across 
C2.  Therefore, the team connected the probe across the auxiliary winding of the transformer in order to 
observe an expected waveform oscillating at 100kHz.  When power was reconnected to the perfboard, 
the primary winding of the transformer experienced a surge of current that caused it to overheat.  The 
heat caused the material in the winding to vaporize, producing an acoustic explosion and a noticeable 
spark.  Subsequent troubleshooting yielded the reason this event occurred. 
 

 
Figure 2‐23: AC side of test bed, circuit diagram (top) and soldered circuit (bottom), (11/20/2007). 
46 

 
  The tip of a typical oscilloscope probe has a high impedance, while the alligator clip provides an 
earth ground connection.  According to the conventional dot labeling of an inductor, the high voltage is 
connected  to  the  side  of  the  winding  where  the  dot  is  located.    Theoretically,  connecting  the  probe 
ground to the low‐potential node of the auxiliary winding is not hazardous since the adapter schematic 
shows that the auxiliary winding is in  fact connected to earth ground.  However, the team discovered 
that  the  input  power  connections  were  connected  with  the  120VRMS  signal  at  the  bottom  rail  and  the 
neutral connection at the top rail.  Since the neutral input connection was attached to the top rail, the 
input rectifier produced a 0V output.  More importantly, the 120VRMS connection was shorted to earth 
ground  via  the  oscilloscope  probe,  causing  an  excessive  level  of  current  to  flow  through  the  primary 
winding.  Figure 2‐24 shows a representation of the nodes in a typical wall socket and the connections 
made to the each node [34].   
 

 
Figure  2‐24:  Diagram  depicting  the  delivery  of  AC  power,  from  the  utility  transformer  to  the  outlet  and  the 
eventual device’s interface with it.  Note that line is represented as a white wire while neutral is black [34]. 
 

47 

 
 The wall socket’s ground and neutral connections are given access to earth ground via a ground 
rod.    Since  the  neutral  input  has  a  path  to  earth  ground,  a  third  connection  from  the  adapter  to  the 
ground  connection  of  the  wall  socket  is  not  required.    However,  the  live  connection  (denoted  by  L) 
oscillates between 170V and ‐170V.  AC adapters designed around the linear power supply configuration 
shown  in  Figure  2‐1  can  transform  the  input  signal  regardless  if  the  input  is  connected  in  a  reverse 
manner  or  not.    If  the  neutral  and  live  connections  are  interchanged  in  a  linear  power  supply,  the 
transformer is able to translate in an inverted signal (180° out of phase) to the output.  This is harmless 
to the linear power adapter, since the input is a symmetrical AC signal with little DC bias.  The adapter 
test bed used in this project, on the other hand, requires a neutral connection to the bottom rail of the 
AC  input  in  order  for  the  input  rectifier  and  NCP1011  to  operate  appropriately.    Figure  2‐3  shows  the 
several ground connections in the adapter. 
The team realized that resistors R8 and R1 were also damaged during the initial testing of the AC 
side of the adapter.  Once both resistors as well as the transformer were replaced, the team switched 
the polarity of the input connections.  Next, the DC side of the adapter was implemented.  Since the first 
perfboard was not wide enough to fit all circuitry, a second perfboard was used to build the DC stage.  
Two  10‐gauge  wires  were  attached  to  the  positive  and  negative  DC  output  connections.    Since  the 
prototype would undergo many trials using a variety of resistive loads, the wire connections allow load 
connections to be made through a breadboard.  Figure 2‐25 and Figure 2‐26 show the front and back of 
the completed perfboards.     
 
DC Output 
Wire Connections 
Input Rectifier  Transformer

Output Rectifier 
and Current Sense 

NCP1011 IC
AC Input 
Wire Connections 
 
Figure 2‐25:  Top view of first prototype of adapter test bed implemented on perfboards (11/21/2007).  Major 
circuit stages are labeled with arrows and descriptions. 

48 

 
  Since the adapter is implemented on two separate perfboards, connections between the DC and 
AC  side  were  made  via  10‐gauge  wire.    Figure  2‐26  show  the  connections  made  throughout  the 
prototype, including the crossover connections between the AC and DC stages. 
 

DC Output  Secondary Winding 
Wire Connections  Connections

AC Input 
Feedback Signal to  Wire Connections 
Optocoupler 

 
Figure  2‐26:  Bottom  view  of  the  first  prototype  of  the  adapter  test  bed  implemented  on  perfboards 
(11/21/2007).    Connections  between  both  perfboards  have  been  labeled  with  arrows  and  descriptions  in 
addition to input and output connections. 
 
  Before connecting the input power to the prototype, an oscilloscope was connected across the 
DC output of the adapter.  When the AC input connection was made to a wall socket, a 5.6V DC signal 
was observed at the output, shown in Figure 2‐27. 
 

 
Figure 2‐27: 5.6V DC output of first adapter prototype. 
49 

 
  Like the input rectifier output, the team pursued to increase the volts per division scale of the 
oscilloscope  to  analyze  the  noise  level  of  the  signal.    Figure  2‐28  shows  a  small  amount  of  high‐
frequency noise at the output because capacitor C4 was unable to filter the entire 100‐kHz signal from 
the secondary winding.  However, the amplitude of the noise is small enough to be negligible for battery 
charging applications.   
 

 
Figure  2‐28:  Close‐up  probe  capture  of  noise  observed  at  the  DC  output  of  the  first  test  bed  implementation.  
The level of noise varies slightly relative to the DC bias, so the effect of these oscillations on the battery load is 
negligible. 

Once an operational model of the adapter was accomplished, the team designed a PCB of the 
test bed.  Building the test bed on a PCB had a few benefits.  For instance, board space was conserved 
since all connections were pre‐made by the PCB manufacturer.  An array of 868 pinholes was placed in 
the vacant area above the adapter circuitry so experimental circuitry could be implemented later in the 
project.    Another  advantage  to  building  the  test  bed  onto  a  PCB  was  integrating  both  the  AC  and  DC 
stages onto one board.  The interconnections between one perfboard and the other were under much 
tension  due  to  the  two‐board  arrangement.    Constructing  the  test  bed  on  one  board  eliminated  the 
possibility of connectivity issues throughout the circuit.  The original PCB design is shown in Figure 2‐29. 
 

50 

 
  
Figure  2‐29:  First  revision  of  adapter  PCB  design  (11/29/2007).    Green  traces  represent  top‐level  copper 
connections while red traces represent bottom copper connections.  The top silkscreen is shown as light blue to 
outline component footprints and pin holes.  The bottom copper area on the AC portion of the PCB is connected 
to AC ground via a jumper [27]. 
 
The  light  blue  traces  indicate  the  silkscreen  prints  used  for  component  footprints  and 
identification markings.  The two‐level board’s trace layers are shown in Figure 2‐29 by color.  The light 
green  traces  represent  top‐layer  copper  connections,  while  the  red  traces  show  bottom‐layer  traces 
located  underneath  the  board.    The  dashed  line  on  the  top  silkscreen  layer  represents  the  isolation 
between the AC side and the DC side of the adapter.   
The  red  area  located  on  the  left‐hand  side  of  the  board  provides  a  power  plane  for  all 
connections made to AC ground.  Its odd shape is attributed to the team’s efforts in minimizing charge 
collection  at  particular  points  in  the  plane.    If  the  plane  was  shaped  as  a  polygon  with  right  angles, 
charge  would  collect  at  these  points  of  transition.    In  effect,  charge  differentials  could  occur  between 
other points in the circuit and the charge collections on the power plane.  Ideally, the plane should have 
a  uniform  charge  density,  so  the  area  is  enclosed  by  obtuse  angles  in  order  to  minimize  charge 
collection.  The ground plane was also designed to flow under the top‐layer copper trace connecting pin 

51 

 
5 of the NCP1011 (output) and pin 10 of the transformer (top node of primary winding) to minimize the 
effect of noise on the 100‐kHz signal. 
The PCB design contains other changes from the perfboard implementation.  A footprint for an 
AC power cable connection plug was placed before the input to the adapter for simplification.  Also, test 
points  were  implemented  throughout  the  design  so  probe  measurements  could  be  made  at  critical 
nodes.    The  ground  plane’s  connection  to  the  neutral  input  is  intentionally  disrupted  by  a  resistor 
footprint.    This  way,  the  adapter’s  supplied  current  can  be  measured  using  Ohm’s  Law.    If  normal 
adapter operation is desired, the team has the option of placing a 0Ω jumper in lieu of a true resistor to 
directly connect the neutral input to the ground plane.  Finally, the connection between the DC output 
and the output rectifier was broken in the same manner.  The team intended to place a current‐sensing 
resistor in this footprint to measure the output current delivered to the connected load, since a current 
sense implementation of some kind was expected in the final design. 
 

Measured Waveforms of Test Bed 2.5

 
  After  completing  a  working  adapter  test  bed,  the  team  obtained  measurements  of  various 
waveforms in the design.  All test bed measurements were obtained using the first prototype of the test 
bed.  Notwithstanding, the measured waveforms throughout the adapter test bed were consistent with 
the team’s preconceptions of circuit behavior.   
A  variety  of  waveforms  of  the  adapter  test  bed  were  captured  and  analyzed.    Input  power 
signals, NCP1011‐related waveforms, and DC output voltages were observed via an oscilloscope.  Before 
presenting  the  waveforms  and  the  team’s  analysis  thereof,  the  test  bed  schematic  is  shown  again  in 
Figure 2‐30 for convenience [27]. 

52 

 
  
Figure 2‐30: Test bed schematic from ON Semiconductor’s DN06017/D Design Note. 
 
  Initial  waveforms  were  captured  of  the  adapter’s  DC  output,  but  these  waveforms  were 
obtained  under  no‐load  conditions.    Figure  2‐31  shows  the  DC  output  of  the  adapter  with  a  purely 
resistive  load  200Ω.    The  DC  bias  level  of  the  output  waveform  during  no‐load  conditions  and  load 
conditions remains the same.  Therefore, a large variation in drawn current does not dramatically affect 
the output voltage, which is a desired characteristic of an AC adapter. 
 

 
Figure 2‐31: Oscilloscope capture of DC output voltage with 200Ω load using the first test bed implementation.  
The mean voltage was observed to be slightly above 5V. 
 

53 

 
  While the voltage level remained constant regardless of load connectivity, the team wondered 
why the DC bias was significantly greater than the nominal voltage.  The reason for this discrepancy is 
due to two components in the circuit: transformer T1 and Zener diode D5.  The transformer used in this 
project is different from the one specified in ON Semiconductor’s original schematic of the adapter.  In 
fact, the transformer model used by ON Semiconductor was designed by Mesa Power Systems.  Since 
the exact transformer model specified in the original design was unavailable, the team chose Coilcraft’s 
A9619‐C  Flyback  transformer.    The  Coilcraft  A9619‐C  was  created  specifically  for  SMPS  applications 
designed  around  the  NCP101X  IC  family  [32].    Although  both  models  are  similar,  the  specifications  of 
each  vary  slightly.    The  turn  ratio  between  the  primary  and  secondary  windings  are  equal  in  both 
models, but there may be a small discrepancy between the waveforms produced by each transformer.   
  It  is  also  possible  that  Zener  diode  D5  may  contribute  to  the  output  voltage  difference.  
Although Zener diodes are designed for specific reverse breakdown voltages, each diode model requires 
a  rated  avalanche  current  to  produce  the  expect  voltage  drop.    Therefore,  the  reverse  breakdown 
voltage may vary slightly between Zener diodes of the same model.  In addition, the pull‐up resistor of 
200Ω may vary between 190Ω and 210Ω, causing a variation in voltage on the DC output.  However, the 
team  decided  that  a  small  discrepancy  of  600mV  was  acceptable,  since  many  batteries  are  designed 
with a reasonable tolerance of charging voltages. 
Once  the  DC  output  waveform  was  measured,  the  switching  behavior  of  the  NCP1011  was 
observed.    Figure  2‐32  shows  two  waveforms  each  oscillating  at  100kHz.    Figure  2‐33  redisplays  the 
simplified diagram of the NCP1011 switcher for reference [28]. 
 

Voltage across transformer 
winding averages 0V

   
Figure 2‐32: IC  output  with 200Ω  load  (left),  Voltage  across  primary  winding  with  200Ω  load  (right)  using  first 
test bed implementation. 
54 

 
 
 

 
Figure 2‐33: The simplified block diagram of the NCP1011.  Pin 1 is the VCC pin, and pins 3, 7, and 8 are connected 
to AC ground.  Pin 4 is the feedback pin from optocoupler U2 and pin 5 is the output of the switcher.  Pins 2 and 
6 are not connected, and are therefore absent from the diagram [28]. 

The left‐hand waveform shown in Figure 2‐32 shows the voltage at the output of the NCP1011.  
As  expected,  the  internal  power  MOSFET  in  the  IC  switches  the  output  between  AC  ground  and  the 
voltage output of the input rectifier (170VDC).  The sinusoidal oscillations that are observed after low‐to‐
high transitions can be attributed to damping effects introduced by the snubber circuit [29].  Without a 
snubber, high‐voltage transients would appear across the power MOSFET’s drain and source terminals.  
The  inclusion  of  a  snubber  circuit  dampens  the  high‐voltage  transients  caused  by  fast‐switching 
applications by creating an alternative path for current to flow during transitions.  When current flows 
through  the  snubber,  the  system  comprised  of  resistor  R2,  capacitor  C5,  and  the  inductance  of  the 
primary winding is underdamped, causing oscillations to occur in the voltage waveform until the switch 
is closed. 
Next,  the  voltage  at  the  VCC  pin  of  the  NCP1011  (pin  1)  was  observed.    Figure  2‐34  shows  the 
voltage waveform measured at the VCC pin.  The left waveform shows a small voltage ripple at a DC bias 
level  of  approximately  8V.    The  frequency  of  the  ripple  was  measured  to  be  83.3Hz.    Therefore,  the 
duration of each ripple lasts 12ms.  According to the datasheet of the NCP1011, the ripple frequency is 
55 

 
contingent on the adapter load.  If the adapter is delivering a significant amount of power to the load, 
the  ripple  frequency  increases.    Conversely,  the  ripple  period  increases  if  a  high‐impedance  load  is 
connected to the adapter. 
   

 
 Figure  2‐34:  The  left  waveform  shows  the  voltage  on  the  NCP1011’s  Vcc  pin  with  200Ω  load,  while  the  right 
waveform shows a 10X magnification of the left waveform using the first implementation of the test bed. 
 
  After collecting the various waveforms measured under a DC output load of 200Ω, the adapter 
was  then  tested  under  the  two  extreme  conditions:  no  load  and  a  0Ω  load  (output  short).    The  right‐
hand waveform in Figure 2‐35 shows the output voltage of the NCP1011 (pin 5) with no load attached to 
the output.  The left‐hand waveform redisplays the IC’s output voltage for a 200Ω load to juxtapose the 
no‐load waveform.  The no‐load waveform, while maintaining signal integrity, has a much smaller duty 
cycle  than  the  200Ω  waveform.    The  reduced  duty  cycle  follows  the  specifications  of  the  NCP1011’s 
behavior under standby conditions (i.e., no load).   
 

 
Figure 2‐35: IC output with 200Ω load (left), no load (right) using first test bed implementation. 

56 

 
  On the other hand, the 0Ω load exhibited a much different behavior.  After shorting the positive 
DC  output  connection  to  the  negative  output,  the  voltage  waveform  shown  in  the  right  oscilloscope 
capture in Figure 2‐36 was observed.  In order to prevent the transformer from delivering an excessive 
amount of power to the DC side of the adapter, the duty cycle of the NCP1011 output is decreased to 
almost 0%.  Under the shorted load condition, the high‐current sense circuitry signals the optocoupler to 
alert the NCP1011 of a high output current condition.  The NCP1011 reactivates momentarily every 10µs 
to check for a load condition change.  The NCP1011 resumes normal switching behavior once the output 
terminals of the adapter are opened.  This behavior follows the specifications stipulated in the datasheet 
for the NCP1011 [28]. 
 

    
 Figure 2‐36: IC output with 200Ω load (left), shorted load (right) using the first test bed implementation. 
 
  The  short‐circuit  protection  feature  of  the  NCP1011  was  further  tested  by  connecting  its 
feedback  pin  (pin  4)  directly  to  AC  ground.    The  resulting  waveform  of  the  IC’s  output  shows  that 
switching behavior is ceased while the feedback pin is constantly grounded.  Under this condition, the IC 
is unable to power itself via the auxiliary winding, so power is drawn from the high DC voltage produced 
by the input rectifier.  Figure 2‐37 shows the output of the NCP1011 when the feedback pin is shorted to 
AC ground. 

57 

 
  
Figure 2‐37: Using the first test bed implementation, IC output is shown with pin 4 of the NCP1011 shorted to AC 
ground, simulating a high‐current condition.  Switching behavior is completely ceased under this condition. 
 
  After the test bed was tested under extreme output conditions, the team simulated a defective 
battery load by introducing an output current above the maximum of 500mA.  Instead of connecting a 
low‐impedance output, a voltage source was placed across the current sense resistor R4.  The output of 
the  voltage  source  was  set  to  736mVDC,  producing  a  current  of  587mA  through  R4.    Theoretically,  the 
736mV  drop  across  base‐emitter  junction  of PNP  BJT  Q1  would  cause  the  transistor  to  source  current 
through its collector and  emitter terminals.  In effect, the sourced current from the top  DC rail would 
drive the internal LED of the optocoupler on, signaling the NCP1011 of an over‐current condition at the 
output.  Figure 2‐38 shows that the theoretical operation of the adapter under this condition matches its 
actual behavior.  Similar to the shorted feedback pin, the adapter halts high‐frequency switching until 
the high‐current condition is cleared. 
 

 
Figure 2‐38: Using the first test bed implementation, IC output is shown with 587mA flowing through the 
current‐sensing resistor R4, simulating a high‐current condition.  Switching behavior is completely ceased under 
this condition. 
58 

 
  At this point, the team confirmed many of the specifications described in ON Semiconductor’s 
datasheet of the NCP1011 monolithic switcher.  However, the output of the adapter was observed once 
more  to  capture  the  ripple  voltage.    Figure  2‐39  shows  waveforms  of  voltages  measured  across  filter 
capacitor  C4.    The  left  waveform  shows  the  waveform  under  a  100Ω  load  condition,  and  the  right 
waveform was captured while no load was connected to the output.  After placing the oscilloscope on a 
50mV per division vertical scale, a small ripple effect was observed.  The waveform measured under the 
100Ω condition shows a periodic occurrence of voltage spikes at a frequency of 100kHz.  While the left 
waveform  exhibits  a  50%  duty  cycle,  the  no‐load  waveform  shows  a  much  smaller  duty  cycle  across 
capacitor C4.  In addition, the DC bias level is reduced by 100mV.  Overall, the power consumption of the 
adapter is significantly reduced under standby conditions. 
 

 
  Figure 2‐39: Voltage across C4, 50mA load (left), open (no) load (right) using first test bed implementation. 
   
Once  various  waveforms  of  the  NCP1011  were  analyzed  under  selected  load  conditions,  the 
team focused on obtaining power efficiency measurements of the adapter.  Since the ON Semiconductor 
design note claims that the adapter is highly‐efficient, it was important to verify the adapter’s small level 
of power loss.  Power efficiency is defined as the ratio of power delivered to the output compared to 
power  supplied  by  the  input.    Measuring  the  power  delivered  to  the  output  was  simple  using  the 
following relationship: 

                    (2‐2) 

On the other hand, calculating the power supplied by the input is more challenging.   

59 

 
 Initially, the team attempted to calculate the input power using an ammeter at the input of the 
adapter.   Figure 2‐40 shows the setup used to measure the input power with the ammeter. 
 

 
Figure  2‐40:  Initial  input  power  measurement  setup  for  adapter  test  bed.    The  ammeter  is  placed  in  series, 
separating the live, 120VRMS input from the adapter input. 

In order to measure current, the connection between the live, 120VRMS node and the adapter input was 
broken.  Subsequently, the ammeter was placed in series with the two inputs.  The continuous power 
supplied  by  the  input  was  then  measured  by  calculating  the  product  of  the  input  RMS  current  and 
voltage: 
  , ,                   (2‐3) 
When the adapter was plugged in with a 200Ω DC load, the ammeter measured an RMS current 
of  1mA.    According  to  (2‐3),  the  supplied  power  to  the  adapter  was  120mW.    Likewise,  (2‐2)  yields  a 
delivered power of 28mW.  Dividing the output power by the input power gives an efficiency of 23.3%.  
Realizing  that  the  adapter  is  a  SMPS  and  is  described  to  operate  at  a  high  efficiency,  the  team  was 
skeptical at the calculated efficiency.   
It was later determined that the ammeter was designed to measure RMS currents of sinusoidal 
waveforms.    Since  the  adapter  utilizes  an  input  rectifier  for  its  operation,  the  input  current  is  not 
sinusoidal.  Figure 2‐41 shows the schematic of a typical half‐wave rectifier with a filtering capacitor and 
the output waveform produced by a rectifier.  The diode in the rectifier eliminates the negative voltage 
swing of the sinusoidal AC voltage, yielding a half‐wave signal.  The filter capacitor then charges up to 
the  peak  amplitude  of  the  signal.    Once  the  voltage  of  the  half‐wave  signal  begins  decreasing,  the 
capacitor  slowly  discharges,  producing  a  relatively  stable  output  signal  with  a  slight  ripple  voltage.  
Therefore,  current  is  drawn  from  the  adapter  only  during  time  periods  when  the  capacitor  recharges 
back to the peak amplitude of the half‐wave signal.   Therefore, a new method is required to measure 
power supplied by the AC input. 

60 

 
  

 
Figure 2‐41: Example of a typical rectifier with smoothing capacitor, and its output waveform.  Current is only 
drawn  during  the  periods  in  which  the  capacitor’s  voltage  is  charging,  so  the  current  waveform  will  not  be 
sinusoidal [35]. 
 

An  alternative  way  of  measuring  current  is  by  placing  a  series  resistance  in  the  path  of  the 
supplying  voltage  source.    As  long  as  the  resistance  is  small  in  value,  the  circuit  is  not  affected  by  its 
presence.    Therefore,  the  team  placed  a  series  resistance  in  the  return  path  of  the  AC  input.    Using 
Ohm’s Law, the voltage measured across the resistor is linearly proportional to current flowing through 
the  resistor.    An  oscilloscope  probe  can  then  be  placed  across  the  introduced  resistor,  while  another 
probe can be placed in parallel with the voltage source.  Figure 2‐42 explains this arrangement, showing 
Scope  A  measuring  the  input  voltage  while  Scope  B  measures  a  voltage  proportional  to  the  input 
current.    The  MATH  function  of  the  oscilloscope  allowed  the  team  to  use  the  continuous  power 
relationship in (2.3) by multiplying the waveforms of Scope A and Scope B together.    
 

 
Figure  2‐42:  The  second  arrangement  used  in  test  bed  power  measurements.    Input  voltage  is  measured  by 
scope A, while a voltage directly related to the input current is measured by probe B. 

61 

 
  Rsense was selected to be 1Ω for initial measurements using the alternative method.   The team 
rationalized  that  the  voltage  drop  across  Rsense  would  equal  the  exact  value  of  current  in  amperes.  
Figure 2‐43 shows the oscilloscope probes arranged according  to Figure 2‐42.  Looking at  Figure 2‐44, 
Probe B is connected across Rsense, while Probe A is connected across the AC input.  The output load was 
connected to the adapter using the green and white alligator clips as depicted in Figure 2‐43. 
 

Probe B

Test bed 

Probe A 

Load resistor

 
Figure 2‐43: Test setup for measuring the power efficiency of the original test bed configuration. 
 
Rsense 

Probe B 

Probe A 

 
Figure 2‐44: Configuration of oscilloscope probes for input current measurement of initial adapter test bed. 
62 

 
 Under  the  test  setup  shown  in  Figure  2‐43  and  Figure  2‐44,  waveforms  shown  in  Figure  2‐45 
were observed on the oscilloscope.  Channel 1 shows the voltage across Rsense and Channel 2 shows the 
AC  input  voltage.    Although  the  AC  input  voltage  waveform  was  observed  as  expected,  Channel  1 
resembled a 180Hz distorted sinusoid.  The signal observed on Channel 1 was determined to be noise 
from the three‐phase power system [36].  Although the supplied power to the adapter is clearly a single‐
phase sinusoid, a three‐phase to single‐phase power conversion takes place prior to reaching the wall 
socket.  This converts most of the three‐phase signal to a single‐phase signal, but produces noise on the 
AC line connected to the wall socket.  Since each signal of the three‐phase system is separated by a third 
of a cycle from the others, the noise grants the illusion of a 180Hz signal.  Therefore, the team needed a 
way to eliminate the noise produced by the three‐phase power system in order to accurately measure 
the power efficiency of the adapter.   
 

            
 Figure  2‐45:  Oscilloscope  capture  of  input  power  measurement  using  1Ω  sensing  resistor  (left)  for  the  initial 
adapter  test  bed.    The  adapter  is  connected  to  AC  power  via  a  surge  protector.    The  observed  noise  was 
attributed  to  the  three‐phase  to  single‐phase  power  conversion.    The  right‐hand  signal  shows  the  noise 
produced while the surge protector is switched off. 
 
  In order to minimize the effect the 180Hz noise had on input current measurements, a value of 
100Ω was substituted in for Rsense.  Using a resistance 100 times the original value amplified the power 
measurement by an equal factor.  However, a simple division by the same amount yielded an accurate 
measurement of the power supplied to the adapter.  Therefore, the next input power measurement was 
conducted using a 100Ω resistor for Rsense and a 51Ω resistor for the output load.  Figure 2‐46 displays 
the  results  of  the  input  voltage  and  current  waveforms.    While  a  noticeable  amount  of  noise  was 
observed between cycles, the periodic current spikes were located where expected.  The true RMS value 

63 

 
of the input current was displayed as 1.76V which, given the 100 Ω sensing resistor, converts to 17.6mA.  
The  MATH  function  of  the  oscilloscope  was  observed  at  an  average  of  78V2,  which  translates  to  an 
average power of 780mW.  The output voltage was calculated using a multimeter to be 5.474V.  Using 
(2‐2),  the  power  delivered  to  the  output  load  was  588mW.    The  power  efficiency  was  subsequently 
calculated to be 75.4%, providing a more representative value of the adapter’s efficiency under normal 
operation. 
 

 
Figure 2‐46: Efficiency measurement with 100 Ω sensing resistor – 51 Ω load. 
 
  In  order  to  analyze  a  relationship  between  power  efficiency  and  load  resistance,  power 
measurements were repeated for eight other resistive loads.  Table 2‐2 shows the numerical results of 
each measurement. 
 
Table 2‐2: Original Test Bed Adapter ‐ Efficiency Measurements and Calculations. 

 
64 

 
 
  After  obtaining  results  for  all  loads  in  question,  a  characteristic  showing  the  relationship 
between  power  efficiency  versus  load  resistance  was  obtained.    Figure  2‐47  shows  the  relationship 
between the two values graphically.   As the impedance of the  output load increases, the efficiency of 
the adapter decreases.  On the other hand, the power consumed by components in the adapter does 
not  change  proportionally  to  the  power  delivered  to  variable  loads.    Therefore,  high‐impedance  loads 
use a smaller portion of the supplied power than the internal circuitry, yielding a poor efficiency rating.  
However, battery loads have characteristically small impedances, so the reduction of power efficiency is 
never experienced by the adapter.   
 

Efficiency vs. Load Resistance
70.00

60.00

50.00
Efficiency (%)

40.00

30.00

20.00

10.00

0.00
0 500 1000 1500 2000 2500
Load (Ω)
 
Figure 2‐47: Plot of efficiency percentage versus load resistance. 
 
Next, the team analyzed the relationship between the output power and the input power of the 
adapter.  Figure 2‐48 shows the plot of the two values.  According to Figure 2‐48, the operating region of 
the adapter is 300mW and 2.5W delivered to the DC load.  In other words, the adapter is designed for a 
maximum nominal load of 100Ω.  Once the output load exceeds this resistance, the efficiency decreases 
significantly.    The  power  efficiency  dramatically  decreases  under  100mW  output  power,  since  the 
NCP1011  operates  in  latch‐off  mode.      In  the  operating  region,  the  power  efficiency  is  around  80%, 
which is calculated by measuring the inverse slope of the curve.  Immediately below 300mW, the power 

65 

 
efficiency is approximately 50%.  Since most battery impedances are much less than 100Ω, the operating 
region is wide enough for the intended application. 
 

Drawn Power vs. Output Power
1000
900
Input Power Draw  (mW)

800
700
600
500
400
300
200
100
0
0 100 200 300 400 500 600 700
Output Power  (mW)
 
Figure 2‐48: Plot of power drawn by the adapter versus power delivered to output. 
 

  After measuring the power efficiency of the adapter under a variety of resistive load conditions, 
the two extreme output  cases were examined.  An analysis of each condition provided  the team with 
information  regarding  the  adapter’s  performance  under  such  terms.    Figure  2‐49  shows  waveforms 
observed when the DC output rails were shorted, emulating a 0Ω load.  The measured input current was 
equal  to  13.9mARMS,  yielding  an  input  power  of  1.67W.    The  supplied  power  under  the  output  short 
condition is about 1W higher than the largest power consumption observed during resistive load testing.  
However, the input power level does not meet nor does it exceed the maximum output power rating of 
2.5W.  Therefore, the adapter uses less power during a short load condition, improving efficiency and 
meeting the over‐current protection specification stipulated in the NCP1011 datasheet [28].   
 

66 

 
  
Figure 2‐49: Original test bed power measurement with 100Ω sensing resistor under a shorted load condition. 
 
  In  order  to  verify  the  power  efficiency  of  less  than  100mW  during  standby  conditions,  the 
shorted load was opened at the DC output.  Figure 2‐50 shows the input voltage and current waveforms 
used  to  measure  the  input  power  under  the  no‐load  condition.    According  to  the  oscilloscope’s 
measurement  of  the  average  current,  the  power  consumed  by  the  adapter  during  standby  equaled 
201mW.    Therefore,  the  actual  power  measured  was  over  double  the  amount  stipulated  by  ON 
Semiconductor’s design note.  Unless the Coilcraft A9619‐C transformer consumes a significant amount 
of excess power relative to the Mesa model used by ON Semiconductor, the calculation is accurate for 
the adapter design.  Nevertheless, the team believed that standby power could be significantly reduced. 
 

 
Figure 2‐50: Original test bed power measurement with 100Ω sensing resistor under a no‐load condition. 
 
The final measurement of the test bed involved the connection of a cell phone battery load to 
the adapter.  The plug that connected the cell phone to its actual charger was disconnected.  The outer 

67 

 
sheath  was  then  stripped  to  reveal  the  positive  and  negative  connections  to  the  plug.    Similar  to 
connecting the input of the adapter to the AC power cable, the plug from the cell phone’s charger was 
soldered onto the DC output.  Once this was completed, the adapter was setup to charge the cell phone. 
  The  cell  phone  was  turned  off  and  then  plugged  into  the  adapter.    When  the  adapter  was 
plugged  in,  the  phone  began  charging.      In  order  to  measure  the  current  delivered  to  the  battery,  an 
ammeter was connected in series with the DC output of the adapter and the cell phone battery.  When 
the  phone  indicated  that  it  was  fully  charged,  the  ammeter  was  observed  during  the  trickle  current 
operation of the adapter.  The trickle current delivered by the adapter allows the cell phone battery to 
remain charged up to peak capacity while connected to the adapter.  Over a period of a couple minutes, 
the output current averaged 37.4mA, with occasional and very brief current spikes over 100mA. 
  After completing test bed assembly and measurements, the team both confirmed and disproved 
adapter specifications stipulated by design note DN06017/D from ON Semiconductor [27].  In the design 
of  a  more  efficient  wall  adapter,  the  team  plans  on  using  an  output  current  detection  much  like  the 
high‐current sensing subcircuit implemented by ON Semiconductor’s design.  However, the planned use 
of the detection would be to evaluate when the output current is insufficient, indicating a nonexistence 
of a load.  In the specification goals section of this report, one of the stipulations for the design is the 
ability to detect a threshold current of 15mA.  Since the lowest trickle current observed during the cell 
phone  charging  test  was  37.4mA,  the  specified  threshold  is  sufficiently  low  enough  to  prevent  the 
hindering of the test bed’s operation while activated.  Moreover, the capacity of the battery used in the 
charging  test  was  850mAh,  which  is  relatively  small  for  a  cell  phone.    Given  that  larger  cell  phone 
batteries draw even higher levels of trickle current, the threshold current of 15mA is reasonable. 
  The assembly and subsequent measurement of test bed characteristics was critical in developing 
the team’s understanding of a modern efficient cell phone adapter.  In addition, specifications made by 
the designers of the adapter were mostly confirmed, while some were disproved.  The knowledge of the 
test  bed’s  operation  allowed  to  the  team  to  begin  formulating  ideas  to  increase  the  efficiency  of  the 
original adapter. 
 
   

68 

 
 Approach  3 

The  early  stages  of  the  project  involved  the  development  of  three  methods  for  creating  an 
efficient wall adapter.  All three solutions address the efficiency of the adapter while approaching the 
problem  in  different  ways.    Once  three  ideas  were  formulated,  each  proposed  method  was  evaluated 
according to a particular set of criteria, producing the most viable idea.  Next, two general approaches 
were developed to achieve desired functionality.  At this point, a detailed design was needed to properly 
evaluate the remaining options. 
 

Initial Proposals 3.1

   
In  order  to  formulate  ideas  for  an  efficient  wall  adapter,  it  was  necessary  to  address  the 
specification goals outlined in Chapter 1.  A low‐current sense subcircuit would be required to measure 
the output current and determine if its value is below the threshold built into the design.  Secondly, a 
power interrupt circuit is needed to deactivate or reactivate the adapter according to readings from the 
low‐current sense.  Finally, an interface will have to be developed between the two so the low‐current 
sense  readings  and  decisions  will  be  relayed  to  the  power  interrupt.    Therefore,  three  specific 
approaches  to  developing  these  stages  were  designed  on  a  functional  level  to  meet  the  specified 
requirements.    Each  of  these  solutions  will  be  illustrated  in  relation  to  the  simplified  model  of  the  AC 
adapter, established in Chapter 2.  It is provided for reference in Figure 3‐1. 

 
Figure 3‐1: Simplified functional diagram of a modern switch mode power supply. 
69 

 
Polling Timer 3.1.1
 
Functionally,  there  are  two  fundamental  ways  to  actively  monitor  and  record  voltages  and 
currents  in  a  circuit.    Both  of  these  ways  are  similar  to  their  software  counterparts,  and  perform 
identical functionality in different ways.  In programming, the first of these methods involves executing a 
while  loop  continuously  under  a  certain  condition.    This  behavior  is  called  polling,  as  the  loop 

repeatedly runs a set code while the Boolean expression given is true.  In analog design, polling can be 
realized with a timer IC.   
In  whatever  manner  it  is  implemented,  the  timer  activates  monitoring  circuitry  and  adapter 
functionality  periodically  according  to  a  configured  timescale.    In  the  adapter  design,  it  is  desired  to 
activate polling only when the load is disconnected.  Otherwise, the timer needlessly polls the adapter 
while a load is connected.  Therefore, the monitoring circuitry detects the DC current draw and signals 
the interruption circuit to either turn the adapter off or leave the adapter on according to the reading.  
When the adapter’s power throughput drops below typical active levels, the power interruption circuit 
disables  as  many  components  as  allowable.    Since  the  timer  reactivates  the  adapter  periodically,  the 
previously  mentioned  monitoring  circuitry  will  have  regular  opportunities  to  reassess  whether  the 
adapter should remain idle, or whether it is needed for sourcing a device.  The interruption circuit can 
then respond accordingly.  The relationship of these subcircuits is illustrated in Figure 3‐2. 
 

70 

 
  
Figure  3‐2:  Top‐level  schematic  of  Polling  Timer  implementation.    Using  some  form  of  current  sensing  at  the 
output of the adapter, the Low‐Current Detection stage alerts the Interrupt Switch, which disconnects the input 
to  the  adapter.    The  Timing  circuitry  periodically  deactivates  the  Interrupt  Switch,  allowing  the  Low‐Current 
Detection to re‐evaluate the adapter’s current state. 

The  benefits  of  using  this  solution  are  threefold.    One  prime  advantage  of  utilizing  the  polling 
timer  solution  is  that  it  can  be  used  in  any  adapter  configuration.    Since  the  solution  needs  only  to 
monitor an output and disconnect an input, it does not rely on any of the existing adapter circuitry.  This 
non‐reliance allows the solution to be self‐contained and modular.  Another benefit of the polling timer 
circuit is that the configuration is reliable.  The polling feature allows room for error since the next poll 
can rectify any potential miscalculations, and the adapter will never become permanently dormant. 
Of  course,  there  are  also  some  drawbacks  of  implementing  this  solution.    While  the  self‐
containment of the device is a benefit in implementation and versatility, it adversely affects the cost of 
71 

 
such  a  solution.    In  other  words,  all  components  used  in  the  solution  circuit  are  additional  to  the 
components  used  in  the  original  adapter  design.    Therefore,  it  is  unlikely  that  existing  parts  will  serve 
dual  purposes.    The  additional  circuitry  would  inevitably  increase  adapter  size  if  it  is  integrated  with 
present products. 
Finally,  it  should  be  noted  that  the  concept  of  polling  can  be  a  very  inefficient  technique  for 
monitoring  devices.    For  instance,  a  software  program  can  use  two  techniques  to  trigger  an  event:  
polling or interrupts.  Polling forces the processor to rerun the program code every so often, which in 
turn  forces  the  processor  to  run  constantly  until  the  event  is  triggered.    The  program  therefore  uses 
processing  power  that  could  otherwise  be  allocated  to  other  tasks.    An  interrupt  is  the  most  efficient 
technique  because  it  interrupts  the  processor’s  operation  to  trigger  an  event  only  when  a  certain 
condition  is  met.    Since  processing  power  in  this  analogy  is  similar  to  power  consumption,  an  ideal 
solution would have the ability to inform the adapter when a certain condition is met (i.e., when the cell 
phone is plugged in).   
 

Jump Start 3.1.2

 
Building  off  the  idea  that  an  ideal  solution  would  utilize  interrupts,  the  team  concocted  its 
second  solution,  nicknamed  the  Jump  Start.    Illustrated  in  Figure  3‐3,  this  configuration  utilizes  the 
interrupt technique to reactivate the adapter after a disconnection.  The solution works in a similar way 
to the Polling Timer idea, in that when low‐current throughput is detected, the adapter is deactivated.  
However, instead of polling, the adapter only responds to an external trigger.  When the user connects 
the cell phone, the remaining charge from the phone’s battery triggers the current‐sensing circuit.  The 
sensing circuit flips the interrupt switch to reconnect the AC input to the adapter, effectively restarting 
the entire adapter.  Conversely, when the user disconnects the cell phone from the adapter, the current 
sense  signals  the  interrupt  switch  to  disconnect  the  AC  mains  from  the  adapter.    Since  batteries  in 
rechargeable devices are rarely completely depleted of energy, this technique should work even at the 
most critical of battery charge levels.  However, to prevent an adapter from becoming inoperable due to  
insufficient battery charge, a simple pin‐hole manual reset switch could be implemented that would re‐
enable the supply. 
 

72 

 
  
Figure 3‐3: Top‐level schematic of Jump Start implementation.  Using some form of current sensing at the output 
of the adapter, the Low‐Current Detection stage alerts the Interrupt Switch, which disconnects the input to the 
adapter.  The Reverse‐Current Activation deactivates the Interrupt Switch using residual power in a reconnected 
load device. 

The Jump Start configuration has many positive aspects that advocate its implementation.  Since 
a  deactivated  adapter  receives  power  from  the  external  interrupt,  the  adapter  can  be  completely 
disconnected from the AC mains when idle.  In addition, the current‐controlled switch and monitoring 
components require little additional circuitry to be added to adapters. 
Although this solution may seem ideal, the Jump Start does contain a critical inherent flaw.  The 
configuration  depends  on  the  energy  from  an  external  source  (which  is  a  cell  phone  battery  in  this 
particular application).  This flaw would become a major obstacle if the cell phone battery contained too 

73 

 
little energy to jump start the adapter.  The manual reset option allows adapter functionality to resume, 
but this is an inconvenience that the consumer should not have to endure. 
 

Hijack 3.1.3
 
The Hijack solution was the third idea formulated by the team, and is illustrated in Figure 3‐4.  
The Hijack uses existing adapter functionality to consume little power when no load is attached to the 
output.    In  the  previously  discussed  ON  Semiconductor  2.5W  Low‐Power  Cell  Phone  Charger,  the 
NCP1011  high‐frequency  switching  IC  contains  a  low‐power  standby  function  [28].    The  current 
configuration  utilizes  this  function  when  high‐current  conditions  are  detected  to  prevent  potential 
overloads.    In  the  original  configuration,  high  output  current  is  detected  by  a  PNP  transistor  switch.  
When  the  PNP  turns  on, current  is  sourced  to  the  optoisolator.   The  activated  optoisolator  shorts  the 
feedback  pin  on  the  NCP1011  Switcher  to  AC  ground,  forcing  the  IC  into  the  low‐power  standby 
function.  The Hijack idea reapplies this standby function to the detection of a no‐load output current.  
When a no‐load current is detected, the Hijack sends feedback to the IC, which would in turn cause the 
adapter to transition into standby mode. 
 

74 

 
  
Figure 3‐4: Top‐level schematic of hijack implementation.  Using some form of current sense at the output of the 
adapter, the Low‐Current Detection stage triggers pre‐existing reduced power state in the switching IC, typically 
reserved for high‐current protection. 

The Hijack’s main selling point is that it requires little additional circuitry to implement for the 
concerned  adapter.    The  high‐current  sense  arrangement  on  the  output  would  simply  have  to  be 
manipulated so that the optoisolator is triggered during no‐load current conditions in addition to high‐
current conditions.  Moreover, adapter size does not have to be increased since little additional circuitry 
is required. 
However,  while  the  idea  requires  few  design  changes  to  be  made,  there  are  quite  a  few 
drawbacks to using the Hijack.  First, the switcher IC must remain powered in order for the adapter to 
operate  in  standby.    It  is  therefore  impossible  to  disconnect  all  power  to  the  adapter  during  idle‐use 
periods.    Moreover,  the  IC’s  latch‐off  mode  is  not  consistent  with  all  input  voltages.    In  other  words, 
power savings are not consistent across different AC power signals, so savings would be unpredictable.  
The biggest drawback, however, is that the configuration is not universal for all SMPS AC adapters.  This 
particular configuration utilizes a unique function of a specific IC from a certain adapter design.  Other 

75 

 
SMPS adapters do not have the NCP1011 IC to utilize for a low‐power standby function,  so the Hijack 
could not be implemented. 
 
Evaluation 3.2
   
After  creating  three  approaches  to  address  inefficiencies  of  the  original  adapter,  it  became 
necessary  to  evaluate  each  approach  against  the  others  in  terms  of  both  plausibility  and  potential 
reward.    Assessing  all  ideas  critically  allowed  the  team  to  make  an  educated  choice  for  preliminary 
design.   The Jump Start idea seemed to be the ideal implementation since it would allow the adapter to 
consume 0W during standby.  However, the Jump Start’s dependence on an external source outweighed 
its  potential  to  eliminate  standby  power  consumption.    Moreover,  the  team  discovered  during  initial 
tests with a sample cell phone that adapter reactivation via the load battery was impossible.  Even with 
a fully‐charged battery, 0V was observed across the power connections to the phone.  This is likely due 
to the phone’s internal circuitry which prevents battery discharge through the adapter. 
The  elimination  of  the  Jump  Start  as  a  potential  candidate  left  the  Polling  Timer  and  Hijack 
approaches for building an efficient wall adapter.  The Hijack seemed like the next logical choice seeing 
that it required little additional circuitry for its implementation.   However, the first problem associated 
with implementing the Hijack was that it relied too heavily on specific power adapter technology, such 
as the power saving modes of the NCP1011 switching IC.  The team preferred a solution that would be 
applicable to any power adapter. 
The  effectiveness  of  the  Hijack  was  another  concern.    While  building  the  test  bed,  the  team 
recorded waveforms of the NCP1011’s output (pin 5).   Figure 2‐36 below shows the IC’s typical active 
output characteristic, as well as the output of the same pin taken after the adapter had entered its low‐
power  protection  mode.    While  there  is  some  reduction  in  the  amplitude  and  frequency  of  the  minor 
oscillations, the base oscillations still occur at 100kHz while the switcher moves in and out of low‐power 
mode.  Such constant oscillations were considered to be far too wasteful, a point supported by the data 
sheet proclaiming that the low‐power latch‐off mode allows the adapter to consume under 0.3W during 
standby [28].  Considering the team’s goal was to reduce the original adapter’s consumption by at least 
75%,  the  Hijack  implementation  would  not  provide  sufficient  improvement  to  meet  the  stated  power 
consumption requirement.  
 

76 

 
 Switching IC continues oscillating with slightly less 
amplitude but the same base frequency in protection mode 

    
 Figure 3‐5: Active switching IC output (left), low power switching IC output (right).  Note that even in low power 
mode, there is still a significant amount of 100kHz activity produced by the IC.  Since the Hijack idea relies on 
this mode, it would not be able to reduce power consumption much below 300mW. 

  Having logically eliminated two of the three original propositions, the team was left to further 
develop the Polling Timer idea.  Each of the team’s ideas for the Polling Timer had two main functions in 
common: current sensing and power interrupt.  It was necessary to first decide at a top level how both 
of these subcircuits would be implemented. 

 
Current Sensing 3.2.1
 
In  order  to  deactivate  the  adapter  under  appropriate  circumstances  and  decrease  idle  power 
consumption, the solution must have circuitry that can sense current.  The ability to sense current would 
allow  the  adapter  to  identify  when  a  load  is  connected  and  decide  whether  it  is  appropriate  to 
deactivate.  The team reasoned that the easiest way to identify such a standby condition was to monitor 
the current flowing through the output of the adapter.  Several current‐sensing options were proposed 
by  the  team  as  potential  choices  for  the  current‐sensing  stage.    These  ideas  fell  into  one  of  two 
categories:    magnetic  devices  or  resistive  devices.    The  following  section  describes  the  physical 
characteristics and operations of each device and reveals how the team made its choice. 

Hall Effect Sensor 

Hall Effect sensors utilize the Lorenz Force to output a voltage that is linearly proportional to the 
input current within a specified range.  This effect was discovered by Edwin Hall in 1879 [37].  When an 

77 

 
electrical carrier carries a current of charge, and this carrier experiences an external uniform magnetic 
field,  a  force  called  the  Lorenz  Force  acts  perpendicular  to  both  the  current  and  the  direction  of  the 
magnetic flux density.  Mathematically, this force is expressed as: 
  (3‐1) 
The value q is representative of a particle’s charge, u is the velocity of the particle, and B is the magnetic 
flux density.  Figure 3‐6 shows the direction of the Lorenz Force according to the configuration. 
 

Figure 3‐6: NIST Representation of Hall Effect [37]. 

  The  Lorenz  Force  is  directed  out  of  the  page  in  the  above  arrangement.    If  an  electrical 
conductor is placed in series with the current, the electron paths through the conductor will be arched 
toward the side of the Lorenz Force (out of the page).  The arched path allows a buildup of charge on 
the side coming out of the page which in turn creates a potential difference between both narrow sides 
of the conductor, as indicated in Figure 3‐6.  This voltage is termed the Hall voltage.  The Hall Effect is a 
powerful tool that allows a circuit to monitor current. 
  Hall  Effect  sensors  exclusively  monitor  RMS  current  and  output  a  proportional  small  signal  AC 
voltage  with  a  DC  offset.    If  the  application  is  set  up  to  monitor  DC  voltage,  small  signal  AC  can  be 
78 

 
eliminated  using  a  filter  capacitor,  while  the  DC  offset  can  be  eliminated  using  a  coupling  capacitor.  
From  this  point  on  the  representative  DC  voltage  can  be  analyzed  using  digital  or  analog  comparing 
techniques.    Schmitt  triggers  and  other  op‐amp‐based  comparators  are  possible  solutions  for  analog 
comparison of voltages while a combination of logic gates and ADCs and DACs provide a possible digital 
comparator circuit.  Finally, an interrupt switch would be implemented to disconnect or reconnect the 
adapter  according  to  the  comparator  output.    Latching  relays  and  power  MOSFETs  are  two 
considerations for the interrupt switch. 
  The principle downside to Hall Effect sensors is their overall cost to implement.  The sensor itself 
is can cost over $1 per unit, and around $0.50 per unit in bundles of 1,000 [38].  Moreover, amplifiers 
and comparators are required to monitor the Hall voltage appropriately.  Collectively, the cost of a Hall 
Effect centered current monitor can be very expensive relative to the cost of the end product. 

Current Transformer 

  A current transformer is designed around the principle of coupled inductors with an iron core.  
Its basic schematic is shown in Figure 3‐7 [39].  AC current is sent through the primary winding of the 
coupled configuration, causing a magnetic flux to appear in the iron core.  The magnetic flux also varies 
in  value  causing  a  current  to  flow  through  the  secondary  winding.    According  to  Faraday’s  Law  this 
alternating magnetic flux is related to the coil voltage by: 

    (3‐2) 

Similarly, the secondary voltage can also be related to the same magnetic flux: 

    (3‐3) 

The  terms  Np  and  Ns  refer  to  each  coil’s  number  of  turns.    Dividing  one  equation  by  the  other  gives  a 
ratio of: 

    (3‐4) 

In an ideal transformer, the conservation of energy dictates that the power input must equal the power 
output.   In other words, 

    (3‐5) 

According  to  (3‐5),  the  currents  through  the  primary  and  secondary  coils  are  also  proportional  to  the 
turn ratio. 

79 

 
  

Figure 3‐7: Schematic of an ideal transformer [39]. 

Similar  to  the  Hall  Effect  sensor,  the  current  transformer  implementation  would  require 
additional  circuitry  to  process  the  output  of  the  transformer  and  activate  an  interrupt  switch 
accordingly.  The same comparing and interrupt switching techniques outlined in the Hall Effect sensor 
section would also be considered for the current transformer current detector. 
The main downside of the current transformer is its inefficiency.  Real current transformers are 
unable  to  output  power  equal  to  its  input  power  due  to  internal  losses.    Leakage  currents  and 
magnetizing inductances in the transformer dissipate a fraction of the input power.  In addition, the size 
and  cost  of  current  transformers  are  large  compared  to  other  electrical  components,  causing  the  end 
product to become much larger, heavier, and more expensive than originally planned. 

Difference Amplifier IC 

Analog  Devices  offers  a  product  called  the  ADM4073:  Low  Cost,  Voltage  Output,  High‐side 
Current Sense Amplifier [40].  The IC utilizes an internal op‐amp in an adder configuration biased with 
resistors  to  apply  to  one  input  a  gain  of  1,  and  the  other  input  a  gain  of  ‐1.    The  ADM4073  could  be 
applied  to  the  current‐sensing  circuit  exactly  as  suggested  in  the  schematic  in  Figure  3‐8,  with  Rsense 
placed  in  series  with  the  DC  output  of  the  adapter.    Vout  on  the  IC  would  then  provide  the  current‐
sensing system with a voltage proportional to Iload.  When the adapter’s current drops, such as when a 
load  device  is  unplugged,  the  output  voltage  of  the  IC  would  also  drop.    This  output  voltage  could  be 
used  by  the  current‐sensing  stage,  sending  an  alert  to  the  power  disconnect  stage  when  the  output 
current drops below the specified threshold. 

80 

 
  

Figure 3‐8: ADM4073 Low Cost, Voltage Output, High‐Side, Current‐Sense Amplifier Internal Schematic [40]. 

  Pre‐built  for  a  current‐sensing  application,  the  ADM4073  would  represent  the  easiest  of  the 
possible approaches to implement.  However, it also has three potential setbacks.   

1. Cost.  The ADM4073 is currently priced at $0.60 for 1000 pieces from Analog Devices [41].  While 
it was possible the team could fit this into its solution budget of approximately $1, it was higher 
than preferred. 
2. Any tuning that may have to be done with regard to the Iload  to Vout relationship and interfacing 
with the interrupt stage would have to be done externally since the IC is pre‐built. 
3. The  device’s  need  for  supply  voltage.    As  an  active  device,  it  will  need  a  dedicated  power 
connection to operate, and while the required current is a low 500µA, ensuring that it remains 
powered  when  needed  presents  an  additional  complication  for  the  circuit’s  overall  layout  and 
operation. 
 

81 

 
Custom Difference Amplifier  
 
Often  referred  to  as  a  high‐side  current‐sensing  amplifier,  this  circuit  is  a  custom 
implementation  of  the  Analog  Devices  ADM4073  IC  described  previously  [40].    The  high‐side  current‐
sense  amplifier  refers  to  the  placement  of  the  current‐sensing  resistor  between  the  source  and  load, 
which  avoids  adding  resistance  to  the  ground  of  the  circuit.    Similar  to  the  implementation  of  the 
ADM4073,  load  current  passing  through  the  sensing  resistor  develops  a  linearly  proportional  voltage 
across  that  resistor,  according  to  Ohm’s  Law.    This  voltage  is  amplified  by  the  op‐amp  and  then 
subsequently used to drive the MOSFET, drawing current through R.  The voltage drop across R would 
be equal to the voltage drop across the sensing resistor, allowing the following calculation: 
 
  (3‐6) 

  (3‐7) 

  (3‐8) 

 
The  sensor  output  voltage  is  proportional  to  the  load  current  as  derived  by  (3‐8).    A  current 
mirror  can  be  included  to  amplify  the  output  current  by  a  factor  of  K,  if  a  larger  output  voltage  is 
desired.  The entire schematic is shown in Figure 3‐9  [40]. 

82 

 
  

Figure 3‐9: Current‐sensing amplifier outputs a voltage proportional to the load current [40]. 

  This  approach  to  current  sensing  offers  a  couple  potential  benefits  over  buying  the  pre‐built 
Analog Devices implementation.   

1. Buying an inexpensive op‐amp allows the custom difference amplifier to be more cost‐effective 
than the ADM4073.   
2. Each  component  in  the  custom  difference  amplifier  can  be  manipulated  to  produce  the 
appropriate output voltage. 

BJT­Based Current Detection with Input Interrupt 
 

  The  BJT‐based  current  detection  utilizes  a  current‐sensing  resistor  to  incur  a  voltage  drop 
proportional to the output current.  This technique is similar to the built‐in high current detection in the 
ON Semiconductor adapter configuration [27].  The proportional voltage is connected in parallel to the 
base  and  emitter  respectively  of  a  NPN  bipolar  junction  transistor  (BJT).    The  BJT  turns  on  when  the 
voltage  difference  is  around  0.65V  nominal.    If  the  BJT  is  turned  on,  it  operates  in  the  active  region, 
83 

 
allowing a large amount of current to flow through the collector and emitter terminals.  This current is 
directed  through  an  optocoupler  with  a  series  resistance.    The  resistance  drives  the  LED  within  the 
optocoupler when current is experienced.  When sufficient current flows through the LED, the switch on 
the opposite terminals of the optocoupler is activated.   

Figure 3‐10: Transistor‐Based Current Detection Schematic [27]. 

The  model  in  Figure  3‐10  exemplifies  the  general  implementation  of  the  current  sense.    The 
current source I1 represents the output current of the adapter,  which is 500mA.  Most of the current 
flows through current‐sensing resistor R1 while a small amount of current flows through the base of the 
2N3904 BJT.  When current through the 3Ω resistor produces a voltage of about 0.7V, the BJT turns on 
and  allows  current  to  flow  from  its  emitter  to  its  collector  terminals.    The  collector‐emitter  current 
equals the voltage across the 1kΩ resistor divided by its resistance, which is around 30mA.  The same 
current  activates  the  optocoupler.    Once  the  output  current  of  the  adapter  drops  below  200mA,  the 
voltage across the base and emitter of the BJT becomes less than 0.7V.  In effect, the transistor and the 
LED in the optocoupler are turned off. 
Once  the  presented  current‐sensing  ideas  were  conceived,  the  team  created  a  qualitatitive 
selection  table  for  the  various  methods.    This  way,  an  educated,  deliberate  decision  was  made  to 
implement each idea.  This is shown in  
 
Table 3‐1. 
 

 
84 

 
Table 3‐1: Qualitative Analysis of Current‐Sensing Devices. 

     
Transformer  Difference  Custom Diff. 
Hall Effect  BJT 
Based  Amplifier IC  Amplifier 
Cost‐Effectiveness  NO  NO  Yes  Yes  Yes 
Low Power  ‐‐‐  ‐‐‐  Yes  Yes  Yes 
Availability  ‐‐‐  ‐‐‐  Yes  Yes  Yes 
Durability  ‐‐‐  ‐‐‐  Yes  Yes  NO 
Ease of Manipulation  ‐‐‐  ‐‐‐  NO  Yes  ‐‐‐ 
Compactness  ‐‐‐  ‐‐‐  ‐‐‐  Yes  ‐‐‐ 
 
  The criteria shown in the first column of the table are listed in order of importance.  Since the 
purpose of the envisioned device is to save money, the final product must be designed for the smallest 
cost  possible.    The  Hall  Effect  and  transformer‐based  options  are  simply  too  expensive,  so  they  were 
quickly  eliminated  as  viable  options.    Low  power  consumption  is  an  inherent  requirement  for  an 
efficient  wall  adapter,  and  the  remaining  three  options  consume  a  negligable  amount  of  power 
compared to the overall consumption of the adapter.  Furthermore, each of the three current‐sensing 
devices are readily available at several electronic distributors.   
However, the BJT current‐sensing operation varies greatly with introduced temperature change.  
It was determined that the BJT current sensor was not plausible for the adapter design due to its high 
rate of variability during operation.  The pre‐built difference amplifier was also subsequently removed as 
a viable implementation.  Although the ADM4073 provides an integrated current‐sensing solution, the 
manipulation of internal components is not possible.  Since manipulation of the current sensing will be 
needed to obtain a threshold output current of 15mA, the custom difference amplifier implementation 
was chosen as the most beneficial approach to building a low‐current sense for the adapter. 

Power Interrupt 3.2.2

   
The power interrupt stage is vital to the Polling Timer’s power saving method.  In order to shut 
down or disconnect parts of the adapter to save power, a component capable of interrupting power is 
necessary.  Several power interrupt methods were discussed as potential choices to disconnect the high‐
voltage rail of the adapter from the primary winding of the transformer.  These ideas fell into one of two 
85 

 
categories:  semiconductor devices or electromechanical switches.  The TRIAC, power MOSFET, and the 
power  BJT  are  all  semiconductor  devices,  and  the  optorelay  is  an  electromechanical  switch.    The 
following section will describe the physical characteristics and operations of each device and present the 
criteria used in choosing the actual implementation. 
 

Power BJT 
 
  In  general,  power  transistors  are  similar  in  operation  compared  to  their  small‐signal 
counterparts.  However, power transistors are custom‐designed to handle higher voltages.  One of the 
primary advantages of using a power BJT is its high bandwidth and its isolation between the base and 
the  transistor’s  other  two  terminals.    It  is  also  capable  of  handling  high‐power  signals  between  its 
collector and emitter.  However, there are many downsides to using a power BJT as a disconnect device. 
  Power BJTs have relatively smaller gain factors compared to small signal BJT’s [42].  While a β‐
factor of 100 is typical for a small signal BJT, an active‐region amplification of 10 is not uncommon for a 
power  BJT.    The  small  β‐factor  of  the  power  BJT  necessitates  a  large  bias  current  at  the  base  of  the 
transistor in order to produce a large current through the collector and emitter terminals.  In addition, 
the β‐factor varies greatly with a change in temperature, which could pose a problem due to the heat 
dissipated by the transformer. 
 

Power MOSFET 
 

  Unlike the power BJT, a power MOSFET requires little input current to bias the device due to its 
gate isolation.  Moreover, it is well‐known that “the gates of some 10‐A power MOSFET’s can be driven 
by the output of standard logic gates" [42].  Furthermore, this driving current does not fluctuate greatly 
with  temperature  variation.    In  addition,  the  channel  resistance  is  designed  to  be  very  small,  which 
allows the input current from the AC line to pass through uninhibited. 
  One of the major downsides of using a power MOSFET is that the breakdown voltages between 
the drain and source and vice‐versa are not equivalent.  In other words, most power MOSFET’s are not 
able  to  handle  high‐voltage  AC  signals.    When  an  N‐Channel  MOSFET  is  placed  in  reverse  bias,  the 
reverse breakdown voltage is high, allowing much of the source current to flow.  On the other hand, if 
the  N‐Channel  MOSFET  is  placed  in  forward  bias,  the  breakdown  voltage  is  low.    Overall,  power 
86 

 
MOSFET’s are used widely in high‐power DC disconnect circuits, but not as an alternating‐current signal 
disconnect. 
 

TRIAC 
 
  The acronym TRIAC stands for triode for alternating currents.  It is therefore not surprising that 
TRIAC’s are used heavily in AC power applications like dimmer circuits.  Like other transistors, the TRIAC 
is driven via its gate terminal to allow current to flow through its anode and cathode terminals.  Unlike 
the power BJT, the TRIAC can be driven with a low power signal.  Therefore, the output of a logic gate or 
an operational amplifier would be suitable drivers of a TRIAC power disconnect. 
 

Relays 
 
  Relays  are  electromechanical  switches  that  rely  on  magnetism  to  physically  connect  and 
disconnect  contacts.    Unlike  semiconductor  devices,  relays  are  able  to  physically  break  a  circuit  and 
provide  total  isolation  between  the  break.    This  feature  allows  relays  to  be  effective  power  interrupt 
switches. 
  The types of relays chosen by the team for possible implementations was the optorelay and the 
latching relay.  The optorelay utilizes the principle design of an optoisolator but uses a relay in lieu of a 
transistor.  The latching relay is triggered at its gate and latches on one contact until a second trigger 
voltage is experienced.  The benefit of the optorelay is that it disconnects the input while maintaining 
isolation between the input and output stages.  The latching relay, on the other hand, holds its position 
even  when  the  gate  power  is  disconnecting,  providing  independence  from  a  constant  supply  power 
source. 
However,  because  of  its  mechanical  nature,  relays  have  inherent  flaws  for  relatively  small 
electronic  applications.    First,  relays  are  larger  in  size  compared  to  semiconductor  devices.    Since  AC 
adapters are small in nature, it would be difficiult to implement a relay in a cell phone wall adapter.  In 
addition, most relays require a significant bias current to drive.   
Table 3‐2 shows how each of the potential power interrupt devices were evaluated against the 
others.  Like Table 3‐1, the criteria listed in the first column of the table are in order of importance from 
top to bottom.  The first criterion used to evaluate the power interrupt devices was cost‐effectiveness.  

87 

 
The  capability  of  handling  high  voltage  is  next  in  importance  since  the  determined  method  must 
disconnect an input rated at 170V.  Low power consumption is third in the list to comply with one of the 
team’s  long  term  goals  of  lowering  power  consumption  of  the  adapter.    Thereafter,  the  chosen 
implementation must be widely available for future mass production. 
 
Table 3‐2: Qualitative Analysis on Power Interrupt Devices. 

 
Power 
Optorelay  TRIAC  BJT  Solid‐State Relay 
MOSFET 
Cost‐Effectiveness  Yes  NO  Yes  Yes  NO 
High Voltage Capability  Yes  ‐‐‐  Yes  Yes  ‐‐‐ 
Low Power  Yes  ‐‐‐  Yes  Yes  ‐‐‐ 
Availability  Yes  ‐‐‐  Yes  Yes  ‐‐‐ 
Durability  Yes  ‐‐‐  Yes  NO  ‐‐‐ 
Compactness  Yes  ‐‐‐  Yes  ‐‐‐  ‐‐‐ 
Ease of Switching  Yes  ‐‐‐  Yes  ‐‐‐  ‐‐‐ 
AC‐Disconnect   
Capability  NO  ‐‐‐  Yes  ‐‐‐  ‐‐‐ 
 
  After  evaluating  each  potential  method  by  its  cost‐effectivness,  the  three  semiconductor 
options  still  remained:    the  power  MOSFET,  the  TRIAC,  and  the  power  BJT.    Although  each  of  these 
devices is comparable in size, the power BJT has a small β‐factor, thus requiring a significant bias current 
to  drive  it.    Moreover,  active‐region  operation  of  the  power  BJT  introduces  unwanted  complication  in 
design.  Lastly, the power BJT is highly susceptible to voltage spikes and can fail under high‐temperature 
conditions (e.g.  heat from transformer).  It was for these reasons that the power BJT was dropped from 
the team’s power interrupt considerations. 
  The last criterion shown in Table 3‐2 is the AC disconnect capability.  While there are a multitude 
of  power  MOSFETs  that  can  handle  high‐voltage  DC  signals  across  their  drain  and  source  terminals, 
there are few that can withstand high‐voltage AC signals.  TRIACs, on the other hand, are designed for 
such  conditions.    Normally,  the  difference  between  disconnecting  the  power  before  and  after  the 
rectifier is negligible.  However, since the final product would ideally consume close to 0W during no‐
load conditions, the team chose the triac as their power disconnecting device. 

88 

 
 Consolidation 3.3
   
  After  evaluating  each  initial  proposal,  the  polling  timer  technique  was  chosen  as  the  team’s 
general approach to designing an efficient wall adapter.  In particular, it was determined that the polling 
timer would be designed with a low‐current sensing circuit as well as a power interrupt switch.  After 
critiquing  several  options  for  each,  the  custom  difference  amplifier  was  chosen  for  detecting  the 
adapter’s output current and the TRIAC was selected to activate and reactivate the adapter accordingly.  
The next step involved the further specification of the polling timer design.  The team first determined 
that there were two passive devices that could serve as the foundation of the control input to the timer:  
inductors  and  capacitors.    While  capacitors  charge  and  discharge  to  certain  voltages,  inductors  vary 
between  current  peaks  and  troughs.    However,  inductors  are  relatively  expensive  compared  to  their 
capacitive  counterparts.    In  addition,  the  team  previously  discovered  the  difficulties  of  monitoring 
current levels in a circuit.  These reasons encouraged the team in choosing a capacitive‐based control for 
the polling timer.   
  Once the polling method was defined, the team formulated ideas that utilized capacitive polling.  
Two  basic  implementations  were  discussed;  one  configuration  placed  the  capacitive  control  on  the 
output stage of the circuit, while the other arranged the control on the input side.  In order to determine 
which  implementation  was  most  logical,  the  team  analyzed  each  by  several  criteria:    size,  cost,  and 
power consumption.   
 

Capacitor-Based Polling Configuration 3.3.1

 

 
Figure 3‐11: First‐order RC circuit. 
 

89 

 
  In  order  to  meet  the  low‐power  specification  goal  stipulated  in  Chapter  1,  the  team  made  a 
concerted  effort  to  utilize  passive  components  as  much  as  possible.    The  passive  timer  consists  of  a 
simple,  first‐order  RC  circuit  whose  time  constant  is  determined  by  the  product  of  the  resistance  and 
capacitance as given in (3‐9). 
     (3‐9)   
For long delays between polling, a large combination of the resistance and capacitance is needed.  The 
time constant specifies the delay required for the output voltage to match 63% of the input voltage.  If a 
polling  duty  cycle  of  50%  is  desired,  the  capacitor  can  charge  during  polling  and  discharge  when 
dormant.   
 

 
Figure 3‐12: Example polling duty cycle of 50% for capacitive‐based polling method. 
 
The voltage across the capacitor Vc in Figure 3‐12 shows the charging and discharging characteristics of a 
capacitor. 
  Ideally,  this  particular  solution  would  involve  a  much  shorter  duty  cycle.    When  the  adapter 
polls, a large surge of current is experienced at the output, and power dissipation reaches a maximum.  
Therefore, keeping this polling as short as possible attenuates this surge.  The complication in obtaining 
the characteristic shown in Figure 10 is that it requires two time constants:  one for the charging voltage 
and another for the discharging voltage.   
 

90 

 
  
Figure 3‐13: Example polling duty cycle much less than 50% for capacitive‐based polling method. 
 
  The transient behavior of the capacitor during charging and discharging is the characteristic 
used to provide a passive way of polling the adapter.  The intended flow of such a system can be 
explained using the block diagram in Figure 3‐14. 

 
Figure 3‐14: Functional block diagram of efficient wall adapter with capacitive‐based polling. 

91 

 
  Prior  to  a  detailed  analysis  and  design  of  this  configuration,  the  team  ascertained  the  several 
advantages  and  disadvantages  of  using  the  capacitive‐based  polling  method.    In  terms  of  cost,  the 
natural  inclination  of  purchasing  one  capacitor  instead  of  multiple  components  for  a  timing  subcircuit 
suggests a benefit.  However, large‐value capacitors required for such a circuit may be large in physical 
size as well, providing complications in implementing the circuit into a present adapter.  In addition, the 
power  consumption  of  this  method  is  questionable,  since  extra  energy  will  be  required  to  charge  the 
capacitor  to  the  proper  voltage.    Moreover,  power  surges  caused  by  the  constant  reactivation  of  the 
adapter  may  increase  power  consumption.    Although  simplistic  in  operation,  the  capacitive‐based 
polling timer may provide many complications if implemented in the adapter. 

Monostable Multivibrator-Based Polling Configuration 3.3.2

 

 
Figure 3‐15:  Schematic for adapter reactivation.  The TLC555 subcircuit periodically reactivates the P‐Channel 
MOSFET  to  re‐enable  connection  between  the  top  voltage  rail  to  the  transformer.    The  Zener‐based  voltage 
regulator provides the necessary voltage level to the TLC555 subcircuit. 
 
  Clearly, the capacitive‐based polling timer has inherent flaws that must be addressed during the 
design  phases.    An  alternative  to  this  configuration  is  one  built  around  a  timer  IC.    The  multivibrator‐
based polling timer uses a low power oscillator to drive the adapter on and off.  One of the most popular 
timer IC's on the market is the 555 timer.  The following table overviews the 555 timer's pin descriptions 
[43]: 
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Table 3‐3: Pin Descriptions of 555 Timer [43]. 
Pin #  Pin Label  Description 
1  Ground  Reference Voltage 
2  Trigger  High Signal Starts Timer 
3  Output  Output of Timer 
4  Reset  Low Signal Stops Timer 
5  Control Voltage  Allows Manipulation of Cycle 
6  Threshold  Allows Normal Cycle to go Low 
7  Discharge  Timing Capacitor Discharges through Pin 
8  VDD  Supply Power 
   
Using  the  pin  layout  described  above,  the  timer  can  operate  in  several  multivibrator  modes:  
astable,  monostable,  or  bistable.    The  astable  multivibrator  is  one  of  the  most  popular  timer 
configurations due to its perpetual operation.  In fact, the team considered using this configuration in 
the polling circuit.  However, its constant operation is also a drawback.  Even if a load was connected at 
the output, an astable multivibrator, by definition, would not settle into a stable state, but would rather 
continue  polling  the  adapter.    Polling  while  a  load  is  connected  does  not  necessarily  disrupt 
functionality,  but  repeats  a  needless  task.    Therefore,  the  team  chose  to  operate  the  timer  in 
monostable mode. 
  A monostable multivibrator, like its astable counterpart, operates continuously regardless of its 
output state.  However, unlike the astable multivibrator, a monostable multivibrator operates under one 
stable output condition.  In order to disrupt this steady output, a signal must be sent to the trigger pin of 
the 555 timer.  The timer remains in the unstable state until the designated time period expires.  At this 
moment, the output switches levels and returns to the stable state.  For the polling timer approach, this 
interrupt event would occur during low‐current conditions on the output.  The event would cause the 
trigger pin to switch from low to high, turning off the adapter.  After a programmed amount of time, the 
output would return high, activating the adapter.    

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Figure 3‐16: Example polling cycle of monostable multivibrator [44]. 
 
The first two pulses in Figure 3‐16 resemble the temporary reactivation of the adapter.  When the circuit 
determines an insufficient amount of current is being drawn by the output, the monostable 555 timer 
returns to a low state, effectively deactivating the adapter.  The third reactivation resembles the output 
voltage when a DC load is connected.  At this point, the 555 timer returns to its stable state, leaving the 
adapter active.   
  The 555 timer subcircuit is shown below for monostable mode.  Resistors R and capacitor C form 
the RC timing circuit for the unstable region of operation.  This configuration was chosen as the baseline 
design for the polling timer. 
 

 
Figure 3‐17: Schematic showing monostable configuration of the TS555 timer [44]. 

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  Overall,  it  seems  that  the  monostable  multivibrator‐based  polling  timer  has  several  positives 
that make it an attractive choice.  However, there are two key drawbacks to this implementation.  Along 
with  the  possible  cost  increase  of  a  monostable  configuration,  the  multivibrator‐based  polling  timer 
must operate on the AC‐side of the adapter.  The absolute maximum supply voltage for the 555 timer is 
18V,  so  a  voltage  of  170V  is  incompatible.    Therefore,  a  voltage  regulator  is  needed  to  supply  the 
necessary power to the 555 timer subcircuit. 
    

 
Figure 3‐18: Functional Block Diagram of Adapter with Monostable Multivibrator Polling. 

 
  Once the team determined the means to power the multivibrator subcircuit, a functional block 
diagram  of  the  entire  adapter  circuit  was  created,  shown  in  Figure  3‐18.    The  next  step  involves  the 
analysis of each functional block in order to determine the detailed design of the entire system. 
  This chapter determined the following important points: 
• A polling timer would be used as the foundation of the efficient adapter design. 
• A  custom  difference  amplifier  would  serve  as  a  basis  for  designing  the  current‐sensing 
subcircuit. 
• A TRIAC would serve as the basis for designing the power disconnect subcircuit. 
• A monostable multivibrator would be used to implement the polling, or periodic reactivation of 
the adapter. 
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 Detailed Design  4 

Once preliminary design was completed for each functional block of the proposed solution, the 
team  began  implementing  each  stage  at  the  component  level.    While  two  separate  techniques  are 
presented  for  periodic  adapter  reactivation,  the  manner  in  which  the  output  current  was  detected  as 
well as how the input to the adapter was disconnected from remainder of the circuit is consistent for 
both approaches.  Therefore, this section describes the systematic progression of designing the current‐
sensing and power interrupt functionality of the efficient wall adapter. 
Looking at the specification goals of this project, the additional circuitry must reduce the power 
consumption by 75% while only adding $1.30 to the overall cost of the adapter.  Therefore, the following 
guidelines were used while designing the added circuit stages: 
1. A large majority of additional components should be passive 
2. Only basic ICs should be implemented (op‐amps, optocouplers, timers) 
3. Capacity of energy storage devices (i.e., capacitors and inductors) should be minimized 
The  list  of  guidelines  above  allowed  the  team  to  design  an  efficient  wall  adapter  that  met  the 
specification goals outlined for this project.    
 

Low-Current Sensing Circuit 4.1

In  the  previous  chapter,  a  functional  flowchart  was  presented  to  demonstrate  low‐current 
sensing functionality.  In addition, it was determined that the team would use a difference amplifier and 
current‐sensing  resistor  combination  to  measure  the  output  current.    Since  a  current‐sensing  resistor 
already exists in the original adapter design, the team used resistor R4 for low‐current sensing as well.  
The functional diagram in Figure 4‐1 lists the interface stages required to process the information from 
the current‐sensing circuit in order to make a decision with regards to raising the low‐current flag. 

96 

 
  
Figure 4‐1: Processing diagram for current sense stage of proposed solution, from sensing resistor to flag output. 
 
As current flows through the DC top rail, a proportional voltage drop appears across resistor R4.  
The magnitude of the voltage is on the scale of tens of mV, so measuring the output current according 
to  the  proportional  voltage  drop  across  R4  is  difficult  using  basic  electrical  components.    In  fact,  an 
output current of 50mA produces a voltage drop across R4 of 60mV.   
97 

 
 In  order  to  appropriately  measure  the  current,  the  proportional  voltage  must  be  amplified.  
Once  the  voltage  drop  across  the  current  sense  resistor  is  amplified  between  0V  and  5V,  the  output 
current can be effectively measured.  Despite amplification, the proportionality between the amplified 
voltage and the output current around the 15mA threshold is linear.  Therefore, the amplified voltage is 
indicative of the output current for measured currents around 15mA.   
To determine whether the measured output current is above or below the threshold of 15mA, a 
reference voltage indicative of a 15mA output current is required for comparison.  The sensing circuitry 
can then make a simple one‐to‐one comparison of the amplified voltage and the reference voltage.  If 
the amplified voltage is greater than the reference, the low‐current sense should take no action, since 
the  output  current  is  sufficiently  high.    However,  if  the  amplified  voltage  is  less  than  or  equal  to  the 
reference, the circuit must notify the power cutoff stage of a low‐current condition so the adapter can 
be deactivated temporarily due to an insufficient amount of output current.   
Once  the  functional  operation  of  sensing  circuitry  was  determined,  the  team  listed  a  set  of 
requirements for the low‐current sense subcircuit.  Methods required for functionality are: 
1. Measurement of the adapter’s output current 
2. Manipulation of current measurement for comparison with threshold value 
3. Comparison of reference indicative of threshold current to measured output current 
4. Notification of low‐current condition to input stage 
The  first  and  second  requirements  were  met  by  using  the  custom  difference  amplifier  with  a  current‐
sensing  resistor.    The  remaining  requirements  were  met  using  an  open  loop  comparator  and  an 
optoisolator.   
In analog design, the operational amplifier can be arranged to function as a digital gate.  Figure 
4‐2  shows  the  op‐amp  configured  as  an  open‐loop  amplifier  with  an  inverted  output.    If  the  voltage 
input VDIFF is higher than the reference voltage VREF, the voltage at VOUT will be low.  On the other hand, 
VOUT will be high if VDIFF is less than VREF.  In the open loop configuration, the voltage difference at the 
input  is  amplified  with  a  very  high  gain.    When  VDIFF  is  slightly  greater  than  VREF,  the  negative  voltage 
difference  between  the  non‐inverting  and  the  inverting  terminals  drive  VOUT  down  to  the  minimum 
possible output voltage.  In the same way, VOUT is pulled up to the maximum allowable output voltage 
when VDIFF is less than VREF due to a positive voltage difference between the input terminals.  If both VDIFF 
and VREF equal the same voltage, VOUT will equal the average of the supply rails.  When both inputs of the 
open loop comparator are equal, the amplifier is functioning at its DC operating point.  Many amplifiers 

98 

 
are designed with an output voltage of half the supply voltage range at the DC operating point.  For the 
comparator shown in Figure 4‐2, VOUT would equal 2.5V.  The three input scenarios and related output 
voltage conditions are shown in Table 4‐1. 
 

 
Figure  4‐2:  Inverting  open  loop  comparator  configuration  used  in  low‐current  sensing  for  proposed  solution; 
used to raise a flag high if sensing resistor’s voltage is low, and vice‐versa.  Also sets the cutoff level with VREF. 

 
Table 4‐1: Input/output characteristic of inverting comparator (Figure 4‐2) for three possible input scenarios.  A 
flag voltage sufficient to activate the disconnect stage should be raised in any of the cases. 
Input Scenario  Output Behavior 
Vref>Vdiffamp  Vout ≈ 5V 
Vref=Vdiffamp  Vout ≈ 2.5V 
Vref<Vdiffamp  Vout ≈ 0V 
 
  Realistically,  operational  amplifiers  contain  non‐idealities  that  affect  their  operation.    For 
instance, the output of a general‐purpose op‐amp is only able to come within a few hundred mV of the 
supply rails.  This behavior is attributed to the internal MOSFETs of the output stage within the op‐amp.  
When  the  output  voltage  is  between  its  minimum  and  maximum  values,  the  MOSFETs  in  the  output 
stage operate in the active region.  However, when the voltage difference at the input drives the output 
toward a supply rail, one of the MOSFETs in the output stage is forced to operate in the triode region, 
causing the output voltage to converge before hitting the supply rails.  Another characteristic of an op‐
amp is a voltage offset at the input of the device.  Since all MOSFETs cannot be manufactured exactly to 
design parameters, a very small voltage difference is required between the non‐inverting and inverting 
inputs in order to obtain a 2.5V output.   
In the design of an efficient wall adapter, the input offset of a general‐purpose op‐amp will not 
adversely  affect  system  functionality.    Since  the  output  threshold  current  was  selected  to  be  a  value 

99 

 
much less than the smallest trickle current drawn by cell phone batteries [21], the comparator output 
will only change with the disconnect or the reconnect of an output load.  On the other hand, the output 
voltage  limits  must  be  taken  into  consideration  when  choosing  an  optoisolator.    Nevertheless,  the 
function  of  an  open‐loop  comparator  configuration  meets  the  third  requirement  for  the  low‐current 
sensing circuit design.   
Like  the  high‐current  sensing  circuitry  already  existent  in  the  original  adapter  design,  the  low‐
current  sense  needs  a  way  to  communicate  output  current  status  to  the  AC  side  of  the  adapter.  
Optoisolators are often used to relay information from one isolated circuit to the other.  The LED inside 
an optoisolator is placed in the circuit that communicates the information.  When the LED is turned on 
by one circuit, a photosensitive switch is closed to communicate the necessary information to the other 
circuit.  In the efficient wall adapter, the low‐current sense needs to be interfaced with an optoisolator 
to  alert  power  cutoff  circuitry  of  a  low  output  current  condition.    Figure  4‐3  shows  the  open  loop 
comparator  directly  connected  to  a  MOC3023  optoisolator  [45].    Theoretically,  the  output  of  the 
comparator  should  be  able  to  drive  the  LED  of  the  optoisolator  either  on  or  off.    However,  there  are 
many issues with connecting the LED directly to the output of the comparator. 
 

 
Figure  4‐3:  Theoretical  arrangement  of  inverting  comparator  and  LED  of  optoisolator.    However,  current  and 
voltage limitations must be overcome. 
 
  Fundamentally,  there  are  two  reasons  why  this  arrangement  will  not  function  as  expected.  
First,  an  activated  LED  incurs  a  specific  voltage  drop  and  requires  a  minimum  amount  of  current.  
Therefore, a resistor must be placed in series with the LED to incur the remaining voltage drop, as well 
as regulate the amount of current that flows through the LED.  Moreover, the output current limit of an 
op‐amp introduces another non‐ideality of the device.  However, if a transistor was used in an emitter 

100 

 
follower configuration, the output of the comparator would be able to drive the LED on and off without 
sourcing  an  excess  amount  of  current.    Figure  4‐4  shows  the  actual  implementation  of  low‐current 
sensing feedback circuitry. 
 

 
Figure 4‐4: Inverting comparator with current amplifier on output to drive LED.  This circuit should light properly 
and on command. 
 
  Assuming the comparator has a rail‐to‐rail output, VOUT can either be 5V or 0V.  If VOUT is equal to 
0V, the NPN BJT will operate in the cutoff region, since the voltage drop across the base‐emitter junction 
is 0V.  In effect, the LED will be off, and the voltage drop across the collector and emitter of the BJT will 
be 5V.  When VOUT is 5V,  the  base‐emitter voltage  drop will  be  around 0.7V  (if silicon‐based), and  the 
potential at the emitter of the BJT will be 4.3V.  Since the LED in the MOC3023 optoisolator is rated for a 
forward bias voltage drop of 1.15V, the voltage drop across resistor R22 will consequently be 3.15V.  As 
a  result,  around  9.5mA  would  flow  through  the  LED,  allowing  it  to  emit  light  given  that  the  minimum 
forward bias current rating is 5mA.   
Figure  4‐5  shows  a  comprehensive  schematic  of  low‐current  sense  circuitry.    The  difference 
amplifier  stage  precedes  the  comparator  and  optoisolator.    The  input  terminals  of  the  difference 
amplifier are connected across the current sense resistor R4, and its output is connected to the inverting 
input of the open loop comparator.  Once the general layout of the circuit was determined, the values of 
individual components were calculated. 

101 

 
  
Figure 4‐5: Preliminary schematic of low‐current sense stage prior to calculation of component values. 
 
  The OPA344 was chosen by the team to perform comparing and difference amplification for the 
low‐current  sense  circuit  since  it  was  a  rail‐to‐rail  input  and  output  op‐amp  compatible  for  a  single 
supply  of  5V  [46].    Although  other  less‐expensive  options  could  have  been  pursued,  the  OPA344  was 
readily available, so the team used it for both purposes during initial testing of the modified adapter. 
  Capacitor C12 is placed at the output of the comparator as a signal filter.  Since the adapter uses 
a switching frequency of 100kHz, high‐frequency behavior can be observed at output filter capacitor C4.  
To prevent the possibility of high‐frequency noise activating the LED in the optoisolator, capacitor C12 is 
chosen  large  enough  to  filter  unwanted  components  out  of  the  signal.      The  capacitance  of  C12  was 
chosen to be 10μF since it was both a sufficiently‐high value and a common component in the adapter. 
  Given a 1.2Ω value for R4, the ratio of resistances in the difference amplifier can be determined.  
According to equations specified in the last chapter for the difference amplifier, the output voltage of 
the subcircuit is as follows: 
, ,
    (4‐1) 
, ,

  The  output  of  the  difference  amplifier  is  simplified  by  (4‐1)  to  be  equal  to  the  voltage  drop 
across  R4  multiplied  by  the  ratio  of  the  resistances  in  the  configuration.    In  the  difference  amplifier, 

102 

 
resistances R10 and R12 are equal, and R9 and R11 have equal resistances.  Choosing the right values for 
resistors R9 through R12 was done according to system level requirements.  In particular, the difference 
amplifier needed to magnify the voltage drop to equal VREF when the output current was 15mA.  Initially, 
VREF  was  chosen  to  be  2.5V  to  provide  the  maximum  range  of  amplification  for  both  sufficient  and 
insufficient currents.  If the expected amplified voltage is divided by the measured voltage drop across 
R4, the gain of the difference amplifier can be estimated: 
, .
  140            (4‐2) 
, . Ω

In order for the output of the difference amplifier to be 2.5V, the ratio of R10 and R12 to R11 and R9 
must be at least 140.  Assuming that 5% tolerance resistors are used, the gain of the difference amplifier 
should be designed slightly above this calculation to compensate for variable resistances.  Therefore, a 
value of 2kΩ was chosen for R9 and R11.  R10 and R12 were assigned resistances of 360kΩ to provide an 
approximate gain of 180.  Ideally, the threshold current for the adapter is equal to 2.5V divided by the 
gain  of  180,  which  is  then  divided  by  the  1.2Ω  resistance  of  R4.    The  resulting  nominal  threshold  is 
11.6mA.   
  Next, the values of R14 and R13 can be determined since VREF is equal to 2.5V.  Accordingly, R14 
and R13 were set to 510kΩ in an effort to minimize power consumption of the voltage divider.  Resistors 
R20  and  R21  were  each  set  to  100kΩ  to  bias  the  inputs  to  the  comparator  equally.    Using  Kirchhoff’s 
Voltage Law (KVL), the maximum resistance of R22 was calculated: 
  0 4 0.7 1.15 0.005 0  (4‐3) 
  430Ω  (4‐4) 
To ensure consistent functionality, R22 was chosen to be 330Ω.  Figure 4‐6 depicts the first schematic of 
the current‐sense subcircuit with all appropriate component values included. 

103 

 
  
Figure 4‐6: First schematic of low‐current sense stage of proposed solution, with component values. 
 
  Given  a  DC  current,  a  proportional  voltage  is  produced  across  the  1.2Ω  resistor,  which  is 
amplified  by  approximately  180.    If  the  current  is  sufficiently  high,  the  comparator  output  will  remain 
low  and  the  current  amplifier  will  remain  off.    The  moment  this  current  falls  below  a  certain  value 
(between 10mA and 15mA), the amplified voltage will be less than the reference voltage of 2.5V, and 
the  comparator  will  be  driven  high.    NPN  BJT  Q2  will  provide  current  to  the  LED  of  the  MOC3023, 
signaling  a  low‐current  condition.    Since  this  stage  of  the  solution  includes  active  devices,  the  output 
current  will  be  monitored  as  long  as  the  adapter  is  on.    Once  the  adapter  is  deactivated,  the  current 
sense circuit shown in Figure 4‐6 will turn off.   
  The  low‐current  sense  stage  provides  all  necessary  processing  to  correctly  calculate  output 
voltage  and  to  signal  adapter  reactivation  when  appropriate.    The  first  requirement  stipulated  in  the 
104 

 
beginning of  this section is met using the current‐sensing resistor R4  to output a linearly proportional 
voltage  to  the  experienced  current.    The  voltage  drop  across  R4  is  appropriately  handled  through 
amplification, which is realized by the difference amplifier implementation.  The amplified output of the 
difference amplifier can be accurately compared to the reference voltage set by a simple resistor‐based 
voltage divider.  Depending on the level of output current, the feedback stage of the low‐current sense 
can alert the input stage of an undercurrent condition via the MOC3023 optoisolator.  In order to poll 
the adapter effectively, power cutoff and timing circuitry are required on the AC side of the adapter.   
  Earlier in this section, it was explained that the OPA344 was used for implementing the op‐amps 
in both the comparator and difference amplifier parts of the low‐current sense.  Although the OPA344 is 
low‐power and its input and output voltage range are rail‐to‐rail, the price of each op‐amp is expensive 
compared to the project’s overall budget (See Appendix A).   Consequently, a cost‐effective op‐amp with 
similar specifications was needed for the final design of the low‐current sense.   Texas Instruments also 
manufacturers  a  dual‐channel  operational  amplifier  IC  called  the  TLC27L2  [47].    This  particular  model 
was chosen for two reasons.   The cost of purchasing a dual‐channel IC was less than the total cost of 
two, one‐channel ICs, and the output voltage range is rated 1V less than the supply rail difference.  The 
TLC27L2  Dual‐Channel  Operational  Amplifier  [47]  from  Texas  Instruments  provides  a  cost‐efficient 
alternative to the OPA344 [46]. 
 

Adapter Cutoff and Reactivation Circuit 4.2

 
Once  the  low‐current  sensing  subcircuit  was  completed,  the  team  began  designing  the  power 
cutoff and reactivation circuitry.  Circuitry is required to reactivate or deactivate the adapter on the AC 
side of the circuit according to the output load condition.  Shown in Figure 4‐7 is the required processing 
flow of the cutoff circuitry. 

105 

 
  
Figure 4‐7:  Processing diagram for power cutoff stage of proposed solution, including low‐current flag reaction. 
 
  The flowchart begins with the initial condition that the output current level is sufficient and the 
adapter is operating normally.  At this point, the cutoff and reactivation subcircuit awaits input from the 
feedback  of  the  MOC3023  optoisolator.    If  the  output  current  condition  changes  from  normal  to  an 
excessive amount above the maximum rating, the subcircuit maintains stable operation since the high‐
current  sense  preconfigured  in  the  adapter  handles  such  cases.    However,  when  the  output  load  is 
disconnected,  the  MOC3023  triggers  the  cutoff  circuitry  to  deactivate  the  adapter.    Once  the  cutoff 
circuitry cuts the power connection to the primary winding of the transformer, the system waits for a 
determined period of time before reactivating the adapter.  While there is a no‐load condition on the 
adapter output, the flowchart follows the left‐hand process flow.  When a load is connected to the DC 
output, the process flow follows the right‐hand side of the chart.  The active nature of the cutoff and 
reactivation circuitry eliminates the possibility of a permanently deactivated adapter.   
Once  the  functional  operation  of  cutoff  and  reactivation  circuitry  was  determined,  the  team 
listed a set of requirements for the subcircuit.  Methods required for functionality were: 

106 

 
 1. Utilization of a TRIAC for adapter deactivation and reactivation 
2. Triggering polling of adapter during no‐load conditions via MOC3023 optoisolator 
3. Periodic reactivation of adapter during polling 
Unlike  the  low‐current  sensing  circuitry,  there  were  two  proposed  ideas  to  implement  the 
power cutoff function.  Although both methods used the polling timer approach described in Chapter 3, 
one design utilized active polling while the other depended on passively polling the adapter.   
 

555 Timer-Based Polling Method 4.2.1

 
555 timers are versatile ICs that are widely applied in many analog and digital circuits.  Using a 
combination of resistors and capacitors, the 555 timer can be implemented as a bistable, monostable, or 
astable  multivibrator.    Each  type  of  multivibrator  configuration  could  be  used  to  realize  the  periodic 
reactivation requirement for the power cutoff circuitry.  However, the 555 IC requires continuous power 
for proper operation.  Therefore, the timer must be powered whenever the adapter is plugged into the 
AC input, regardless of output load connectivity.  The problem with powering the 555 timer on the AC 
side of the isolation is producing a constant low DC voltage from a high‐voltage source.    
 Since most inexpensive 555 timers require input sources of 5V to 15V, the team analyzed ways 
to  step  down  the  170VDC  rail  to  a  workable  low‐voltage  signal.    Common  voltage  regulators,  such  as 
buck‐boost converters, are relatively expensive to purchase.  LED driver devices were also researched as 
a possibility,  like  the Supertex  HV9921  [48].   The Supertex HV9921 accepts a  DC voltage ranging from 
20V  to  400V  and  converts  it  into  a  7V  output.    While  the  Supertex  HV9921  was  cost‐effective,  it 
consumed a substantial amount of power, particularly between 175 mW and 300mW on its own [48].  It 
was finally determined that a Zener‐based voltage regulator provided the ideal solution.   
Zener  regulators  are  often  overlooked  as  a  voltage  converter  utility  because  they  operate  at 
poor efficiencies with high‐impedance loads.  For instance, a Zener diode may only deliver 100µA to the 
load  while  sinking  10mA.    However,  because  the  Zener  breakdown  voltage  is  only  around  3%  of  the 
supply  voltage  of  170V,  a  very  large  resistor  can  be  placed  as  a  pull‐up  resistor  between  the  diode’s 
anode  and  AC  ground.    The  presence  of  a  large  pull‐up  resistor  would  significantly  reduce  the  power 
consumed by the Zener regulator. 
  Using a Zener rectifying diode to step down voltage is a fairly simple process.  The 170VDC input 
to the converter encounters a series resistance.  This resistance is high in value in order to incur a large 

107 

 
portion  of  the  voltage  while  producing  a  low  current.    The  latter  part  of  the  converter  consists  of  the 
Zener  diode  and  the  555  timer  as  the  load.    The  1N5229B  breaks  down  in  the  neighborhood  of  4.3V 
given a minimum current of 20mA [49].  Since the timer is placed in parallel with the 1N5229B Zener, 
the 555 IC experiences the same voltage at its supply.  At a supply between 3V and 5V, the TS555 timer 
draws a nominal 250μA of current [44].  Therefore, the difference between the source current from the 
high‐voltage rail and the supply current of the timer is the sink current of the Zener diode.  There is no 
issue of damaging the diode in this configuration since the power rating of the 1N5229B is 500mW [49]. 
  The following scenario demonstrates the viability of this configuration.  The series resistance RS 
is  assigned  a  value  of  500kΩ  and  the  load  resistance  RL  is  assigned  a  value  of  12kΩ.    Although  the 
nominal value of the 1N5229B is 4.3V, the resulting voltage drop in this scenario will be 3.7V in order to 
limit power consumption.  If there is a 3.7V drop across the Zener, then there is a 166.3V drop across RS.  
The source current can then be calculated: 
.
  333   (4‐5) 

The source power, in turn, can also be determined: 
  170 56.5   (4‐6) 
Assuming this is the finalized value, the adapter’s standby consumption would be greatly reduced, since 
56.5mW is much less than the rated 300mW. 
  In the same manner, the load current can be found: 
.
  308   (4‐7) 

This value is slightly larger than the nominal supply current of 250μA, but can still represent an actual 
load current.  The sink current of the Zener diode is now found subtracting the source and load currents: 
  333 308 24.3   (4‐8) 
This current value is very small, allowing a majority of the source current to flow through the load.  The 
efficiency  of  this  regulator  is  attributed  to  the  large  attenuation  of  the  source  voltage  to  the  load 
voltage.    If  a  small  supply  voltage  was  applied  to  the  regulator,  the  sink  current  of  the  Zener  would 
become  a  larger  proportion  of  the  total  current  supplied  by  the  source,  effectively  decreasing  the 
efficiency of the system.   
The  netlist  and  schematic  shown  in  Figure  4‐8  represent  the  scenario  described  above.    The 
configuration was simulated in PSpice using a model created by Diodes, Inc. for the 1N5229B [50].   

108 

 
  

 
Figure  4‐8:    PSpice  schematic  and  netlist  of  Zener‐based  voltage  converter  for  supplying  power  to  555  timer; 
created to determine the viability of using the 170V adapter input to run a low power IC and associated circuitry 
[50]. 

The simulated circuit produced the plots shown in Figure 4‐9 and Figure 4‐10, which represent 
critical voltages, currents, and power values. 

Vast majority of the 170V drops 
across the series resistance… 

…but current remains low 
thanks to high resistance value 

Meanwhile, Zener holds load 
voltage to usable level 

Most of the current is delivered to the 
source rather than sunk through the resistor

 
Figure 4‐9:  PSpice simulation results; voltage and current plots for Zener‐based voltage converter configuration 
shown in Figure 4‐8 schematic.  Circuit appears to function as expected, creating a relatively small voltage drop 
across the Zener. 

109 

 
 Less than 25μA are 
lost through the Zener

With these conservative resistance values, about 55mW 
are wasted by the series resistance. This can likely be 
decreased depending on the required load current

A very small proportion of the energy is used 
by the load, but at least the 170V source has 
been rendered useable 

Lastly, the Zener diode is in 
no danger of overheating

 
Figure 4‐10:  PSpice simulation results; current and power plots for Zener‐based voltage converter configuration 
shown in Figure 4‐8 schematic.  Resistor and Zener values may need modification to save power and increase 
load voltage, but this step‐down application appears to work. 
 
  The  last  three  plots  show  the  power  consumption  calculations  for  RS,  RL,  and  X1.    The  power 
consumed by RS is very close to the source power of 56.5mW, since it experiences a large proportion of 
the  170V  source.    The  load  power  consumption  is  shown  to  be  around  1.1mW,  which  is  around  the 
1mW nominal supply power of the micro‐power 555 timer  [44].  Lastly, the Zener power consumption is 
under  100μW,  a  value  much  less  than  the  maximum  of  500mW.    Overall,  the  simulation  provided 
assurance of the Zener regulator operation.  Based on simulation and analysis, the team chose to use 
the Zener‐based voltage regulator to deliver the necessary power to the 555 timer subcircuit. 
After finding a viable way to power the 555 circuit, the team explored the possibility of using the 
MOC3023’s TRIAC output as the power interrupt switch.  The idea seemed plausible for initially shutting 
down the adapter, but it would be impossible to reactivate the adapter without breaching the isolation.  
Therefore, the team developed a way to disconnect the adapter while maintaining polling functionality. 
Initially,  the  power  cutoff  circuitry  for  the  adapter  was  designed  as  illustrated  in  Figure  4‐11.  
When  current  is  flowing  through  the  output  of  the  adapter,  the  current‐sensing  stage  keeps  the 
110 

 
MOC3023 active and the  input  current flowing regardless of the state of the  polling stage.  When the 
load device is unplugged and the current stops flowing, the current‐sensing stage will shut off the TRIAC, 
deactivating the adapter.  With the TRIAC deactivated, the only way for current to flow into the adapter 
is  through  the  MOSFET  in  the  lower  branch,  controlled  by  the  polling  circuit.    The  polling  circuit  now 
effectively has control over the entire adapter, which is desired while the adapter operates in standby. 
 

   
Figure 4‐11: Branching the input path for dual controls would allow for the current‐sensing circuitry to directly 
control  the  functionality  of  the  adapter  while  the  555  can  still  reactivate  it  from  the  opposite  side  of  the 
isolation barrier. 
 
The  schematic  in  Figure  4‐12  shows  the  planned  implementation  for  polling  the  adapter.    The 
rectified  AC  input  is  connected  to  the  top  rail  and  AC  ground.    The  Zener  is  chosen  to  have  a  5V 
breakdown voltage.  The resistor, on the other hand, takes on the remaining 165V.  The 5V across the 
Zener  is  connected  to  the  supply  terminals  of  the  555  timer  subcircuit,  which  includes  resistors  and 
capacitors, along with the actual IC.  The subcircuit outputs a trigger voltage with a low duty cycle.  The 
short time period when the 555 timer outputs a high voltage is set to be long enough to allow for the 
adapter’s reactivation.  The pulse drives a power MOSFET which intercepts the rectified AC line.  When 
the  MOSFET  experiences  a  sufficient  voltage  drop  across  its  gate  and  source  terminals,  the  adapter  is 
reactivated. 
 

111 

 
  
Figure  4‐12:    First  top‐level  drawing  of  the  adapter  polling  circuit  layout.    The  TLC555  subcircuit  periodically 
activates the P‐Channel  MOSFET,  which  impedes  the  top  voltage  rail  from  reaching  the  transformer’s primary 
winding.  The Zener‐based voltage regulator supplies the TLC555 subcircuit with an appropriate voltage. 
 

  Although  the  team  planned  on  using  an  N‐Channel  enhancement  mode  power  MOSFET  to 
deactivate  and  reactivate  the  adapter,  the  present  configuration  did  not  accommodate  its 
implementation.  Since the output of the 555 timer is 170V, the necessary voltage difference between 
the gate and source terminals of the MOSFET cannot be obtained.  The high output of the 555 timer was 
measured  at  around  170V,  and  the  low  output  was  measured  around  150V.    Therefore,  a  P‐Channel 
MOSFET  was  used  instead.    When  the  MOSFET  was  activated,  the  voltage  at  its  drain  terminal  was 
measured to be 168V.  In the case that the MOSFET was operating in the cutoff region, the voltage level 
at the drain drops to around 1mV.  Both of these voltages show that the adapter would be activated and 
deactivated effectively.   
Once the first two requirements were met for the cutoff circuitry, the polling requirement was 
met after the team decided the multivibrator operation of the 555 timer.  At first, the astable operation 
of  the  555  seemed  to  be  the  necessary  implementation.    However,  an  astable  multivibrator 
continuously polls regardless of adapter operation.  When the adapter is functioning normally with an 
output load, there is no need for the 555 timer to continue its polling behavior.   Therefore, the team 
investigated the possibility of a monostable multivibrator configuration.  The 555 timer’s output could 
be set to low during stable mode, which is when the adapter is in normal operation.  Then, using the 

112 

 
MOC3023 as an intermediary device, the 555 timer could be set to its polling operation during standby.   
In order to alert the 555 of a low‐current condition, the MOC3023 could be placed to switch the voltage 
at  the  trigger  pin  of  the  timer  to  the  555  IC’s  ground,  causing  the  output  to  transition  from  stable  to 
polling.    While  the  555  timer  is  unstable,  a  resistor  and  capacitor  combination  dictate  the  delays 
between polling.  While the output of the adapter has no load, the MOC3023 will repeatedly short the 
trigger pin of the 555 whenever the adapter is reactivated.  Only when a load is connected will the 555 
timer  resume  stable  mode,  and  the  adapter  will  consequently  resume  normal  operation.    The 
monostable operation of the 555 timer was chosen as the correct implementation to conserve energy 
while maintaining system functionality. 
 

 
Figure 4‐13: 555 timer configured for monostable operation; pulse time is determined by RC combination [44]. 
 
  In lieu of the TS555 timer, the ICM7555 was chosen due to its lower cost as well as its lower 
power consumption.  The resistor R and capacitor C were chosen in the monostable configuration 
shown in Figure 4‐13 so the polling period would equal approximately a minute.  Since higher‐rated 
resistors are less expensive than higher‐rated capacitors, a relatively large resistance value was chosen 
for R, and a medium‐sized capacitance was selected for C.  The team chose C to be 10µF, and R can be 
calculated.  In the monostable configuration, the polling period can be expressed by the following 
equation [44]: 
1.1                   (4‐9) 

113 

 
Therefore, in order to obtain a polling period of at least one minute, R must be greater than 5.45MΩ.  A 
value of 5.6MΩ was chosen for R since it is a standard 5% resistor value. 
  Using the resistor and capacitor combination as well as the trigger pin of the 555 timer, the 
monostable multivibrator configuration is able obtain long polling periods while consuming a minimal 
amount of power. 
 

Capacitive Polling Method 4.2.2

Although the 555 timer‐based polling circuit offers a low‐power method of polling the adapter, 
it  falls  short  of  providing  an  overall  power  consumption  of  0W.    Therefore,  the  team  designed  an 
alternative polling method that exclusively utilized passive components.  In order to create a circuit to 
perform this functionality, an energy storage device is required.  The rate at which energy is stored and 
discharged  from  the  device  determines  polling  frequency  of  the  adapter  during  standby.    A  large 
capacitor  could  serve  as  this  energy  storage  device,  providing  long  charging  and  discharging 
characteristics.    Figure  4‐14  shows  the  capacitive‐polling  design  designed  by  the  team  in  efforts  to 
minimize standby power consumption. 
 

114 

 
  
Figure 4‐14: Final low‐current sensing schematic with added polling capacitor CP.  Capacitor will hold the low‐
current flag voltage, keeping the adapter deactivated until it discharges. 
 
Polling capacitor CP is placed in parallel with the  MOC3023’s internal LED and R22.  When the 
current‐sensing  circuit  detects  a  low  level  of  current,  it  charges  the  capacitor  and  activates  the  LED, 
which  in  turn  triggers  the  disconnect  circuitry.    Once  power  has  been  disconnected  from  the  entire 
adapter,  the  capacitor  begins  to  discharge  through  MOC3023’s  LED  and  R22.    While  CP  discharges  its 
stored  energy,  the  LED  in  the  optoisolator  remains  active,  keeping  the  adapter  in  a  dormant  state.  
When the capacitor discharges below a certain voltage, the LED is unable to emit light and the adapter is 
thereby  reactivated  via  the  TRIAC  output  of  the  MOC3023.    The  time  period  between  adapter 
deactivation and reactivation is dependent on the length of the discharge cycle for capacitor CP.   
The low‐current sensing in the capacitive‐polling adapter uses the same implementation as the 
555‐timer‐based adapter.  However, the feedback circuitry from the 555 timer‐based adapter has been 

115 

 
modified  in  the  capacitive‐polling  design  to  include  the  capacitor  CP.    In  order  to  minimize  the  polling 
frequency  of  the  adapter,  the  value  of  CP  must  be  very  large.    Therefore,  the  value  chosen  for  CP  was 
10mF.  The 10mF capacitor provides the polling nature for the adapter in zero‐load conditions.   
When  a  load  is  connected  to  the  adapter,  the  capacitor  is  discharged  due  to  the  low  output 
state of the comparator.  The LED in the MOC3023, meanwhile, remains deactivated.  When the load is 
disconnected, the comparator switches to a high output state, activating the NPN switch to supply 5V to 
the capacitor and LED driver.  The 10mF capacitor subsequently charges toward the 5V rail.  Once the 
voltage reaches around 3V, which is the sum of the voltage drops across the LED and series resistance, 
the LED is activated.  The reactivation circuitry is then signaled to switch the AC input off.  At this point, 
the power connection is removed from the DC portion of the adapter, causing all active devices to turn 
off.  In particular, the NPN switch located at the cathode of the MOC3023 LED is turned off, effectively 
blocking the 10mF capacitor and LED from the DC ground.   
The  capacitor,  LED,  and  resistance  remain  in  their  own  circuit  loop,  causing  the  capacitor  to 
discharge  its  stored  energy  through  the  LED  and  the  resistance.    The  LED  remains  activated  until 
capacitor CP discharges to approximately 2.8V.  At this value, the forward bias voltage drop across the 
LED forces the current to drop below the holding  current, turning the  device off.  However, the delay 
caused  by  the  10mF  capacitor  allows  the  system  to  poll  for  a  load  connection  before  periodically 
reactivating itself.   

116 

 
  
Figure  4‐15:    Polling capacitor  implementation;  transistor  QP prevents  the capacitor  from  discharging  through 
ground, allowing it to stay charged for longer, thereby increasing the time between polls. 
 
  The circuit loop comprised of capacitor CP, resistor R22, and the MOC3023’s LED is disconnected 
from  both  supply  rails  when  the  TRIAC  output  of  the  optoisolator  is  activated.    Subsequently,  the 
capacitor dissipates its energy through the resistor and the LED in this first‐order system.  The value of 
the capacitor was obtained using the first order time constant relationship between the resistance and 
capacitance: 
    (4‐10) 
  For a first order system, this constant represents the time needed for the voltage to drop to 37% 
above  its  final  value.    In  this  circuit,  the  LED  will  be  deactivated  after  one  time  constant  due  to  the 
forward  bias  voltage  drop.    Therefore,  the  capacitance  needed  for  the  adapter  to  be  off  for  10s  is 
calculated: 
  10 330 30.3   (4‐11) 
According  to  (4‐10),  a  capacitor  of  30.3mF  is  needed  for  the  desired  polling  period.    However,  a 
capacitor of that value is very expensive and relatively large compared to other devices in the adapter.  
The team decided to use a 10mF capacitor, as its physical size was not too hindering.  Plugging this value 
into (4‐8) resulted in a much smaller polling period: 
  330 10 3.3   (4‐12) 

117 

 
Although  it  is  only  one‐third  of  the  desired  value,  the  3.3s  period  should  still  be  long  enough  to 
effectively poll the adapter. 
After designing the capacitive‐polling adapter’s DC circuitry, focus was shifted to implementing 
the  power  cutoff  subcircuit.    Although  the  TRIAC  was  originally  chosen  to  perform  as  the  power 
interrupt for the adapter, the team was unable to use the MOC3023’s output to deactivate the adapter.  
Since the MOC3023 remains on while the adapter is supposedly deactivated, the TRIAC output cannot 
be  used  to  interrupt  power  to  the  transformer.    The  cutoff  circuitry  called  for  an  inverting 
implementation  that  deactivated  the  adapter  while  the  MOC3023  was active.    Therefore, a  P‐Channel 
enhancement mode MOSFET was used to implement this inverting functionality and power disconnect 
[51].  Figure 4‐16 shows the power cutoff circuitry used in the capacitive‐polling adapter. 
 

 
Figure  4‐16:    Adapter  cutoff  schematic;  disconnection  circuitry  was  redesigned  to  allow  an  active  TRIAC  to 
disable the adapter, which is opposite to its foreseen function.  Resistive voltage divider keeps MOSFET’s gate‐
source  voltage  from  exceeding  component  limits,  while  simultaneously  keeping  TRIAC  current  below  active 
holding level [51]. 
 
The  adapter  cutoff  was  designed  to  break  the  rectified  170V  input  line  when  low  current  is 
detected at the output, and to connect the input to the transformer when a sufficient value of current is 
detected  at  the  DC  load.    If  the  MOC3023  is  activated,  the  170V  line  is  connected  directly  to  the  P‐
Channel MOSFET gate via its TRIAC output.  In effect, the voltage drop from the source of the MOSFET to 
its  gate  is  0V.    The  MOSFET  operates  in  cutoff  mode  under  this  condition,  and  no  current  flows  from 
source to drain.  However, if the MOC3023 is deactivated, a voltage division occurs at the gate between 
170V and ground.  The ratio of the resistances was chosen such that approximately 165V is experienced 
118 

 
at the MOSFET gate.  With a 5V difference between the source and gate of the MOSFET, the 170V line is 
connected to the transformer, resuming adapter functionality.   
Once  the  power  cutoff  circuitry  was  developed,  the  capacitive‐polling  adapter  design  was 
completed.  The layout of the capacitive‐polling method meets the requirement specified for the power 
cutoff circuitry and adapter reactivation.  Although a TRIAC was not used as the actual power interrupt 
switch,  the  MOC3023’s  output  was  used  to  trigger  a  power  MOSFET  to  activate  and  reactivate  the 
adapter, which satisfied the circuit’s first two requirements.  The third requirement was achieved using a 
large capacitor to poll the adapter periodically.  In order to determine which polling adapter consumes 
less  power  during  standby  and  operates  more  efficiently,  a  series  of  tests  was  completed  on  both 
adapters.  The results of these tests allowed the team to choose the appropriate design for an efficient 
wall adapter.   

119 

 
 Results  5 

In  the  previous  chapter,  the  team  designed  two  separate  adapter  models  that  utilize  polling 
during  standby  mode.    In  order  to  definitively  determine  which  model  consumes  the  least  amount  of 
energy while maintaining adapter functionality, a variety of tests were conducted on each design.  The 
two  designs  each  contain  their  own  advantages  and  drawbacks.    While  the  capacitive‐polling  adapter 
uses passive devices exclusively in its layout, the polling period of the adapter during standby is limited 
by  the  time  constant  determined  by  the  polling  capacitance  and  the  series  resistance.      On  the  other 
hand, the 555 timer‐based polling adapter can be programmed for a long polling period, but constantly 
consumes  power  regardless  of  the  output  load  condition.    However,  the  desired  outcome  of  the 
following  measurements  is  to  determine  at  least  one  configuration  that  will  reduce  the  original 
adapter’s standby power consumption by 75%, as specified in Chapter 1 of this report. 
 

Capacitive Polling 5.1

 
The  capacitive‐polling  adapter  configuration  was  tested  prior  to  the  555  timer‐based  polling 
adapter because it would have been the ideal choice had it performed up to the project’s specification 
goals.    The  team  believed  that  the  design  would  only  meet  specifications  if  the  polling  period  was 
lengthened  as  much  as  possible.    Efforts  were  made  in  designing  the  capacitive‐polling  adapter  to 
maximize  the  polling  period  by  disconnecting  the  supply  rails  during  polling  as  well  as  increasing  the 
polling capacitance value.  However, the MOC3023’s LED and the neighboring series resistance could not 
be altered without sacrificing system functionality.   
In order to test the polling period of the configuration, the TRIAC output of the MOC3023 was 
placed in series with a typical 2V, 10mA LED.  The series arrangement was placed in parallel with a DC 
power source set to 2V.  Figure 5‐1 shows the test setup used to determine the polling frequency of the 
capacitive‐polling adapter.   

120 

 
  
Figure 5‐1: Initial test setup of capacitive‐polling adapter using an external DC source and test LED.   

To emulate the power cutoff circuitry  deactivating  the adapter  when the low‐current flag was 

raised  at  the  output,  the  AC  input  was  manually  disconnected  from  the  adapter  once  the  LED  was 
observed to be emitting light.  Subsequently, the polling period was recorded as the duration the test 
LED emitted light before becoming inactive.  The full test procedure is shown in Table 5‐1. 
 
Table 5‐1:  Initial procedure followed to record polling period of capacitive‐polling adapter. 
Step  Description 
1  Place a resistive load to adapter output between 100Ω and 300Ω. 
2  Connect adapter input to AC power source via wall outlet. 
3  Remove resistive load from output while adapter is activated. 
4  Simultaneous to output disconnect, unplug adapter input from wall outlet. 
5  Record the amount of time the test LED remains active. 
 

121 

 
  
Figure  5‐2:  Capacitive  polling  solution  schematic;  10mF  capacitor  charges  when  low‐current  alert  is  activated, 
and holds the TRIAC’s LED on (and thereby the adapter off) until it discharges. 
 
The results of initial tests yielded a polling period approximately equal to the value calculated in 
Chapter 4.  When the adapter was connected to AC power with no output load, the test LED remained 
active for a time of 3s to 4s, which encompasses the theoretical value of 3.3s.  However, this test was 
performed using an incomplete adapter model.  The test LED emulates the time period during which the 
power  cutoff  circuitry  will  deactivate  the  adapter,  but  may  not  represent  the  actual  time  period.    In 
addition,  the  manual  disconnect  of  the  AC  input  power  is  not  a  true  representation  of  power  cutoff 
functionality.    Therefore,  the  remaining  circuitry  was  integrated  into  the  adapter  so  a  test  of  the  full 
configuration could be conducted. 
  Figure 5‐2 shows the final configuration of the capacitive polling solution used in testing.  After 
integrating the power cutoff subcircuit into the adapter, the team connected the input to the AC power 
source and once again observed the polling period with no load at the output.  Since the TRIAC output of 
the  MOC3023  was  now  connected  to  the  power  cutoff  circuitry,  an  oscilloscope  was  used  to  visually 
measure the polling period.  One of the scope probes was connected across the capacitor voltage so the 
polling period could be observed. 

122 

 
  

Figure 5‐3: Oscilloscope capture of output voltage for capacitive‐based polling timer configuration.  The polling 
period was limited to around 1s. 
 
The results of the full configuration test can be seen in Figure 5‐3.  Unlike results from the initial 
test with the LED and DC power source, the polling period of the full configuration was observed to be a 
mere 1s.  The reason a dramatically‐shortened polling period was observed is due to the speed at which 
the  low‐current  sense  alerts  the  power  cutoff  circuitry  of  a  no‐load  condition.    In  the  first  test  of  the 
capacitive‐polling  adapter,  the  capacitor  was  allowed  to  discharge  its  energy  well  after  the  MOC3023 
began to deactivate.  Since the propagation delay of low‐current sense processing is small with respect 
to  the  time  constant  of  the  polling  capacitor’s  voltage  characteristic,  capacitor  CP  is  only  able  to 
discharge to a 2.5V potential in the actual adapter model.  Once the low‐current sense alerts the power 
cutoff circuitry of the insufficient amount of output current, power is disconnected from the DC side of 
the  adapter  and  CP  begins  to  discharge.      Therefore,  the  polling  period  is  limited  by  the  propagation 
delay of the low‐current sense subcircuit.  The limitation of the polling period forced the team to deem 
the capacitive polling adapter as an unusable design for this project since the design would not be able 
to reduce standby power consumption by 75%.   

123 

 
555 Timer Polling 5.2

After  the  capacitive‐polling  adapter  was  ruled  out  as  a  potential  design  implementation,  the 
team  focused  its  efforts  on  manipulating  the  555  timer‐based  polling  adapter  to  meet  project 
specifications.    Figure  5‐4  shows  the  fully‐integrated  adapter  with  low‐current  sensing  and  polling 
stages. 
 

 
Figure 5‐4: Final schematic; adapter with monostable multivibrator timing. 
 
In  Chapter  4,  it  was  determined  that  the  555  timer  would  be  configured  for  monostable 
operation to  consume  the least amount of power during both operating and standby conditions.  The 
large  values  of  capacitor  C11  and  resistor  R16  allows  the  polling  period  of  the  adapter  to  equal 
approximately 60s according to calculations made in Chapter 4.   In order for the 555 timer‐based polling 
adapter design to remain a practical solution, the polling period must first be verified according to this 
calculation. 
124 

 
  Originally, the team planned to use the pinhole array on the upper portion of the first PCB board 
to implement possible solutions.  However, to allow for easy manipulation and substitution of additional 
circuitry,  breadboards  were  used  to  implement  the  low‐current  sense  as  well  as  the  polling  circuitry.  
Wire  connections  were  attached  to  specific  nodes  of  the  test  bed  and  then  connected  to  the 
appropriate  nodes  on  the  breadboard  implementations.    Figure  5‐5  shows  the  additional  wires 
connected  to  the  original  adapter  test  bed  in  order  to  implement  the  low‐current  sensing  and  polling 
circuitry.  Figure 5‐6 shows the entire implementation of the 555 timer‐based polling adapter on the PCB 
and two breadboards collectively. 
 

 
Figure  5‐5:  Shown  is  a  close‐up  view  of  the  adapter  test  bed  configuration  used  for  555  timer‐based  polling 
adapter tests.  The red and black wires on the right are attached to the DC output and the orange and yellow 
wires above the DC output are connected across the current‐sensing resistor R4.  In addition, two more wires 
were  connected  across  output  filter  capacitor  C4  to  provide  a  5V  supply  for  low‐current  sense  circuitry.    The 
purple and leftmost orange wires were attached to the 170VDC rail and AC ground respectively to provide power 
for  the  555  timer  subcircuit.    The  rightmost  wire  provided  the  drain  of  the  p‐channel  power  MOSFET  with  a 
connection to the primary winding of the transformer. 

125 

 
  
Figure 5‐6:  Shown is the interconnections between the original adapter test bed and the additional low‐current 
sensing  and  polling  circuitry.    The  right‐hand  breadboard  in  the  figure  holds  all  circuitry  for  the  low‐current 
sense,  while  the  left‐hand  breadboard  holds  the  555  timer  polling  subcircuit.    The  green  and  yellow  wires 
provide the feedback connection between the TRIAC output of the MOC3023 and the 555 timer.  The white and 
yellow  alligator  clips  were  use  to  connect  DC  output  to  a  resistive  load.    Moreover,  oscilloscope  probes  were 
connected to the alligator clips to measure the DC output voltage during testing. 
 
Once the physical arrangement depicted in Figure 5‐6 represented the adapter schematic shown 
in Figure 5‐4, the 555 timer‐based polling adapter was ready for testing.  The first test conducted on the 
adapter was a measurement of the polling period.  It was necessary to verify the functionality of the 555 
timer’s  polling  of  the  adapter  before  power  consumption  measurements  were  undertaken.    After 
plugging in the adapter, the team attached an oscilloscope probe to its DC output.  Figure 5‐7 shows the 
output waveform of the adapter with no load connected. 
 

 
Figure 5‐7: Output waveform of adapter; 555 Timer polling intervals are shown to be around 62s. 

126 

 
 Using the time cursors of the oscilloscope, the observed polling period was measured to be 62s.  
In  addition  to  polling  the  adapter  according  to  previous  calculations,  the  output  voltage  reached  the 
nominal 5V rating.  Therefore, the adapter polls according to specifications and is able to resume normal 
operation once it is reactivated with a load connected.   
After the functionality of the 555 timer’s polling of the adapter was confirmed, the team moved 
on to testing the power consumption of the system.  While the output power consumption is simple to 
measure, the input power consumption is more difficult.  Chapter 2 describes the process of measuring 
the  input  power  measurement  via  a  series  resistance  in  the  return  path  of  the  adapter  input.    In  the 
same manner, a sensing resistance of 10Ω is placed as shown in Figure 5‐8.  Scope A is used to measure 
the input AC voltage, while Scope B is placed across resistor RSENSE to measure the experienced voltage 
drop.  The input current can be determined by attenuating the signal observed on Scope B by 10, since 
the voltage drop is ten times the current flowing through RSENSE.   
 

 
Figure 5‐8: Power measurement setup; input voltage measured by Scope B, input current related to voltage on 
Scope B. 
 
Once  two oscilloscope probes were arranged according to the layout shown in Figure 5‐8, the 
adapter  was  plugged  in  so  the  team  could  observed  the  resulting  waveforms.    Figure  5‐9  shows  a 
standard  120VRMS  voltage  reading  on  channel  2  of  the  oscilloscope,  but  channel  1  shows  the  input 
current coupled with noise from the AC line.  It was determined in Chapter 2 that this noise is due to the 
three‐phase to single‐phase power conversion carried out before power is delivered to the consumer.  
In  previous  input  power  consumption  measurements,  RSENSE  was  increased  to  100Ω  to  attenuate  the 
noise and the MATH function of the oscilloscope was used to produce a 100X power signal.  However, 
the team discovered a more precise way of measuring the input power to the adapter. 

127 

 
 While  RSENSE  is  maintained  at  10Ω,  the  adapter  is  connected  to  the  wall  outlet  via  a  surge 
protector.    When  the  surge  protector  is  switched  to  the  off  position,  the  oscilloscope  observes  the 
waveforms  shown  in  Figure  5‐10.    Although  the  input  voltage  is  completely  disconnected  from  the 
adapter’s input, the noise on the AC line is still observed across resistor RSENSE.  Using the SAVE option on 
the oscilloscope, the noise was converted into a series of voltages over time and stored as a CSV file.   
 

 
Figure 5‐9: Input voltage (CH2) and amplified Input Current (CH1) waveforms of initial 555 timer‐based polling 
adapter with 200Ω load. 

 
Figure 5‐10: Noise observed on CH1 when surge protector is switched to off position.  The noise is attributed to 
three‐phase to single‐phase power conversion. 

128 

 
 After  subsequently  switching  the  surge  protector  to  the  on  position,  the  oscilloscope  reading 
shown  in  Figure  5‐11  was  observed  during  the  adapter’s  polling  period.    Although  the  input  current 
signals  from  Figure  5‐10  and  Figure  5‐11  appear  to  be  identical,  the  input  current  peaks  that  occur 
whenever the input voltage swings to its peaks are slightly higher when the adapter is active.  However, 
the slight difference between the two oscilloscope plots implies that the power consumption of the 555 
timer subcircuit is very small with respect to the overall test bed’s power consumption.   

 
Figure 5‐11: Input voltage (CH2) and amplified Input Current (CH1) waveforms of initial 555 timer‐based polling 
adapter during standby (no load). 
 
  When  the  adapter’s  output  is  coupled  with  a  resistive  load,  a  much  different  input  current  is 
observed.    Figure  5‐9  shows  an  oscilloscope  reading  of  the  input  voltage  and  current  when  a  200Ω 
output load is connected to the adapter.   
  Although  the  current  peaks  are  much  higher  while  the  output  is  coupled  with  a  load,  the 
observed noise inherent in the signal remains the same.  Therefore, if the noise is subtracted from the 
input current signal, an accurate measurement of the current can be obtained.  In efforts to eliminate 
the noise, the voltages from the waveforms captured in Figure 5‐11 and Figure 5‐9 were saved as CSV 
files.    For  each  input  current  measurement,  the  data  from  the  noise  captured  in  Figure  5‐10  was 
subtracted,  resulting  in  data  truly  representative  of  the  input  current.    Finally,  the  data  field  for  each 
input current measurement was divided by the measured resistance of RSENSE to attenuate the data to 
the actual current level.  Figure 5‐12 shows the data transformation of the input current. 

129 

 
 1 1
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
‐0.04 ‐0.02 ‐0.2 0 0.02 0.04 ‐0.04 ‐0.02 ‐0.2 0 0.02 0.04

‐0.4 ‐0.4
 

Figure 5‐12: Noisy current measurement (left) and true current measurement with noise subtracted (right). 
 
While the left‐hand plot shows the presence of the AC line noise, the right‐hand plot shows a 
filtered signal that is representative of the actual current supplied to the adapter.  Using this technique, 
power  measurements  were  obtained  by  multiplying  the  RMS  value  of  the  actual  current  data  by  the 
RMS voltage.   
 
 
Table  5‐2  shows  the  results  of  input  power  measurements  for  the  555  timer‐based  polling 
adapter and the original adapter with an output load of 200Ω.   
 
Table 5‐2: Input power measurements of the modified and original adapter with 200Ω load. 

Consumed Power During Normal Operation (200Ω load) 

Unmodified Power Adapter  Modified Power Adapter 

447 mW  461 mW 

Although the additional circuitry consumes an extra 3% of the original adapter’s overall power 
consumption when active, the difference between the power consumption of the original adapter and 
the modified adapter is negligible during charging.  Moreover, since adapters operate in standby more 
than they operate in charging mode, the small increase in power consumption experienced by the 555 
timer‐based polling adapter over the original design is a nonissue. 

130 

 
 In the same way, standby power consumption was tested by disconnecting the 200Ω load from 
the adapter and reacquiring data from the oscilloscope.  Table 5‐3 shows the results of standby power 
consumption measurements for both the original and modified adapters after the data was manipulated 
to represent actual values. 
 
Table 5‐3: Input power measurements of the modified and original adapter with no load. 

Consumed Power During Idle Operation (No Load) 

Unmodified Power Adapter  The Modified Power Adapter 

224 mW  34 mW  (momentary 263 mW spikes) 

  While  the  original  test  bed  was  measured  to  consume  201mW  standby  power,  the  PCB 
implementation  was  measured  to  consume  224mW  during  no‐load  conditions.    The  discrepancy  in 
power values can be credited to either the deviation of component values or the increased precision of 
measurement used in  the new calculations.  Nevertheless, the results showed a substantial savings of 
85% less power consumption with the modified adapter implemented, exceeding the specification goal 
of a 75% reduction.  Figure 5‐13 shows a simulated plot of the modified adapter’s power consumption 
and  the  unmodified  adapter’s  power  consumption  over  a  period  of  250  seconds.    The  adapters  both 
start  at  0s, supplying  a  200Ω  load  which  is  disconnected  after  50  seconds.    The  shaded  areas  indicate 
energy savings, which will only continue to accumulate for as long as the adapter is in the idle state. 

131 

 
 500
Our Solution
450
Unmodified Adapter
400
Power Consumption (mW)

350
300
250
200
150  Energy
100 Savings
50
0
0 50 100 150 200 250
Time (seconds)
 

Figure  5‐13:  Power  consumption  comparison  of  modified  adapter  and  original  test  bed  over  time.    Load  is 
disconnected after 50 seconds. 
 
  Figure 5‐14 shows the adapter’s power usage as a function of the amount of resistance used for 
a  load.    To  collect  the  necessary  data,  16  resistor  values  in  the  range  of  100Ω  to  1.5kΩ  were  each 
connected to the output load and the output power was measured for both the original and modified 
adapter  implementations.    The  resulting  plot  of  the  measured  data  provides  an  alternative  visual 
representation for seeing the effect of the modified solution on standby power consumption.  It should 
be  noted  that  the  shaded  area  representing  energy  savings  extends  toward  an  infinite  resistance, 
creating a large window in which the modified adapter consumes a much smaller amount of power than 
the original adapter test bed. 
 

132 

 
 Power Consumption (W)

0.25

Our Solution
Unmodified Adapter
0.025
0.0006 Inverse of Load Resistance   (1/Ω) 0.006
 
Figure 5‐14: Plot of power consumption for both the modified and the unmodified adapter versus the inverse of 
the attached load resistance. 
 
The measurements of standby power consumption for the modified adapter provided the team 
assurance that the 555 timer‐based adapter has viability.  However, one specification goal remained to 
be  accomplished  in  the  design.    Since  the  tested  555  timer‐based  adapter  model  utilized  operational 
amplifiers  and  power  MOSFETs  whose  individual  costs  exceeded  the  project’s  budget,  the  team 
researched for potential alternatives to substitute into the design.  In Chapter 4, the team describes how 
a dual‐channel op‐amp IC called the TLC27L2 was used to replace the two OPA344 op‐amps used in the 
low‐current  sensing  circuitry,  and  how  the  FQPF2P25  p‐channel  power  MOSFET  was  purchased  to 
replace  the  IRF9640.    Originally,  the  team  believed  that  the  specifications  for  the  substituted 
components were similar to the original parts used in the design.  While the FQPF2P25 power MOSFET 
was  successfully  implemented  in  the  design,  the  incorporation  of  the  TLC27L2  disrupted  system 
functionality.    Figure  5‐15  shows  the  PCB  layout  of  the  555  timer‐based  polling  adapter  using  the 
TLC27L2 and the FQPF2P25 power MOSFET. 

133 

 
  

Figure 5‐15:  PCB layout of the 555 timer‐based polling adapter.  Original test bed circuitry is located on the 
lower half of the PCB while additional circuitry such as the low‐current sense and the 555 timer subcircuit are 
located on the upper half of the board. 

After  troubleshooting  the  circuit,  the  team  reexamined  the  datasheet  specifications  for  the 
TLC27L2.  It was determined that although the TLC27L2 consumes much less power (135µW) than two 
OPA344  ICs,  the  input  and  output  voltage  ranges  of  each  op‐amp  are  much  less.    The  output  voltage 
range is stipulated to be between 50mV and 4.1V given a supply of 5V.  The common mode input range, 
on  the  other  hand,  is  between  ‐0.2V  and  4.2V  when  the  TLC27L2  is  operating  at  5V.    While  the 
shortened  output  voltage  range  does  not  affect  system  functionality,  the  introduced  limitation  of  the 
common  mode  input  range  provides  a  hindrance  for  the  low‐current  sensing  operation.    Since  both 
voltages connected to the inputs of the difference amplifier arrangement are within only a few mV of 
the supply rail, the TLC27L2 was not able to appropriately interpret the voltages outside its input range.  
After  manipulating  the  resistors  in  the  low‐current  sensing  circuit,  a  functional  adapter  was  realized 
according  to  the  schematic  shown  in  Figure  5‐16.    The  team  reasoned  that  lowering  the  reference 
voltage  and  reducing  the  amplification  of  the  difference  amplifier  would  help  the  system  regain  its 
normal operation. 

134 

 
  
Figure 5‐16: Final schematic; adapter with monostable multivibrator timing. 
 
  In order to return the proper functionality to the adapter, the values of resistors R9, R10, R11, 
and  R12  from  the  difference  amplifier  as  well  as  resistors  R13  and  R14  of  the  voltage  divider  were 
altered.  The voltage reference was reduced to 169mV by setting R14 equal to 4.3MΩ and R13 equal to 
150kΩ.    In  addition,  the  amplification  of  the  input  voltage  of  the  difference  amplifier  was  reduced  to 
13.3 by substituting a resistance of 200kΩ for R10 and R12 and placing resistances of 15kΩ for R9 and 
R11.  In effect, the newly‐established threshold current was calculated by the following equation: 

  10.5             (5‐1) 
. . Ω

Therefore,  the  new  implementation  of  the  low‐current  sensing  signals  the  555  timer  of  a  standby 
condition when the output current drops below 10.5mA.  In addition to changing the output threshold 
current,  the  reduced  amplification  factor  of  the  difference  amplifier  shortens  the  linear  range  of  its 
output voltages.  Besides these changes, however, the adapter  operates in the same manner as it did 
using the OPA344 and the IRF9640.   
135 

 
  Although adapter functionality was restored, the team pursued alternatives for a dual‐channel 
op‐amp  that  had  a  rail‐to‐rail  input  and  output  voltage  range.    The  LMV932  dual‐channel  operational 
amplifier manufactured by Texas Instruments provides a rail‐to‐rail input and output voltage range and 
costs only a few cents more than the TLC27L2 [52].  The LMV932’s common mode input voltage range is 
between ‐0.2V and 5.3V and the output voltage can range between 0.12V and 4.89V when operated at 
5V.  Although the LMV932 consumes more power than the TLC27L2, the power consumption is still less 
per amplifier than one OPA344 [52].  In fact, each amplifier’s supply current of the LMV932 is 34µA less 
than the OPA344’s supply current of 150µA.  Since it matches the specifications of two OPA344 op‐amps 
and  costs  only  $0.04  per  1000  units  more  than  the  TLC27L2,  the  LMV932  dual‐channel  operational 
amplifier was chosen for implementation in the efficient wall adapter design.   The implementation of 
the  LMV932  IC  allowed  the  team  to  revert  all  other  components  in  the  design  back  to  their  original 
values while remaining under budget.  Once the team obtained a cost‐effective solution to the OPA344, 
the final design met all specification goals laid out for the project.  The final schematic of the 555 timer‐
based polling timer can be found in Appendix A. 
   

136 

 
 Future Work  6 

The  efficient  wall  adapter  designed  in  this  project  significantly  reduces  power  consumption 
compared to present‐day models.  However, the team acknowledges that the design presented in this 
report  does  not  represent  an  ideal  solution.    In  fact,  it  may  be  that  additional  research  into  different 
adapter  reactivation  methods  would yield  a  more efficient  product.    The  purpose  of  this  chapter  is  to 
provide  a  framework  that  could  be  used  in  further,  related  research.    In  Figure  6‐1,  the  basic  adapter 
functionality is shown and described on a high level. 
 

 
Figure 6‐1: Basic adapter functionality.  When the adapter is activated, storage device is filled to full capacity 
with electrical or magnetic energy.  During this time, the load is charged.  When the load is disconnected, energy 
is discharged from the storage device until the energy drops below a particular threshold.  When this occurs, the 
adapter is reactivated.  Notice the charge cycle when the adapter is activated and the discharge cycle when the 
adapter is deactivated. 
137 

 
 Figure 6‐1 shows a flowchart of an efficient wall adapter with a low‐power standby mode.  The 
critical  components  for  implementing  this  functionality  lie  with  the  decisions  made  by  the  control 
system: 
1. Is a load connected to the DC output? 
2. When the adapter is off, has the energy in the storage device depleted past a particular level? 
One potential way of using passive components to reactivate the adapter was explored in the Jump Start 
approach presented in Chapter 3.  In this case, the passive nature of the design should cause the system 
to react to a load reconnect.  The adapter presented in this report performs this function using active 
devices that signal the 555 timer subcircuit when the load is disconnected.  However, it would be more 
efficient if an adapter modeled around the Jump Start approach utilized passive components to realize 
this precise functionality of flagging the power interrupt circuitry whenever low current is detected. 
In theory, the Jump Start could provide an ideal standby power consumption of 0W.  However, 
the team encountered a number of functional problems that could not be overcome within the scope of 
this project.  Mainly, a voltage could not be obtained across the power connections to the cell phone’s 
battery.  While a phone manufacturer can design a phone to accommodate the Jump Start idea, it would 
require  prior  acceptance  of  the  design  amongst  the  cellular  phone  community.    Other  problems 
inherent  in  the  idea,  such  as  reactivating  the  adapter  from  a  completely  dead  battery,  could  be 
overcome with additions like a manual reset switch on the adapter.  Therefore, the team believes that 
although the Jump Start approach may be feasible and potentially rewarding, it would require more of a 
concerted full‐system design effort from a phone manufacturer.   
Another  idea  inspired  by  the  design  process,  but  left  undeveloped  within  the  scope  of  this 
project was that of capacitive current sensing.  The team implemented a capacitive polling method as 
one  solution,  though  it  underperformed  expectations.    Yet,  capacitors  still  have  potential  as  current‐
sensing  devices.    In  particular,  it  would  be  particularly  efficient  to  make  use  of  the  already  existing 
capacitors located across the output of the adapter, as seen in Figure 6‐2. 
 

 
Figure 6‐2: The output stage of the power adapter, showing two filter capacitors. 

138 

 
  The capacitor on the left, with its proximity to the active transformer, seems like a viable option.  
When  the  transformer  coil  produces  positive  current,  the  diode  becomes  forward  biased  and  the 
capacitor charges to about 5V, as seen in Figure 6‐3.  When the current from the transformer reverses, 
the  diode  becomes  reverse  biased,  and  the  current  drawn  at  the  adapter  output  is  supplied  by  the 
capacitor only, as seen in Figure 6‐4. 
 

 
Figure 6‐3: Output stage of an adapter.  Rectifier diode is forward biased, capacitor is charging. 
 

 
Figure 6‐4: Output stage of an adapter.  Rectifier diode is reverse biased, capacitor is discharging. 
 
  This  period  of  discharging  provides  an  opportunity  to  determine  how  much  current  is  being 
drawn by the output.  A capacitor’s current‐voltage relationship is given by the following formula: 

    (6‐1) 

Notice  that  the  more  current  that  is  drawn  from  the  capacitor,  the  faster  its  voltage  will  drop.    This 
relationship is illustrated in Figure 6‐5.  Given equal run times, a capacitor with a high current draw will 
fall to a lower voltage than a capacitor with a lower current  draw.  Monitoring the voltage across the 
capacitor, then, becomes a viable way of determining how much current is being drawn by the source. 

139 

 
 The more current that gets 
drawn from a capacitor…

…the faster the voltage 
across that capacitor drops

 
Figure 6‐5: Current‐voltage relationship for a capacitor; the voltage across an adapter drops as the integral of 
the  current  being  drawn  from  it.    Therefore,  by  monitoring  how  low  the  capacitor’s  voltage  gets  between 
recharges, the current that was being drawn from it can be determined. 
 
  However, in attempting to find a way to use this technique in sensing current, there are three 
key  roadblocks.    The  first  problem  arises  due  to  the  frequency  at  which  the  current  cycles  from  the 
transistor.    The  NCP1011  switching  IC  that  runs  this  switch  mode  power  supply  runs  at  100kHz.    This 
provides only 5μs for the capacitor to act as a source for the DC load.  The output voltage is intended to 
remain  as  constant  as  possible,  but  it  makes  the  task  of  detecting  meaningful  voltage  differences 
difficult.  The expected voltage drop across the 1mF capacitor for a 50mA load can be determined using 
the following equations: 

    (6‐2) 
.
  5 10 25   (6‐3) 
.

With only a 25µV drop appearing across the capacitor, it would seem far more practical to continue to 
amplify the 60mV difference that would appear across current‐sensing resistor R4 with a 50mA load. 
  The second problem was a logistical problem with triggering.  It is necessary to be able to trigger 
an  adapter  shutdown  when  the  load  current  becomes  too  low.    However,  the  capacitor’s  voltage 
actually  drops  less  when  there  is  a  lower  load  current.    In  this  case,  any  trigger  set  would  also  be 
exceeded  by  a  large  load  current,  which  drops  the  capacitor  voltage  even  further.    The  only  apparent 
way around this would involve polling the capacitor voltage at the end of every 100kHz cycle, at which 
point  a  high  voltage  would  indicate  low  current  and  a  low  voltage  would  indicate  high  current.  

140 

 
However, this form of polling would likely require additional components to implement, removing some 
of the benefit of switching to capacitive current sensing. 
  The third problem is one that may not be immediately recognizable until investigating the circuit 
with  an  oscilloscope.    By  monitoring  the  voltage  across  the  capacitor  with  both  a  50mA  load  and  an 
open (no) load, it is possible to capture the two plots shown in Figure 6‐6. 
 

Meanwhile, overall voltage actually 
drops considerably with no load, due 
to NCP1011’s idle power saving mode 

During discharge phase voltage 
does not change much, due to 
100 kHz speed of oscillations 
 
Figure 6‐6: Voltage across adapter’s output capacitor; with 50mA load (left), open load (right).  The discharging 
voltage  drop  is  relatively  very  small,  due  to  the  fast  100  kHz  charge‐discharge  cycles.    The  capacitive  voltage 
drop  is  further  confused  by  a  large  overall  voltage  drop  when  no  load  is  applied  and  the  NCP1011  switcher 
enters power saving mode. 
 
The voltage across the capacitor with no load was significantly less than the voltage across the 
capacitor when a load was present.  This seems to contradict the theory that high currents would reduce 
the voltage across the capacitor faster.  However, this drop was not being caused by current draining the 
capacitor.  It instead appears to be the result of the NCP1011’s built‐in idle power saving technique, in 
which it slows or stops its oscillation momentarily, resulting in this drop in voltage at the output [28].  
The  result  of  this  is  added  complication  to  any  monitoring  technique  that  may  be  implemented,  as 
higher current produces larger and larger voltage drops. 

Therefore,  it  does  not  appear  that  it  would  be  possible  to  easily  make  use  of  the      

relation of the capacitor.  However, it is conceivable that the voltage drop caused by the NCP’s power 
saving mode could be used to trigger a full shutdown.  Capacitive current sensing might also be made 
more effective if a switcher was used that did not have its own power saving modes, making the voltage 
level on the output capacitors more reliable.  The team simply decided that for this project, it would not 

141 

 
be suitable to implement a solution that relies on proprietary or specific technology implemented in the 
basic adapter itself, instead opting for  a solution that could be applied to any manufacturer’s adapter 
design since the end product was intended as an adapter modification and not a new design altogether. 
  In  addition  to  using  an  output  capacitor  as  a  current‐sensing  component,  future  work  can  be 
conducted regarding the improvement of the capacitive‐polling proposition in this project.   Capacitors 
are used predominantly for energy storage since they are relatively inexpensive compared to inductors.  
It can therefore be assumed that efforts made to simplify and improve the design will utilize capacitors 
rather  than  inductors.    Assuming  an  initial  condition  of  0V,  a  capacitor's  step  response  follows  an 
exponential relationship: 

     (6‐4) 
The time constant τ is defined as time required for the capacitor to charge up to 63% of V.  In addition, it 
is known that the capacitor has nearly discharged all of its energy after 5 time constants, or (5τ)s.   
 

 
Figure  6‐7:  Schematic  of  modeled  DC  output  of  adapter.    V  represents  the  DC  output  voltage,  and  the 
capacitance C1 represents the total capacitance at the output of the adapter. 
 
  Figure 6‐7 shows the circuit described by the step response equation.  The voltage V is a model 
of the DC output voltage as soon as the user plugs in the adapter.  VOUT will charge toward the voltage 
level V.  The capacitor's energy, like other energy storage devices, depends upon its capacity of energy 
and  the  amount  of  energy  supplied.    Given  the  values  stipulated  by  the  schematic  in  Figure  6‐7,  the 
energy stored in the capacitor once VOUT equals V is 720µJ: 

  10 12 720     (6‐5) 

  This  energy  remains  constant  as  long  as  the  adapter  is  functioning.    If  the  user  unplugs  the 
adapter, the energy will slowly decay as the energy is dissipated in other areas of the circuit.  Figure 6‐8 
provides an illustration of a segment of the adapter’s output stage. 

142 

 
  
Figure 6‐8: Segment of the DC output stage of the efficient wall adapter. 
When  the  adapter  is  functioning,  the  voltage  across  C8  and  C9  is  approximately  5V,  since  the 
small series resistance incurs an infinitesimal amount of voltage.  When a capacitor experiences a square 
pulse or step response as mentioned earlier, the time required to meet the expected value is 5τ.  The 
relationship between τ and C8 is shown below: 
  6 9|| 8               (6‐6) 
According  to  (6‐6),  the  time  taken  to  discharge  all  the  energy  in  capacitor  C8  is  equal  to 
R6(C9||C8).    While  R6  has  a  very  low  resistance,  the  impedance  of  capacitor  C8  is  extremely  large 
(ideally ZC9 = ∞).  Taking into account a high impedance combination of R6 and C9, the time required for 
C8 to drain all of its energy will be very long in duration.  An important reason this  duration is rather 
long is due to the rectifier diode D4.  This diode provides another high impedance component between 
the transformer winding and C8, R6, and C9.  A long time constant τ is required for a polling reactivation 
technique using passive components.   
  According to these results, an efficient wall adapter with passive polling is plausible, but includes 
several complications yet to be discussed.  For instance, necessary feedback interfaces are required to 
relay  the  capacitor's  energy  status  with  the  control  circuitry.      In  particular,  a  feedback  network  is 
required with a high impedance input.  If the feedback stage requires a significant amount of power, the 
energy stored in the capacitor C8 will discharge at a more rapid rate.  If this rate is too high, the validity 
of the passive polling idea is jeopardized.   
  Figure  6‐9  describes  the  top‐level  approach  of  implementing  a  passive  polling  adapter.    Once 
again,  a  high‐impedance  feedback  network  is  necessary  to  maintain  a  sufficiently  long  discharge 
characteristic.    Therefore,  an  optoisolator  may  not  be  useful  in  this  situation,  since  the  LED  trigger 
requires a significant amount of power to activate. 
 

143 

 
  
Figure 6‐9: Top‐level design of efficient wall adapter with passive polling. 
 
  A reasonable response to developing a high‐impedance feedback network is to circumvent the 
network  altogether.    This  idea,  however,  has  many  inherent  flaws,  such  as  isolation  infringements.  
Connecting the capacitor C8 directly to the control subcircuit would provide a connection between the 
DC signal and DC ground with the AC signal and AC ground.  Since the grounds of both circuits are not 
identical,  safety  issues  become  prevalent  and  circuit  functionality  will  become  questionable.    In  fact, 
these particular issues encouraged the  team  to steer away from utilizing  passive polling  in  its adapter 
configuration.  In order to build a functioning circuit consuming equal or less power than the project’s 
model, the problems of interfacing and isolation need to be addressed. 
Although  the  team  largely  had  to  dismiss  passive  ideas  such  as  capacitive  polling  and  current 
sensing  during  this  project,  the  actual  concept  of  using  exclusively  passive  components  for  circuit 
reactivation and other functions is ideal.  Instead of a proactive solution, a reactive design would store 
energy  during  operation  and  discharge  this  energy  during  idle  use.    As  long  as  the  circuit  reactivates 
when the detected stored energy plummets below a lower threshold, the adapter would never become 
trapped in a dormant condition.   
Any of these potential avenues for future work, or perhaps others not mentioned here, could be 
expanded in an effort to achieve or approach the ideal solution to the problem posed by this project.  
That is, when there is no load, there should be no loss. 
   
144 

 
 Conclusion  7 

The  Efficient  Wall  Adapter  project  provided  the  team  from  beginning  to  end  with  unique 
requirements  and  guidelines  that  called  for  simplicity  in  design  to  achieve  a  complex  function.    It  is 
hoped that the report highlighted the deliberate, logical progression undertaken by the team to respond 
to necessary concerns in such a design.  Working at the component level, an arrangement of commonly‐
used  configurations  was  configured  to  exceed  expectations  in  creating  an  adapter  that  is  85%  more 
efficient than modern adapters when idle at an additional cost of only $1.21.   
  In  the  first  chapter  of  this  report,  the  team  outlined  its  goals  and  objectives  in  the  hope  that 
they  would  be  fully  met  and  completed.    The  first  objective  was  to  develop  a  product  that  could  be 
universally applied to any variety of external power adapters on the market.  The simplicity of the final 
design  could  provide  universal  application  capability  through  the  simple  manipulation  of  critical 
component  values,  such  as  the  resistors  used  in  the  difference  amplifier  or  555  timer  subcircuits.  
Moreover, a slight change in these component values would have no affect on the overhead cost of the 
product.    The  next  objective  discussed  the  hopes  of  integrating  the  solution  with  present  adapter 
designs  in  efforts  to  minimize  an  increase  in  device  size.    Much  of  the  final  circuit’s  functionality  is 
performed using ICs and basic components, so integration is plausible due to its compactness in design.  
Another specification goal for the project stipulated that the cost impact of the final circuit to existing 
adapters should be minimal.  Calculations were based on a maximum two‐year break‐even proposition, 
equating  to  an  overall  budget  of  $1.30  for  this  project.    Based  upon  the  prices  of  the  final  design’s 
components at the date of this report’s publication, the cost of additional circuitry is under budget. 
  In terms of functionality, it was desired to reduce the modern efficient power adapter’s power 
consumption  by  75%.   According  to  the  Energy  Star  initiative,  the  United  States  government  hopes  to 
reduce  no‐load  power  consumption  to  150mW  [17].    Presently,  the  requirement  is  500mW.    The 
efficient  power  adapter  designed  by  the  team  consumes  34mW  in  standby  mode,  which  is  a  77% 
reduction of even Energy Star’s desired goal.  In order to assure that the product would adapt well to 
future,  more  efficient  cell  phones,  a  requirement  was  set  to  operate  the  adapter  above  a  maximum 
output  current  threshold  of  15mA.    The  low‐current  sensing  performed  in  this  design  permits  a 
minimum output current of around 11.6mA.  Although this may not seem to be a prevalent issue, it is 

145 

 
likely that future cell phones will be smaller in size and more efficient in power consumption.  The ability 
to allow low‐current loads is thus important to the design of the adapter. 
  The project was successful in achieving each objective set in its early stages.  However, the team 
concedes  its  inability  to  design  the  ideal  solution,  which  would  consume  zero  power  during  no‐load 
conditions.    The  scope  and  timetable  for  this  project  did  not  warrant  a  thorough  investigation  of  the 
validity of the Jump Start concept.  Once a power supply of this magnitude is designed, the idle losses 
incurred  by  all  users  of  consumer  electronics  will  be  vanquished  and  deemed  obsolete.    In  fact,  this 
shortcoming  provides  motivation  for  similar  projects  to  be  pursued.    Indeed,  it  is  hoped  that  one  day 
this no load, no loss functionality will be realized. 
  Specifically, the team hopes that parties interested in this project concur with and continue to 
develop the solution proposed for creating an efficient wall adapter.  Furthermore, it is hoped that the 
logical,  deliberate  approach  that  was  taken  to  design  the  final  product  demonstrates  the  thorough 
nature  in  which  this  project  was  conducted.    In  addition  to  the  problem  of  external  power  supplies, 
attention  should  also  be  focused  on  other  integrated  power  supplies,  such  as  those  found  in  large 
household  appliances.    The  sooner  the  problem  is  addressed,  the  more  relief  can  be  granted  to  the 
scarcity of the world’s energy sources.   
When an engineer sits down to work, they can often picture the end user happily enjoying their 
creation.  However, for 23 hours per day, the common reality of the device sitting in a corner, unused, 
fails  to  come  across  the  designer’s  mind.    As  a  result,  society  encounters  problems  such  as  the  idle 
adapter energy waste addressed by this project.  The adapter presented in this report is one of the first 
power adapters specifically designed to not be used.  For the sake of both our wallet and our planet, we 
hope it is not the last. 

146 

 
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151 

 
Appendix A – Final Schematic and Parts List

152 

 
 Test Bed Parts ‐ Revision D
Unit 
Price  Total 
Quantity  Label  Part Type  Value  Distributor Manufacturer Part #  Distributor Part #  (1000)  Price 
1  T1  Transformer  3.5 mH  Coilcraft  A9619‐C  A9619‐C $1.680 $1.680
1  U3  IEC AC PCB  Pin  Mouser  GSP2.8101.13  693‐GSP2.8101.13 $1.150 $1.150
1  U1  Switcher IC  NCP1011ST  Mouser  NCP1011AP100G  863‐NCP1011AP100G $0.604 $0.604
1  L1  Inductor  1mH  Mouser  SDR1005‐102KL  652‐SDR1005‐102KL $0.310 $0.310
1  R1  Resistor  20Ω, 2W  Mouser  CPF220R000FKE14  71‐CPF2‐F‐20‐E3 $0.299 $0.299
1  U2  Optocoupler SFH‐615A‐4  Mouser  SFH615A‐4  782‐SFH615A‐4 $0.250 $0.250
2  C1, C2  Capacitor  4.7uF, 400V  Mouser  UVR2G4R7MPD  647‐UVR2G4R7MPD $0.137 $0.274
1  D2  Diode  MBR150  Mouser  MBR150G  863‐MBR150G $0.097 $0.097
1  Q1  BJT  2N2907  Mouser  PN2907A  610‐PN2907A $0.090 $0.090
2  C5, C6  Capacitor  1nF, 1kV  Mouser  DEHR33A102KA2B  81‐DEHR33A102KA2B $0.088 $0.176
1  C8  Capacitor  4.7nF  Mouser  140‐500P5‐472K‐RC  140‐500P5‐472K‐RC $0.080 $0.080
1  D3  Diode  UF4005  Mouser  UF4005  512‐UF4005 $0.059 $0.059
1  C4  Capacitor  1mF  Mouser  UVR0J102MPD1TA  647‐UVR0J102MPD1TA $0.059 $0.059
1  R4  Resistor  1.2Ω, 0.5W  Mouser  MF1/2LC1R2J  660‐MF1/2LC1R2J $0.057 $0.057
1  C7  Capacitor  100nF  Mouser  K104K15X7RF53H5  594‐K104K15X7RF53H5 $0.050 $0.050
4  C3, C9, C10, C13  Capacitor  10uF  Mouser  USR1E100MDD  647‐USR1E100MDD $0.048 $0.192
1  D1  Diode  1N4007  Mouser  1N4007G  863‐1N4007G $0.019 $0.019
1  D5  Zener  1N5229B  Mouser  1N5229B  512‐1N5229B $0.015 $0.015
1  R2  Resistor  150kΩ  Mouser  CFS1/4CT52R154J  660‐CFS1/4CT52R154J $0.009 $0.009
1  R7  Resistor  10Ω  Mouser  CFS1/4CT52R100J  660‐CFS1/4CT52R100J $0.009 $0.009
3  R8, R10, R11  Resistor  2kΩ  Mouser  CFS1/4CT52R202J  660‐CFS1/4CT52R202J $0.009 $0.027
1  R3  Resistor  200Ω  Mouser  CFS1/4CT52R201J  660‐CFS1/4CT52R201J $0.009 $0.009
1  D4  Diode  1N4148  Mouser  1N4148‐TR  78‐1N4148 $0.008 $0.008
1  R5  Resistor  100Ω  Mouser  CFS1/4CT52R101J  660‐CFS1/4CT52R101J $0.008 $0.008
1  Q3  PMOSFET  FQPF2P25  Mouser  FQPF2P25  512‐FQPF2P25 $0.218 $0.218
1  U6  Opto‐TRIAC  MOC3023  Digi‐Key  MOC3023  160‐1378‐5‐ND $0.210 $0.210
1  D6  Zener  1N4733A  Mouser  1N4733A  78‐1N4733A $0.025 $0.025
 1  R19  Resistor  1.5MΩ  Digi‐Key  CFR‐25JB‐1M5  1.5MQBK‐ND $0.008 $0.008
1  R9  Resistor  750kΩ  Digi‐Key  CFR‐25JB‐750K  750KQBK‐ND $0.008 $0.008
1  R21  Resistor  5.6MΩ  Digi‐Key  CFR‐25JB‐5M6  5.6MQBK‐ND $0.008 $0.008
2  C11, C12  Capacitor  0.01uF  Mouser  140‐50Q5‐103Z‐RC  140‐50Q5‐103Z‐RC $0.020 $0.040
1  R20  Resistor  560kΩ  Digi‐Key  CFR‐25JB‐560K  560KQBK‐ND $0.008 $0.008
2  R12, R13  Resistor  360kΩ  Digi‐Key  CFR‐25JB‐360K  360KQBK‐ND $0.008 $0.016
2  R16, R17  Resistor  510kΩ  Digi‐Key  CFR‐25JB‐510K  510KQBK‐ND $0.008 $0.016
1  R18  Resistor  330Ω  Digi‐Key  CFR‐25JB‐330R  330QBK‐ND $0.008 $0.008
1  Q2  BJT  2N3904  Mouser  2N3904TA  512‐2N3904TA $0.017 $0.017
1  U5  Amplifier  LMV932  Mouser  LMV932ID  595‐LMV932ID $0.372 $0.372
1  U4  Timer IC  ICM7555  Digi‐Key  ICM7555CN/01  568‐1819‐5‐ND $0.133 $0.133
1  R6  Jumper  0Ω  Mouser  Z25YC  660‐Z25YC $0.007 $0.007
Total  $6.63
Date:  3/5/2007 

154 

 
Appendix B – Common Mode Effect Derivation
  The  team's  current‐monitoring  solution  is  centered  on  the  differential  amplifier,  such  the  one 
shown in Figure B‐1.  One of the potential issues with differential amplifiers is that, unless the resistors 

are  matched  precisely,  the  ideal  formula  of    does  not  hold.    If  the  resistor 

ratio is not    , noise will be introduced in the form of what is called common mode amplification.  

If, for example, the input nodes of a difference amplifier were 5V and 5.01V, the output would ideally be 
0.01V,  amplified  by  the  given  resistor  ratio.    If  this  resistor  ratio  is  not  accurate,  however,  the  5V 
common  to  each  input  node  begins  to  affect  the  output  voltage  as  well.    The  quality  of  differential 
amplifiers is often judged by the degree of common mode rejection they offer. 

 
FigureB‐1: Generic differential amplifier configuration. 
  Typical resistors have tolerances of 5%, though 1% and lower tolerances are available at added 
cost.  In order to see what effect these variances could have on amplifier in the low‐current sense, the 
amplifier’s performance when its associated resistors vary in value must be determined.   
Kirchhoff’s Current Law, as applied to the inverting node of the op‐amp, assuming infinite input 
impedance is: 

  (B‐1) 

   
 

155 

 
Solving for Vout: 

  (B‐2) 

  (B‐3) 

1   (B‐4) 

 
The voltage at the non‐inverting node of the op‐amp is: 

  (B‐5) 

 
  Due to the virtual ground effect, the voltages at the inverting and non‐inverting nodes are equal.  
Substituting into (B‐4): 
 

     (B‐6) 

So: 

  (B‐7) 

 
  (B‐7) defines the resistor‐based factors each input is amplified by before the difference is taken.  
Ideally these factors are equal, but it is clear that as resistor values vary this will not be the case.  This 
lopsided amplification factor can be emphasized with some further manipulation: 

  (B‐8) 

1   (B‐9) 

1   (B‐10) 

1   (B‐11) 

   (B‐12) 

156 

 
  (B‐12)  clearly  illustrates  the  results  of  resistor  mismatching,  amplifying  some  of  the  absolute 

(common)  voltage  at  the  input  rather  than  just  the  relative  (difference).    Notice  that  if      ,  the 

equation simplifies to the ideal difference‐amplifying case.   
There  is  even  a  third  way  to  look  at  this  unwanted  amplification,  by  explicitly  separating  the 
difference and common mode amplification factors.  We will begin with Equation 3, but first note that 
this equation is in the form: 
 
  (B‐13) 
 
Where: 
 

  and     (B‐14) 

 
We can then make the following manipulations: 

    (B‐15) 

    (B‐16) 

   (B‐17) 

   (B‐18) 

   (B‐19) 

 
So: 

  (B‐20) 

 
Note that the first half of (B‐20) is an amplification factor for the difference between the input 
voltages,  and  the  second  half  of  the  equation  is  an  amplification  factor  for  the  average  of  the  input 
voltages, or the common mode.  More explicitly: 
Difference gain: 

  (B‐21) 

157 

 
   (B‐22) 

Common mode gain: 

  (B‐23) 

  (B‐24) 

 
  Now  that  we  have  defined  the  difference  and  common  mode  gains,  we  can  return  to  our 

original  concern.    Note  that  the  common  mode  gain  in  (B‐24)  reduces  to  zero  if      .    However, 

what  happens  when  the  resistor  ratio  is  disturbed  by  inaccuracies,  such  that  1   ?    To 

determine  this  effect  we  will  assume  R1  is  equal  to  R2,  but  replace  R3  with  R3 1   and  R4  with 

R3 1 .  Starting with (B‐24), and assuming Gd remains approximately    , this effects performance as 

follows: 

   (B‐25) 

   (B‐26) 

   (B‐27) 

Assuming a relatively small tolerance,  1  approaches 1, leaving: 

  (B‐28) 

 
Gc  is  clearly  directly  related  to  resistor  tolerance.    But  common  mode  rejection  is  usually 
measured in what is called the Common Mode Rejection Ratio, or CMRR.  The CMRR is found by simply 
dividing the difference gain by the common mode gain.  It is commonly measured in decibels, with  

20    (B‐29) 

This ratio can be derived using our tolerance‐added resistors as follows: 

  (B‐30) 

158 

 
    (B‐31) 

   (B‐32) 

   (B‐33) 

   (B‐34) 

   (B‐35) 

Given any reasonably low tolerance,  1  will be very near 1, so: 

   (B‐36) 

   (B‐37) 

20   (B‐38) 

 
(B‐38) describes the relation between common mode reduction and resistor tolerance, where G 
is  the  desired  gain.    Notice  that  by  either  reducing  tolerance  or  increasing  the  desired  gain,  common 
mode rejection can be improved. 
 
   

159 

 
Appendix C – PSpice Simulation Code

Full Adapter
**ON Semiconductor DN06017/D Cell Phone Charger**
*
*
*Brendan Barschdorf & Russell Kernan
*Worcester Polytechnic Institute
*Dept. of Electrical & Computer Engineering
*Major Qualifying Project - Design of an Efficient Wall Adapter
*
*
*Friday, September 14, 2007

*Input Rectifier Model*

Vs 1 0 AC 1 SIN(0V 169.7V 60Hz) ; AC Input

C8 1 0 4.7n IC=0
R1 1 2 20
D1 2 3 D1N4007GP
C1 3 0 4.7u IC=0
L1 3 4 1m IC=0
C2 4 0 4.7u IC=0

*Snubber*

C5 4 5 1n IC=0
R2 4 5 150k
D3 6 5 DMUR160

*NCP1011 Subcircuit*

X1 10 11 6 0 NCP1011P10
*.SUBCKT NCP1011P10 VCC FB DRAIN GND
*X1 VCC FB DRAIN GND NCP101X PARAMS: Fsw=100k Conso=1m Ipeak=250m Rdson=26
*.ENDS
.LIB [Link]

*Aux Winding Rectifier*

R7 7 8 10
D4 8 9 D1N4148
C9 9 0 10u IC=0

*NCP1011 Vcc Voltage Regulation*

R8 9 10 2k
C3 10 0 10u IC=0

*Transformer*

X3 6 4 12 13 7 0 XFMRAUX
.SUBCKT XFMRAUX 1 2 3 4 5 6
*PRIMARY
L1 1 2 2000
RT 1 7 1u
RU 2 8 1u
L2 7 8 2000

160 

 
*SECONDARY
L3 3 4 20
L4 5 6 39.2
*MAGNETIC COUPLING
K13 L1 L3 0.99999
K24 L2 L4 0.99999
.ENDS

*Optocoupler Isolator*

C6 11 0 1n IC=0
X2 17 13 11 0 MOC8101
.SUBCKT MOC8101 1 2 3 5
* ISOLATOR AN CA CO EM
RB 4 0 1T
VM 1 6
D1 6 2 LED
H1 7 0 VM .0055
R1 7 8 1K
C1 8 0 3.35nF
G1 3 4 8 0 1
Q1 3 4 5 MPSA06
.MODEL LED D(N=1.7 RS=.7 CJO=23.9P IS=85.3p BV=6 IBV=10U
+ VJ=0.75 M=0.333 TT=4.32U)
.MODEL MPSA06 NPN (IS=15.2F NF=1 BF=589 VAF=98.6 IKF=90M ISE=3.34P NE=2
+ BR=4 NR=1 VAR=16 IKR=0.135 RE=0.343 RB=1.37 RC=0.137 XTB=1.5
+ CJE=9.67P VJE=1.1 MJE=0.5 CJC=7.34P VJC=0.3 MJC=0.3 TF=10.29n TR=276N)
.ENDS

*Output Filter*

D2 12 14 DMBR150RL
C4 14 13 1m IC=0
R4 14 15 1.2
C7 15 13 100n IC=0
Q1 16 15 14 D2N2907
X4 16 15 D1N4623
.SUBCKT D1N4623 4 2
.MODEL DHIGH D (
+IS=1E-7 RS=9.11 N=4.989)
.MODEL DLO D (IS=3.1E-7 RS=1.5K
+N=14.589)
.MODEL DF D (IS=1.76E-13
+RS=1.638M N=1.18 CJO=296.3P
+VJ=.547 M=.294)
V1 1 4 3.281
D2 2 3 DLO
V3 3 4 1.916
D3 4 2 DF
D1 2 1 DHIGH
.ENDS
R3 16 13 200
R5 16 17 100

*Output Load*

RL 15 13 100

*Resistive Isolation*

RB 13 0 1T

161 

 
.MODEL D1N4007GP D (
+ IS = 6.698e-07
+ RS = 0.04255
+ CJO = 1.949e-11
+ VJ = 0.3909
+ TT = 4.933e-06
+ M = 0.3577
+ BV = 1000
+ N = 2.412
+ EG = 1.11
+ XTI = 3
+ KF = 0
+ AF = 1
+ FC = 0.5
+ IBV = 0.005177
+ TNOM = 27
+ )

.MODEL DMUR160 D (
+IS=1.08U
+RS=55.5M
+N=2.59
+BV=800
+IBV=5U
+CJO=15.7P
+VJ=.75
+M=.310
+TT=108N
+ )

.MODEL D1N4148 D (
+IS=0.1P
+RS=16
+CJO=2P
+TT=12N
+BV=100
+IBV=3.867E-10
+ )

.MODEL DMBR150RL D (
+IS=6.47666e-09
+RS=0.184739
+N=0.832706
+EG=0.673879
+XTI=0.05
+BV=50
+IBV=0.0001
+CJO=2.81635e-10
+VJ=0.4
+M=0.559152
+FC=0.5
+TT=0
+KF=0
+AF=1
+ )

.MODEL D2N2907 PNP (

+IS=1.1p
+BF=200
+NF=1.2
+VAF=50
+IKF=0.1
162 

 
+ISE=13p
+NE=1.9
+BR=6
+RC=0.6
+CJE=23p
+VJE=0.85
+MJE=1.25
+TF=0.5n
+CJC=19p
+VJC=0.5
+MJC=0.2
+TR=34n
+XTB=1.5
+ )

.END

Simplified Adapter
**Simplified ON Semiconductor DN06017/D Cell Phone Charger**
*
*
*Brendan Barschdorf & Russell Kernan
*Worcester Polytechnic Institute
*Dept. of Electrical & Computer Engineering
*Major Qualifying Project - Design of an Efficient Wall Adapter
*
*
*Friday, September 18, 2007

*Input Rectifier Model*

Vs 1 0 AC 1 SIN(0V 169.7V 60Hz) ; AC Input

C8 1 0 4.7n IC=0
R1 1 2 20
D1 2 3 D1N4007GP
C1 3 0 4.7u IC=0
L1 3 4 1m IC=0
C2 4 0 4.7u IC=0

*Snubber*

C5 4 5 1n IC=0
R2 4 5 150k
D3 6 5 DMUR160

*Transformer*

X3 6 4 8 9 XFMRAUX
.SUBCKT XFMRAUX 1 2 3 4
*PRIMARY
L1 1 2 3.5m
*SECONDARY
L2 3 4 3.5m
*MAGNETIC COUPLING
K12 L1 L2 0.2500
.ENDS
163 

 
*Output Filter*

D2 8 10 DMBR150RL
C4 10 9 1m IC=0
R4 10 11 1.2
C7 11 9 100n IC=0
RL 11 9 100
Q1 12 11 10 D2N2907
X4 12 11 D1N4623
.SUBCKT D1N4623 4 2
.MODEL DHIGH D (
+IS=1E-7 RS=9.11 N=4.989)
.MODEL DLO D (IS=3.1E-7 RS=1.5K
+N=14.589)
.MODEL DF D (IS=1.76E-13
+RS=1.638M N=1.18 CJO=296.3P
+VJ=.547 M=.294)
V1 1 4 3.281
D2 2 3 DLO
V3 3 4 1.916
D3 4 2 DF
D1 2 1 DHIGH
.ENDS
R3 12 9 200
R5 12 13 100
RB 9 0 1T

*Optocoupler Isolator*

Vo 13 14 0
Ro 14 0 1m

*NCP1011 Output*

Vp 7 0 PULSE(0 339.4 0ms 20ns 10ns 5us 10us)

S1 6 0 7 0 Smod
.MODEL Smod VSWITCH(Ron=22 Roff=1MEG Von=339.4V Voff=0V)

.MODEL D1N4007GP D (
+ IS = 6.698e-07
+ RS = 0.04255
+ CJO = 1.949e-11
+ VJ = 0.3909
+ TT = 4.933e-06
+ M = 0.3577
+ BV = 1000
+ N = 2.412
+ EG = 1.11
+ XTI = 3
+ KF = 0
+ AF = 1
+ FC = 0.5
+ IBV = 0.005177
+ TNOM = 27
+ )

.MODEL DMUR160 D (
+IS=1.08U
+RS=55.5M
+N=2.59
+BV=800
164 

 
+IBV=5U
+CJO=15.7P
+VJ=.75
+M=.310
+TT=108N
+ )

.MODEL DMBR150RL D (
+IS=6.47666e-09
+RS=0.184739
+N=0.832706
+EG=0.673879
+XTI=0.05
+BV=50
+IBV=0.0001
+CJO=2.81635e-10
+VJ=0.4
+M=0.559152
+FC=0.5
+TT=0
+KF=0
+AF=1
+ )

.MODEL D2N2907 PNP (

+IS=1.1p
+BF=200
+NF=1.2
+VAF=50
+IKF=0.1
+ISE=13p
+NE=1.9
+BR=6
+RC=0.6
+CJE=23p
+VJE=0.85
+MJE=1.25
+TF=0.5n
+CJC=19p
+VJC=0.5
+MJC=0.2
+TR=34n
+XTB=1.5
+ )

.END
 

   

165 

 
Appendix D – Related Patent
   
When  first  approaching  the  project,  and  occasionally  throughout  the  process,  the  team 
searched journals and patents for any possible insight that might be had there.  While largely coming up 
empty,  in  the  final  month  of  the  project  the  team  happened  upon  United  States  Patent  6,339,314,  a 
Battery Charger Circuit with Low Standby Power Dissipation.  The patent, presented here over the next 8 
pages,  lists  Gert  W.    Bruning  as  inventor  and  Philips  Electronics  as  assignee  and  address  the  same 
problem of no‐load waste current in battery charging AC adapters. 
The patent describes a similar polling solution to ours, vaguely referencing load detection and 
timing circuitry.  Interestingly, all of this added solution circuitry is placed on the AC side of the adapter, 
including the current‐sensing subcircuit.  The team feels that this puts too much reliance on predictable 
transformer  performance.    Additionally,  the  team  discovered  over  the  course  of  the  project  that  the 
apparent  input  current  is  not  always  accurate  or  easily  measured,  and  believes  sensing  the  current  at 
the  output  logically  results  in  a  value  much  closer  to  what  is  actually  being  sourced  to  the  load.  
Therefore, while it was interesting to find another  effort made  previously to solve the same problem, 
the team considers their solution more complete and efficient. 
 
 
 
 
   

166 

 
Appendix E – Datasheets
   
The following pages contain the datasheets of all major ICs referenced within this report.  They 
are, in order: 
NCP1011  Self‐Supplied Monolithic Switcher for Low Standby‐Power Offline SMPS 
OPA344   Low Power, Single‐Supply, Rail‐to‐Rail Operational Amplifiers 
TLC27L2   Precision Dual Operational Amplifiers 
LMV932   Operational Amplifiers with Rail‐to‐Rail Input and Output 
ICM7555   General Purpose Timers 
FQPF2P25   250V P‐Channel MOSFET 
MOC3023   Optocouplers/Optoisolators 
 

175 

 
NCP1010, NCP1011,
NCP1012, NCP1013,
NCP1014
Self-Supplied Monolithic
Switcher for Low Standby-
Power Offline SMPS
[Link]
The NCP101X series integrates a fixed-frequency current-mode
controller and a 700 V MOSFET. Housed in a PDIP-7, MARKING DIAGRAMS
PDIP-7 Gull Wing, or SOT-223 package, the NCP101X offers 4
everything needed to build a rugged and low-cost power supply, 4 SOT-223
including soft-start, frequency jittering, short-circuit protection, CASE 318E AYW
1 101xyG
skip-cycle, a maximum peak current setpoint and a Dynamic ST SUFFIX G
Self-Supply (no need for an auxiliary winding).
1
Unlike other monolithic solutions, the NCP101X is quiet by nature:
during nominal load operation, the part switches at one of the available
frequencies (65 - 100 - 130 kHz). When the current setpoint falls PDIP-7 P101xAPyy
below a given value, e.g. the output power demand diminishes, the IC CASE 626A AWL
8 AP SUFFIX YYWWG
automatically enters the so-called skip-cycle mode and provides
excellent efficiency at light loads. Because this occurs at typically 1/4 1 1
of the maximum peak value, no acoustic noise takes place. As a result,
standby power is reduced to the minimum without acoustic noise PDIP-7
generation. (Gull Wing) 1xAPLyyy
CASE 626AA AWL
Short-circuit detection takes place when the feedback signal fades YYWWG
1 APL SUFFIX
away, e.g. in true short-circuit conditions or in broken Optocoupler
1
cases. External disabling is easily done either simply by pulling the
feedback pin down or latching it to ground through an inexpensive x = Current Limit (0, 1, 2, 3, 4)
SCR for complete latched-off. Finally soft-start and frequency y = Oscillator Frequency
jittering further ease the designer task to quickly develop low-cost and A (65 kHz), B (100 kHz), C (130 kHz)
yy = 06 (65 kHz), 10 (100 kHz), 13 (130 kHz)
robust offline power supplies. yyy = 065, 100, 130
For improved standby performance, the connection of an auxiliary A = Assembly Location
winding stops the DSS operation and helps to consume less than WL, L = Wafer Lot
YY, Y = Year
100 mW at high line. In this mode, a built-in latched overvoltage WW, W = Work Week
protection prevents from lethal voltage runaways in case the G or G = Pb-Free Package
Optocoupler would brake. These devices are available in economical (Note: Microdot may be in either location)
8-pin dual-in-line and 4-pin SOT-223 packages.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
Features
• Built-in 700 V MOSFET with Typical RDSon of 11 W • Auto-Recovery Internal Output Short-Circuit
and 22 W Protection
• Large Creepage Distance Between High-Voltage Pins • Below 100 mW Standby Power if Auxiliary Winding
• Current-Mode Fixed Frequency Operation: is Used
65 kHz – 100 kHz - 130 kHz • Internal Temperature Shutdown
• Skip-Cycle Operation at Low Peak Currents Only: • Direct Optocoupler Connection
No Acoustic Noise! • SPICE Models Available for TRANsient Analysis
• Dynamic Self-Supply, No Need for an Auxiliary • Pb-Free Packages are Available
Winding
• Internal 1.0 ms Soft-Start Typical Applications
• Latched Overvoltage Protection with Auxiliary • Low Power AC/DC Adapters for Chargers
Winding Operation • Auxiliary Power Supplies (USB, Appliances,TVs, etc.)
• Frequency Jittering for Better EMI Signature

© Semiconductor Components Industries, LLC, 2007 1 Publication Order Number:

July, 2007 - Rev. 18 NCP1010/D
 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

PIN CONNECTIONS
PDIP-7
PDIP-7 (Gull Wing) SOT-223

VCC 1 8 GND VCC 1 8 GND VCC 1

NC 2 7 GND NC 2 7 GND FB 2 4 GND

GND 3 GND 3 DRAIN 3

FB 4 5 DRAIN FB 4 5 DRAIN
(Top View)
(Top View) (Top View)

Indicative Maximum Output Power from NCP1014

RDSon - Ip 230 Vac 100 - 250 Vac
11 W - 450 mA DSS 14 W 6.0 W
11 W - 450 mA Auxiliary Winding 19 W 8.0 W
1. Informative values only, with: Tamb = 50°C, Fswitching = 65 kHz, circuit mounted on minimum copper area as recommended.

Vout

100-250 Vac
1 8

2 7

4 5
+
NCP101X

GND

Figure 1. Typical Application Example

Quick Selection Table

NCP1010 NCP1011 NCP1012 NCP1013 NCP1014
RDSon [W] 22 11
Ipeak [mA] 100 250 250 350 450
Freq [kHz] 65 100 130 65 100 130 65 100 130 65 100 130 65 100

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 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

PIN FUNCTION DESCRIPTION

Pin No.
Pin No. (PDIP-7,
(SOT-223) PDIP-7/Gull Wing) Pin Name Function Description
1 1 VCC Powers the Internal Circuitry This pin is connected to an external capacitor of typic‐
ally 10 mF. The natural ripple superimposed on the
VCC participates to the frequency jittering. For im‐
proved standby performance, an auxiliary VCC can be
connected to Pin 1. The VCC also includes an active
shunt which serves as an opto fail-safe protection.
- 2 NC - -
- 3 GND The IC Ground -
2 4 FB Feedback Signal Input By connecting an optocoupler to this pin, the peak
current setpoint is adjusted accordingly to the output
power demand.
3 5 Drain Drain Connection The internal drain MOSFET connection.
- - - - -
- 7 GND The IC Ground -
4 8 GND The IC Ground -

VCC Startup Source

Iref = 7.4 mA -
VCC 1 Drain 8 GND
IVCC +
Vclamp*
Rsense
High when VCC t 3 V S
I? UVLO R
IVCC 250 ns
Management
Q L.E.B.

Reset
NC 2 7 GND
EMI Jittering 65, 100 or Set Q
4V Flip-Flop
130 kHz Driver
Clock DCmax = 65%

Reset
18 k VCC

Error flag armed?

GND 3 -
+
+
-

0.5 V
+
Overload?
-
Startup Sequence
Soft-Start Overload

FB 4 Drain 5 Drain

*Vclamp = VCCOFF + 200 mV (8.7 V Typical)

Figure 2. Simplified Internal Circuit Architecture

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 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MAXIMUM RATINGS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating
Power Supply Voltage on all pins, except Pin 5 (Drain)
Symbol
VCC
Value
-0.3 to 10
Unit
V
Drain Voltage - -0.3 to 700 V
Drain Current Peak during Transformer Saturation IDS(pk)
NCP1010/11 550 mA
NCP1012/13/14 1.0 A
Maximum Current into Pin 1 when Activating the 8.7 V Active Clamp I_VCC 15 mA
Thermal Characteristics °C/W
P Suffix, Case 626A
 Junction-to-Lead RqJL 9.0
 Junction-to-Air, 2.0 oz (70 mm) Printed Circuit Copper Clad RqJA
  0.36 Sq. Inch (2.32 Sq. Cm) 77
  1.0 Sq. Inch (6.45 Sq. Cm) 60
PL Suffix (Gull Wing), Case 626AA
 Junction-to-Lead RqJL 11.9
 Junction-to-Air, 2.0 oz (70 mm) Printed Circuit Copper Clad RqJA
  0.36 Sq. Inch (2.32 Sq. Cm) 92
  1.0 Sq. Inch (6.45 Sq. Cm) 71
ST Suffix, Plastic Package Case 318E
 Junction-to-Lead RqJL 14
 Junction-to-Air, 2.0 oz (70 mm) Printed Circuit Copper Clad RqJA
  0.36 Sq. Inch (2.32 Sq. Cm) 74
  1.0 Sq. Inch (6.45 Sq. Cm) 55
Maximum Junction Temperature TJmax 150 °C
Storage Temperature Range - -60 to +150 °C
ESD Capability, Human Body Model (All pins except HV) - 2.0 kV
ESD Capability, Machine Model - 200 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

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 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
VCC = 8.0 V unless otherwise noted.)
Rating Pin Symbol Min Typ Max Unit
SUPPLY SECTION AND VCC MANAGEMENT
VCC Increasing Level at which the Current Source Turns-off 1 VCCOFF 7.9 8.5 9.1 V
VCC Decreasing Level at which the Current Source Turns-on 1 VCCON 6.9 7.5 8.1 V
Hysteresis between VCCOFF and VCCON 1 - - 1.0 - V
VCC Decreasing Level at which the Latch-off Phase Ends 1 VCClatch 4.4 4.7 5.1 V
VCC Decreasing Level at which the Internal Latch is Released 1 VCCreset - 3.0 - V
Internal IC Consumption, MOSFET Switching at 65 kHz 1 ICC1 - 0.92 1.1 mA
(Note 2)
Internal IC Consumption, MOSFET Switching at 100 kHz 1 ICC1 - 0.95 1.15 mA
(Note 2)
Internal IC Consumption, MOSFET Switching at 130 kHz 1 ICC1 - 0.98 1.2 mA
(Note 2)
Internal IC Consumption, Latch-off Phase, VCC = 6.0 V 1 ICC2 - 290 - mA
Active Zener Voltage Positive Offset to VCCOFF 1 Vclamp 140 200 300 mV
Latch-off Current 1 ILatch mA
NCP1012/13/14 6.3 7.4 9.2
NCP1010/11 5.8 7.3 9.0
POWER SWITCH CIRCUIT
Power Switch Circuit On-state Resistance 5 RDSon - W
NCP1012/13/14 (Id = 50 mA)
TJ = 25°C 11 16
TJ = 125°C 19 24
NCP1010/11 (Id = 50 mA)
TJ = 25°C 22 35
TJ = 125°C 38 50
Power Switch Circuit and Startup Breakdown Voltage 5 BVdss 700 - - V
(ID(off) = 120 mA, TJ = 25°C)
Power Switch and Startup Breakdown Voltage Off-state IDS(OFF) mA
Leakage Current
TJ = 25°C (Vds = 700 V) 5 - 50 -
TJ = 125°C (Vds = 700 V) 5 - 30 -

Switching Characteristics ns
(RL = 50 W, Vds Set for Idrain = 0.7 x Ilim)
Turn-on Time (90%-10%) 5 ton - 20 -
Turn-off Time (10%-90%) 5 toff - 10 -

INTERNAL STARTUP CURRENT SOURCE

High-voltage Current Source, VCC = 8.0 V 1 IC1 mA
NCP1012/13/14 5.0 8.0 10
NCP1010/11 5.0 8.5 10.3
High-voltage Current Source, VCC = 0 1 IC2 - 10 - mA
CURRENT COMPARATOR TJ = 25°C (Note 2)
Maximum Internal Current Setpoint, NCP1010 (Note 3) 5 Ipeak (22) 90 100 110 mA
Maximum Internal Current Setpoint, NCP1011 (Note 3) 5 Ipeak (22) 225 250 275 mA
Maximum Internal Current Setpoint, NCP1012 (Note 3) 5 Ipeak (11) 225 250 275 mA
Maximum Internal Current Setpoint, NCP1013 (Note 3) 5 Ipeak (11) 315 350 385 mA
Maximum Internal Current Setpoint, NCP1014 (Note 3) 5 Ipeak (11) 405 450 495 mA
Default Internal Current Setpoint for Skip-Cycle Operation, - ILskip - 25 - %
Percentage of Max Ip
Propagation Delay from Current Detection to Drain OFF State - TDEL - 125 - ns
Leading Edge Blanking Duration - TLEB - 250 - ns
2. See characterization curves for temperature evolution.
3. Adjust di/dt to reach Ipeak in 3.2 msec.

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 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C,
Max TJ = 150°C, VCC= 8.0 V unless otherwise noted.)
Rating Pin Symbol Min Typ Max Unit
INTERNAL OSCILLATOR
Oscillation Frequency, 65 kHz Version, TJ = 25°C (Note 4) - fOSC 59 65 71 kHz
Oscillation Frequency, 100 kHz Version, TJ = 25°C (Note 4) - fOSC 90 100 110 kHz
Oscillation Frequency, 130 kHz Version, TJ = 25°C (Note 4) - fOSC 117 130 143 kHz
Frequency Dithering Compared to Switching Frequency - fdither - "3.3 - %
(with active DSS)
Maximum Duty-cycle - Dmax 62 67 72 %
FEEDBACK SECTION
Internal Pull-up Resistor 4 Rup - 18 - kW
Internal Soft-Start (Guaranteed by Design) - Tss - 1.0 - ms
SKIP-CYCLE GENERATION
Default Skip Mode Level on FB Pin 4 Vskip - 0.5 - V
TEMPERATURE MANAGEMENT
Temperature Shutdown - TSD 140 150 160 °C
Hysteresis in Shutdown - - - 50 - °C
4. See characterization curves for temperature evolution.

TYPICAL CHARACTERISTICS
-2.0 1.50
1.40
-3.0
1.30
-4.0
1.20
-5.0 1.10
IC1 ( mA)

ICC1 (mA)

-6.0 1.00
0.90
-7.0
0.80
-8.0
0.70
-9.0 0.60
-10.0 0.50
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 3. IC1 @ VCC = 8.0 V, FB = 1.5 V Figure 4. ICC1 @ VCC = 8.0 V, FB = 1.5 V
vs. Temperature vs. Temperature
0.40 9.00
0.38
8.90
0.36
8.80
0.34
VCC-OFF ( V )

8.70
ICC2 (mA)

0.32
0.30 8.60
0.28
8.50
0.26
8.40
0.24
0.22 8.30

0.20 8.20
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 5. ICC2 @ VCC = 6.0 V, FB = Open Figure 6. VCC OFF, FB = 1.5 V vs. Temperature
vs. Temperature

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 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

TYPICAL CHARACTERISTICS

8.00 68
7.90
68
7.80
7.70

DUTY CYCLE (%)

67
VCC-ON ( V)

7.60
7.50 67
7.40
66
7.30
7.20
66
7.10
7.00 65
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 7. VCC ON, FB = 3.5 V vs. Temperature Figure 8. Duty Cycle vs. Temperature

9.00 500
8.80 480
8.60 460
8.40 440
I_Latch (mA)

8.20 420
Ipeak (mA)

8.00 400
7.80 380 NCP1013

7.60 360
7.40 340
7.20 320
7.00 300
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 9. ILatch, FB = 1.5 V vs. Temperature Figure 10. Ipeak-RR, VCC = 8.0 V, FB = 3.5 V
vs. Temperature
160 25.00

140
130 kHz 20.00

120
15.00
fOSC (kHz)

RDSon (W)

100 kHz
100
10.00
80

5.00
60

40 0.00
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 11. Frequency vs. Temperature Figure 12. ON Resistance vs. Temperature,
NCP1012/1013

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 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

APPLICATION INFORMATION

Introduction No acoustic noise while operating: Instead of skipping

The NCP101X offers a complete current-mode control cycles at high peak currents, the NCP101X waits until the
solution (actually an enhanced NCP1200 controller section) peak current demand falls below a fixed 1/4 of the maximum
together with a high-voltage power MOSFET in a limit. As a result, cycle skipping can take place without
monolithic structure. The component integrates everything having a singing transformer … You can thus select cheap
needed to build a rugged and low-cost Switch-Mode Power magnetic components free of noise problems.
Supply (SMPS) featuring low standby power. The Quick SPICE model: A dedicated model to run transient
Selection Table on Page 2, details the differences between cycle-by-cycle simulations is available but also an
references, mainly peak current setpoints and operating averaged version to help close the loop. Ready-to-use
frequency. templates can be downloaded in OrCAD's PSpice, and
No need for an auxiliary winding: ON Semiconductor INTUSOFT's IsSpice4 from ON Semiconductor web site,
Very High Voltage Integrated Circuit technology lets you NCP101X related section.
supply the IC directly from the high-voltage DC rail. We call
it Dynamic Self-Supply (DSS). This solution simplifies the Dynamic Self-Supply
transformer design and ensures a better control of the SMPS When the power supply is first powered from the mains
in difficult output conditions, e.g. constant current outlet, the internal current source (typically 8.0 mA) is
operations. However, for improved standby performance, biased and charges up the VCC capacitor from the drain pin.
an auxiliary winding can be connected to the VCC pin to Once the voltage on this VCC capacitor reaches the VCCOFF
disable the DSS operation. level (typically 8.5 V), the current source turns off and
pulses are delivered by the output stage: the circuit is awake
Short-circuit protection: By permanently monitoring the
and activates the power MOSFET. Figure 13 details the
feedback line activity, the IC is able to detect the presence of
internal circuitry.
a short-circuit, immediately reducing the output power for
a total system protection. Once the short has disappeared, the Vref OFF = 8.5 V
controller resumes and goes back to normal operation. Vref ON = 7.5 V
Drain

Fail-safe optocoupler and OVP: When an auxiliary Vref Latch = 4.7 V*

winding is connected to the VCC pin, the device stops its
internal Dynamic Self-Supply and takes its operating power +
Startup Source
from the auxiliary winding. A 8.7 V active clamp is -
connected between VCC and ground. In case the current
injected in this clamp exceeds a level of 7.4 mA (typical), Internal Supply VCC
the controller immediately latches off and stays in this
position until VCC cycles down to 3.0 V (e.g. unplugging the
converter from the wall). By adjusting a limiting resistor in + +
Vref VCCOFF CVCC
series with the VCC terminal, it becomes possible to
+200 mV
implement an overvoltage protection function, latching off (8.7 V Typ.)
the circuit in case of broken optocoupler or feedback loop
problems. *In fault condition
Low standby-power: If SMPS naturally exhibits a good
efficiency at nominal load, it begins to be less efficient when Figure 13. The Current Source Regulates VCC
the output power demand diminishes. By skipping unneeded by Introducing a Ripple
switching cycles, the NCP101X drastically reduces the
power wasted during light load conditions. An auxiliary
winding can further help decreasing the standby power to
extremely low levels by invalidating the DSS operation.
Typical measurements show results below 80 mW @
230 Vac for a typical 7.0 W universal power supply.

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 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

8.5 V
8.00

Vcc 7.5 V

6.00

4.00

Device
Internally
2.00
Pulses

0
Startup Period

Figure 14. The Charge/Discharge Cycle Over a 10 mF VCC Capacitor

The protection burst duty-cycle can easily be computed for the presence of the error flag every time VCC crosses
through the various timing events as portrayed by Figure 16. VCCON. If the error flag is low (peak limit not active) then
Being loaded by the circuit consumption, the voltage on the IC works normally. If the error signal is active, then the
the VCC capacitor goes down. When the DSS controller NCP101X immediately stops the output pulses, reduces its
detects that VCC has reached 7.5 V (VCCON), it activates the internal current consumption and does not allow the startup
internal current source to bring VCC toward 8.5 V and stops source to activate: VCC drops toward ground until it reaches
again: a cycle takes place whose low frequency depends on the so-called latch-off level, where the current source
the VCC capacitor and the IC consumption. A 1.0 V ripple activates again to attempt a new restart. When the error is
takes place on the VCC pin whose average value equals gone, the IC automatically resumes its operation. If the
(VCCOFF + VCCON)/2. Figure 14 portrays a typical default is still there, the IC pulses during 8.5 V down to 7.5 V
operation of the DSS. and enters a new latch-off phase. The resulting burst
As one can see, the VCC capacitor shall be dimensioned to operation guarantees a low average power dissipation and
offer an adequate startup time, i.e. ensure regulation is lets the SMPS sustain a permanent short-circuit. Figure 15
reached before VCC crosses 7.5 V (otherwise the part enters shows the corresponding diagram.
the fault condition mode). If we know that DV = 1.0 V
and ICC1 (max) is 1.1 mA (for instance we selected an 11 W Current Sense
device switching at 65 kHz), then the VCC capacitor can Information
4V
ICC1·tstartup (eq. 1)
be calculated using: C w . Let's
DV
suppose that the SMPS needs 10 ms to startup, then we will FB +
calculate C to offer a 15 ms period. As a result, C should be Division - To
Latch
greater than 20 mF thus the selection of a 33 mF/16 V VCC VCCON Reset
capacitor is appropriate. Max
Signal
Ip
Short Circuit Protection
The internal protection circuitry involves a patented
arrangement that permanently monitors the assertion of an Flag
Clamp
internal error flag. This error flag is, in fact, a signal that Active?
instructs the controller that the internal maximum peak
current limit is reached. This naturally occurs during the
startup period (Vout is not stabilized to the target value) or
when the optocoupler LED is no longer biased, e.g. in a Figure 15. Simplified NCP101X Short-Circuit
short-circuit condition or when the feedback network is Detection Circuitry
broken. When the DSS normally operates, the logic checks

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 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

Tsw
1 V Ripple
Tstart

TLatch

Latch-off
Level

Figure 16. NCP101X Facing a Fault Condition (Vin = 150 Vdc)

The rising slope from the latch-off level up to 8.5 V Vds(t)

is expressed by: Tstart + DV1·C. The time during which

IC1 toff
the IC actually pulses is given by tsw + DV2·C. Vr
ICC1
Finally, the latch-off time can be derived Vin dt

using the same formula topology: TLatch + DV3·C.

ICC2
From these three definitions, the burst duty-cycle
can be computed: dc + Tsw (eq. 2) .
Tstart ) Tsw ) TLatch
ton
dc + DV2 . Feeding the t
ICC1·ǒICC1
DV2
) DV1
IC1
DV3 Ǔ (eq. 3)
) ICC2 Tsw
equation with values extracted from the parameter section
gives a typical duty-cycle of 13%, precluding any lethal Figure 17. A typical drain-ground waveshape
where leakage effects are not accounted for.
thermal runaway while in a fault condition.

DSS Internal Dissipation By looking at Figure 17, the average result can easily be
The Dynamic Self-Supplied pulls energy out from the derived by additive square area calculation:
drain pin. In Flyback-based converters, this drain level can
t Vds(t) u+ Vin·(1 * d) ) Vr· toff (eq. 5)
easily go above 600 V peak and thus increase the stress on the Tsw
DSS startup source. However, the drain voltage evolves with By developing Equation 5, we obtain:
time and its period is small compared to that of the DSS. As
a result, the averaged dissipation, excluding capacitive losses, t Vds(t) u+ Vin * Vin· ton ) Vr· toff (eq. 6)
Tsw Tsw
can be derived by: PDSS + ICC1· t Vds(t) u . (eq. 4) .
Lp
Figure 17 portrays a typical drain-ground waveshape where toff can be expressed by: toff + Ip· (eq. 7) where ton
Vr
leakage effects have been removed. Lp
can be evaluated by: ton + Ip· (eq. 8) .
Vin

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 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

Plugging Equations 7 and 8 into Equation 6 leads to Itrip is the current corresponding to the nominal operation.
t Vds(t) u+ Vin and thus, PDSS + Vin ICC1 (eq. 9) . It must be selected to avoid false tripping in overshoot
The worse case occurs at high line, when Vin equals conditions.
370 Vdc. With ICC1 = 1.1 mA (65 kHz version), we can ICC1 is the controller consumption. This number slightly
expect a DSS dissipation around 407 mW. If you select a decreases compared to ICC1 from the spec since the part in
higher switching frequency version, the ICC1 increases and standby almost does not switch.
it is likely that the DSS consumption exceeds that number.
VCCON is the level above which Vaux must be maintained
In that case, we recommend to add an auxiliary winding in
to keep the DSS in the OFF mode. It is good to shoot around
order to offer more dissipation room to the power MOSFET.
8.0 V in order to offer an adequate design margin, e.g. to not
Please read application note AND8125/D, “Evaluating
reactivate the startup source (which is not a problem in itself
the Power Capability of the NCP101X Members” to help in
if low standby power does not matter).
selecting the right part/configuration for your application.
Since Rlimit shall not bother the controller in standby, e.g.
Lowering the Standby Power with an Auxiliary Winding keep Vaux to around 8.0 V (as selected above), we purposely
The DSS operation can bother the designer when its select a Vnom well above this value. As explained before,
dissipation is too high and extremely low standby power is experience shows that a 40% decrease can be seen on
a must. In both cases, one can connect an auxiliary winding auxiliary windings from nominal operation down to standby
to disable the self-supply. The current source then ensures mode. Let's select a nominal auxiliary winding of 20 V to
the startup sequence only and stays in the off state as long as offer sufficient margin regarding 8.0 V when in standby
VCC does not drop below VCCON or 7.5 V. Figure 18 shows (Rlimit also drops voltage in standby…). Plugging the
that the insertion of a resistor (Rlimit) between the auxiliary values in Equation 10 gives the limits within which Rlimit
DC level and the VCC pin is mandatory to not damage the shall be selected:
internal 8.7 V active Zener diode during an overshoot for 20 * 8.7 v Rlimit v 12 * 8
instance (absolute maximum current is 15 mA) and to 6.3m 1.1m , that is to say:
(eq. 11)
implement the fail-safe optocoupler protection as offered by 1.8k t Rlimit t 3.6k
the active clamp. Please note that there cannot be bad If we design a power supply delivering 12 V, then the ratio
interaction between the clamping voltage of the internal between auxiliary and power must be: 12/20 = 0.6. The OVP
Zener and VCCOFF since this clamping voltage is actually latch will activate when the clamp current exceeds 6.3 mA.
built on top of VCCOFF with a fixed amount of offset This will occur when Vaux increases to: 8.7 V + 1.8 k x
(200 mV typical). (6.4m + 1.1m) = 22.2 V for the first boundary or 8.7 V +
Self-supplying controllers in extremely low standby 3.6 k x (6.4m +1.1m) = 35.7 V for second boundary. On the
applications often puzzles the designer. Actually, if a SMPS power output, it will respectively give 22.2 x 0.6 = 13.3 V
operated at nominal load can deliver an auxiliary voltage of and 35.7 x 0.6 = 21.4 V. As one can see, tweaking the Rlimit
an arbitrary 16 V (Vnom), this voltage can drop to below value will allow the selection of a given overvoltage output
10 V (Vstby) when entering standby. This is because the level. Theoretically predicting the auxiliary drop from
recurrence of the switching pulses expands so much that the nominal to standby is an almost impossible exercise since
low frequency refueling rate of the VCC capacitor is not many parameters are involved, including the converter time
enough to keep a constant auxiliary voltage. Figure 19 constants. Fine tuning of Rlimit thus requires a few
portrays a typical scope shot of a SMPS entering deep iterations and experiments on a breadboard to check Vaux
standby (output unloaded). So care must be taken when variations but also output voltage excursion in fault. Once
calculating Rlimit 1) to not trigger the VCC over current properly adjusted, the fail-safe protection will preclude any
latch [by injecting 6.3 mA (min. value) into the active lethal voltage runaways in case a problem would occur in the
clamp] in normal operation but 2) not to drop too much feedback loop.
voltage over Rlimit when entering standby. Otherwise the When an OVP occurs, all switching pulses are
DSS could reactivate and the standby performance would permanently disabled, the output voltage thus drops to zero.
degrade. We are thus able to bound Rlimit between two The VCC cycles up and down between 8.5–4.7 V and stays
equations: in this state until the user unplugs the power supply and
Vnom * Vclamp Vstby * VCCON (eq. 10) forces VCC to drop below 3.0 V (VCCreset). Below this
v Rlimit v value, the internal OVP latch is reset and when the high
Itrip ICC1
Where: voltage is reapplied, a new startup sequence can take place
in an attempt to restart the converter.
Vnom is the auxiliary voltage at nominal load.
Vstdby is the auxiliary voltage when standby is entered.

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 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

Drain
VCCON = 8.5 V
VCCOFF = 7.5 V

-
+ Startup Source
+
VCC Rlimit D1

+
-
+ + +
Vclamp = 8.7 V typ. CVcc Caux Laux

Permanent +
Latch -
+ I > 7.4m
(Typ.)

Ground

Figure 18. A more detailed view of the NCP101X offers better insight on how to
properly wire an auxiliary winding.

u30 ms

Figure 19. The burst frequency becomes so low that it is difficult to keep
an adequate level on the auxiliary VCC . . .

Lowering the Standby Power with Skip-Cycle which is excited by the skipping pulses. A possible
Skip-cycle offers an efficient way to reduce the standby solution, successfully implemented in the NCP1200 series,
power by skipping unwanted cycles at light loads. also authorizes skip-cycle but only when the power
However, the recurrent frequency in skip often enters the demand has dropped below a given level. At this time, the
audible range and a high peak current obviously generates peak current is reduced and no noise can be heard.
acoustic noise in the transformer. The noise takes its origins Figure 20 pictures the peak current evolution of the
in the resonance of the transformer mechanical structure NCP101X entering standby.

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 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

100%
Peak current
at nominal power

Skip-cycle
current limit

25%

Figure 20. Low Peak Current Skip-Cycle Guarantees Noise-Free Operation

Full power operation involves the nominal switching the benefit to artificially reduce the measurement noise on
frequency and thus avoids any noise when running. a standard EMI receiver and pass the tests more easily. The
Experiments carried on a 5.0 W universal mains board EMI sweep is implemented by routing the VCC ripple
unveiled a standby power of 300 mW @ 230 Vac with the (induced by the DSS activity) to the internal oscillator. As a
DSS activated and dropped to less than 100 mW when an result, the switching frequency moves up and down to the
auxiliary winding is connected. DSS rhythm. Typical deviation is "3.3% of the nominal
frequency. With a 1.0 V peak-to-peak ripple, the frequency
Frequency Jittering for Improved EMI Signature will equal 65 kHz in the middle of the ripple and will
By sweeping the switching frequency around its nominal increase as VCC rises or decrease as VCC ramps down.
value, it spreads the energy content on adjacent frequencies Figure 21 portrays the behavior we have adopted.
rather than keeping it centered in one single ray. This offers

VCCOFF
VCC Ripple
67.15 kHz

65 kHz

62.85 kHz
Internal Sawtooth
VCCON

Figure 21. The VCC ripple is used to introduce a frequency jittering on the internal oscillator sawtooth.
Here, a 65 kHz version was selected.

[Link]
13
 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

Soft-Start
The NCP101X features an internal 1.0 ms soft-start (OCP) sequence. Every restart attempt is followed by a
activated during the power on sequence (PON). As soon as soft-start activation. Generally speaking, the soft-start will
VCC reaches VCCOFF, the peak current is gradually be activated when VCC ramps up either from zero (fresh
increased from nearly zero up to the maximum internal power-on sequence) or 4.7 V, the latch-off voltage
clamping level (e.g. 350 mA). This situation lasts 1.0 ms occurring during OCP. Figure 22 portrays the soft-start
and further to that time period, the peak current limit is behavior. The time scales are purposely shifted to offer a
blocked to the maximum until the supply enters regulation. better zoom portion.
The soft-start is also activated during the over current burst

VCC 8.5 V

0 V (Fresh PON)
or
4.7 V (Overload)

Current Max Ip
Sense

1.0 ms

Figure 22. Soft-Start is activated during a startup sequence or an OCP condition.

Non-Latching Shutdown
In some cases, it might be desirable to shut off the part and ground. By pulling FB below the internal skip level
temporarily and authorize its restart once the default has (Vskip), the output pulses are disabled. As soon as FB is
disappeared. This option can easily be accomplished relaxed, the IC resumes its operation. Figure 23 depicts the
through a single NPN bipolar transistor wired between FB application example.

1 8

2 7

4 5 Drain

ON/OFF +
CVcc

Figure 23. A non-latching shutdown where pulses are stopped as long as the NPN is biased.

[Link]
14
 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

Full Latching Shutdown

Other applications require a full latching shutdown, e.g. voltage, the NPN biases the PNP and fires the equivalent
when an abnormal situation is detected (overtemperature SCR, permanently bringing down the FB pin. The
or overvoltage). This feature can easily be implemented switching pulses are disabled until the user unplugs the
through two external transistors wired as a discrete SCR. power supply.
When the OVP level exceeds the Zener breakdown
Rhold
OVP 12 k
1 8

2 7
10 k
BAT54 3

4 5 Drain

+
CVcc
10 k

Figure 24. Two Bipolars Ensure a Total Latch-Off of the SMPS in Presence of an OVP

Rhold ensures that the SCR stays on when fired. The bias maximum power the device can thus evacuate is:
current flowing through Rhold should be small enough to let T * Tambmax
Pmax + Jmax (eq. 12) which gives around
the VCC ramp up (8.5 V) and down (7.5 V) when the SCR RqJA
is fired. The NPN base can also receive a signal from a 1.0 W for an ambient of 50°C. The losses inherent to the
temperature sensor. Typical bipolars can be MMBT2222 MOSFET RDSon can be evaluated using the following
and MMBT2907 for the discrete latch. The MMBT3946 formula: Pmos + 1 ·Ip2·d·RDSon (eq. 13) , where Ip
features two bipolars NPN+PNP in the same package and 3
is the worse case peak current (at the lowest line input), d is
could also be used.
the converter operating duty-cycle and RDSon, the
Power Dissipation and Heatsinking MOSFET resistance for TJ = 100°C. This formula is only
The NCP101X welcomes two dissipating terms, the DSS valid for Discontinuous Conduction Mode (DCM)
current-source (when active) and the MOSFET. Thus, operation where the turn-on losses are null (the primary
Ptot = PDSS + PMOSFET. When the PDIP-7 package is current is zero when you restart the MOSFET). Figure 25
surrounded by copper, it becomes possible to drop its gives a possible layout to help drop the thermal resistance.
thermal resistance junction-to-ambient, RqJA down When measured on a 35 mm (1 oz) copper thickness PCB,
to 75°C/W and thus dissipate more power. The we obtained a thermal resistance of 75°C/W.

Figure 25. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction-to-Ambient

[Link]
15
 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

Design Procedure
The design of an SMPS around a monolithic device does and a MOSFET. However, one needs to be aware of certain
not differ from that of a standard circuit using a controller characteristics specific of monolithic devices:

350

250

150

50.0

> 0 !!
-50.0

1.004M 1.011M 1.018M 1.025M 1.032M

Figure 26. The Drain-Source Wave Shall Always be Positive . . .

1. In any case, the lateral MOSFET body-diode shall Ctot is the total capacitance at the drain node
never be forward biased, either during startup (which is increased by the capacitor wired between
(because of a large leakage inductance) or in drain and source), N the Np:Ns turn ratio, Vout the
normal operation as shown by Figure 26. output voltage, Vf the secondary diode forward
As a result, the Flyback voltage which is reflected on the drop and finally, Ip the maximum peak current.
drain at the switch opening cannot be larger than the input Worse case occurs when the SMPS is very close to
voltage. When selecting components, you thus must adopt regulation, e.g. the Vout target is almost reached
a turn ratio which adheres to the following equation: and Ip is still pushed to the maximum.
N·(Vout ) Vf) t Vin min (eq. 14) . For instance, if Taking into account all previous remarks, it becomes
operating from a 120 V DC rail, with a delivery of 12 V, we possible to calculate the maximum power that can be
can select a reflected voltage of 100 Vdc maximum: transferred at low line.
120–100 > 0. Therefore, the turn ratio Np:Ns must be When the switch closes, Vin is applied across the primary
smaller than 100/(12 + 1) = 7.7 or Np:Ns < 7.7. We will see inductance Lp until the current reaches the level imposed by
later on how it affects the calculation. the feedback loop. The duration of this event is called the ON
2. A current-mode architecture is, by definition, time and can be defined by:
sensitive to subharmonic oscillations. Lp·Ip
Subharmonic oscillations only occur when the ton + (eq. 16)
Vin
SMPS is operating in Continuous Conduction At the switch opening, the primary energy is transferred
Mode (CCM) together with a duty-cycle greater to the secondary and the flyback voltage appears across
than 50%. As a result, we recommend to operate Lp, resetting the transformer core with a slope of
the device in DCM only, whatever duty-cycle it N·(Vout ) Vf)
implies (max = 65%). However, CCM operation . toff, the OFF time is thus:
Lp
with duty-cycles below 40% is possible.
Lp·Ip
3. Lateral MOSFETs have a poorly dopped toff + (eq. 17)
N·(Vout ) Vf)
body-diode which naturally limits their ability to
sustain the avalanche. A traditional RCD clamping If one wants to keep DCM only, but still need to pass the
network shall thus be installed to protect the maximum power, we will not allow a dead-time after the
MOSFET. In some low power applications, core is reset, but rather immediately restart. The switching
a simple capacitor can also be used since time can be expressed by:

 Vdrain max + Vin ) N·(Vout ) Vf) ) Ip· ǸCtot

Lf Tsw + toff ) ton + Lp·Ip· ǒVin1 ) N·(Vout1 ) Vf)Ǔ
(eq. 15) , where Lf is the leakage inductance, (eq. 18)

[Link]
16
 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

The Flyback transfer formula dictates that: Example 1. A 12 V 7.0 W SMPS operating on a large
Pout + 1 ·Lp·Ip2·Fsw (eq. 19) which, by extracting mains with NCP101X:
h 2 Vin = 100 Vac to 250 Vac or 140 Vdc to 350 Vdc once
Ip and plugging into Equation 19, leads to:
rectified, assuming a low bulk ripple
Tsw + Lp Ǹh·Fsw·Lp
2·Pout  ·ǒ 1 ) 1
Vin N·(Vout ) Vf)
Ǔ Efficiency = 80%
(eq. 20) Vout = 12 V, Iout = 580 mA
Extracting Lp from Equation 20 gives: Fswitching = 65 kHz
(Vin·Vr)2·h Ip max = 350 mA – 10% = 315 mA
Lpcritical +
2·Fsw·[Pout·(Vr2 ) 2·Vr·Vin ) Vin2)] Applying the above equations leads to:
(eq. 21) , with Vr = N . (Vout + Vf) and h the efficiency.
Selected maximum reflected voltage = 120 V
If Lp critical gives the inductance value above which
DCM operation is lost, there is another expression we can with Vout = 12 V, secondary drop = 0.5 V → Np:Ns = 1:0.1
write to connect Lp, the primary peak current bounded by Lp critical = 3.2 mH
the NCP101X and the maximum duty-cycle that needs to Ip = 292 mA
stay below 50%:
Duty-cycle worse case = 50%
Lpmax + DCmax·Vinmin·Tsw (eq. 22) where Vinmin Idrain RMS = 119 mA
Ipmax
corresponds to the lowest rectified bulk voltage, hence the PMOSFET = 354 mW at RDSon = 24 W (TJ > 100°C)
longest ton duration or largest duty-cycle. Ip max is the PDSS = 1.1 mA x 350 V = 385 mW, if DSS is used
available peak current from the considered part, e.g. 350 mA
typical for the NCP1013 (however, the minimum value of Secondary diode voltage stress = (350 x 0.1) + 12 = 47 V
this parameter shall be considered for reliable evaluation). (e.g. a MBRS360T3, 3.0 A/60 V would fit)
Combining Equations 21 and 22 gives the maximum Example 2. A 12 V 16 W SMPS operating on narrow
theoretical power you can pass respecting the peak current European mains with NCP101X:
capability of the NCP101X, the maximum duty-cycle and
Vin = 230 Vac " 15%, 276 Vdc for Vin min to 370 Vdc
the discontinuous mode operation:
once rectified
Pmax :+ Tsw2·Vinmin2·Vr2·h·
Efficiency = 80%
Fsw
(2·Lpmax·Vr2 ) 4·Lpmax·Vr·Vinmin Vout = 12 V, Iout = 1.25 A
) 2·Lpmax·Vinmin2) (eq. 23) Fswitching = 65 kHz
From Equation 22 we obtain the operating duty-cycle Ip max = 350 mA – 10% = 315 mA
Ip·Lp Applying the equations leads to:
d+ (eq. 24) which lets us calculate the RMS
Vin·Tsw
current circulating in the MOSFET: Selected maximum reflected voltage = 250 V
IdRMS + Ip· Ǹd3 (eq. 25) . From this equation, we with Vout = 12 V, secondary drop = 0.5 V → Np:Ns = 1:0.05
Lp = 6.6 mH
obtain the average dissipation in the MOSFET:
Ip = 0.305 mA
Pavg + 1 ·Ip2·d·RDSon (eq. 26) to which switching
3 Duty-cycle worse case = 0.47
losses shall be added.
Idrain RMS = 121 mA
If we stick to Equation 23, compute Lp and follow the
above calculations, we will discover that a power supply PMOSFET = 368 mW at RDSon = 24 W (TJ > 100°C)
built with the NCP101X and operating from a 100 Vac line PDSS = 1.1 mA x 370 V = 407 mW, if DSS is used below an
minimum will not be able to deliver more than 7.0 W ambient of 50°C.
continuous, regardless of the selected switching frequency Secondary diode voltage stress = (370 x 0.05) + 12 = 30.5 V
(however the transformer core size will go down as (e.g. a MBRS340T3, 3.0 A/40 V)
Fswitching is increased). This number increases Please note that these calculations assume a flat DC rail
significantly when operated from a single European mains whereas a 10 ms ripple naturally affects the final voltage
(18 W). Application note AND8125/D, “Evaluating the available on the transformer end. Once the Bulk capacitor has
Power Capability of the NCP101X Members” details how been selected, one should check that the resulting ripple (min
to assess the available power budget from all the NCP101X Vbulk?) is still compatible with the above calculations. As an
series. example, to benefit from the largest operating range, a 7.0 W
board was built with a 47 mF bulk capacitor which ensured
discontinuous operation even in the ripple minimum waves.

[Link]
17
 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

MOSFET Protection
As in any Flyback design, it is important to limit the BVDSS which is 700 V. Figure 27 presents possible
drain excursion to a safe value, e.g. below the MOSFET implementations:

HV HV HV

Rclamp Cclamp Dz

D D

1 8 1 8 1 8

2 7 2 7 2 7

3 3 3

4 5 4 5 4 5
+ + +
CVcc CVcc CVcc
NCP101X NCP101X NCP101X
C

A B C

Figure 27. Different Options to Clamp the Leakage Spike

Figure 27A: The simple capacitor limits the voltage Figure 27C: This option is probably the most expensive of
according to Equation 15. This option is only valid for low all three but it offers the best protection degree. If you need
power applications, e.g. below 5.0 W, otherwise chances a very precise clamping level, you must implement a Zener
exist to destroy the MOSFET. After evaluating the leakage diode or a TVS. There are little technology differences
inductance, you can compute C with Equation 15. Typical behind a standard Zener diode and a TVS. However, the die
values are between 100 pF and up to 470 pF. Large area is far bigger for a transient suppressor than that of Zener.
capacitors increase capacitive losses. A 5.0 W Zener diode like the 1N5388B will accept 180 W
Figure 27B: This diagram illustrates the most standard peak power if it lasts less than 8.3 ms. If the peak current in
circuitry called the RCD network. Rclamp and Cclamp are the worse case (e.g. when the PWM circuit maximum
calculated using the following formulas: current limit works) multiplied by the nominal Zener
voltage exceeds these 180 W, then the diode will be
2·Vclamp·(Vclamp * (Vout ) Vfsec)·N)
Rclamp + destroyed when the supply experiences overloads. A
Lleak·Ip2·Fsw transient suppressor like the P6KE200 still dissipates 5.0 W
(eq. 27)
of continuous power but is able to accept surges up to 600 W
Vclamp @ 1.0 ms. Select the Zener or TVS clamping level between
Cclamp + (eq. 28)
Vripple·Fsw·Rclamp 40 to 80 V above the reflected output voltage when the
Vclamp is usually selected 50-80 V above the reflected supply is heavily loaded.
value N x (Vout + Vf). The diode needs to be a fast one and
a MUR160 represents a good choice. One major drawback
of the RCD network lies in its dependency upon the peak
current. Worse case occurs when Ip and Vin are maximum
and Vout is close to reach the steady-state value.

[Link]
18
 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

Typical Application Examples

A 6.5 W NCP1012-Based Flyback Converter

Figure 28 shows a converter built with a NCP1012 feedback. This configuration was selected for cost reasons
delivering 6.5 W from a universal input. The board uses the and a more precise circuitry can be used, e.g. based on a
Dynamic Self-Supply and a simplified Zener-type TL431:

D6
B150
1 TR1 8
7
D1 D2 E3
R2 C1
1N4007 1N4007 D5 470 m/25 V
150 k 2.2 nF
U160 6 2
4 5 1
E1
R1 10 m/400 V IC1 ZD1
47 R NCP1012 J2
11 V
1 5 CZM5/2
1 VCC HV IC2
2 PC817 R3
2 4
GND FB 100 R
J1 E2 3
D3 D4 GND 8 R4
CEE7.5/2 10 m/16 V 7
1N4007 1N4007 GND GND 180 R

C2
2n2/Y

Figure 28. An NCP1012-Based Flyback Converter Delivering 6.5 W

The converter built according to Figure 29 layouts, gave

the following results:
•Efficiency at Vin = 100 Vac and Pout = 6.5 W = 75.7%
•Efficiency at Vin = 230 Vac and Pout = 6.5 W = 76.5%

Figure 29. The NCP1012-Based PCB Layout . . . and its Associated Component Placement

[Link]
19
 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

A 7.0 W NCP1013-based Flyback Converter power since an auxiliary winding is used, the DSS is
Featuring Low Standby Power disabled, and thus offering more room for the MOSFET. In
Figure 30 depicts another typical application showing a this application, the feedback is made via a TLV431 whose
NCP1013-65 kHz operating in a 7.0 W converter up to low bias current (100 mA min) helps to lower the no-load
70°C of ambient temperature. We can increase the output standby power.

Vbulk

1N4148
D4 R4 22
C8 R7 D2 L2
10 nF 100 k/ MBRS360T3 22 mH
12 V @
400 V 1W 0.6 A
T1 + +
+ C10 + 100 mF/16 V
Aux
33 mF/25 V C7
GND
T1 C6 C8
470 mF/16 V

R2 D3
3.3 k MUR160

R3
NCP1013P06
C2 1k
+ R5
47 mF/ 1 VCC GND 8
450 V 39 k
2 NC GND 7

3 GND

4 FB D 5

+ 100 mF/10 V
C4
C3
C9
1 nF IC1 100 nF
SFH6156-2

IC2
TLV431 R6
4.3 k
C5

2.2 nF
Y1 Type
Figure 30. A Typical Converter Delivering 7.0 W from a Universal Mains

Measurements have been taken from a demonstration For a quick evaluation of Figure 30 application example,
board implementing the diagram in Figure 30 and the the following transformers are available from Coilcraft:
following results were achieved, with either the auxiliary A9619-C, Lp = 3.0 mH, Np:Ns = 1:0.1, 7.0 W
winding in place or through the Dynamic Self-Supply: application on universal mains, including auxiliary winding,
Vin = 230 Vac, auxiliary winding, Pout = 0, Pin = 60 mW NCP1013-65kHz.
Vin = 100 Vac, auxiliary winding, Pout = 0, Pin = 42 mW A0032-A, Lp = 6.0 mH, Np:Ns = 1:0.055, 10 W
Vin = 230 Vac, Dynamic Self-Supply, Pout = 0, application on European mains, DSS operation only,
Pin = 300 mW NCP1013-65 kHz.
Vin = 100 Vac, Dynamic Self-Supply, Pout = 0, Coilcraft
Pin = 130 mW 1102 Silver Lake Road
CARY IL 60013
Pout = 7.0 W, h = 81% @ 230 Vac, with auxiliary winding
Email: info@[Link]
Pout = 7.0 W, h = 81.3 @ 100 Vac, with auxiliary winding Tel.: 847-639-6400
Fax.: 847-639-1469

[Link]
20
 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

ORDERING INFORMATION
Frequency RDSon
Device Order Number (kHz) Package Type Shipping† (W) Ipk (mA)
NCP1010AP065 65 PDIP-7 23 100
NCP1010AP065G 65 PDIP-7 23 100
(Pb-Free)
NCP1010AP100 100 PDIP-7 23 100
NCP1010AP100G 100 PDIP-7 50 Units / Rail 23 100
(Pb-Free)
NCP1010AP130 130 PDIP-7 23 100
NCP1010AP130G 130 PDIP-7 23 100
(Pb-Free)
NCP1011APL065R2G 65 PDIP-7 (Gull Wing) 23 250
1000 / Tape & Reel
(Pb-Free)
NCP1010ST65T3 65 SOT-223 23 100
NCP1010ST65T3G 65 SOT-223 23 100
(Pb-Free)
NCP1010ST100T3 100 SOT-223 23 100
NCP1010ST100T3G 100 SOT-223 4000 / Tape & Reel 23 100
(Pb-Free)
NCP1010ST130T3 130 SOT-223 23 100
NCP1010ST130T3G 130 SOT-223 23 100
(Pb-Free)
NCP1011AP065 65 PDIP-7 23 250
NCP1011AP065G 65 PDIP-7 50 Units / Rail 23 250
(Pb-Free)
NCP1011APL065R2G 65 PDIP-7 (Gull Wing) 1000 / Tape & Reel 23 250
(Pb-Free)
NCP1011AP100 100 PDIP-7 23 250
NCP1011AP100G 100 PDIP-7 23 250
(Pb-Free)
50 Units / Rail
NCP1011AP130 130 PDIP-7 23 250
NCP1011AP130G 130 PDIP-7 23 250
(Pb-Free)
NCP1011APL130R2G 130 PDIP-7 (Gull Wing) 23 250
1000 / Tape & Reel
(Pb-Free)
NCP1011ST65T3 65 SOT-223 23 250
NCP1011ST65T3G 65 SOT-223 23 250
(Pb-Free)
NCP1011ST100T3 100 SOT-223 23 250
NCP1011ST100T3G 100 SOT-223 4000 / Tape & Reel 23 250
(Pb-Free)
NCP1011ST130T3 130 SOT-223 23 250
NCP1011ST130T3G 130 SOT-223 23 250
(Pb-Free)
NCP1012AP065 65 PDIP-7 11 250
NCP1012AP065G 65 PDIP-7 50 Units / Rail 11 250
(Pb-Free)
NCP1012APL065R2G 65 PDIP-7 (Gull Wing) 11 250
1000 / Tape & Reel
(Pb-Free)
NCP1012AP100 100 PDIP-7 11 250
NCP1012AP100G 100 PDIP-7 50 Units / Rail 11 250
(Pb-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Additional Gull Wing option may be available upon request. Please contact your ON Semiconductor representative.

[Link]
21
 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

ORDERING INFORMATION
Frequency RDSon
Device Order Number (kHz) Package Type Shipping† (W) Ipk (mA)
NCP1012APL100R2G 100 PDIP-7 (Gull Wing) 1000 / Tape & Reel 11 250
(Pb-Free)
NCP1012AP133 130 PDIP-7 11 250
NCP1012AP133G 130 PDIP-7 50 Units / Rail 11 250
(Pb-Free)
NCP1012APL130R2G 130 PDIP-7 (Gull Wing) 11 250
1000 / Tape & Reel
(Pb-Free)
NCP1012ST65T3 65 SOT-223 11 250
NCP1012ST65T3G 65 SOT-223 11 250
(Pb-Free)
4000 / Tape & Reel
NCP1012ST100T3 100 SOT-223 11 250
NCP1012ST100T3G 100 SOT-223 11 250
(Pb-Free)
NCP1012ST130T3 130 SOT-223 11 250
NCP1012ST130T3G 130 SOT-223 4000 / Tape & Reel 11 250
(Pb-Free)
NCP1013AP065 65 PDIP-7 11 350
NCP1013AP065G 65 PDIP-7 11 350
(Pb-Free)
NCP1013AP100 100 PDIP-7 11 350
NCP1013AP100G 100 PDIP-7 50 Units / Rail 11 350
(Pb-Free)
NCP1013AP133 130 PDIP-7 11 350
NCP1013AP133G 130 PDIP-7 11 350
(Pb-Free)
NCP1013ST65T3 65 SOT-223 11 350
NCP1013ST65T3G 65 SOT-223 11 350
(Pb-Free)
NCP1013ST100T3 100 SOT-223 11 350
NCP1013ST100T3G 100 SOT-223 4000 / Tape & Reel 11 350
(Pb-Free)
NCP1013ST130T3 130 SOT-223 11 350
NCP1013ST130T3G 130 SOT-223 11 350
(Pb-Free)
NCP1014AP065 65 PDIP-7 11 450
NCP1014AP065G 65 PDIP-7 50 Units / Rail 11 450
(Pb-Free)
NCP1014APL065R2G 65 PDIP-7 (Gull Wing) 11 450
1000 / Tape & Reel
(Pb-Free)
NCP1014AP100 100 PDIP-7 11 450
NCP1014AP100G 100 PDIP-7 50 Units / Rail 11 450
(Pb-Free)
NCP1014APL100R2G 100 PDIP-7 (Gull Wing) 11 450
1000 / Tape & Reel
(Pb-Free)
NCP1014ST65T3 65 SOT-223 11 450
NCP1014ST65T3G 65 SOT-223 11 450
(Pb-Free)
4000 / Tape & Reel
NCP1014ST100T3 100 SOT-223 11 450
NCP1014ST100T3G 100 SOT-223 11 450
(Pb-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Additional Gull Wing option may be available upon request. Please contact your ON Semiconductor representative.

[Link]
22
 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

PACKAGE DIMENSIONS

PDIP-7
AP SUFFIX
CASE 626A-01
ISSUE O

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
8 5 3. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
4. DIMENSION L TO CENTER OF LEAD WHEN
B L FORMED PARALLEL.
5. DIMENSIONS A AND B ARE DATUMS.
1 4 M
MILLIMETERS INCHES
J DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
F B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
NOTE 3 A D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
C K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M --- 10_ --- 10_
-T- N 0.76 1.01 0.030 0.040
SEATING N
PLANE
D K
H G
0.13 (0.005) M T A M B M

PDIP-7, GULL WING

APL SUFFIX
CASE 626AA-01
ISSUE O
A
NOTES:
H R 0.030 0.015 DP MAX 1. DIMENSIONS AND TOLERANCING PER
Bottom Ejector Pin ASME Y14.5M, 1994.
2. DIMENSIONS IN INCHES.
4 1
INCHES
B S
DIM MIN MAX
5 8 A 0.365 0.385
B 0.240 0.260
C 0.120 0.150
F C1 0.124 0.162
E BOTTOM VIEW D 0.018 TYP
E 0.039 TYP
D F 0.045 0.065
TOP VIEW G 0.100 BSC
H 0.023 0.033
J 0.010 TYP
P K 0.004 0.012
GAUGE
T PLANE 0.015 L 0.036 0.044
M 0_ 8_
N
N 12 _ TYP
C C1 -H- P 0.300 BSC
S 0.372 0.388

R 0.016 TYP 0.004

G K J M
L
SIDE VIEW FRONT VIEW

[Link]
23
 NCP1010, NCP1011, NCP1012, NCP1013, NCP1014

PACKAGE DIMENSIONS

SOT-223
ST SUFFIX
CASE 318E-04
ISSUE L
NOTES:
D 1. DIMENSIONING AND TOLERANCING PER ANSI
b1 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.

MILLIMETERS INCHES
4
DIM MIN NOM MAX MIN NOM MAX
HE E A 1.50 1.63 1.75 0.060 0.064 0.068
1 2 3 A1 0.02 0.06 0.10 0.001 0.002 0.004
b 0.60 0.75 0.89 0.024 0.030 0.035
b1 2.90 3.06 3.20 0.115 0.121 0.126
c 0.24 0.29 0.35 0.009 0.012 0.014
D 6.30 6.50 6.70 0.249 0.256 0.263
b E 3.30 3.50 3.70 0.130 0.138 0.145
e1 e 2.20 2.30 2.40 0.087 0.091 0.094
e e1 0.85 0.94 1.05 0.033 0.037 0.041
L1 1.50 1.75 2.00 0.060 0.069 0.078
C HE 6.70 7.00 7.30 0.264 0.276 0.287
q q 0° - 10° 0° - 10°
A
0.08 (0003)
A1
L1

SOLDERING FOOTPRINT*
3.8
0.15

2.0
0.079

6.3
2.3 2.3
0.248
0.091 0.091

2.0
0.079

1.5 SCALE 6:1 ǒinches

mm Ǔ

0.059
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

The products described herein (NCP1010, 1011, 1012, 1013, 1014), may be covered by one or more of the following U.S. patents: 6,271,735, 6,362,067,
6,385,060, 6,429,709, 6,587,357, 6,633,193. There may be other patents pending.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free ON Semiconductor Website: [Link]
 Literature Distribution Center for ON Semiconductor  USA/Canada
 P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: [Link]
 Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada  Phone: 421 33 790 2910
 Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local
 Email: orderlit@[Link]  Phone: 81-3-5773-3850 Sales Representative

[Link] NCP1010/D
24
 ®
OPA344
OPA
434
4
OPA2344
OPA
344 OPA4344
OPA345
OPA
345

OPA ®
342

OPA2345
For most current data sheet and other product
information, visit [Link] OPA4345

LOW POWER, SINGLE-SUPPLY, RAIL-TO-RAIL

OPERATIONAL AMPLIFIERS
MicroAmplifier ™ Series

FEATURES DESCRIPTION
● RAIL-TO-RAIL INPUT The OPA344 and OPA345 series rail-to-rail CMOS
● RAIL-TO-RAIL OUTPUT (within 1mV) operational amplifiers are designed for precision, low-
● LOW QUIESCENT CURRENT: 150µA typ power, miniature applications. The OPA344 is unity
gain stable, while the OPA345 is optimized for gains
● MicroSIZE PACKAGES greater than or equal to five, and has a gain-bandwidth
SOT23-5 product of 3MHz.
MSOP-8 The OPA344 and OPA345 are optimized to operate on
TSSOP-14 a single supply from 2.5V and up to 5.5V with an input
● GAIN-BANDWIDTH common-mode voltage range that extends 300mV
OPA344: 1MHz, G ≥ 1 beyond the supplies. Quiescent current is only
250µA (max).
OPA345: 3MHz, G ≥ 5
Rail-to-rail input and output make them ideal for driving
● SLEW RATE sampling analog-to-digital converters. They are also well
OPA344: 0.8V/µs suited for general purpose and audio applicaitons and
OPA345: 2V/µs providing I/V conversion at the output of D/A converters.
● THD + NOISE: 0.006% Single, dual and quad versions have identical specs for
design flexibility.
A variety of packages are available. All are specified for
APPLICATIONS operation from –40ºC to 85ºC. A SPICE macromodel is
● PCMCIA CARDS available for design analysis.
● DATA ACQUISITION
OPA344, OPA345
● PROCESS CONTROL
● AUDIO PROCESSING Out 1 5 V+
● COMMUNICATIONS V– 2
● ACTIVE FILTERS OPA4344, OPA4345
+In 3 4 –In
● TEST EQUIPMENT
Out A 1 14 Out D
SOT23-5
–In A 2 13 –In D
OPA2344, OPA2345 A D
OPA344, OPA345
+In A 3 12 +In D

Out A 1 8 V+ NC 1 8 NC +V 4 11 –V

–In A 2 A 7 Out B –In 2 7 V+ +In B 5 10 +In C

B C
+In A 3 B 6 –In B Out
+In 3 6 –In B 6 9 –In C

V– 4 5 +In B V– 4 5 NC Out B 7 8 Out C

SO-8, MSOP-8, 8-Pin DIP (OPA2344 Only) SO-8, 8-Pin DIP (OPA344 Only) TSSOP-14, SO-14, 14-PIn DIP (OPA4344 Only)

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: [Link] • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

© 2000 Burr-Brown Corporation PDS-1486A Printed in U.S.A. April, 2000

SBOS107
SPECIFICATIONS: VS = 2.7V to 5.5V
At TA = +25°C, RL = 10kΩ connected to VS /2 and VOUT = VS /2, unless otherwise noted.
Boldface limits apply over the temperature range, TA = –40°C to +85°C.

OPA344NA, UA, PA
OPA2344EA, UA, PA
OPA4344EA, UA, PA
PARAMETER CONDITION MIN TYP MAX UNITS
OFFSET VOLTAGE
Input Offset Voltage VOS VS = +5.5V, VCM = VS/2 ±0.2 ±1 mV
Over Temperature ±0.8 ±1.2 mV
vs Temperature dVOS/dT ±3 µV/°C
vs Power Supply PSRR VS = 2.7V to 5.5V, VCM < (V+) -1.8V 30 200 µV/V
Over Temperature VS = 2.7V to 5.5V, VCM < (V+) -1.8V 250 µV/V
Channel Separation, dc 0.2 µV/V
f = 1kHz 130 dB
INPUT BIAS CURRENT
Input Bias Current IB ±0.2 ±10 pA
Over Temperature See Typical Curve pA
Input Offset Current IOS ±0.2 ±10 pA
NOISE
Input Voltage Noise f = 0.1 to 50kHz 8 µVrms
Input Voltage Noise Density en f = 10kHz 30 nV/√Hz
Current Noise Density in f = 10kHz 0.5 fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM –0.3 (V+) + 0.3 V
Common-Mode Rejection Ratio CMRR VS = +5.5V, –0.3V < VCM < (V+)-1.8 76 92 dB
Over Temperature VS = +5.5V, –0.3V < VCM < (V+)-1.8 74 dB
Common-Mode Rejection CMRR VS = +5.5V, –0.3V < VCM < 5.8V 70 84 dB
Over Temperature VS = +5.5V, –0.3V < VCM < 5.8V 68 dB
Common-Mode Rejection CMRR VS = +2.7V, –0.3V < VCM < 3V 66 80 dB
Over Temperature VS = +2.7V, –0.3V < VCM < 3V 64 dB
INPUT IMPEDANCE
Differential 1013 || 3 Ω || pF
Common-Mode 1013 || 6 Ω || pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL RL = 100kΩ, 10mV < VO < (V+) –10mV 104 122 dB
Over Temperature RL = 100kΩ, 10mV < VO < (V+) –10mV 100 dB
R L = 5kΩ, 400mV < VO < (V+) –400mV 96 120 dB
Over Temperature RL = 5kΩ, 400mV < VO < (V+) –400mV 90 dB
FREQUENCY RESPONSE CL = 100pF
Gain-Bandwidth Product GBW 1 MHz
Slew Rate SR 0.8 V/µs
Settling Time, 0.1% VS = 5.5V, 2V Step 5 µs
0.01% VS = 5.5V, 2V Step 8 µs
Overload Recovery Time VIN • G = VS 2.5 µs
Total Harmonic Distortion + Noise THD+N VS = 5.5V, VO = 3Vp-p, G = 1, f = 1kHz 0.006 %
OUTPUT
Voltage Output Swing from Rail(1) RL = 100kΩ, AOL ≥ 96dB 1 mV
RL = 100kΩ, AOL ≥ 104dB 3 10 mV
Over Temperature RL = 100kΩ, AOL ≥ 100dB 10 mV
RL = 5kΩ, AOL ≥ 96dB 40 400 mV
Over Temperature RL = 5kΩ, AOL ≥ 90dB 400 mV
Short-Circuit Current I SC ±15 mA
Capacitive Load Drive CLOAD See Typical Curve
POWER SUPPLY
Specified Voltage Range VS 2.7 5.5 V
Operating Voltage Range 2.5 to 5.5 V
Quiescent Current (per amplifier) IQ VS = 5.5V, IO = 0 150 250 µA
Over Temperature 300 µA
TEMPERATURE RANGE
Specified Range –40 85 °C
Operating Range –55 125 °C
Storage Range –65 150 °C
Thermal Resistance θJA
SOT23-5 Surface Mount 200 °C/W
MSOP-8 Surface Mount 150 °C/W
8-Pin DIP 100 °C/W
SO-8 Surface Mount 150 °C/W
TSSOP-14 Surface Mount 100 °C/W
14-Pin DIP 80 °C/W
SO-14 Surface Mount 100 °C/W

NOTE: (1) Output voltage swings are measured between the output and power-supply rails.

®
OPA344, 2344, 4344
OPA345, 2345, 4345 2
SPECIFICATIONS: VS = 2.7V to 5.5V
At TA = +25°C, RL = 10kΩ connected to VS /2 and VOUT = VS /2, unless otherwise noted.
Boldface limits apply over the temperature range, TA = –40°C to +85°C.

OPA345NA, UA
OPA2345EA, UA
OPA4345EA, UA
PARAMETER CONDITION MIN TYP MAX UNITS
OFFSET VOLTAGE
Input Offset Voltage VOS VS = +5.5V, VCM = VS/2 ±0.2 ±1 mV
Over Temperature ±0.8 ±1.2 mV
vs Temperature dVOS/dT ±3 µV/°C
vs Power Supply PSRR VS = 2.7V to 5.5V, VCM < (V+) -1.8V 30 200 µV/V
Over Temperature VS = 2.7V to 5.5V, VCM < (V+) -1.8V 250 µV/V
Channel Separation, dc 0.2 µV/V
f = 1kHz 130 dB
INPUT BIAS CURRENT
Input Bias Current IB ±0.2 ±10 pA
Over Temperature See Typical Curve pA
Input Offset Current IOS ±0.2 ±10 pA
NOISE
Input Voltage Noise f = 0.1 to 50kHz 8 µVrms
Input Voltage Noise Density en f = 10kHz 30 nV/√Hz
Current Noise Density in f = 10kHz 0.5 fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM –0.3 (V+) + 0.3 V
Common-Mode Rejection Ratio CMRR VS = +5.5V, –0.3V < VCM < (V+)-1.8 76 92 dB
Over Temperature VS = +5.5V, –0.3V < VCM < (V+)-1.8 74 dB
Common-Mode Rejection Ratio CMRR VS = +5.5V, –0.3V < VCM < 5.8V 70 84 dB
Over Temperature VS = +5.5V, –0.3V < VCM < 5.8V 68 dB
Common-Mode Rejection Ratio CMRR VS = +2.7V, –0.3V < VCM < 3V 66 80 dB
Over Temperature VS = +2.7V, –0.3V < VCM < 3V 64 dB
INPUT IMPEDANCE
Differential 1013 || 3 Ω || pF
Common-Mode 1013 || 6 Ω || pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL RL = 100kΩ, 10mV < VO < (V+) –10mV 104 122 dB
Over Temperature RL = 100kΩ, 10mV < VO < (V+) –10mV 100 dB
RL = 5kΩ, 400mV < VO < (V+) –400mV 96 120 dB
Over Temperature RL = 5kΩ, 400mV < VO < (V+) –400mV 90 dB
FREQUENCY RESPONSE CL = 100pF
Gain-Bandwidth Product GBW 3 MHz
Slew Rate SR 2 V/µs
Settling Time, 0.1% G = 5, 2V Output Step 1.5 µs
0.01% G = 5, 2V Output Step 1.6 µs
Overload Recovery Time VIN • G = VS 2.5 µs
Total Harmonic Distortion + Noise THD+N VS = 5.5V, VO = 2.5Vp-p, G = 5, f = 1kHz 0.006 %
OUTPUT
Voltage Output Swing from Rail(1) RL = 100kΩ, AOL ≥ 96dB 1 mV
RL = 100kΩ, AOL ≥ 104dB 3 10 mV
Over Temperature RL = 100kΩ, AOL ≥ 100dB 10 mV
RL = 5kΩ, AOL ≥ 96dB 40 400 mV
Over Temperature RL = 5kΩ, AOL ≥ 90dB 400 mV
Short-Circuit Current I SC ±15 mA
Capacitive Load Drive CLOAD See Typical Curve
POWER SUPPLY
Specified Voltage Range VS 2.7 5.5 V
Operating Voltage Range 2.5 to 5.5 V
Quiescent Current (per amplifier) IQ VS = 5.5V, IO = 0 150 250 µA
Over Temperature 300 µA
TEMPERATURE RANGE
Specified Range –40 85 °C
Operating Range –55 125 °C
Storage Range –65 150 °C
Thermal Resistance θJA
SOT23-5 Surface Mount 200 °C/W
MSOP-8 Surface Mount 150 °C/W
SO-8 Surface Mount 150 °C/W
TSSOP-14 Surface Mount 100 °C/W
SO-14 Surface Mount 100 °C/W

NOTE: (1) Output voltage swings are measured between the output and power-supply rails.

OPA344, 2344, 4344 ®

3 OPA345, 2345, 4345

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
Supply Voltage, V+ to V- ................................................................... 7.5V
Signal Input Terminals, Voltage(2) ..................... (V–) –0.5V to (V+) +0.5V DISCHARGE SENSITIVITY
Current(2) .................................................... 10mA
Output Short-Circuit(3) .............................................................. Continuous This integrated circuit can be damaged by ESD. Burr-Brown
Operating Temperature .................................................. –55°C to +125°C recommends that all integrated circuits be handled with
Storage Temperature ..................................................... –65°C to +150°C appropriate precautions. Failure to observe proper handling
Junction Temperature ...................................................................... 150°C
Lead Temperature (soldering, 10s) ................................................. 300°C and installation procedures can cause damage. ESD damage
ESD Tolerance (Human Body Model) ............................................ 4000V can range from subtle performance degradation to complete
NOTES: (1) Stresses above these ratings may cause permanent damage. device failure. Precision integrated circuits may be more
Exposure to absolute maximum conditions for extended periods may susceptible to damage because very small parametric
degrade device reliability. These are stress ratings only. Functional opera-
changes could cause the device not to meet its published
tion of the device at these conditions, or beyond the specified operating
conditions, is not implied. (2) Input terminals are diode-clamped to the power specifications.
supply rails. Input signals that can swing more than 0.5V beyond the supply
rails should be current-limited to 10mA or less. (3) Short-circuit to ground,
one amplifier per package.

PACKAGE/ORDERING INFORMATION
PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER(1) MEDIA

OPA344NA SOT23-5 331 –40°C to +85°C B44 OPA344NA/250 Tape and Reel
" " " " " OPA344NA/3K Tape and Reel
OPA344UA SO-8 182 –40°C to +85°C OPA344UA OPA344UA Rails
" " " " " OPA344UA /2K5 Tape and Reel
OPA344PA 8-Pin Dip 006 –40° C to +85°C OPA344PA OPA344PA Rails

OPA2344EA MSOP-8 337 –40°C to +85°C C44 OPA2344EA /250 Tape and Reel
" " " " " OPA2344EA /2K5 Tape and Reel
OPA2344UA SO-8 182 –40°C to +85°C OPA2344UA OPA2344UA Rails
" " " " " OPA2344UA/2K5 Tape and Reel
OPA2344PA 8-Pin DIP 006 –40°C to +85°C OPA2344PA OPA2344PA Rails

OPA4344EA TSSOP-14 357 –40°C to +85°C OPA4344EA OPA4344EA /250 Rails

" " " " " OPA4344EA /2K5 Tape and Reel
OPA4344UA SO-14 235 –40°C to +85°C OPA4344UA OPA4344UA Rails
" " " " " OPA4344UA/2K5 Tape and Reel
OPA4344PA 14-Pin DIP 010 –40°C to +85°C OPA4344PA OPA4344PA Rails

OPA345NA SOT23-5 331 –40°C to +85°C A45 OPA345NA/250 Tape and Reel
" " " " " OPA345NA/3K Tape and Reel
OPA345UA SO-8 182 –40°C to +85°C OPA345UA OPA345UA Rails
" " " " " OPA345UA/2K5 Tape and Reel

OPA2345EA MSOP-8 337 –40°C to +85°C B45 OPA2345EA/250 Tape and Reel
" " " " " OPA2345EA /2K5 Tape and Reel
OPA2345UA SO-8 182 –40°C to +85°C OPA2345UA OPA2345UA Rails
" " " " " OPA2345UA/2K5 Tape and Reel

OPA4345EA TSSOP-14 357 –40°C to +85°C OPA4345EA OPA4345EA/250 Tape and Reel
" " " " " OPA4345EA /2K5 Tape and Reel
OPA4345UA SO-14 235 –40°C to +85°C OPA4345UA OPA4345UA Rails
" " " " " OPA4345UA/2K5 Tape and Reel

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “OPA344UA/2K5” will get a single 2500-piece Tape and Reel.

®
OPA344, 2344, 4344
OPA345, 2345, 4345 4
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = +5V, and RL = 10kΩ connected to VS/2, unless otherwise noted.

OPEN-LOOP GAIN/PHASE vs FREQUENCY OPEN-LOOP GAIN/PHASE vs FREQUENCY

120 0 120 0

100 30 100 30
OPA344 OPA345
Phase Phase
80 60 80 60
Gain (dB)

Gain (dB)
Phase (°)

Phase (°)
60 90 60 90

40 120 40 120
Gain Gain
20 150 20 150

0 180 0 180
0.1 1 10 100 1k 10k 100k 1M 10M 0.1 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

POWER SUPPLY AND COMMON-MODE

REJECTION RATIO vs FREQUENCY MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
100 6
+PSRR VS = +5.5V
Maximum Output Voltage (Vp-p) 5
80 VS =
CMRR
+5V
Rejection Ratio (dB)

–PSRR 4
60 OPA344 OPA345
3
40 VS = +2.7V
2

20
1

10 0
10 100 1k 10k 100k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

VOLTAGE AND CURRENT NOISE

CHANNEL SEPARATION vs FREQUENCY SPECTRAL DENSITY vs FREQUENCY
140 10000 100
Channel Separation (dB)

Voltage Noise (nV/√Hz)

120
IN Current Noise (fA/√Hz)
1000 10

100 VN
Dual and quad devices.
G = 1, all channels.
Quad measured channel 100 1
80 A to D or B to C—other
combinations yield improved
rejection.
60 10 0.1
100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

OPA344, 2344, 4344 ®

5 OPA345, 2345, 4345

TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VS = +5V, and RL = 10kΩ connected to VS/2, unless otherwise noted.

TOTAL HARMONIC DISTORTION + NOISE OPEN-LOOP GAIN, COMMON-MODE REJECTION RATIO,

vs FREQUENCY AND POWER-SUPPLY REJECTION vs TEMPERATURE
1 140
AOL
OPA344: G = 1 120
OPA345: G = 5

AOL, CMRR, PSRR (dB)

100
0.1 CMRR
THD+N (%)

80
PSRR
60
0.010
40

20

0.001 0
20 100 1k 10k 20k –75 –50 –25 0 25 50 75 100 125
Frequency (Hz) Temperature (°C)

QUIESCENT CURRENT AND

INPUT BIAS CURRENT vs TEMPERATURE SHORT-CIRCUIT CURRENT vs TEMPERATURE
10000 200 40

175 35
IQ
1000

Short-Circuit Current (mA)

Quiescent Current (µA)

150 30
Input Bias Current (pA)

100 135 25
+ISC
100 20
–ISC
10 75 15

50 10
1
25 5

0.1 0 0
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

INPUT BIAS CURRENT

SLEW RATE vs TEMPERATURE vs COMMON-MODE VOLTAGE
3.0 6

SR–
2.5 4
V– V+
Input Bias Current (pA)

OPA345 SR+ Supply Supply

Slew Rate (V/µs)

2.0 2

1.5 0

OPA344 SR–
1.0 –2
Input voltage ≤ –0.3V
SR+
can cause op amp output
0.5 –4
to lock up. See text.

0 –6
–75 –50 –25 0 25 50 75 100 125 –1 0 1 2 3 4 5 6
Temperature (°C) Common-Mode Voltage (V)

®
OPA344, 2344, 4344
OPA345, 2345, 4345 6
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VS = +5V, and RL = 10kΩ connected to VS/2, unless otherwise noted.

QUIESCENT CURRENT AND

SHORT-CIRCUIT CURRENT vs SUPPLY VOLTAGE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
160 20 V+
+ISC
(V+) – 1

Short-Circuit Current (mA)

Quiescent Current (µA)

155 15 –40°C 25°C 85°C

Output Voltage (V)

≈ ≈
(V+) – 2
–ISC
150 10
2
IQ
25°C 85°C
145 5 –40°C
1

140 0 0
2 3 4 5 6 0 5 10 15 20
Supply Voltage (V) Output Current (mA)

OFFSET VOLTAGE
OPEN-LOOP GAIN vs OUTPUT VOLTAGE SWING PRODUCTION DISTRIBUTION
140

RL = 100kΩ
130
Open-Loop Gain (dB)

Population
RL = 5kΩ
120

110

100
120 100 80 60 40 20 0
–1000

–800

–600

–400

–200

200

400

600

800

1000
Output Voltage Swing from Rail (mV)
Offset Voltage (µV)

OFFSET VOLTAGE DRIFT QUIESCENT CURRENT

PRODUCTION DISTRIBUTION PRODUCTION DISTRIBUTION
Population

Population
–10

–8

–6

–4

–2

10

100

115

130

145

160

175

190

205

220

235

250

Offset Voltage Drift (µV/°C) Quiescent Current (µA)

OPA344, 2344, 4344 ®

7 OPA345, 2345, 4345

TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VS = +5V, and RL = 10kΩ connected to VS/2, unless otherwise noted.

SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE

50 70
45 OPA344 OPA345
60

Small-Signal Overshoot (%)

Small-Signal Overshoot (%)

40 G = +5
35 50
G = +1 G = –5
30
G = +5 40
25
G = –1 30
20
G = –10, +10
15 20
10
G = –5 10
5
0 0
1 10 100 1k 10k 10 100 1k 10k
Load Capacitance (pF) Load Capacitance (pF)

LARGE-SIGNAL STEP RESPONSE: OPA344 LARGE-SIGNAL STEP RESPONSE: OPA345

G = +1, RL = 10kΩ, CL = 100pF G = +5, RL = 10kΩ, CL = 100pF

OPA344 OPA345
1V/div
1V/div

5µs/div 5µs/div

SMALL-SIGNAL STEP RESPONSE: OPA344 SMALL-SIGNAL STEP RESPONSE: OPA345

G = +1, RL = 10kΩ, CL = 100pF G = +5, RL = 10kΩ, CL = 100pF

OPA344 OPA345
20mV/div

20mV/div

5µs/div 5µs/div

®
OPA344, 2344, 4344
OPA345, 2345, 4345 8
APPLICATIONS INFORMATION OPERATING VOLTAGE
OPA344 and OPA345 series op amps are fully specified and
OPA344 series op amps are unity gain stable and can operate guaranteed from +2.7V to +5.5V. In addition, many specifi-
on a single supply, making them highly versatile and easy to cations apply from –40ºC to +85ºC. Parameters that vary
use. OPA345 series op amps are optimized for applications significantly with operating voltages or temperature are
requiring higher speeds with gains of 5 or greater. shown in the Typical Performance Curves.
Rail-to-rail input and output swing significantly increases
dynamic range, especially in low supply applications. Figure RAIL-TO-RAIL INPUT
1 shows the input and output waveforms for the OPA344 in The input common-mode voltage range of the OPA344 and
unity-gain configuration. Operation is from VS = +5V with OPA345 series extends 300mV beyond the supply rails.
a 10kΩ load connected to VS/2. The input is a 5Vp-p This is achieved with a complementary input stage—an N-
sinusoid. Output voltage is approximately 4.997Vp-p. channel input differential pair in parallel with a P-channel
Power supply pins should be by passed with 0.01pF ceramic differential pair (see Figure 2). The N-channel pair is active
capacitors. for input voltages close to the positive rail, typically (V+) –
1.3V to 300mV above the positive supply, while the P-
channel pair is on for inputs from 300mV below the negative
G = +1, VS = +5V
supply to approximately (V+) –1.3V. There is a small
Input
transition region, typically (V+) – 1.5V to (V+) – 1.1V, in
5V
which both pairs are on. This 400mV transition region can
vary 300mV with process variation. Thus, the transition
region (both stages on) can range from (V+) – 1.8V to (V+)
1V/div

– 1.4V on the low end, up to (V+) – 1.2V to (V+) – 0.8V on

the high end. Within the 400mV transition region PSRR,
CMRR, offset voltage, offset drift, and THD may be de-
graded compared to operation outside this region. For more
0V
information on designing with rail-to-rail input op amps, see
Output (inverted on scope)
Figure 3 “Design Optimization with Rail-to-Rail Input Op
5µs/div Amps.”

FIGURE 1. Rail-to-Rail Input and Output.

V+

Reference
Current

VIN+ VIN–

VBIAS1 Class AB
Control VO
Circuitry
VBIAS2

V–
(Ground)

FIGURE 2. Simplified Schematic.

OPA344, 2344, 4344 ®

9 OPA345, 2345, 4345

 DESIGN OPTIMIZATION WITH RAIL-TO-RAIL INPUT OP AMPS
Rail-to-rail op amps can be used in virtually any op amp With a unity-gain buffer, for example, signals will traverse
configuration. To achieve optimum performance, how- this transition at approximately 1.3V below V+ supply
ever, applications using these special double-input-stage and may exhibit a small discontinuity at this point.
op amps may benefit from consideration of their special The common-mode voltage of the non-inverting ampli-
behavior. fier is equal to the input voltage. If the input signal always
In many applications, operation remains within the com- remains less than the transition voltage, no discontinuity
mon-mode range of only one differential input pair. will be created. The closed-loop gain of this configura-
However some applications exercise the amplifier through tion can still produce a rail-to-rail output.
the transition region of both differential input stages. Inverting amplifiers have a constant common-mode volt-
Although the two input stages are laser trimmed for age equal to VB. If this bias voltage is constant, no
excellent matching, a small discontinuity may occur in discontinuity will be created. The bias voltage can gener-
this transition. Careful selection of the circuit configura- ally be chosen to avoid the transition region.
tion, signal levels and biasing can often avoid this transi-
tion region.
G = 1 Buffer Non-Inverting Gain Inverting Amplifier

V+ V+ V+
VB VIN

VO VO VO
VIN VIN

VB

VCM = VIN = VO VCM = VIN VCM = VB

FIGURE 3. Design Optimization with Rail-to-Rail Input Op Amps.

COMMON-MODE REJECTION between V+ and ground. For light resistive loads (> 50kΩ),
The CMRR for the OPA344 and OPA345 is specified in the output voltage can typically swing to within 1mV from
several ways so the best match for a given application may supply rail. With moderate resistive loads (2kΩ to 50kΩ),
be used. First, the CMRR of the device in the common-mode the output can swing to within a few tens of milli-volts from
range below the transition region (VCM < (V+) – 1.8V) is the supply rails while maintaining high open-loop gain. See
given. This specification is the best indicator of the capabil- the typical performance curve “Output Voltage Swing vs
ity of the device when the application requires use of one of Output Current.”
the differential input pairs. Second, the CMRR at VS = 5.5V
over the entire common-mode range is specified. Third, the
CMRR at VS = 2.7V over the entire common-mode range is
provided. These last two values include the variations seen V+
through the transition region.
IOVERLOAD
10mA max
OPA344 VOUT
INPUT VOLTAGE BEYOND THE RAILS VIN
If the input voltage can go more than 0.3V below the 1kΩ
negative power supply rail (single-supply ground), special
precautions are required. If the input voltage goes suffi- IN5818
ciently negative, the op amp output may lock up in an
Schottky diode is required only
inoperative state. A Schottky diode clamp circuit will pre- if input voltage can go more
vent this—see Figure 4. The series resistor prevents exces- than 0.3V below ground.
sive current (greater than 10mA) in the Schottky diode and
in the internal ESD protection diode, if the input voltage can FIGURE 4. Input Current Protection for Voltages Exceed-
exceed the positive supply voltage. If the signal source is ing the Supply Voltage.
limited to less than 10mA, the input resistor is not required.

CAPACITIVE LOAD AND STABILITY

RAIL-TO-RAIL OUTPUT
The OPA344 in a unity-gain configuration and the OPA345
A class AB output stage with common-source transistors is
in gains greater than 5 can directly drive up to 250pF pure
used to achieve rail-to-rail output. This output stage is
capacitive load. Increasing the gain enhances the amplifier’s
capable of driving 600Ω loads connected to any potential
ability to drive greater capacitive loads. See the typical
®
OPA344, 2344, 4344
OPA345, 2345, 4345 10
performance curve “Small-Signal Overshoot vs Capacitive DRIVING A/D CONVERTERS
Load.” In unity-gain configurations, capacitive load drive The OPA344 and OPA345 series op amps are optimized for
can be improved by inserting a small (10Ω to 20Ω) resistor, driving medium-speed sampling A/D converters. The
RS, in series with the output, as shown in Figure 5. This OPA344 and OPA345 op amps buffer the A/D’s input
significantly reduces ringing while maintaining dc perfor- capacitance and resulting charge injection while providing
mance for purely capacitive loads. However, if there is a signal gain.
resistive load in parallel with the capacitive load, a voltage
Figures 6 shows the OPA344 in a basic noninverting con-
divider is created, introducing a dc error at the output and
figuration driving the ADS7822. The ADS7822 is a 12-bit,
slightly reducing the output swing. The error introduced is
micro-power sampling converter in the MSOP-8 package.
proportional to the ratio RS/RL, and is generally negligible. When used with the low-power, miniature packages of the
OPA344, the combination is ideal for space-limited, low-
power applications. In this configuration, an RC network at
the A/D’s input can be used to filter charge injection.
V+
Figure 7 shows the OPA2344 driving an ADS7822 in a
RS speech bandpass filtered data acquisition system. This small,
OPA344 VOUT low-cost solution provides the necessary amplification and
VIN 10Ω to signal conditioning to interface directly with an electret
RL CL
20Ω
microphone. This circuit will operate with VS = +2.7V to
+5V with less than 500µA quiescent current.

FIGURE 5. Series Resistor in Unity-Gain Configuration

Improves Capacitive Load Drive.

+5V

0.1µF 0.1µF

8 V+ 1 VREF
7
DCLOCK
500Ω +In ADS7822 6 Serial
OPA344 DOUT
2 12-Bit A/D Interface
VIN 5
–In CS/SHDN
3300pF 3
GND 4
VIN = 0V to 5V for
0V to 5V output.
NOTE: A/D Input = 0 to VREF
RC network filters high frequency noise.

FIGURE 6. OPA344 in Noninverting Configuration Driving ADS7822.

V+ = +2.7V to 5V
Passband 300Hz to 3kHz

R9
510kΩ
R1 R2 R4
1.5kΩ 1MΩ 20kΩ
C3
C1 33pF
1000pF R7 R8
51kΩ 150kΩ VREF 1 8 V+
1/2
OPA2344 7 DCLOCK
Electret R3 1/2 +IN ADS7822 6 DOUT Serial
Microphone(1) 1MΩ R6 OPA2344 2 12-Bit A/D Interface
C2 1000pF –IN 5 CS/SHDN
100kΩ
3
4
NOTE: (1) Electret microphone R5 G = 100
powered by R1. GND
20kΩ

FIGURE 7. Speech Bandpass Filtered Data Acquisition System.

OPA344, 2344, 4344 ®

11 OPA345, 2345, 4345

 PACKAGE OPTION ADDENDUM
[Link] 24-Dec-2007

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
OPA2344EA/250 ACTIVE MSOP DGK 8 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2344EA/250G4 ACTIVE MSOP DGK 8 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2344EA/2K5 ACTIVE MSOP DGK 8 2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2344EA/2K5G4 ACTIVE MSOP DGK 8 2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2344PA ACTIVE PDIP P 8 50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA2344PAG4 ACTIVE PDIP P 8 50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA2344UA ACTIVE SOIC D 8 100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2344UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2344UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2344UAG4 ACTIVE SOIC D 8 100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2345EA/250 ACTIVE MSOP DGK 8 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2345EA/250G4 ACTIVE MSOP DGK 8 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2345EA/2K5G4 ACTIVE MSOP DGK 8 TBD Call TI Call TI
OPA2345UA ACTIVE SOIC D 8 100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2345UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2345UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2345UAG4 ACTIVE SOIC D 8 100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA344NA/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA344NA/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA344NA/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA344NA/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA344PA ACTIVE PDIP P 8 50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA344PAG4 ACTIVE PDIP P 8 50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA344UA ACTIVE SOIC D 8 100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA344UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
[Link] 24-Dec-2007

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
OPA344UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA344UAG4 ACTIVE SOIC D 8 100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA345NA/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA345NA/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA345NA/3KG4 ACTIVE SOT-23 DBV 5 TBD Call TI Call TI
OPA345UA ACTIVE SOIC D 8 100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA345UAG4 ACTIVE SOIC D 8 100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA4344EA/250 ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OPA4344EA/250G4 ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OPA4344EA/2K5 ACTIVE TSSOP PW 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OPA4344EA/2K5G4 ACTIVE TSSOP PW 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OPA4344PA ACTIVE PDIP N 14 25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA4344PAG4 ACTIVE PDIP N 14 25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA4344UA ACTIVE SOIC D 14 58 Green (RoHS & Call TI Level-2-260C-1 YEAR
no Sb/Br)
OPA4344UA/2K5 ACTIVE SOIC D 14 2500 Green (RoHS & Call TI Level-2-260C-1 YEAR
no Sb/Br)
OPA4344UA/2K5G4 ACTIVE SOIC D 14 2500 Green (RoHS & Call TI Level-2-260C-1 YEAR
no Sb/Br)
OPA4344UAG4 ACTIVE SOIC D 14 58 Green (RoHS & Call TI Level-2-260C-1 YEAR
no Sb/Br)
OPA4345EA/250 ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA4345EA/250G4 ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA4345UA ACTIVE SOIC D 14 58 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA4345UA/2K5G4 ACTIVE SOIC D 14 TBD Call TI Call TI
OPA4345UAG4 ACTIVE SOIC D 14 58 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
[Link] for the latest availability information and additional product content details.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM
[Link] 24-Dec-2007

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION
[Link] 21-Dec-2007

TAPE AND REEL BOX INFORMATION

Device Package Pins Site Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Diameter Width (mm) (mm) Quadrant
(mm) (mm)
OPA2344EA/250 DGK 8 SITE 41 180 12 5.3 3.4 1.4 8 12 Q1
OPA2344EA/2K5 DGK 8 SITE 41 330 12 5.3 3.4 1.4 8 12 Q1
OPA2344UA/2K5 D 8 SITE 41 330 12 6.4 5.2 2.1 8 12 Q1
OPA2345EA/250 DGK 8 SITE 41 180 12 5.3 3.4 1.4 8 12 Q1
OPA2345UA/2K5 D 8 SITE 41 330 12 6.4 5.2 2.1 8 12 Q1
OPA344NA/250 DBV 5 SITE 41 180 8 3.2 3.1 1.39 4 8 Q3
OPA344NA/3K DBV 5 SITE 41 180 8 3.2 3.1 1.39 4 8 Q3
OPA344UA/2K5 D 8 SITE 41 330 12 6.4 5.2 2.1 8 12 Q1
OPA345NA/250 DBV 5 SITE 41 180 8 3.2 3.1 1.39 4 8 Q3
OPA4344EA/250 PW 14 SITE 41 180 12 7.0 5.6 1.6 8 12 Q1
OPA4344EA/2K5 PW 14 SITE 41 330 12 7.0 5.6 1.6 8 12 Q1
OPA4344UA/2K5 D 14 SITE 41 330 16 6.5 9.0 2.1 8 16 Q1
OPA4345EA/250 PW 14 SITE 67 177 12 6.95 5.6 1.6 8 12 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION
[Link] 21-Dec-2007

Device Package Pins Site Length (mm) Width (mm) Height (mm)
OPA2344EA/250 DGK 8 SITE 41 184.0 184.0 50.0
OPA2344EA/2K5 DGK 8 SITE 41 346.0 346.0 29.0
OPA2344UA/2K5 D 8 SITE 41 346.0 346.0 29.0
OPA2345EA/250 DGK 8 SITE 41 184.0 184.0 50.0
OPA2345UA/2K5 D 8 SITE 41 346.0 346.0 29.0
OPA344NA/250 DBV 5 SITE 41 190.0 212.7 31.75
OPA344NA/3K DBV 5 SITE 41 190.0 212.7 31.75
OPA344UA/2K5 D 8 SITE 41 346.0 346.0 29.0
OPA345NA/250 DBV 5 SITE 41 190.0 212.7 31.75
OPA4344EA/250 PW 14 SITE 41 184.0 184.0 50.0
OPA4344EA/2K5 PW 14 SITE 41 346.0 346.0 29.0
OPA4344UA/2K5 D 14 SITE 41 346.0 346.0 33.0
OPA4345EA/250 PW 14 SITE 67 187.0 187.0 25.6

Pack Materials-Page 2
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Copyright © 2007, Texas Instruments Incorporated
 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

D Trimmed Offset Voltage: D, JG, OR P PACKAGE

TLC27L7 . . . 500 µV Max at 25°C, (TOP VIEW)
VDD = 5 V
1OUT VDD
D Input Offset Voltage Drift . . . Typically 1IN –
1
2
8
7 2OUT
0.1 µV/Month, Including the First 30 Days
1IN + 3 6 2IN –
D Wide Range of Supply Voltages Over GND 4 5 2IN +
Specified Temperature Range:
0°C to 70°C . . . 3 V to 16 V
– 40°C to 85°C . . . 4 V to 16 V FK PACKAGE
(TOP VIEW)
– 55°C to 125°C . . . 4 V to 16 V

1OUT
D

VDD
Single-Supply Operation

NC

NC

NC
D Common-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix, 3 2 1 20 19
NC 4 18 NC
I-Suffix Types)
1IN – 2OUT
D 5 17
Ultra-Low Power . . . Typically 95 µW NC 16 NC
6
at 25°C, VDD = 5 V 1IN + 15 2IN –
7
D Output Voltage Range Includes Negative NC 8 14 NC
Rail 9 10 11 12 13

D High Input Impedance . . . 1012 Ω Typ

2IN +
NC

NC

NC
GND
D ESD-Protection Circuitry
D Small-Outline Package Option Also
NC – No internal connection
Available in Tape and Reel
D Designed-In Latch-Up immunity
DISTRIBUTION OF TLC27L7

ÎÎÎÎÎÎÎÎÎÎÎ
INPUT OFFSET VOLTAGE
description 30

The TLC27L2 and TLC27L7 dual operational

amplifiers combine a wide range of input offset ÎÎÎÎÎÎÎÎÎÎÎ
25
335 Units Tested From 2 Wafer Lots
VDD = 5 V
TA = 25°C
Percentage of Units – %

voltage grades with low offset voltage drift, high P Package

input impedance, extremely low power, and high 20
gain.
15
AVAILABLE OPTIONS
PACKAGE
VIOmax 10
TA SMALL CHIP CERAMIC PLASTIC
AT 25°C OUTLINE CARRIER DIP DIP
(D) (FK) (JG) (P)
5
500 µV TLC27L7CD TLC27L7CP
0°C
2 mV TLC27L2BCD TLC27L2BCP
to — — 0
5 mV TLC27L2ACD TLC27L2ACP
70°C
70 C – 800 – 400 0 400 800
10 mV TLC27L2CD TLC27L2CP
VIO – Input Offset Voltage – µV
500 µV TLC27L7ID TLC27L7IP
– 40°C
2 mV TLC27L2BID TLC27L2BIP
to — —
5 mV TLC27L2AID TLC27L2AIP
85°C
85 C
10 mV TLC27L2ID TLC27L2IP

– 55°C
500 µ
µV TLC27L7MD TLC27L7MFK TLC27L7MJG TLC27L7MP
to
10 mV TLC27L2MD TLC27L2MFK TLC27L2MJG TLC27L2MP
125°C

The D package is available taped and reeled. Add R suffix to the device type
(e.g., TLC27L7CDR).

LinCMOS is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Copyright  2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

description (continued)
These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset voltage
stability far exceeding the stability available with conventional metal-gate processes.
The extremely high input impedance, low bias currents, and low power consumption make these cost-effective
devices ideal for high gain, low frequency, low power applications. Four offset voltage grades are available
(C-suffix and I-suffix types), ranging from the low-cost TLC27L2 (10 mV) to the high-precision TLC27L7
(500 µV). These advantages, in combination with good common-mode rejection and supply voltage rejection,
make these devices a good choice for new state-of-the-art designs as well as for upgrading existing designs.
In general, many features associated with bipolar technology are available in LinCMOS operational amplifiers,
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27L2 and
TLC27L7. The devices also exhibit low voltage single-supply operation and ultra-low power consumption,
making them ideally suited for remote and inaccessible battery-powered applications. The common-mode input
voltage range includes the negative rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand – 100-mA surge currents without sustaining latch-up.
The TLC27L2 and TLC27L7 incorporate internal ESD-protection circuits that prevent functional failures at
voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in
handling these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-Suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from – 40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of – 55°C to 125°C.

equivalent schematic (each amplifier)

VDD

P3 P4
R6

R1 R2 N5
IN –
P5 P6
P1 P2
IN + C1
R5

OUT

N3

N1 N2 N6 N7
N4
R3 D1 R4 D2 R7

GND

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Total current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN –.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).

DISSIPATION RATING TABLE

TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C TA = 125°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING
D 725 mW 5.8 mW/°C 464 mW 377 mW —
FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW
P 1000 mW 8.0 mW/°C 640 mW 520 mW —

recommended operating conditions

C SUFFIX I SUFFIX M SUFFIX
UNIT
MIN MAX MIN MAX MIN MAX
Supply voltage, VDD 3 16 4 16 4 16 V
VDD = 5 V – 0.2 3.5 – 0.2 3.5 0 3.5
Common mode input voltage,
Common-mode voltage VIC V
VDD = 10 V – 0.2 8.5 – 0.2 8.5 0 8.5
Operating free-air temperature, TA 0 70 – 40 85 – 55 125 °C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)

TLC27L2C
TLC27L2AC
PARAMETER TEST CONDITIONS TA† TLC27L2BC UNIT
TLC27L7C
MIN TYP MAX
VO = 1.4 V,, VIC = 0,, 25°C 1.1 10
TLC27L2C
RS = 50 Ω, RL = 1 MΩ Full range 12
mV
VO = 1.4 V,, VIC = 0,, 25°C 0.9 5
TLC27L2AC
RS = 50 Ω, RL = 1 MΩ Full range 6.5
VIO Input offset voltage
VO = 1.4 V,, VIC = 0,, 25°C 204 2000
TLC27L2BC
RS = 50 Ω, RL = 1 MΩ Full range 3000
µV
VO = 1.4 V,, VIC = 0,, 25°C 170 500
TLC27L7C
RS = 50 Ω, RL = 1 MΩ Full range 1500
Averageg temperature coefficient of input 25°C to
αVIO 11
1.1 µV/°C
offset voltage 70°C
25°C 0.1 60
IIO Input offset current (see Note 4) VO = 2
2.5
5VV, VIC = 2
2.5
5V pA
70°C 7 300
25°C 0.6 60
IIB Input bias current (see Note 4) VO = 2 5V
2.5 V, VIC = 2 5V
2.5 pA
70°C 50 600
– 0.2 – 0.3
25°C to to V
Common-mode input voltage
g range
g 4 4.2
VICR
(see Note 5) – 0.2
Full range
g to V
3.5
25°C 3.2 4.1
VOH High-level output voltage VID = 100 mV, RL = 1 MΩ 0°C 3 4.1 V
70°C 3 4.2
25°C 0 50
VOL Low-level output voltage VID = – 100 mV, IOL = 0 0°C 0 50 mV
70°C 0 50
25°C 50 700
Large-signal
L i l differential
diff ti l voltage
lt
AVD VO = 0.25 V to 2 V, RL = 1 MΩ 0°C 50 700 V/mV
am lification
amplification
70°C 50 380
25°C 65 94
CMRR Common-mode rejection ratio VIC = VICRmin 0°C 60 95 dB
70°C 60 95
25°C 70 97
Supply-voltage
S l lt rejection
j ti ratio
ti
kSVR VDD = 5 V to 10 V, VO = 1.4 V 0°C 60 97 dB
(∆VDD /∆VIO)
70°C 60 98
25°C 20 34
VO = 2
2.5
5VV, VIC = 2
2.5
5VV,
IDD Supply current (two amplifiers) 0°C 24 42 µA
No load
70°C 16 28
† Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)

TLC27L2C
TLC27L2AC
PARAMETER TEST CONDITIONS TA† TLC27L2BC UNIT
TLC27L7C
MIN TYP MAX
VO = 1.4 V,, VIC = 0,, 25°C 1.1 10
TLC27L2C
RS = 50 Ω, RL = 1 MΩ Full range 12
mV
VO = 1.4 V,, VIC = 0,, 25°C 0.9 5
TLC27L2AC
RS = 50 Ω, RL = 1 MΩ Full range 6.5
VIO Input offset voltage
VO = 1.4 V,, VIC = 0,, 25°C 235 2000
TLC27L2BC
RS = 50 Ω, RL = 1 MΩ Full range 3000 µV
VO = 1.4 V,, VIC = 0,, 25°C 190 800
TLC27L7C
RS = 50 Ω, RL = 1 MΩ Full range 1900
Average temperature coefficient of input 25°C to
αVIO 1 µV/°C
offset voltage 70°C
25°C 0.1 60
IIO Input offset current (see Note 4) VO = 5 V
V, VIC = 5 V pA
70°C 8 300
25°C 0.7 60
IIB Input bias current (see Note 4) VO = 5 V
V, VIC = 5 V pA
70°C 50 600
– 0.2 – 0.3
25°C to to V
Common-mode input voltage
g range
g 9 9.2
VICR
(see Note 5) – 0.2
Full range
g to V
8.5
25°C 8 8.9
VOH High-level output voltage VID = 100 mV, RL = 1 MΩ 0°C 7.8 8.9 V
70°C 7.8 8.9
25°C 0 50
VOL Low-level output voltage VID = – 100 mV, IOL = 0 0°C 0 50 mV
70°C 0 50
25°C 50 860
Large-signal
L i l differential
diff ti l voltage
lt
AVD VO = 1 V to 6 V, RL = 1 MΩ 0°C 50 1025 V/mV
am lification
amplification
70°C 50 660
25°C 65 97
CMRR Common-mode rejection ratio VIC = VICRmin 0°C 60 97 dB
70°C 60 97
25°C 70 97
Supply-voltage
S l lt rejection
j ti ratio
ti
kSVR VDD = 5 V to 10 V, VO = 1.4 V 0°C 60 97 dB
(∆VDD /∆VIO)
70°C 60 98
25°C 29 46
VO = 5 V,
V VIC = 5 V,
V
IDD Supply current (two amplifiers) 0°C 36 66 µA
No load
70°C 22 40
† Full range is 0°C to 70°C.
NOTES: 4 The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5 This range also applies to each input individually.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)

TLC27L2I
TLC27L2AI
PARAMETER TEST CONDITIONS TA† TLC27L2BI UNIT
TLC27L7I
MIN TYP MAX
VO = 1.4 V,, VIC = 0,, 25°C 1.1 10
TLC27L2I
RS = 50 Ω, RL = 1 MΩ Full range 13
mV
VO = 1.4 V,, VIC = 0,, 25°C 0.9 5
TLC27L2AI
RS = 50 Ω, RL = 1 MΩ Full range 7
VIO Input offset voltage
VO = 1.4 V,, VIC = 0,, 25°C 240 2000
TLC27L2BI
RS = 50 Ω, RL = 1 MΩ Full range 3500
µV
VO = 1.4 V,, VIC = 0,, 25°C 170 500
TLC27L7I
RS = 50 Ω, RL = 1 MΩ Full range 2000
Average
g temperature coefficient of 25°C to
αVIO 11
1.1 µV/°C
input offset voltage 85°C
25°C 0.1 60
IIO Input offset current (see Note 4) VO = 2
2.5
5VV, VIC = 2
2.5
5V pA
85°C 24 1000
25°C 0.6 60
IIB Input bias current (see Note 4) VO = 2 5V
2.5 V, VIC = 2 5V
2.5 pA
85°C 200 2000
– 0.2 – 0.3
25°C to to V
Common-mode input voltage
g range
g 4 4.2
VICR
(see Note 5) – 0.2
Full range
g to V
3.5
25°C 3.2 4.1
VOH High-level output voltage VID = 100 mV, RL = 1 MΩ – 40°C 3 4.1 V
85°C 3 4.2
25°C 0 50
VOL Low-level output voltage VID = – 100 mV, IOL = 0 – 40°C 0 50 mV
85°C 0 50
25°C 50 480
Large-signal
L i l diff
differential
ti l
AVD VO = 0.25 V to 2 V, RL = 1 MΩ – 40°C 50 900 V/mV
voltage am lification
amplification
85°C 50 330
25°C 65 94
CMRR Common-mode rejection ratio VIC = VICRmin – 40°C 60 95 dB
85°C 60 95
25°C 70 97
Supply-voltage
S l lt rejection
j ti ratio
ti
kSVR VDD = 5 V to 10 V, VO = 1.4 V – 40°C 60 97 dB
(∆VDD /∆VIO)
85°C 60 98
25°C 20 34
VO = 2
2.5
5VV, VIC = 2
2.5
5VV,
IDD Supply current (two amplifiers) – 40°C 31 54 µA
No load
85°C 15 26
† Full range is – 40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)

TLC27L2I
TLC27L2AI
PARAMETER TEST CONDITIONS TA† TLC27L2BI UNIT
TLC27L7I
MIN TYP MAX
VO = 1.4 V,, VIC = 0,, 25°C 1.1 10
TLC27L2I
RS = 50 Ω, RL = 1 MΩ Full range 13
mV
VO = 1.4 V,, VIC = 0,, 25°C 0.9 5
TLC27L2AI
RS = 50 Ω, RL = 1 MΩ Full range 7
VIO Input offset voltage
VO = 1.4 V,, VIC = 0,, 25°C 235 2000
TLC27L2BI
RS = 50 Ω, RL = 1 MΩ Full range 3500
µV
VO = 1.4 V,, VIC = 0,, 25°C 190 800
TLC27L7I
RS = 50 Ω, RL = 1 MΩ Full range 2900
Averageg temperature coefficient of input 25°C to
αVIO 1 µV/°C
offset voltage 85°C
25°C 0.1 60
IIO Input offset current (see Note 4) VO = 5 V
V, VIC = 5 V pA
85°C 26 1000
25°C 0.7 60
IIB Input bias current (see Note 4) VO = 5 V
V, VIC = 5 V pA
85°C 220 2000
– 0.2 – 0.3
25°C to to V
Common-mode input voltage
g range
g 9 9.2
VICR
(see Note 5) – 0.2
Full range
g to V
8.5
25°C 8 8.9
VOH High-level output voltage VID = 100 mV, RL = 1 MΩ – 40°C 7.8 8.9 V
85°C 7.8 8.9
25°C 0 50
VOL Low-level output voltage VID = – 100 mV, IOL = 0 – 40°C 0 50 mV
85°C 0 50
25°C 50 860
Large-signal
L i l differential
diff ti l voltage
lt
AVD VO = 1 V to 6 V, RL = 1 MΩ – 40°C 50 1550 V/mV
am lification
amplification
85°C 50 585
25°C 65 97
CMRR Common-mode rejection ratio VIC = VICRmin – 40°C 60 97 dB
85°C 60 98
25°C 70 97
Supply-voltage
S l lt rejection
j ti ratio
ti
kSVR VDD = 5 V to 10 V, VO = 1.4 V – 40°C 60 97 dB
(∆VDD /∆VIO)
85°C 60 98
25°C 29 46
VO = 5 V
V, VIC = 5 V,
V
IDD Supply current (two amplifiers) – 40°C 49 86 µA
No load
85°C 20 36
† Full range is – 40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)

TLC27L2M
PARAMETER TEST CONDITIONS TA† TLC27L7M UNIT
MIN TYP MAX
VO = 1.4 V, VIC = 0, 25°C 1.1 10
TLC27L2M mV
RS = 50 Ω, RL = 1 MΩ Full range 12
VIO Input offset voltage
VO = 1.4 V, VIC = 0, 25°C 170 500
TLC27L7M µV
RS = 50 Ω, RL = 1 MΩ Full range 3750
Average
g temperature coefficient of 25°C to
αVIO 14
1.4 µV/°C
input offset voltage 125°C
25°C 0.1 60 pA
IIO Input offset current (see Note 4) VO = 2
2.5
5VV, VIC = 2
2.5
5V
125°C 1.4 15 nA
25°C 0.6 60 pA
IIB Input bias current (see Note 4) VO = 2
2.5
5VV, VIC = 2
2.5
5V
125°C 9 35 nA
0 – 0.3
25°C to to V
Common-mode input voltage
g range
g 4 4.2
VICR
(see Note 5) 0
Full range
g to V
3.5
25°C 3.2 4.1
VOH High-level output voltage VID = 100 mV, RL = 1 MΩ – 55°C 3 4.1 V
125°C 3 4.2
25°C 0 50
VOL Low-level output voltage VID = – 100 mV, IOL = 0 – 55°C 0 50 mV
125°C 0 50
25°C 50 500
Large-signal
Large signal differential voltage
AVD VO = 0.25 V to 2 V, RL = 1 MΩ – 55°C 25 1000 V/mV
amplification
am lification
125°C 25 200
25°C 65 94
CMRR Common-mode rejection ratio VIC = VICRmin – 55°C 60 95 dB
125°C 60 85
25°C 70 97
Supply-voltage
Supply voltage rejection ratio
kSVR VDD = 5 V to 10 V, VO = 1.4 V – 55°C 60 97 dB
(∆VDD /∆VIO)
125°C 60 98
25°C 20 34
VO = 2 5V
2.5 V, VIC = 2 5V
2.5 V,
IDD Supply current (two amplifiers) – 55°C 35 60 µA
No load
125°C 14 24
† Full range is – 55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)

TLC27L2M
PARAMETER TEST CONDITIONS TA† TLC27L7M UNIT
MIN TYP MAX
VO = 1.4 V, VIC = 0, 25°C 1.1 10
TLC27L2M mV
RS = 50 Ω, RL = 1 MΩ Full range 12
VIO Input offset voltage
VO = 1.4 V, VIC = 0, 25°C 190 800
TLC27L7M µV
RS = 50 Ω, RL = 1 MΩ Full range 4300
Average
g temperature coefficient of 25°C to
αVIO 14
1.4 µV/°C
input offset voltage 125°C
25°C 0.1 60 pA
IIO Input offset current (see Note 4) VO = 5 V
V, VIC = 5 V
125°C 1.8 15 nA
25°C 0.7 60 pA
IIB Input bias current (see Note 4) VO = 5 V
V, VIC = 5 V
125°C 10 35 nA
0 – 0.3
25°C to to V
Common-mode input voltage
g range
g 9 9.2
VICR
(see Note 5) 0
Full range
g to V
8.5
25°C 8 8.9
VOH High-level output voltage VID = 100 mV, RL = 1 MΩ – 55°C 7.8 8.8 V
125°C 7.8 9
25°C 0 50
VOL Low-level output voltage VID = – 100 mV, IOL = 0 – 55°C 0 50 mV
125°C 0 50
25°C 50 860
Large-signal
Large signal differential voltage
AVD VO = 1 V to 6 V, RL = 1 MΩ – 55°C 25 1750 V/mV
amplification
am lification
125°C 25 380
25°C 65 97
CMRR Common-mode rejection ratio VIC = VICRmin – 55°C 60 97 dB
125°C 60 91
25°C 70 97
Supply-voltage
Supply voltage rejection ratio
kSVR VDD = 5 V to 10 V, VO = 1.4 V – 55°C 60 97 dB
(∆VDD /∆VIO)
125°C 60 98
25°C 29 46
VO = 5 V
V, VIC = 5 V
V,
IDD Supply current (two amplifiers) – 55°C 56 96 µA
No load
125°C 18 30
† Full range is – 55 °C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

operating characteristics, VDD = 5 V

TLC27L2C
TLC27L2AC
PARAMETER TEST CONDITIONS TA TLC27L2BC UNIT
TLC27L7C
MIN TYP MAX
25°C 0.03
VI(PP)
( )=1V 0°C 0.04
RL = 1 MΩ, 70°C 0.03
SR Slew rate at unity gain CL = 20 pF
pF, V/µs
See Figure 1 25°C 0.03
VI(PP)
( ) = 2.5 V 0°C 0.03
70°C 0.02
f = 1 kHz,, RS = 20 Ω,,
Vn Equivalent input noise voltage 25°C 68 nV/√H
nV/√Hz
See Figure 2
25°C 5
VO = VOH, CL = 20 pF,
F
BOM Maximum output-swing bandwidth 0°C 6 kHz
RL = 1 MΩ
MΩ, See Figure 1
70°C 4.5
25°C 85
VI = 10 mV,
V CL = 20 pF,
F
B1 Unity-gain bandwidth 0°C 100 kHz
See Figure 3
70°C 65
25°C 34°
VI = 10 mV,
mV f = B1,
φm Phase margin 0°C 36°
CL = 20 pF,
F, See Figure 3
70°C 30°

operating characteristics, VDD = 10 V

TLC27L2C
TLC27L2AC
PARAMETER TEST CONDITIONS TA TLC27L2BC UNIT
TLC27L7C
MIN TYP MAX
25°C 0.05
VI(PP)
( )=1V 0°C 0.05
RL = 1 MΩ, 70°C 0.04
SR Slew rate at unity gain CL = 20 pF
pF, V/µs
See Figure 1 25°C 0.04
VI(PP)
( ) = 5.5 V 0°C 0.05
70°C 0.04
f = 1 kHz,, RS = 20 Ω,,
Vn Equivalent input noise voltage 25°C 68 nV/√H
nV/√Hz
See Figure 2
25°C 1
VO = VOH, CL = 20 pF,
F
BOM Maximum output-swing bandwidth 0°C 1.3 kHz
RL = 1 MΩ
MΩ, See Figure 1
70°C 0.9
25°C 110
VI = 10 mV,
V CL = 20 pF,
F
B1 Unity-gain bandwidth 0°C 125 kHz
See Figure 3
70°C 90
25°C 38°
VI = 10 mV,
mV f = B1,
φm Phase margin 0°C 40°
CL = 20 pF,
F, See Figure 3
70°C 34°

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

operating characteristics, VDD = 5 V

TLC27L2I
TLC27L2AI
PARAMETER TEST CONDITIONS TA TLC27L2BI UNIT
TLC27L7I
MIN TYP MAX
25°C 0.03
VI(PP)
( )=1V – 40°C 0.04
RL = 1 MΩ, 85°C 0.03
SR Slew rate at unity gain CL = 20 pF
pF, V/µs
See Figure 1 25°C 0.03
VI(PP)
( ) = 2.5 V – 40°C 0.04
85°C 0.02
f = 1 kHz,, RS = 20 Ω,,
Vn Equivalent input noise voltage 25°C 68 nV/√H
nV/√Hz
See Figure 2
25°C 5
VO = VOH, CL = 20 pF,
F
BOM Maximum output-swing bandwidth – 40°C 7 kHz
RL = 1 MΩ
MΩ, See Figure 1
85°C 4
25°C 85
VI = 10 mV,
V CL = 20 pF,
F
B1 Unity-gain bandwidth – 40°C 130 kHz
See Figure 3
85°C 55
25°C 34°
VI = 10 mV,
mV f = B1,
φm Phase margin – 40°C 38°
CL = 20 pF,
F, See Figure 3
85°C 29°

operating characteristics, VDD = 10 V

TLC27L2I
TLC27L2AI
PARAMETER TEST CONDITIONS TA TLC27L2BI UNIT
TLC27L7I
MIN TYP MAX
25°C 0.05
VI(PP)
( )=1V – 40°C 0.06
RL = 1 MΩ, 85°C 0.03
SR Slew rate at unity gain CL = 20 pF
pF, V/µs
See Figure 1 25°C 0.04
VI(PP)
( ) = 5.5 V – 40°C 0.05
85°C 0.03
f = 1 kHz,, RS = 20 Ω,,
Vn Equivalent input noise voltage 25°C 68 nV/√H
nV/√Hz
See Figure 2
25°C 1
VO = VOH, CL = 20 pF,
F
BOM Maximum output-swing bandwidth – 40°C 1.4 kHz
RL = 1 MΩ
MΩ, See Figure 1
85°C 0.8
25°C 110
VI = 10 mV,
V CL = 20 pF,
F
B1 Unity-gain bandwidth – 40°C 155 kHz
See Figure 3
85°C 80
25°C 38°
VI = 10 mV,
mV f = B1,
φm Phase margin – 40°C 42°
CL = 20 pF,
F, See Figure 3
85°C 32°

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

operating characteristics, VDD = 5 V

TLC27L2M
PARAMETER TEST CONDITIONS TA TLC27L7M UNIT
MIN TYP MAX
25°C 0.03
VI(PP)
( )=1V – 55°C 0.04
RL = 1 MΩ, 125°C 0.02
SR Slew rate at unity gain CL = 20 pF,
pF V/µs
See Figure 1 25°C 0.03
VI(PP)
( ) = 2.5 V – 55°C 0.04
125°C 0.02
f = 1 kHz,, RS = 20 Ω,,
Vn Equivalent input noise voltage 25°C 68 nV/√H
nV/√Hz
See Figure 2
25°C 5
VO = VOH, CL = 20 pF,
F
BOM Maximum output-swing bandwidth – 55°C 8 kHz
RL = 1 MΩ
MΩ, See Figure 1
125°C 3
25°C 85
VI = 10 mV,
V CL = 20 pF,
F
B1 Unity-gain bandwidth – 55°C 140 kHz
See Figure 3
125°C 45
25°C 34°
VI = 10 mV,
mV f = B1,
φm Phase margin – 55°C 39°
CL = 20 pF
F, See Figure 3
125°C 25°

operating characteristics, VDD = 10 V

TLC27L2M
PARAMETER TEST CONDITIONS TA TLC27L7M UNIT
MIN TYP MAX
25°C 0.05
VI(PP)
( )=1V – 55°C 0.06
RL = 1 MΩ, 125°C 0.03
SR Slew rate at unity gain CL = 20 pF,
pF V/µs
See Figure 1 25°C 0.04
VI(PP)
( ) = 5.5 V – 55°C 0.06
125°C 0.03
f = 1 kHz,, RS = 20 Ω,,
Vn Equivalent input noise voltage 25°C 68 nV/√Hz
See Figure 2
25°C 1
VO = VOH, CL = 20 pF,
F
BOM Maximum output-swing bandwidth – 55°C 1.5 kHz
RL = 1 MΩ
MΩ, See Figure 1
125°C 0.7
25°C 110
VI = 10 mV,
V CL = 20 pF,
F
B1 Unity-gain bandwidth – 55°C 165 kHz
See Figure 3
125°C 70
25°C 38°
VI = 10 mV,
mV f = B1,
φm Phase margin – 55°C 43°
CL = 20 pF
F, See Figure 3
125°C 29°

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

PARAMETER MEASUREMENT INFORMATION

single-supply versus split-supply test circuits

Because the TLC27L2 and TLC27L7 are optimized for single-supply operation, circuit configurations used for
the various tests often present some inconvenience since the input signal, in many cases, must be offset from
ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to
the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either
circuit gives the same result.

VDD VDD +
– –

VO VO
VI + VI +
CL RL CL RL

VDD –

(a) SINGLE SUPPLY (b) SPLIT SUPPLY

Figure 1. Unity-Gain Amplifier

2 kΩ 2 kΩ

VDD VDD +
20 Ω –
–
1/2 VDD VO VO
+ +

20 Ω
20 Ω 20 Ω

VDD –
(a) SINGLE SUPPLY (b) SPLIT SUPPLY

Figure 2. Noise-Test Circuit

10 kΩ 10 kΩ

VDD +
VDD 100 Ω
100 Ω –
VI – VI
VO VO
+
+
1/2 VDD
CL
CL

VDD –

(a) SINGLE SUPPLY (b) SPLIT SUPPLY

Figure 3. Gain-of-100 Inverting Amplifier

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

PARAMETER MEASUREMENT INFORMATION

input bias current

Because of the high input impedance of the TLC27L2 and TLC27L7 operational amplifiers, attempts to measure
the input bias current can result in erroneous readings. The bias current at normal room ambient temperature
is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are
offered to avoid erroneous measurements:
1. Isolate the device from other potential leakage [Link] a grounded shield around and between the
device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using
a picoammeter) with no device in the test socket. The actual input bias current can then be calculated
by subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the
servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires that a
device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not
feasible using this method.

8 5

V = VIC

1 4

Figure 4. Isolation Metal Around Device Inputs

(JG and P packages)

low-level output voltage

To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise
results in the device low-level output being dependent on both the common-mode input voltage level as well
as the differential input voltage level. When attempting to correlate low-level output readings with those quoted
in the electrical specifications, these two conditions should be observed. If conditions other than these are to
be used, please refer to Figures 14 through 19 in the Typical Characteristics of this data sheet.

input offset voltage temperature coefficient

Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

PARAMETER MEASUREMENT INFORMATION

full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.

(a) f = 100 kHz (b) BOM > f > 100 kHz (c) f = BOM (d) f > BOM

Figure 5. Full-Power-Response Output Signal

test time
Inadequate test time is a frequent problem, especially when testing CMOS high-volume, short-test-time
environment. Internal capacitances are inherently higher in CMOS devices and require longer test times than
their bipolar and BiFET counterparts. The problem becomes more pronounced with reduced supply levels and
lower temperatures.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

TYPICAL CHARACTERISTICS

Table of Graphs
FIGURE
VIO Input offset voltage Distribution 6, 7
αVIO Temperature coefficient of input offset voltage Distribution 8, 9
High-level
vs High output
level out ut current 10, 11
VOH High-level
g output voltage
g vs Supplyy voltage
g 12
vs Free-air temperature 13
vs Differential input
in ut voltage 14 16
14,16
VOL Low level output voltage
Low-level vs Free-air
Free air temperature 15,17
15 17
L l
vs Low-level l output
t t currentt 18 19
18,
vs Supply
Su ly voltage 20
AVD Large-signal
g g differential voltage
g amplification vs Free-air temperature 21
vs Frequency 32, 33
IIB Input bias current vs Free-air temperature 22
IIO Input offset current vs Free-air temperature 22
VIC Common-mode input voltage vs Supply voltage 23
vs Supplyy voltage
g 24
IDD Supply current
vs Free-air temperature 25
vs Supplyy voltage
g 26
SR Slew rate
vs Free-air temperature 27
Normalized slew rate vs Free-air temperature 28
VO(PP) Maximum peak-to-peak output voltage vs Frequency 29
vs Free-air temperature 30
B1 Unity gain bandwidth
Unity-gain
vs Supply voltage 31
vs Supply
Su ly voltage 34
φm Phase margin
g vs Free-air temperature 35
vs Capacitive Load 36
Vn Equivalent input noise voltage vs Frequency 37
Phase shift vs Frequency 32, 33

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

TYPICAL CHARACTERISTICS

DISTRIBUTION OF TLC27L2 DISTRIBUTION OF TLC27L2

INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE
70 70
905 Amplifiers Tested From 6 Wafer Lots 905 Amplifiers Tested From 6 Wafer Lots
VDD = 5 V VDD = 10 V
60 60
TA = 25°C TA = 25°C
P Package P Package

Percentage of Units – %
Percentage of Units – %

50 50

40 40

30 30

20 20

10 10

0 0
–5 –4 –3 –2 –1 0 1 2 3 4 5 –5 –4 –3 –2 –1 0 1 2 3 4 5
VIO – Input Offset Voltage – mV VIO – Input Offset Voltage – mV

Figure 6 Figure 7

DISTRIBUTION OF TLC27LC AND TLC27L7 DISTRIBUTION OF TLC27LC AND TLC27L7

INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT TEMPERATURE COEFFICIENT
70 70
356 Amplifiers Tested From 8 Wafer Lots 356 Amplifiers Tested From 8 Wafer Lots
VDD = 5 V VDD = 10 V
60 60
TA = 25°C to 125°C TA = 25°C to 125°C
P Package P Package
Outliers: Outliers:
Percentage of Units – %
Percentage of Units – %

50 50
(1) 19.2 µV/°C (1) 18.7 µV/°C
(1) 12.1 µV/°C (1) 11.6 µV/°C
40 40

30 30

20 20

10 10

0 0
– 10 – 8 – 6 – 4 – 2 0 2 4 6 8 10 – 10 – 8 – 6 – 4 – 2 0 2 4 6 8 10
αVIO – Temperature Coefficient – µV/°C αVIO – Temperature Coefficient – µV/°C

Figure 8 Figure 9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

TYPICAL CHARACTERISTICS†

HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE

vs vs
HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
5 16

ÎÎÎÎÎ
VID = 100 mV VID = 100 mV
TA = 25°C 14 TA = 25°C
VOH – High-Level Output Voltage – V

ÎÎÎÎÎ

VOH – High-Level Output Voltage – V

VDD = 16 V
4
12
VDD = 5 V
3 10
VDD = 4 V
8
VDD = 10 V
2 VDD = 3 V
6

ÁÁ ÁÁ
ÁÁ ÁÁ 4
VOH

ÁÁ ÁÁ VOH
1
2

0 0
0 –2 –4 –6 –8 – 10 0 – 5 – 10 – 15 – 20 – 25 – 30 – 35 – 40
IOH – High-Level Output Current – mA IOH – High-Level Output Current – mA

Figure 10 Figure 11

HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE

vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE

ÎÎÎÎÎ ÁÁÁÁÁ
16 VDD – 1.6

ÎÎÎÎÎ
ÎÎÎÎÎÎ ÁÁÁÁÁ
VID = 100 mV IOH = – 5 mA
– 1.7
VOH – High-Level Output Voltage – V

14

ÎÎÎÎÎ
VOH – High-Level Output Voltage – V

RL = 10 kΩ VID = 100 mA
TA = 25°C VDD = 5 V
12 – 1.8

10 – 1.9

8 –2
VDD = 10 V
– 2.1

ÁÁ ÁÁ
6

ÁÁ ÁÁ
4 – 2.2
VOH
VOH

ÁÁ 2
ÁÁ – 2.3

– 2.4
0
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 20 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C

Figure 12 Figure 13

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

TYPICAL CHARACTERISTICS†

LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE

vs vs
DIFFERENTIAL INPUT VOLTAGE FREE-AIR TEMPERATURE
700 500
VDD = 5 V VDD = 10 V
IOL = 5 mA
VOL – Low-Level Output Voltage – mV

VOL – Low-Level Output Voltage – mV

IOL = 5 mA
TA = 25°C TA = 25°C
450
600

400
VID = – 100 mV
500 VID = – 100 mV
VID = – 1 V
350
VID = – 2.5 V

ÁÁ ÁÁ
400

ÁÁ ÁÁ
VOL

300

VOL
VID = – 1 V

300 250
0 0.5 1 1.5 2 2.5 3 3.3 4 0 1 2 3 4 5 6 7 8 9 10
VIC – Common-Mode Input Voltage – V VIC – Common-Mode Input Voltage – V

Figure 14 Figure 15

LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE

vs vs

ÁÁÁÁ
DIFFERENTIAL INPUT VOLTAGE FREE-AIR TEMPERATURE

ÁÁÁÁ
800 900
IOL = 5 mA

ÁÁÁÁ
IOL = 5 mA
700 800 VID = – 1 V

ÁÁÁÁ
VOL – Low-Level Output Voltage – mV

VOL – Low-Level Output Voltage – mV

VIC = |VID/2|
VIC = 0.5 V
TA = 25°C
700
600

ÎÎÎÎ
600 VDD = 5 V

ÎÎÎÎ
500
VDD = 5 V 500
400
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
400
VDD = 10 V

ÎÎÎÎÎ
300
300
VDD = 10 V

ÁÁ 200
ÁÁÁ 200

ÁÁ ÁÁÁ
VOL

VOL

100 100

0 0
0 –1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 – 9 – 10 – 75 – 50 – 25 0 25 50 75 100 125
VID – Differential Input Voltage – V TA – Free-Air Temperature – °C

Figure 16 Figure 17

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

TYPICAL CHARACTERISTICS†

LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE

vs vs

ÎÎÎÎÎ
LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT

ÎÎÎÎÎ ÎÎÎÎÎÎ
1 3
VID = – 1 V

ÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ
0.9 VID = – 1 V
VIC = 0.5 V
VIC = 0.5 V

ÎÎÎÎÎ ÎÎÎÎÎ
VOL – Low-Level Output Voltage – V

VOL – Low-Level Output Voltage – V

TA = 25°C 2.5
0.8 TA = 25°C
VDD = 5 V VDD = 16 V
0.7
VDD = 4 V 2
0.6 VDD = 10 V
VDD = 3 V
0.5 1.5

0.4

ÁÁ ÁÁ
0.3 1

ÁÁ 0.2
ÁÁ
VOL

VOL
ÁÁ 0.1

0
ÁÁ 0.5

0
0 1 2 3 4 5 6 7 8 0 5 10 15 20 25 30
IOL – Low-Level Output Current – mA IOL – Low-Level Output Current – mA

Figure 18 Figure 19

LARGE-SIGNAL LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION DIFFERENTIAL VOLTAGE AMPLIFICATION
vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
2000 2000
TA = – 55°C
1800 RL = 1 MΩ 1800 RL = 1 MΩ
– 40°C
AVD – Large-Signal Differential

AVD – Large-Signal Differential

1600 1600
Voltage Amplification – V/mV

Voltage Amplification – V/mV

1400 1400
TA = 0°C

ÎÎ
VDD = 10 V
1200 1200

ÎÎ
25°C

ÎÎ
1000 1000
70°C

Á ÎÎÁÁ
800 800

Á ÁÁ
600 85°C 600
AVD

AVD

Á ÁÁ
VDD = 5 V
400 400
125°C
200 200

0 0
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C

Figure 20 Figure 21

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

TYPICAL CHARACTERISTICS†

INPUT BIAS CURRENT AND INPUT OFFSET CURRENT COMMON-MODE

vs INPUT VOLTAGE POSITIVE LIMIT

ÁÁÁÁFREE-AIR TEMPERATURE vs

ÁÁÁÁ
SUPPLY VOLTAGE
10000
16
I IO – Input Bias and Offset Currents – pA

ÁÁÁÁ
VDD = 10 V
VIC = 5 V TA = 25°C

ÁÁÁÁ
See Note A 14

VI – Common-Mode Input Voltage – V

1000

ÎÎ IIB 12

ÎÎ
100 10
IIO
8
10
6

ÁÁ
4
IB and IIO

ÁÁ VIC
2
IIIB

0.1
25 45 65 85 105 125 0
TA – Free-Air Temperature – °C 0 2 4 6 8 10 12 14 16
VDD – Supply Voltage – V
NOTE A: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
Figure 22 Figure 23

SUPPLY CURRENT SUPPLY CURRENT

vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
90 60
TA = – 55°C
VO = VDD/2 VO = VDD/2
80 No Load No Load
50
70
mA

mA
A

A
DD – Supply Current – µ

I DD – Supply Current – µ

– 40°C
60 40
VDD = 10 V
50
0°C 30
40

ÁÁ ÁÁ
25°C
30 20

ÁÁ ÁÁ
IIDD

IDD

70°C
VDD = 5 V
20
125°C
10
10

0 0
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C

Figure 24 Figure 25
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

TYPICAL CHARACTERISTICS†

SLEW RATE SLEW RATE

vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
0.07 0.07
AV = 1 VDD = 10 V RL =1 MΩ
VI(PP) = 1 V CL = 20 pF
0.06 0.06 VI(PP) = 5.5 V
RL =1 MΩ AV = 1
CL = 20 pF See Figure 1

SR – Slew Rate – V/sµ s

SR – Slew Rate – V/sµ s

0.05 TA = 25°C 0.05

See Figure 1 VDD = 10 V
VI(PP) = 1 V
0.04 0.04

0.03 0.03

VDD = 5 V
0.02 0.02 VI(PP) = 1 V

VDD = 5 V
0.01 0.01 VI(PP) = 2.5 V

0.00 0.00
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C

Figure 26 Figure 27

NORMALIZED SLEW RATE MAXIMUM-PEAK-TO-PEAK OUTPUT VOLTAGE

vs vs
FREE-AIR TEMPERATURE FREQUENCY
VO(PP) – Maximum Peak-to-Peak Output Voltage – V

1.4 10

ÎÎÎÎÎ
AV = 1
1.3 VIPP = 1 V 9

ÎÎÎÎÎ ÎÎÎÎ
VDD = 10 V RL =1 MΩ
8

ÎÎÎÎ
1.2 CL = 20 pF TA = 125°C
VDD = 10 V
Normalized Slew Rate

TA = 25°C

ÎÎÎÎ
7
1.1 TA = – 55°C

ÎÎÎÎ
VDD = 5 V 6
1

ÎÎÎÎ
5
VDD = 5 V

ÁÁ
0.9
4

ÁÁ
0.8
3
0.7

0.6
ÁÁ 2

1
RL = 1 MΩ
See Figure 1

0.5 0
– 75 – 50 – 25 0 25 50 75 100 125 0.1 1 10 100
TA – Free-Air Temperature – °C f – Frequency – kHz

Figure 28 Figure 29

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

TYPICAL CHARACTERISTICS†

UNITY-GAIN BANDWIDTH UNITY-GAIN BANDWIDTH

vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE
150 140
VDD = 5 V VI = 10 mV
VI = 10 mV 130
CL = 20 pF
130 CL = 20 pF
B1 – Unity-Gain Bandwidth – kHz

B1 – Unity-Gain Bandwidth – kHz

TA = 25°C
See Figure 3 120
See Figure 3
110 110

100
90
90

70 80

70
B1

B1
50
60

30 50
– 75 – 50 – 25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16
TA – Free-Air Temperature – °C VDD – Supply Voltage – V

Figure 30 Figure 31
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
10 7
VDD = 10 V
10 6 RL = 1 MΩ
TA = 25°C
VD – Large-Signal Differential

10 5 0°
Voltage Amplification

10 4 30°
Phase Shift

AVD
10 3 60°

ÁÁ ÎÎÎÎÎ
10 2 90°

ÁÁ
Phase Shift
AVD

10 1 120°

ÁÁ
A

1 150°

0.1 180°
1 10 100 1k 10 k 100 k 1M
f – Frequency – Hz

Figure 32

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

TYPICAL CHARACTERISTICS†
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
10 7
VDD = 10 V
10 6 RL = 1 MΩ
TA = 25°C
AVD – Large-Signal Differential

10 5 0°
Voltage Amplification

10 4 30°
AVD

Phase Shift
10 3 60°

ÎÎÎÎÎ
ÁÁ ÎÎÎÎÎ
10 2 90°

ÁÁ
Phase Shift
AVD

10 1

ÁÁ
120°

1 150°

0.1 180°
1 10 100 1k 10 k 100 k 1M
f – Frequency – Hz

Figure 33

PHASE MARGIN PHASE MARGIN

vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
42° 40°
VI = 10 mV VDD = 5 mV
CL = 20 pF VI = 10 mV
40° TA = 25°C 36° CL = 20 pF
See Figure 3 See Figure 3

38°
m – Phase Margin

m – Phase Margin

32°

Á ÁÁ
36°

Á ÁÁ
28°
φm

φm

34°

24°
32°

30° 20°
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C

Figure 34 Figure 35

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

TYPICAL CHARACTERISTICS

PHASE MARGIN EQUIVALENT INPUT NOISE VOLTAGE

vs vs

ÁÁ
CAPACITIVE LOAD FREQUENCY

ÁÁ
37° 200

nV/HzHz
ÁÁ
VDD = 5 mV VDD = 5 V
VI = 10 mV 175 RS = 20 Ω

V n– Equivalent Input Noise Voltage – nV/

ÁÁ
35° TA = 25°C TA = 25°C
See Figure 3 150 See Figure 2
m – Phase Margin

33°
125

31° 100

ÁÁ
ÁÁ
75
φm

29°

50
27°
25

25° VN
0
0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000
CL – Capacitive Load – pF f – Frequency – Hz

Figure 36 Figure 37

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

APPLICATION INFORMATION

single-supply operation
While the TLC27L2 and TLC27L7 perform well using dual power supplies (also called balanced or split
supplies), the design is optimized for single-supply operation. This design includes an input common-mode
voltage range that encompasses ground as well as an output voltage range that pulls down to ground. The
supply voltage range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly
available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is
recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC27L2 and TLC27L7 permits the use of very large resistive values to
implement the voltage divider, thus minimizing power consumption.
The TLC27L2 and TLC27L7 work well in conjunction with digital logic; however, when powering both linear
devices and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require RC decoupling.
VDD

R4
R1
R2
VI –
+ VDD R1 R3
ǒ Ǔ
) R3
VO V
+ REF
VREF
R3 C
V
O
+ VREF – VI R4
R2
) V
REF
0.01 µF

Figure 38. Inverting Amplifier With Voltage Reference

–
Power
VO + Logic Logic Logic Supply

(a) COMMON SUPPLY RAILS

–
Power
VO + Logic Logic Logic Supply

(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)

Figure 39. Common Versus Separate Supply Rails

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

APPLICATION INFORMATION

input characteristics
The TLC27L2 and TLC27L7 are specified with a minimum and a maximum input voltage that, if exceeded at
either input, could cause the device to malfunction. Exceeding this specified range is a common problem,
especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper
range limit is specified at VDD – 1 V at TA = 25°C and at VDD – 1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC27L2 and TLC27L7
very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage
drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC27L2 and
TLC27L7 are well suited for low-level signal processing; however, leakage currents on printed circuit boards
and sockets can easily exceed bias current requirements and cause a degradation in device performance. It
is good practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation.

noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC27L2 and TLC27L7 result in a very low
noise current, which is insignificant in most applications. This feature makes the devices especially favorable
over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit
greater noise currents.

– –
VI –
VO VO VO
VI + +
VI
+

(a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER

Figure 40. Guard-Ring Schemes

output characteristics
The output stage of the TLC27L2 and TLC27L7 is designed to sink and source relatively high amounts of current
(see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can
cause device damage under certain conditions. Output current capability increases with supply voltage.
All operating characteristics of the TLC27L2 and TLC27L7 were measured using a 20-pF load. The devices
drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole
occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many
cases, adding a small amount of resistance in series with the load capacitance alleviates the problem.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

APPLICATION INFORMATION

output characteristics (continued)

(a) CL = 20 pF, RL = NO LOAD (b) CL = 260 pF, RL = NO LOAD

2.5 V
–
TA = 25°C
VO f = 1 kHz
+ VI(PP) = 1 V
VI
CL

– 2.5 V

(c) CL = 310 pF, RL = NO LOAD (d) TEST CIRCUIT

Figure 41. Effect of Capacitive Loads and Test Circuit

Although the TLC27L2 and TLC27L7 possess excellent high-level output voltage and current capability,
methods for boosting this capability are available, if needed. The simplest method involves the use of a pullup
resistor (RP) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages
to the use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a
comparatively large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance
between approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With
very low values of RP, a voltage offset from 0 V at the output occurs. Second, pullup resistor RP acts as a
drain load to N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not
supplying the output current.

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

APPLICATION INFORMATION

output characteristics (continued)

VDD

VI + IP RP

– VO C
IF

R2
R1 IL RL –

VO
+

+
V –V
) )
DD O

ÁÁÁÁÁÁÁÁÁ
R
P I I I
F L P

ÁÁÁÁÁÁÁÁÁ
IP = Pullup current required

ÁÁÁÁÁÁÁÁÁ
by the operational amplifier
(typically 500 µA)
Figure 43. Compensation for
Figure 42. Resistive Pullup to Increase VOH Input Capacitance

feedback
Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.

electrostatic discharge protection

The TLC27L2 and TLC27L7 incorporate an internal electrostatic discharge (ESD) protection circuit that
prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care
should be exercised, however, when handling these devices, as exposure to ESD may result in the degradation
of the device parametric performance. The protection circuit also causes the input bias currents to be
temperature dependent and have the characteristics of a reverse-biased diode.

latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27L2 and
TLC27L7 inputs and outputs were designed to withstand –100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

APPLICATION INFORMATION

1/2
+ TLC27L2

500 kΩ VO1
–
5V

500 kΩ
+
VO2
– 1/2
TLC27L2

0.1 µF 500 kΩ

500 kΩ

Figure 44. Multivibrator

100 kΩ

VDD
100 kΩ
Set +

– 1/2
Reset TLC27L2
100 kΩ

33 kΩ

NOTE: VDD = 5 V to 16 V

Figure 45. Set /Reset Flip-Flop

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

APPLICATION INFORMATION
VDD

1/2
VI + TLC27L7
VO
–

90 kΩ
VDD

C
S1 X1
B
TLC4066 1
A
SELECT: S1 S2 1
AV 10 100 9 kΩ
C
S2 X2
Analog B
2
A Switch
2

1 kΩ

NOTE: VDD = 5 V to 12 V

Figure 46. Amplifier With Digital Gain Selection

10 kΩ

VDD

20 kΩ
VI –

VO
+
1/2
TLC27L2 100 kΩ

NOTE: VDD = 5 V to 16 V

Figure 47. Full-Wave Rectifier

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31

TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052C – OCTOBER 1987 – REVISED MARCH 2001

APPLICATION INFORMATION
0.016 µF

5V

10 kΩ 10 kΩ
VI +

VO
0.016 µF – 1/2
TLC27L2

NOTE: Normalized to fc = 1 kHz and RL = 10 kΩ

Figure 48. Two-Pole Low-Pass Butterworth Filter

R2
100 kΩ

VDD
R1
10 kΩ
VIA –

R1 VO
10 kΩ +
VIB 1/2
TLC27L7

R2
100 kΩ

V
O
ǒ
NOTE: VDD = 5 V to 16 V
+ R2 V – V
R1 IB IA
Ǔ
Figure 49. Difference Amplifier

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
products or services might be or are used. TI’s publication of information regarding any third party’s products
or services does not constitute TI’s approval, license, warranty or endorsement thereof.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
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or reproduction of this information with alteration voids all warranties provided for an associated TI product or
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Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service,
is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.

Also see: Standard Terms and Conditions of Sale for Semiconductor Products. [Link]/sc/docs/[Link]

Mailing Address:

Texas Instruments
Post Office Box 655303
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Copyright  2001, Texas Instruments Incorporated

This datasheet has been download from:

[Link]

Datasheets for electronics components.

 LMV931 SINGLE,, LMV932 DUAL,, LMV934 QUAD
1.8-V OPERATIONAL AMPLIFIERS
WITH RAIL-TO-RAIL INPUT AND OUTPUT
[Link] SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

FEATURES LMV931 . . . DBV (SOT-23-5) OR DCK (SC-70) PACKAGE

• 1.8-V, 2.7-V, and 5-V Specifications (TOP VIEW)
• Rail-to-Rail Output Swing
– 600-Ω Load . . . 80 mV From Rail IN+ 1 5 VCC+
VCC− 2
– 2-kΩ Load . . . 30 mV From Rail
IN− 3 4 OUTPUT
• VICR . . . 200 mV Beyond Rails
• Gain Bandwidth . . . 1.4 MHz
• Supply Current . . . 100 µA/Amplifier LMV932 . . . D (SOIC) OR
DGK (VSSOP/MSOP) PACKAGE
• Max VIO . . . 4 mV (TOP VIEW)
• Space-Saving Packages
1OUT 1 8 VCC+
– LMV931: SOT-23 and SC-70
1IN− 2 7 2OUT
– LMV932: MSOP and SOIC 1IN+ 3 6 2IN−
– LMV934: SOIC and TSSOP VCC− 4 5 2IN+

APPLICATIONS
• Industrial (Utility/Energy Metering) LMV934 . . . D (SOIC) OR PW (TSSOP) PACKAGE
• Automotive (TOP VIEW)
• Communications (Optical Telecom, Data/Voice
Cable Modems) 1OUT 1 14 4OUT
• Consumer Electronics (PDAs, PCs, CDR/W, 1IN− 2 13 4IN−
Portable Audio) 1IN+ 3 12 4IN+
• Supply-Current Monitoring VCC+ 4 11 VCC−
• Battery Monitoring 2IN+ 5 10 3IN+
2IN− 6 9 3IN−
2OUT 7 8 3OUT

DESCRIPTION/ORDERING INFORMATION
XXX

ORDERING INFORMATION
TA PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING (2)
Reel of 3000 LMV931IDBVR RBB_
SOT-23 – DBV
Reel of 250 LMV931IDBVT PREVIEW
Single
Reel of 3000 LMV931IDCKR RB_
SC-70 – DCK
Reel of 250 LMV931IDCKT PREVIEW
Reel of 2500 LMV932IDGKR RD_
MSOP/VSSOP – DGK
Reel of 250 LMV932IDGKT PREVIEW
–40°C to 125°C Dual
Tube of 75 LMV932ID
SOIC – D MV932I
Reel of 2500 LMV932IDR
Tube of 50 LMV934ID
SOIC – D LMV934I
Reel of 2500 LMV934IDR
Quad
Tube of 90 LMV934IPW
TSSOP – PW MV934I
Reel of 2000 LMV934IPWR

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
[Link]/sc/package.
(2) DBV/DCK/DGK: The actual top-side marking has one additional character that designates the assembly/test site.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2004–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMV931 SINGLE,, LMV932 DUAL,, LMV934 QUAD
1.8-V OPERATIONAL AMPLIFIERS
WITH RAIL-TO-RAIL INPUT AND OUTPUT [Link]
SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

The LMV93x devices are low-voltage low-power operational amplifiers that are well suited for today's low-voltage
and/or portable applications. Specified for operation of 1.8 V to 5 V, they can be used in portable applications
that are powered from a single-cell Li-ion or two-cell batteries. They have rail-to-rail input and output capability for
maximum signal swings in low-voltage applications. The LMV93x input common-mode voltage extends 200 mV
beyond the rails for increased flexibility. The output can swing rail-to-rail unloaded and typically can reach 80 mV
from the rails, while driving a 600-Ω load (at 1.8-V operation).
During 1.8-V operation, the devices typically consume a quiescent current of 103 µA per channel, and yet they
are able to achieve excellent electrical specifications, such as 101-dB open-loop DC gain and 1.4-MHz gain
bandwidth. Furthermore, the amplifiers offer good output drive characteristics, with the ability to drive a 600-Ω
load and 1000-pF capacitance with minimal ringing.
The LMV93x devices are offered in the latest packaging technology to meet the most demanding
space-constraint applications. The LMV931 is offered in standard SOT-23 and SC-70 packages. The LMV932 is
available in the traditional MSOP and SOIC packages. The LMV934 is available in the traditional SOIC and
TSSOP packages.
The LMV93x devices are characterized for operation from –40°C to 125°C, making the part universally suited for
commercial, industrial, and automotive applications.

SIMPLIFIED SCHEMATIC
VCC+

VBIAS1 I1 I2
IP
M5 M6

M1 M2

Class AB
OUT
Control
Q1
Q4 Q2
IN− IN+
Q3

M7 M8
M3 M4

VBIAS2 I3 I4
IN

VCC−

2 Submit Documentation Feedback

 LMV931 SINGLE,, LMV932 DUAL,, LMV934 QUAD
1.8-V OPERATIONAL AMPLIFIERS
[Link]
WITH RAIL-TO-RAIL INPUT AND OUTPUT
SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006
(1)
Absolute Maximum Ratings
over free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC+ – VCC– Supply voltage (2) 5.5 V
VID Differential input voltage (3) Supply voltage
VI Input voltage range, either input VCC– – 0.2 VCC+ + 0.2 V
Duration of output short circuit (one amplifier) to VCC± (4) (5) Unlimited
D package (8 pin) 97
D package (14 pin) 86
DBV package 206
θJA Package thermal impedance (5) (6) °C/W
DCK package 252
DGK package 172
PW package 113
TJ Operating virtual junction temperature 150 °C
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values (except differential voltages and VCC specified for the measurement of IOS) are with respect to the network GND.
(3) Differential voltages are at IN+ with respect to IN–.
(4) Applies to both single-supply and split-supply operation. Continuous short-circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely
affect reliability.
(5) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.

Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage (VCC+ – VCC–) 1.8 5 V
TA Operating free-air temperature –40 125 °C

ESD Protection
TYP UNIT
Human-Body Model 2000 V
Machine Model 200 V

Submit Documentation Feedback 3

LMV931 SINGLE,, LMV932 DUAL,, LMV934 QUAD
1.8-V OPERATIONAL AMPLIFIERS
WITH RAIL-TO-RAIL INPUT AND OUTPUT [Link]
SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

Electrical Characteristics
VCC+ = 1.8 V, VCC– = 0 V, VIC = VCC+/2, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
25°C 1 4
LMV931 (single)
Full range 6
VIO Input offset voltage mV
25°C 1 5.5
LMV932 (dual), LMV934 (quad)
Full range 7.5
Average temperature

V
IO coefficient of input 25°C 5.5 µV/°C
offset voltage
VIC = VCC+ – 0.8 V 25°C 15 35
IIB Input bias current 25°C 65 nA
Full range 75
25°C 13 25
IIO Input offset current nA
Full range 40
Supply current 25°C 103 185
ICC µA
(per channel) Full range 205
25°C 60 78
0 ≤ VIC ≤ 0.6 V, 1.4 V ≤ VIC ≤ 1.8 V –40°C to
55
Common-mode 85°C
CMRR dB
rejection ratio –40°C to
0.2 ≤ VIC ≤ 0.6 V, 1.4 V ≤ VIC ≤ 1.6 V 55
125°C
–0.2 ≤ VIC ≤ 0 V, 1.8 V ≤ VIC ≤ 2 V 25°C 50 72
Supply-voltage 25°C 75 100
kSVR 1.8 V ≤ VCC+ ≤ 5 V, VIC = 0.5 V dB
rejection ratio Full range 70
25°C VCC– – 0.2 –0.2 to 2.1 VCC+ + 0.2
–40°C to
Common-mode VCC– VCC+
VICR CMRR ≥ 50 dB 85°C V
input voltage range
–40°C to
VCC– + 0.2 VCC+ – 0.2
125°C
RL = 600 Ω 25°C 77 101
to 0.9 V Full range 73
LMV931
RL = 2 kΩ 25°C 80 105
to 0.9 V Full range 75
Large-signal VO = 0.2 V to 1.6 V,
AV dB
voltage gain VIC = 0.5 V
RL = 600 Ω 25°C 75 90
to 0.9 V Full range 72
LMV932,
LMV934 25°C 78 100
RL = 2 kΩ
to 0.9 V Full range 75
25°C 1.65 1.72
High level
RL = 600 Ω to 0.9 V, Full range 1.63
VID = ±100 mV 25°C 0.077 0.105
Low level
Full range 0.120
VO Output swing V
25°C 1.75 1.77
High level
RL = 2 kΩ to 0.9 V, Full range 1.74
VID = ±100 mV 25°C 0.024 0.035
Low level
Full range 0.040
VO = 0 V, 25°C 4 8
Sourcing
VID = 100 mV Full range 3.3
Output short-circuit
IOS mA
current 25°C 7 9
VO = 1.8 V,
Sinking
VID = –100 mV Full range 5

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SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

Electrical Characteristics (continued)

VCC+ = 1.8 V, VCC– = 0 V, VIC = VCC+/2, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
Gain bandwidth
GBW 25°C 1.4 MHz
product
SR Slew rate (1) 25°C 0.35 V/µS
Φm Phase margin 25°C 67 °
Gain margin 25°C 7 dB
Equivalent input
Vn f = 1 kHz, VIC = 0.5 V 25°C 60 nV/√Hz
noise voltage
Equivalent input
In f = 1 kHz 25°C 0.06 pA/√Hz
noise current
Total harmonic f = 1 kHz, AV = 1, RL = 600 Ω,
THD 25°C 0.023 %
distortion VID = 1 Vp-p
Amplifier-to-amplifier
25°C 123 dB
isolation (2)

(1) Number specified is the slower of the positive and negative slew rates.
(2) Input referred, VCC+ = 5 V and RL = 100 kΩ connected to 2.5 V. Each amplifier is excited, in turn, with a 1-kHz signal to produce
VO = 3 Vp-p.

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SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

Electrical Characteristics
VCC+ = 2.7 V, VCC– = 0 V, VIC = VCC+/2, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
25°C 1 4
LMV931 (single)
Full range 6
VIO Input offset voltage mV
25°C 1 5.5
LMV932 (dual), LMV934 (quad)
Full range 7.5
Average temperature

V
IO coefficient of input 25°C 5.5 µV/°C
offset voltage
VIC = VCC+ – 0.8 V 25°C 15 35
IIB Input bias current 25°C 65 nA
Full range 75
25°C 8 25
IIO Input offset current nA
Full range 40
Supply current 25°C 105 190
ICC µA
(per channel) Full range 210
25°C 60 81
0 ≤ VIC ≤ 1.5 V, 2.3 V ≤ VIC ≤ 2.7 V –40°C to
55
Common-mode 85°C
CMRR dB
rejection ratio –40°C to
0.2 ≤ VIC ≤ 1.5 V, 2.3 V ≤ VIC ≤ 2.5 V 55
125°C
–0.2 ≤ VIC ≤ 0 V, 2.7 V ≤ VIC ≤ 2.9 V 25°C 50 74
Supply-voltage 25°C 75 100
kSVR 1.8 V ≤ VCC+ ≤ 5 V, VIC = 0.5 V dB
rejection ratio Full range 70
25°C VCC– – 0.2 –0.2 to 3 VCC+ + 0.2
–40°C to
Common-mode input VCC– VCC+
VICR CMRR ≥ 50 dB 85°C V
voltage range
–40°C to
VCC– + 0.2 VCC+ – 0.2
125°C
RL = 600 Ω 25°C 87 104
to 1.35 V Full range 86
LMV931
RL = 2 kΩ 25°C 92 110
to 1.35 V Full range 91
Large-signal
AV VO = 0.2 V to 2.5 V dB
voltage gain
RL = 600 Ω 25°C 78 90
to 1.35 V Full range 75
LMV932,
LMV934 25°C 81 100
RL = 2 kΩ
to 1.35 V Full range 78
25°C 2.55 2.62
High level
RL = 600 Ω to 1.35 V, Full range 2.53
VID = ±100 mV 25°C 0.083 0.11
Low level
Full range 0.13
VO Output swing V
25°C 2.65 2.675
High level
RL = 2 kΩ to 1.35 V, Full range 2.64
VID = ±100 mV 25°C 0.025 0.04
Low level
Full range 0.045
VO = 0 V, 25°C 20 30
Sourcing
VID = 100 mV Full range 15
Output short-circuit
IOS mA
current 25°C 18 25
VO = 2.7 V,
Sinking
VID = –100 mV Full range 12
GBW Gain bandwidth product 25°C 1.4 MHz

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Electrical Characteristics (continued)

VCC+ = 2.7 V, VCC– = 0 V, VIC = VCC+/2, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
SR Slew rate (1) 25°C 0.4 V/µS
Φm Phase margin 25°C 70 °
Gain margin 25°C 7.5 dB
Equivalent input
Vn f = 1 kHz, VIC = 0.5 V 25°C 57 nV/√Hz
noise voltage
Equivalent input
In f = 1 kHz 25°C 0.082 pA/√Hz
noise current
f = 1 kHz, AV = 1, RL = 600 Ω,
THD Total harmonic distortion 25°C 0.022 %
VID = 1 Vp-p
Amplifier-to-amplifier
25°C 123 dB
isolation (2)

(1) Number specified is the slower of the positive and negative slew rates.
(2) Input referred, VCC+ = 5 V and RL = 100 kΩ connected to 2.5 V. Each amplifier is excited, in turn, with a 1-kHz signal to produce
VO = 3 Vp-p.

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SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

Electrical Characteristics
VCC+ = 5 V, VCC– = 0 V, VIC = VCC+/2, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
25°C 1 4
LMV931 (single)
Full range 6
VIO Input offset voltage mV
25°C 1 5.5
LMV932 (dual), LMV934 (quad)
Full range 7.5
Average temperature

V
IO coefficient of input 25°C 5.5 µV/°C
offset voltage
VIC = VCC+ – 0.8 V 25°C 15 35
IIB Input bias current 25°C 65 nA
Full range 75
25°C 9 25
IIO Input offset current nA
Full range 40
Supply current 25°C 116 210
ICC µA
(per channel) Full range 230
25°C 60 86
0 ≤ VIC ≤ 3.8 V, 4.6 V ≤ VIC ≤ 5 V –40°C to
55
Common-mode 85°C
CMRR dB
rejection ratio –40°C to
0.3 ≤ VIC ≤ 3.8 V, 4.6 V ≤ VIC ≤ 4.7 V 55
125°C
–0.2 ≤ VIC ≤ 0 V, 5 V ≤ VIC ≤ 5.2 V 25°C 50 78
Supply-voltage 25°C 75 100
kSVR 1.8 V ≤ VCC+ ≤ 5 V, VIC = 0.5 V dB
rejection ratio Full range 70
25°C VCC– – 0.2 –0.2 to 5.3 VCC+ + 0.2
–40°C to
Common-mode input VCC– VCC+
VICR CMRR ≥ 50 dB 85°C V
voltage range
–40°C to
VCC– + 0.3 VCC+ – 0.3
125°C
RL = 600 Ω 25°C 88 102
to 2.5 V Full range 87
LMV931
RL = 2 kΩ 25°C 94 113
to 2.5 V Full range 93
Large-signal
AV VO = 0.2 V to 4.8 V dB
voltage gain
RL = 600 Ω 25°C 81 90
to 2.5 V Full range 78
LMV932,
LMV934 25°C 85 100
RL = 2 kΩ
to 2.5 V Full range 82
25°C 4.855 4.89
High level
RL = 600 Ω to 2.5 V, Full range 4.835
VID = ±100 mV 25°C 0.12 0.16
Low level
Full range 0.18
VO Output swing V
25°C 4.945 4.967
High level
RL = 2 kΩ to 2.5 V, Full range 4.935
VID = ±100 mV 25°C 0.037 0.065
Low level
Full range 0.075
VO = 0 V, 25°C 80 100
Sourcing
VID = 100 mV Full range 68
Output short-circuit
IOS mA
current 25°C 58 65
VO = 5 V,
Sinking
VID = –100 mV Full range 45

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SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

Electrical Characteristics (continued)

VCC+ = 5 V, VCC– = 0 V, VIC = VCC+/2, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
Gain bandwidth
GBW 25°C 1.5 MHz
product
SR Slew rate (1) 25°C 0.42 V/µS
Φm Phase margin 25°C 71 °
Gain margin 25°C 8 dB
Equivalent input
Vn f = 1 kHz, VIC = 0.5 V 25°C 50 nV/√Hz
noise voltage
Equivalent input
In f = 1 kHz 25°C 0.07 pA/√Hz
noise current
Total harmonic f = 1 kHz, AV = 1, RL = 600 Ω,
THD 25°C 0.022 %
distortion VID = 1 Vp-p
Amplifier-to-amplifier
25°C 123 dB
isolation (2)

(1) Number specified is the slower of the positive and negative slew rates.
(2) Input referred, VCC+ = 5 V and RL = 100 kΩ connected to 2.5 V. Each amplifier is excited, in turn, with a 1-kHz signal to produce
VO = 3 Vp-p.

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SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

TYPICAL CHARACTERISTICS
VCC+ = 5 V, Single Supply, TA = 25°C (unless otherwise specified)

SUPPLY CURRENT SLEW RATE

vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
0.17 0.6
125°C RL = 2 kΩ
0.15 AV = 1
85°C 0.55 VI = 1 Vpp
0.13 Falling Edge
Supply Current − mA

25°C
0.5
0.11

Slew Rate − V/µs

0.09 −40°C
0.45 Rising Edge

0.07
0.4
0.05
0.35
0.03

0.01 0.3

−0.01
0 1 2 3 4 5 0.25
0 1 2 3 4 5 6
Supply Voltage − V
Supply Voltage − V

Figure 1. Figure 2.

SOURCE CURRENT SINK CURRENT

vs vs
OUTPUT VOLTAGE OUTPUT VOLTAGE
1000 1000

5-V Source 5-V Sink

100 100
Source Current − mA

Sink Current − mA

2.7-V Source 2.7-V Sink

10 10
1.8-V Source 1.8-V Sink

1 1

0.1 0.1

0.01 0.01
0.001 0.01 0.1 1 10
0.001 0.01 0.1 1 10
Output Voltage Referenced to V+ (V)
Output Voltage Referenced to V− (V)

Figure 3. Figure 4.

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SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

TYPICAL CHARACTERISTICS (continued)

VCC+ = 5 V, Single Supply, TA = 25°C (unless otherwise specified)

OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING

vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
140 45
RL = 600 Ω RL = 2 kΩ
Voltage From Supply Voltage − mV Absolute

Voltage From Supply Voltage − mV Absolute

120 40

35
100
Negative Swing 30 Negative Swing

80
25

60 20

Positive Swing 15
40 Positive Swing
10
20
5
0
0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
Supply Voltage − V Supply Voltage − V

Figure 5. Figure 6.

SHORT-CIRCUIT CURRENT (SINK) SHORT-CIRCUIT CURRENT (SOURCE)

vs vs
TEMPERATURE TEMPERATURE
160 160
5-V Source

140 140

5-V Sink
Short-Circuit Current (Sink) − mA

Short-Circuit Current (Source) − mA

120 120

100 100

80 80

60 60
2.7-V Source
2.7-V Sink
40 40

1.8-V Source
20 1.8-V Sink 20

0
0 −40 −20 0 20 40 60 80 100 120
−40 −20 0 20 40 60 80 100 120
Temperature − °C Temperature − °C

Figure 7. Figure 8.

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SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

TYPICAL CHARACTERISTICS (continued)

VCC+ = 5 V, Single Supply, TA = 25°C (unless otherwise specified)

1.8-V FREQUENCY RESPONSE

vs
CL
60 110
VS = 1.8 V
Phase RL = 600 Ω
50 90

40 70

Phase Margin − Deg

30 Gain 50
Gain − dB

20 30

10 10

0 CL = 0 pF −10
CL = 300 pF
CL = 1000 pF
−10 −30
10k 100k 1M 10M
Frequency − Hz

Figure 9.

5-V FREQUENCY RESPONSE

vs
CL
60 110
VS = 5 V
Phase RL = 600 Ω
50 90

40 70
Phase Margin − Deg

Gain
Gain − dB

30 50

20 30

10 10

CL = 0 pF −10
0 CL = 300 pF
CL = 1000 pF
−10 −30
10k 100k 1M 10M
Frequency − Hz

Figure 10.

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SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

TYPICAL CHARACTERISTICS (continued)

VCC+ = 5 V, Single Supply, TA = 25°C (unless otherwise specified)

1.8-V FREQUENCY RESPONSE

vs
TEMPERATURE
60 110
VS = 1.8 V
RL = 600 Ω
50 Phase 90
CL = 150 pF

40 70

Phase Margin − Deg

30 Gain 25°C 50
Gain − dB

−40°C 25°C
85°C
20 30
125°C 85°C

10 10
125°C

0 −40°C −10

−10 −30
10k 100k 1M 10M
Frequency − Hz

Figure 11.

5-V FREQUENCY RESPONSE

vs
TEMPERATURE
60 110
VS = 5 V
RL = 600 Ω
50 Phase 90
CL = 150 pF

40 70
Phase Margin − Deg

30 Gain 25°C 50
Gain − dB

−40°C 25°C

20 85°C
125°C 30
85°C
125°C
10 10

−40°C
0 −10

−10 −30
10k 100k 1M 10M
Frequency − Hz

Figure 12.

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SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

TYPICAL CHARACTERISTICS (continued)

VCC+ = 5 V, Single Supply, TA = 25°C (unless otherwise specified)

CMRR PSRR
vs vs
FREQUENCY FREQUENCY
100 100
1.8 V
2.7 V
5V 90
90
+PSRR
80
−PSRR
CMRR − dB

80

Gain − dB
70

60
70

50

60
40

50 30
10 100 1k 10k 100k 10 100 1k 10k
Frequency − Hz Frequency − Hz

Figure 13. Figure 14.

THD THD
vs vs
FREQUENCY FREQUENCY
10 10
RL = 600 Ω RL = 600 Ω
AV = 1 AV = 10

1 1
THD − %
THD − %

0.1 0.1

0.01 0.01
1.8 V 1.8 V
2.7 V 2.7 V
5V 5V
0.001 0.001
10 100 1k 10k 100k 10 100 1k 10k 100k
Frequency − Hz Frequency − Hz

Figure 15. Figure 16.

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TYPICAL CHARACTERISTICS (continued)

VCC+ = 5 V, Single Supply, TA = 25°C (unless otherwise specified)

SMALL-SIGNAL NONINVERTING RESPONSE SMALL-SIGNAL NONINVERTING RESPONSE

0.25 0.25
0.1 0.1
VS = 1.8 V VS = 2.7 V
RL = 2 kΩ Input RL = 2 kΩ Input
0.2 0.05 0.05
0.2

0.15 0
0.15 0
Output Voltage − V

Input Voltage − V

Input Voltage − V
Output Voltage − V
0.1 −0.05 0.1 −0.05

Output Output
0.05 −0.1 0.05 −0.1

0 −0.15
0 −0.15

−0.05 −0.2 −0.05 −0.2

−0.1 −0.25 −0.25

−0.1
0.25 µs/div
0.25 µs/div

Figure 17. Figure 18.

SMALL-SIGNAL NONINVERTING RESPONSE LARGE-SIGNAL NONINVERTING RESPONSE

0.25 0.1 4.5 1.8
VS = 5 V VS = 1.8 V
RL = 2 kΩ Input RL = 2 kΩ
Input
0.05 3.6 AV = 1
0.2 0.9

0.15 0 2.7 0

Input Voltage − V
Output Voltage − V
Output Voltage − V

Input Voltage − V

0.1 −0.05 1.8 −0.9

Output Output
0.05 −0.1 0.9 −1.8

0 −0.15 −2.7
0

−0.05 −0.2
−0.9 −3.6

−0.1 −0.25
−1.8 −4.5
0.25 µs/div
10 µs/div

Figure 19. Figure 20.

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SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

TYPICAL CHARACTERISTICS (continued)

VCC+ = 5 V, Single Supply, TA = 25°C (unless otherwise specified)

LARGE-SIGNAL NONINVERTING RESPONSE LARGE-SIGNAL NONINVERTING RESPONSE

6.75 2.7 12.5 5
VS = 2.7 V VS = 5 V
RL = 2 kΩ Input RL = 2 kΩ
Input
5.4 AV = 1 1.35 10 AV = 1 2.5

4.05 0 7.5 0
Output Voltage − V

Output Voltage − V

Input Voltage − V
Input Voltage − V
2.7 −1.35 −2.5
5

Output Output
−5
1.35 −2.7 2.5

0 −7.5
−4.05 0

−1.35 −2.5 −10

−5.4

−2.7 −6.75 −5 −12.5

10 µs/div
10 µs/div

Figure 21. Figure 22.

OFFSET VOLTAGE OFFSET VOLTAGE

vs vs
COMMON-MODE RANGE COMMON-MODE RANGE
1 1
VS = 1.8 V VS = 2.7 V
0.5 0.5

0 0

−0.5 −0.5
VIO − mV

VIO − mV

−1 −1

−1.5 −1.5

−2 −2
125°C 125°C
85°C 85°C
−2.5 25°C −2.5 25°C
−40°C −40°C
−3 −3
−0.4 0 0.4 0.8 1.2 1.6 2 2.4 −0.4 0.1 0.6 1.1 1.6 2.1 2.6 3.1
VIC − V VIC − V

Figure 23. Figure 24.

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SLOS441G – AUGUST 2004 – REVISED FEBRUARY 2006

TYPICAL CHARACTERISTICS (continued)

VCC+ = 5 V, Single Supply, TA = 25°C (unless otherwise specified)

OFFSET VOLTAGE
vs
COMMON-MODE RANGE
1
VS = 5 V
0.5

−0.5
VIO − mV

−1

−1.5

−2
125°C
85°C
−2.5 25°C
−40°C
−3
−0.4 0.6 1.6 2.6 3.6 4.6 5.6
VIC − V

Figure 25.

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 PACKAGE OPTION ADDENDUM
[Link] 9-Oct-2007

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
LMV931IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV931IDBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV931IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV931IDCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV931IDCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV931IDCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV932ID ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV932IDE4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV932IDG4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV932IDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV932IDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV932IDR ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV932IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV932IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV934ID ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV934IDE4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV934IDG4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV934IDR ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV934IDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV934IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV934IPW ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV934IPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV934IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV934IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LMV934IPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
[Link] 9-Oct-2007

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
LMV934IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
[Link] for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION
[Link] 28-Feb-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Type Drawing Diameter Width (mm) (mm) Quadrant
(mm) W1 (mm)
LMV931IDBVR SOT-23 DBV 5 3000 179.0 8.0 3.0 3.0 1.0 4.0 8.0 Q3
LMV931IDCKR SC70 DCK 5 3000 179.0 8.0 2.0 3.0 1.0 4.0 8.0 Q3
LMV932IDGKR MSOP DGK 8 2500 330.0 12.0 5.0 3.0 1.0 8.0 12.0 Q1
LMV932IDGKR MSOP DGK 8 2500 330.0 13.0 5.0 3.0 1.0 8.0 12.0 Q1
LMV932IDR SOIC D 8 2500 330.0 12.0 6.0 5.0 2.0 8.0 12.0 Q1
LMV934IDR SOIC D 14 2500 330.0 16.0 7.0 9.0 2.0 8.0 16.0 Q1
LMV934IPWR TSSOP PW 14 2000 330.0 12.0 7.0 6.0 2.0 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION
[Link] 28-Feb-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV931IDBVR SOT-23 DBV 5 3000 220.0 205.0 50.0
LMV931IDCKR SC70 DCK 5 3000 220.0 205.0 50.0
LMV932IDGKR MSOP DGK 8 2500 370.0 355.0 55.0
LMV932IDGKR MSOP DGK 8 2500 358.0 335.0 35.0
LMV932IDR SOIC D 8 2500 343.0 338.0 21.0
LMV934IDR SOIC D 14 2500 346.0 346.0 33.0
LMV934IPWR TSSOP PW 14 2000 346.0 346.0 29.0

Pack Materials-Page 2
 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 IMPORTANT NOTICE
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Copyright © 2008, Texas Instruments Incorporated
 ____________________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at [Link].
 Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to [Link]/packages.)
FQPF2P25

April 2000

QFET TM

FQPF2P25
250V P-Channel MOSFET

General Description Features

These P-Channel enhancement mode power field effect • -1.8A, -250V, RDS(on) = 4.0Ω @VGS = -10 V
transistors are produced using Fairchild’s proprietary, • Low gate charge ( typical 6.5 nC)
planar stripe, DMOS technology. • Low Crss ( typical 6.5 pF)
This advanced technology has been especially tailored to • Fast switching
minimize on-state resistance, provide superior switching • 100% avalanche tested
performance, and withstand high energy pulse in the • Improved dv/dt capability
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters.

S
!

G!

GD S TO-220F !
FQPF Series D

Absolute Maximum Ratings

TC = 25°C unless otherwise noted

Symbol Parameter FQPF2P25 Units

VDSS Drain-Source Voltage -250 V
ID Drain Current - Continuous (TC = 25°C) -1.8 A
- Continuous (TC = 100°C) -1.14 A
IDM Drain Current - Pulsed (Note 1) -7.2 A
VGSS Gate-Source Voltage ±
30 V
EAS Single Pulsed Avalanche Energy (Note 2) 120 mJ
IAR Avalanche Current (Note 1) -1.8 A
EAR Repetitive Avalanche Energy (Note 1) 3.2 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) -5.5 V/ns
PD Power Dissipation (TC = 25°C) 32 W
- Derate above 25°C 0.26 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
Maximum lead temperature for soldering purposes,
TL 300 °C
1/8
from case for 5 seconds

Thermal Characteristics
Symbol Parameter Typ Max Units
RθJC Thermal Resistance, Junction-to-Case -- 3.9 °CW
RθJA Thermal Resistance, Junction-to-Ambient -- 62.5 °CW

©2000 Fairchild Semiconductor International Rev. A, April 2000

 FQPF2P25
Electrical Characteristics




T C = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -250 -- -- V
∆BVDSS Breakdown Voltage Temperature
ID = -250 µA, Referenced to 25°C -- -0.2 -- V/°C
/ ∆TJ Coefficient
IDSS VDS = -250 V, VGS = 0 V -- -- -1 µA
Zero Gate Voltage Drain Current
VDS = -200 V, TC = 125°C -- -- -10 µA
IGSSF Gate-Body Leakage Current, Forward VGS = -30 V, VDS = 0 V -- -- -100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = 30 V, VDS = 0 V -- -- 100 nA

On Characteristics
VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA -3.0 -- -5.0 V
RDS(on) Static Drain-Source
VGS = -10 V, ID = -0.9 A -- 3.15 4.0 Ω
On-Resistance
gFS Forward Transconductance VDS = -40 V, ID = -0.9 A (Note 4) -- 1.08 -- S

Dynamic Characteristics
Ciss Input Capacitance VDS = -25 V, VGS = 0 V, -- 190 250 pF
Coss Output Capacitance f = 1.0 MHz -- 40 55 pF
Crss Reverse Transfer Capacitance -- 6.5 8.5 pF

Switching Characteristics
td(on) Turn-On Delay Time -- 8.5 25 ns
VDD = -125 V, ID = -2.3 A,
tr Turn-On Rise Time -- 40 90 ns
RG = 25 Ω
td(off) Turn-Off Delay Time -- 12 35 ns
(Note 4, 5)
tf Turn-Off Fall Time -- 25 60 ns
Qg Total Gate Charge VDS = -200 V, ID = -2.3 A, -- 6.5 8.5 nC
Qgs Gate-Source Charge VGS = -10 V -- 1.8 -- nC
Qgd Gate-Drain Charge (Note 4, 5) -- 3.0 -- nC

Drain-Source Diode Characteristics and Maximum Ratings

IS Maximum Continuous Drain-Source Diode Forward Current -- -- -1.8 A
ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 7.2 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -1.8 A -- -- -5.0 V
trr Reverse Recovery Time VGS = 0 V, IS = -2.3 A, -- 110 -- ns
Qrr Reverse Recovery Charge dIF / dt = 100 A/µs (Note 4)
-- 0.4 -- µC

Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 59mH, IAS = -1.8A, VDD = -50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD
-2.3A, di/dt
300A/µs, VDD
BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width
300µs, Duty cycle
2%
5. Essentially independent of operating temperature

©2000 Fairchild Semiconductor International Rev. A, April 2000

FQPF2P25

Typical Characteristics

VGS
Top : -15.0 V
-10.0 V
-8.0 V
-7.0 V
-6.5 V
-6.0 V
Bottom : -5.5 V

-ID , Drain Current [A]

0
10
-I D, Drain Current [A]

0
10
150

25

-1
10

Notes : -55

Notes :
1. 250s Pulse Test 1. VDS = -40V
2. TC = 25 2. 250s Pulse Test

-1
-1 0 1
10
10 10 10 2 4 6 8 10
-VDS, Drain-Source Voltage [V] -VGS , Gate-Source Voltage [V]

Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics

15

12
-I DR , Reverse Drain Current [A]
Drain-Source On-Resistance

VGS = - 10V
RDS(on) [ Ω ],

9
0
VGS = - 20V 10

6 150
25

3
Notes :
1. VGS = 0V

Note : TJ = 25 2. 250s Pulse Test

0 -1
0.0 1.5 3.0 4.5 6.0 10
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
-ID , Drain Current [A] -VSD , Source-Drain Voltage [V]

Figure 3. On-Resistance Variation vs. Figure 4. Body Diode Forward Voltage

Drain Current and Gate Voltage Variation vs. Source Current
and Temperature

12
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
400 Crss = Cgd VDS = -50V
10
VDS = -125V
-VGS, Gate-Source Voltage [V]

VDS = -200V
300 Ciss 8
Capacitance [pF]

Coss
6
200

Notes : 4
1. VGS = 0 V
Crss 2. f = 1 MHz
100
2

Note : ID = -2.3 A

0 0
-1 0 1 0 1 2 3 4 5 6 7
10 10 10
-VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC]

Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics

©2000 Fairchild Semiconductor International Rev. A, April 2000

 FQPF2P25
Typical Characteristics (Continued)

1.2 2.5

2.0
Drain-Source Breakdown Voltage

1.1

Drain-Source On-Resistance
-BV DSS , (Normalized)

RDS(ON) , (Normalized)
1.5

1.0

1.0

0.9
Notes :
1. VGS = 0 V
Notes :
0.5
2. ID = -250 A 1. VGS = -10 V
2. ID = -1.15 A

0.8 0.0
-100 -50 0 50 100 150 200 -100 -50 0 50 100 150 200
o o
TJ, Junction Temperature [ C] TJ, Junction Temperature [ C]

Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation

vs. Temperature vs. Temperature

2.0

Operation in This Area

is Limited by R DS(on)
1
10
1.5
1 ms
-I D, Drain Current [A]

-I D, Drain Current [A]

10 ms
100 ms
0
10 DC 1.0

-1
10 0.5

Notes :
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
-2
10 0.0
0 1 2
10 10 10 25 50 75 100 125 150

-VDS, Drain-Source Voltage [V] TC, Case Temperature [
]

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
( t) , T h e r m a l R e s p o n s e

D = 0 .5
0
10
0 .2

N o te s :
0 .1 1 . Z
J C ( t ) = 3 . 9  /W M a x .
2 . D u ty F a c t o r , D = t 1 /t 2
0 .0 5 3 . T J M - T C = P D M * Z
J C( t )

-1
10 0 .0 2
PDM
0 .0 1

JC

t1
t2
Z

s in g le p u ls e

-2
10
-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10

t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]

Figure 11. Transient Thermal Response Curve

©2000 Fairchild Semiconductor International Rev. A, April 2000

FQPF2P25

Gate Charge Test Circuit & Waveform

VGS
Same Type
50K

as DUT Qg
12V 200nF
300nF -10V
VDS
VGS Qgs Qgd

DUT
-3mA

Charge

Resistive Switching Test Circuit & Waveforms

RL
VDS t on t off
td(on) tr td(off)
VGS VDD tf

RG VGS
10%

-10V DUT

90%
VDS

Unclamped Inductive Switching Test Circuit & Waveforms

L 1 BVDSS
VDS EAS = ---- L IAS2 --------------------
2 BVDSS - VDD
tp Time
ID

RG VDD VDS (t)

VDD
ID (t)
-10V DUT
IAS
tp BVDSS

©2000 Fairchild Semiconductor International Rev. A, April 2000

 FQPF2P25
Peak Diode Recovery dv/dt Test Circuit & Waveforms

VDS

DUT _

I SD
L

Driver
RG
Compliment of DUT
(N-Channel) VDD

VGS • dv/dt controlled by RG

• ISD controlled by pulse period

Gate Pulse Width

VGS D = --------------------------
Gate Pulse Period 10V
( Driver )

Body Diode Reverse Current

I SD
( DUT ) IRM

di/dt

IFM , Body Diode Forward Current

VDS VSD
( DUT )

Body Diode VDD

Forward Voltage Drop

Body Diode Recovery dv/dt

©2000 Fairchild Semiconductor International Rev. A, April 2000

FQPF2P25

Package Dimensions

TO-220F
3.30 ±0.10

10.16 ±0.20 ø3.18 ±0.10 2.54 ±0.20

(7.00) (0.70)

6.68 ±0.20

15.87 ±0.20
15.80 ±0.20

(1.00x45°)

MAX1.47
9.75 ±0.30

0.80 ±0.10
(3
0°
)

#1
0.35 ±0.10 +0.10
0.50 –0.05 2.76 ±0.20
2.54TYP 2.54TYP
[2.54 ±0.20] [2.54 ±0.20]
4.70 ±0.20

9.40 ±0.20

©2000 Fairchild Semiconductor International Rev. A, April 2000

 TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx™ HiSeC™ SuperSOT™-8

Bottomless™ ISOPLANAR™ SyncFET™
CoolFET™ MICROWIRE™ TinyLogic™
CROSSVOLT™ POP™ UHC™
E2CMOS™ PowerTrench® VCX™
FACT™ QFET™
FACT Quiet Series™ QS™
FAST® Quiet Series™
FASTr™ SuperSOT™-3
GTO™ SuperSOT™-6

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
INTERNATIONAL.
As used herein: result in significant injury to the user.
1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In This datasheet contains the design specifications for
Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

©2000 Fairchild Semiconductor International Rev. A, January 2000

 6-PIN DIP RANDOM-PHASE
OPTOISOLATORS TRIAC DRIVER OUTPUT
(250/400 VOLT PEAK)

MOC3010M MOC3011M MOC3012M MOC3020M MOC3021M MOC3022M MOC3023M

PACKAGE SCHEMATIC

ANODE 1 6 MAIN TERM.

6
6 CATHODE 2 5 NC*
1
N/C 3 4 MAIN TERM.
1

*DO NOT CONNECT

(TRIAC SUBSTRATE)

DESCRIPTION
The MOC301XM and MOC302XM series are optically isolated triac driver devices. These devices contain a GaAs infrared
emitting diode and a light activated silicon bilateral switch, which functions like a triac. They are designed for interfacing between
electronic controls and power triacs to control resistive and inductive loads for 115 VAC operations.

FEATURES
• Excellent IFT stability—IR emitting diode has low degradation
• High isolation voltage—minimum 5300 VAC RMS
• Underwriters Laboratory (UL) recognized—File #E90700
• Peak blocking voltage
– 250V-MOC301XM
– 400V-MOC302XM
• VDE recognized (File #94766)
– Ordering option V (e.g. MOC3023VM)

APPLICATIONS
• Industrial controls • Solenoid/valve controls
• Traffic lights • Static AC power switch
• Vending machines • Incandescent lamp dimmers
• Solid state relay • Motor control
• Lamp ballasts

© 2005 Fairchild Semiconductor Corporation Page 1 of 10 6/15/05

 6-PIN DIP RANDOM-PHASE
OPTOISOLATORS TRIAC DRIVER OUTPUT
(250/400 VOLT PEAK)

MOC3010M MOC3011M MOC3012M MOC3020M MOC3021M MOC3022M MOC3023M

ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted)

Parameters Symbol Device Value Units
TOTAL DEVICE
Storage Temperature TSTG All -40 to +150 °C
Operating Temperature TOPR All -40 to +85 °C
Lead Solder Temperature TSOL All 260 for 10 sec °C
Junction Temperature Range TJ All -40 to +100 °C
Isolation Surge Voltage(1)
VISO All 7500 Vac(pk)
(peak AC voltage, 60Hz, 1 sec duration)
Total Device Power Dissipation @ 25°C 330 mW
PD All
Derate above 25°C 4.4 mW/°C
EMITTER
Continuous Forward Current IF All 60 mA
Reverse Voltage VR All 3 V
Total Power Dissipation 25°C Ambient 100 mW
PD All
Derate above 25°C 1.33 mW/°C
DETECTOR
MOC3010M/1M/2M 250
Off-State Output Terminal Voltage VDRM V
MOC3020M/1M/2M/3M 400
Peak Repetitive Surge Current (PW = 1 ms, 120 pps) ITSM All 1 A
Total Power Dissipation @ 25°C Ambient 300 mW
PD All
Derate above 25°C 4 mW/°C

Note
1. Isolation surge voltage, VISO, is an internal device dielectric breakdown rating. For this test, Pins 1 and 2 are common, and
Pins 4, 5 and 6 are common.

© 2005 Fairchild Semiconductor Corporation Page 2 of 10 6/15/05

 6-PIN DIP RANDOM-PHASE
OPTOISOLATORS TRIAC DRIVER OUTPUT
(250/400 VOLT PEAK)

MOC3010M MOC3011M MOC3012M MOC3020M MOC3021M MOC3022M MOC3023M

ELECTRICAL CHARACTERISTICS (TA = 25°C Unless otherwise specified)

INDIVIDUAL COMPONENT CHARACTERISTICS

Parameters Test Conditions Symbol Device Min Typ Max Units
EMITTER
Input Forward Voltage IF = 10 mA VF All 1.15 1.5 V
Reverse Leakage Current VR = 3 V, TA = 25°C IR All 0.01 100 µA
DETECTOR
Peak Blocking Current,Either Direction Rated VDRM, IF = 0 (note 1) IDRM All 10 100 nA
Peak On-State Voltage,Either Direction ITM = 100 mA peak, IF = 0 VTM All 1.8 3 V

TRANSFER CHARACTERISTICS (TA = 25°C Unless otherwise specified.)

DC Characteristics Test Conditions Symbol Device Min Typ Max Units
MOC3020M 30
MOC3010M
15
MOC3021M
LED Trigger Current Voltage = 3V (note 3) IFT MOC3011M mA
10
MOC3022M
MOC3012M
5
MOC3023M
Holding Current, Either Direction IH All 100 µA

Note
1. Test voltage must be applied within dv/dt rating.
2. This is static dv/dt. See Figure 5 for test circuit. Commutating dv/dt is a function of the load-driving thyristor(s) only.
3. All devices are guaranteed to trigger at an IF value less than or equal to max IFT. Therefore, recommended operating IF lies
between max IFT (30 mA for MOC3020M, 15 mA for MOC3010M and MOC3021M, 10 mA for MOC3011M and MOC3022M,
5 mA for MOC3012M and MOC3023M) and absolute max IF (60 mA).

© 2005 Fairchild Semiconductor Corporation Page 3 of 10 6/15/05

 6-PIN DIP RANDOM-PHASE
OPTOISOLATORS TRIAC DRIVER OUTPUT
(250/400 VOLT PEAK)

MOC3010M MOC3011M MOC3012M MOC3020M MOC3021M MOC3022M MOC3023M

Fig. 1 LED Forward Voltage vs. Forward Current Fig. 2 On-State Characteristics
1.8 800

1.7 600

ON-STATE CURRENT - I TM (mA)

1.6 400
VF - FORWARD VOLTAGE (V)

200
1.5

0
1.4
TA = -55oC

-200
1.3
TA = 25oC
-400
1.2
TA = 100oC
-600
1.1

-800
1.0 -3 -2 -1 0 1 2 3
1 10 100
ON-STATE VOLTAGE - V TM (V)
IF - LED FORWARD CURRENT (mA)

Fig. 3 Trigger Current vs. Ambient Temperature Fig. 4 LED Current Required to Trigger vs. LED Pulse Width
1.4 25
TRIGGER CURRENT - I FT (NORMALIZED)

1.3
TRIGGER CURRENT - I FT (NORMALIZED)

20 NORMALIZED TO:
PWin ≥ 100 µs
1.2

15
1.1

1.0 10

0.9
5

0.8

0
0.7 1 2 5 10 20 50 100
NORMALIZED TO T A = 25∞C
LED TRIGGER WIDTH - PWin (µs)
0.6
-40 -20 0 20 40 60 80 100

AMBIENT TEMPERATURE - TA (oC)

Fig. 6 Leakage Current, IDRM vs. Temperature

10000
Fig. 5 dv/dt vs. Temperature
12

1000
STATIC dv/dt
10
IDRM, LEAKAGE CURRENT (nA)

CIRCUIT IN FIGURE 5
STATIC - dv/dt (V/µs)

8
100

4 10

0
25 30 40 50 60 70 80 90 100

Ambient Temperature - TA (oC)

0.1
-40 -20 0 20 40 60 80 100

TA, AMBIENT TEMPERATURE ( oC)

© 2005 Fairchild Semiconductor Corporation Page 4 of 10 6/15/05

 6-PIN DIP RANDOM-PHASE
OPTOISOLATORS TRIAC DRIVER OUTPUT
(250/400 VOLT PEAK)

MOC3010M MOC3011M MOC3012M MOC3020M MOC3021M MOC3022M MOC3023M

1. The mercury wetted relay provides a high speed repeated

400V (MOC302X)
pulse to the D.U.T.
250V (MOC301X)
Vdc RTEST 2. 100x scope probes are used, to allow high speeds and
R = 10 kΩ
voltages.
CTEST 3. The worst-case condition for static dv/dt is established by
PULSE
INPUT triggering the D.U.T. with a normal LED input current, then
MERCURY
WETTED X100 removing the current. The variable RTEST allows the dv/dt
RELAY SCOPE
D.U.T. PROBE to be gradually increased until the D.U.T. continues to
trigger in response to the applied voltage pulse, even
after the LED current has been removed. The dv/dt is
then decreased until the D.U.T. stops triggering. τRC is
measured at this point and recorded.

Vmax = 400 V (MOC302X)

APPLIED VOLTAGE = 250 V (MOC301X)
WAVEFORM 252 V (MOC302X)
158 V (MOC301X)
0.63 Vmax 252
dv/dt = τRC = τ (MOC302X)
0 VOLTS RC
τRC
158
= τ (MOC301X)
RC
Figure 5. Static dv/dt Test Circuit

Note: This optoisolator should not be used to drive a load directly.

It is intended to be a trigger device only.

RL

Rin 1 6 180
VCC 120 V
60 Hz
2 MOC3010M 5
MOC3011M
MOC3012M
3 4

Figure 6. Resistive Load

ZL

Rin 1 6 180 2.4k

VCC
120 V
2 MOC3010M 5 60 Hz
MOC3011M 0.1 µF C1
MOC3012M
3 4

Figure 7. Inductive Load with Sensitive Gate Triac (IGT ≤ 15 mA)

© 2005 Fairchild Semiconductor Corporation Page 5 of 10 6/15/05

 6-PIN DIP RANDOM-PHASE
OPTOISOLATORS TRIAC DRIVER OUTPUT
(250/400 VOLT PEAK)

MOC3010M MOC3011M MOC3012M MOC3020M MOC3021M MOC3022M MOC3023M

ZL

Rin 1 6 180 1.2 k

VCC
120 V
2 MOC3010M 5 60 Hz
MOC3011M 0.2 µF C1
MOC3012M
3 4

Figure 8. Inductive Load with Sensitive Gate Triac (IGT ≤ 15 mA)

Rin 1 6 360 470

VCC HOT
MOC3020M
2 MOC3021M 5
0.05 µF 39
MOC3022M 240
MOC3023M VAC
3 4
0.01 µF

LOAD GROUND

In this circuit the “hot” side of the line is switched and the load connected to the cold or ground side.
The 39 ohm resistor and 0.01µF capacitor are for snubbing of the triac, and the 470 ohm resistor and
0.05 µF capacitor are for snubbing the coupler. These components may or may not be necessary
depending upon the particular and load used.

Figure 9. Typical Application Circuit

© 2005 Fairchild Semiconductor Corporation Page 6 of 10 6/15/05

 6-PIN DIP RANDOM-PHASE
OPTOISOLATORS TRIAC DRIVER OUTPUT
(250/400 VOLT PEAK)

MOC3010M MOC3011M MOC3012M MOC3020M MOC3021M MOC3022M MOC3023M

Package Dimensions (Through Hole) Package Dimensions (Surface Mount)

0.350 (8.89) 0.350 (8.89)

0.320 (8.13) 0.320 (8.13)

0.390 (9.90)
0.332 (8.43)
0.260 (6.60) 0.260 (6.60)
0.240 (6.10) 0.240 (6.10)

0.070 (1.77) 0.070 (1.77)

0.040 (1.02) 0.040 (1.02) 0.320 (8.13)
0.014 (0.36) 0.320 (8.13) 0.014 (0.36)
0.010 (0.25) 0.010 (0.25)

0.200 (5.08)
0.115 (2.93) 0.200 (5.08) 0.012 (0.30)
0.115 (2.93) 0.008 (0.20)

0.100 (2.54)
0.015 (0.38) 0.025 (0.63)
0.020 (0.51)
0.020 (0.50) 15° 0.100 [2.54]
0.100 (2.54) 0.035 (0.88)
0.016 (0.41) 0.020 (0.50)
0.012 (0.30) 0.012 (0.30)
0.016 (0.41)

Package Dimensions (0.4” Lead Spacing) Recommended Pad Layout for

0.350 (8.89)
Surface Mount Leadform
0.320 (8.13)

0.070 (1.78)
0.260 (6.60)
0.240 (6.10)

0.060 (1.52)

0.070 (1.77)
0.040 (1.02)
0.014 (0.36)
0.010 (0.25)
0.425 (10.79) 0.100 (2.54)

0.200 (5.08)
0.305 (7.75) 0.030 (0.76)
0.115 (2.93)

0.100 (2.54)
0.015 (0.38)

0.100 [2.54] 0.012 (0.30)

0.020 (0.50) 0.008 (0.21)
0.016 (0.41)
0.425 (10.80)
0.400 (10.16)

NOTE
All dimensions are in inches (millimeters)

© 2005 Fairchild Semiconductor Corporation Page 7 of 10 6/15/05

 6-PIN DIP RANDOM-PHASE
OPTOISOLATORS TRIAC DRIVER OUTPUT
(250/400 VOLT PEAK)

MOC3010M MOC3011M MOC3012M MOC3020M MOC3021M MOC3022M MOC3023M

ORDERING INFORMATION

Option Order Entry Identifier Description

S S Surface Mount Lead Bend
SR2 SR2 Surface Mount; Tape and reel
T T 0.4" Lead Spacing
V V VDE 0884
TV TV VDE 0884, 0.4" Lead Spacing
SV SV VDE 0884, Surface Mount
SR2V SR2V VDE 0884, Surface Mount, Tape & Reel

MARKING INFORMATION

MOC3010 2

6
V X YY Q

3 4 5

Definitions
1 Fairchild logo
2 Device number
VDE mark (Note: Only appears on parts ordered with VDE
3
option – See order entry table)
4 One digit year code, e.g., ‘3’
5 Two digit work week ranging from ‘01’ to ‘53’
6 Assembly package code
*Note – Parts that do not have the ‘V’ option (see definition 3 above) that are marked with
date code ‘325’ or earlier are marked in portrait format.

© 2005 Fairchild Semiconductor Corporation Page 8 of 10 6/15/05

 6-PIN DIP RANDOM-PHASE
OPTOISOLATORS TRIAC DRIVER OUTPUT
(250/400 VOLT PEAK)

MOC3010M MOC3011M MOC3012M MOC3020M MOC3021M MOC3022M MOC3023M

Carrier Tape Specifications

12.0 ± 0.1
4.5 ± 0.20
2.0 ± 0.05 Ø1.5 MIN
0.30 ± 0.05 4.0 ± 0.1
1.75 ± 0.10

11.5 ± 1.0
21.0 ± 0.1 24.0 ± 0.3
9.1 ± 0.20

0.1 MAX 10.1 ± 0.20 Ø1.5 ± 0.1/-0

User Direction of Feed

NOTE
All dimensions are in inches (millimeters)

Reflow Profile (White Package, -M Suffix)

300
260°C
280
260
>245°C = 42 Sec
240
220
200
180
Time above
160 183°C = 90 Sec
°C
140
120
100 1.822°C/Sec Ramp up rate
80
60
40
20 33 Sec

0
0 60 120 180 270 360
Time (s)

© 2005 Fairchild Semiconductor Corporation Page 9 of 10 6/15/05

 6-PIN DIP RANDOM-PHASE
OPTOISOLATORS TRIAC DRIVER OUTPUT
(250/400 VOLT PEAK)

MOC3010M MOC3011M MOC3012M MOC3020M MOC3021M MOC3022M MOC3023M

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the body, or device or system whose failure to perform can be
(b) support or sustain life, and (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.

© 2005 Fairchild Semiconductor Corporation Page 10 of 10 6/15/05