CS2100 Computer Organisation
Semester 1 2019/2020
Week of 16th September 2019
Tutorial 4: MIPS Encoding & Datapath
1. [Instruction Encoding] You accidentally spilled coffee on your best friend’s MIPS assembly
code printout. Fortunately, there are enough hints for you to reconstruct the code. Fill in the
missing lines (shaded cells) below to save your friendship.
Instruction
MIPS Code
Encoding
# $s1 is the result, $t0 stores a non-negative number
addi $s1, $zero, 0 #Inst. address is 0x00400028
0x00084042 loop: srl $t0, $t0, 1
0x11000002
0x22310001
j loop
exit:
b. Give a simple mathematic expression for the relationship between $s1 and $t0 as
calculated in the code.
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2. [Datapth ‐ AY1314S2 Term Test] Mr. De Blunder made a huge mistake while making his own
non‐pipelined MIPS processor. He accidentally swapped the two input ports for the RegDst
multiplexer:
Correct Wrong!
Unfortunately, the control unit still generate the signal using the original design! For each of
the following instructions, give:
i. One actual instance where the incorrect processor still gives the right execution
result.
ii. One actual instance where the incorrect processor gives the wrong execution result.
If there is no suitable answer, you can just indicate “No Answer”.
(a) add (Addition)
(b) lw (Load Word)
(c) beq (branch‐if‐equal), provide the branch offset as immediate value.
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Questions 3 and 4 refer to the complete datapath and control design covered in lectures #10. For
your convenience, the complete diagram from Lecture #10 is also included at the end of this
tutorial.
3. Let us perform a complete trace to understand the working of the complete datapath and
control implementation. Given the following three hexadecimal representations of MIPS
instructions:
i. 0x8df80000: lw $24, 0($15)
ii. 0x1023000C: beq $1, $3, 12
iii. 0x0285c822: sub $25, $20, $5
For each instruction encoding, do the following:
a. Fill in the tables below. The first table concerns with the various data (information) at
each of the datapath elements, while the second table records the control signals
generated. Use the notation $8 to represent register number 8; [$8] to represent the
content of register number 8; and Mem(X) to represent the memory data at address X.
Registers File ALU Data Memory
RR1 RR2 WR WD Opr1 Opr2 Address Write Data
[Wr = Write; Rd = Read; M = Mem; R = Reg]
RegDst RegWr ALUSrc MRd MWr MToR Brch ALUop ALUctrl
b. Indicate the value of the PC after the instruction is executed.
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4. With the complete datapath and control design, it is now possible to estimate the latency
(time needed for a task) for the various type of instructions. Given below are the resource
latencies of the various hardware components (ps = picoseconds = 10‐12 second):
Left‐shift/
Inst‐ Data‐ Control/
Adder MUX ALU Reg‐File Sign‐Extend/
Mem Mem ALUControl
AND
400ps 100ps 30ps 120ps 200ps 350ps 100ps 20ps
Give the estimated latencies for the following MIPS instructions:
(a) “SUB” instruction (e.g. sub $25, $20, $5)
(b) “LW” instruction (e.g. lw $24, 0($15))
(c) “BEQ” instruction (e.g. beq $1, $3, 12)
What do you think the cycle time should be for this particular processor implementation if
we assume the processor takes 1 cycle to execute any instruction?
Hint: First, you need to find out the critical path of an instruction, i.e. the path that takes the
longest time to complete. Note that there could be several parallel paths that work more or
less simultaneously.
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