Brain Machine Interface : Bioelectronics

Based on 3D Chip Stacking

Mohamad Sawan, Professor

Polytechnique, University of Montreal

PolystIm
neurotechnologies
[Link]

RESMIQ D43D’09, MINATEC, Grenoble

Regroupement Stratégique
en Microsystèmes du Québec 18 June 2009
[Link] [Link]
 Brain Machine Interface : Bioelectronics
Based on 3D Chip Stacking
-- Research and Applications --

 Neuroscience
 High accuracy investigation tools are needed
to study neural activity underlying cognitive
functions and pathologies.

 Neural Prosthetics
 Intracortical stimulation for vision recovery
 Neuro-motor prosthesis: paralysis, physical
impairments.
 Mind driven rehabilitation systems.

Page 2
 Sensing and subsequent treatment
-- Neurons, regions, and neural coding --
A. Sensory map B. Motor map

Coding
Intents
t
Sensations
t

Kandel et al., Principles of

neural science, 4ed

Primary Sensory
and motor cortex

Primary visual
Page 3
cortex
 Medical Microsystems for the Recovery of Vital Neural Functions
-- Main projects in our Polystim Laboratory --
I. Sensors and sensor network (e-Health)
• Sensors (pressure, volume, ENG, etc..) design and implementation

II. Vision for blinds

• Modeling & devices : Recording, monitoring and electrical stimulation

III. Bladder control

• Recuperate bladder functions : Sensing and electrical stimulation

IV. Respiration and gastric functions

• Catheters and signal processing

V. Optic and Ultrasound based medical devices

• Non-invasive diagnostic tools

VI. Laboratory-on-chip
• Diagnostic tools (neurotransmitter detection) and drug delivery.
Page 4
 Smart medical devices
-- Typical topology --

External Test
controller Stimuli
Receiver stimuli generator
Modulator
AC/DC Main
Demodu- Supply Controller
Current
lator sources

Data Back Measure MUX

processing telemetry &
digitize DeMUX
Skin Electrodes
Page 5
 Brain Machine Interface : Bioelectronics Based on 3D
Chip Stacking
-- Outline --
Introduction
I. Parallel sensing from the cortex
• Multi-channel multi-chip neural sensors
• Microelectrodes arrays & Integration/assembly
II. Microstimulation and Monitoring (treatment example)
• Intracortical visual implant
III. Efficient energy delivery and bidirectional data transfer
IV. Other project
• Lab-on-chip - based devices for better diagnostics
V. Research team, labs & facilities (Polystim & ReSMiQ)
Summary
 Parallel recording from the cortex
-- Multichannel Implantable neural sensors --

 Vertical integration of several ASICs

implementing different processing layers
 Post-processing of the array base with
photolithography and wet etching
 Cr-Au layer for contacts and metal
paths. Ch1

Page 7
 Parallel recording from the cortex (Cont’d)
-- Design challenges and bottlenecks --
 Data transmission bandwidth through tissues
 Present low-power telemetry allows around 2 Mb/s
 Energy transfer through tissues
 Thermal effects start to appear near 50 mW/cm2
 Size of implants
 Very small leaving tissues untouched at implantation.

 Design challenges are multidimensional

 Power consumption, frequency band allocations and standards,
testability and fault detection, SNR (noise considerations), etc.

Page 8
 Parallel recording from the cortex (Cont’d)
-- Design challenges : Noise considerations --
Raw neural signal

Time (s)
Voltage (µV)

Needs to measure very low-voltages.

Time (s)
Very Sensitive to Noise !
Action potentials

Page 9
 Multi-channel neural recording interface
-- Mounted ASICs: Mixed-signal front-end --

Micro-
electrodes

Digital readout
array

LN bioamplifier & dc Mixed-signal front-end

suppression SA
ADC

Conditioning: Amplification & Filtering Digitization: 8 bits, 30 ksps/Ch.

Consumption : < 12 μW Consumption : 7.4 μW
Page 10
 Digital ASIC
-- On-chip AP detection and buffering --
 Absolute value detector and on-chip SRAM

Serial
bus

 On-line AP detection & buffering

(bandwidth reduction Strategy = up
to 48 times):
 Absolute value detector
 On-chip SRAM FIFOs and memory buffer
Page 11
 Multi-chip integration
-- Design of microelectrodes array --
Medical grade
stainless-steel

2 mm Electro-
polishing

Grinding of
the base
and
electrodes
insulation
Epoxy base
building
Page 12
 Multi-chip integration (Cont’d)
-- Chip stacking and bonding --
 Conductive traces
are developed on
the back side
 Contacts are
rerouted in any
configuration
 Wedge / ball
bonders are used
for connecting
ASICs

Page 13
 Measured performances
-- Mixed-Signal ASIC (CMOS 0.18 µm)--
Microphotograph of the 16-channel chip Summary of characteristics
C lo c k a n d c o n tro l Mid-band gain 72 dB
s ig n a ls g e n e ra to r
T e s tin g a n a lo g
m u ltip le x e r
Bandwidth 100 Hz – 9.2 kHz
D ig ita l m u ltip le x e rs 1 m ix e d -

B ia s c irc u its
s ig n a l Input-ref. noise 5.4 μVrms
ch an n el

Sampling rate 30 kSps/ch

4 x 4 c h a n n e ls
F iltesr,e n
ams oprlifie r,
Resolution 8 bits
M u ltip le x in g ,
b ia s a n d te s t ADC B io a m p lifie r
c irc u its INL, DNL < ½ LSB
ENOB 7 bits
Power consump. 680 μW
32 kHz 64 kHz
-124 dB Die size 2.304 mm2
96 kHz
( 0.25 x 0.39 mm2 /ch.)

 Inter-channel cross-talk < -57 dB

between adjacent channels (< -67
dB between opposite sides.
Page 14
 Measured performances (Cont’d)
-- Low-power low-noise Bioamplifier --
Summary of bioamplifer
characteristics
Anticipated Measured
Parameters
value value
Gain 52 dB V 51.5 dB V
Bandwidth 10 kHz 9.6 kHz
Input refer- 5.6 µ Vrms 5.0 µ Vrms
red noise
Supply 1.8 V
voltage
Technology CMOS 0.18 µm
Area size 260 µm x 190 µm

• GOSSELIN, SAWAN, CHAPMAN,“A Low-Power Integrated

Bioamplifier With a New DC Rejection Scheme”, IEEE Trans. on
Biomedical Circuits & Systems, Vol. 1, No. 3, Sept. 2007, pp. 184-192.

Page 15
 Measured performances (Cont’d)
-- Digital ASIC --
Summary of characteristics
Input FIFO depth 16 bytes per ch.
Output memory size 64 bytes per ch.
Total on-chip SRAM 1.25 kB (69% of
chip area)
Neural data rate 5.1 to 51 kbits per
with BW reduction channel
Ref. clock freq. 16 MHz
Power consump. 1.53 mW
(96.5 μW/ch)
Die size 1.856 mm2
Microphotograph of the digital integrated Process CMOS 0.18 μm
circuit

Page 16
 In vivo validation (Acute exp.)
-- Performance of the Bioamplifier (cont’d) --
 In vivo neural recording with rats
 Anesthetised animal
 Recording from 16 sites in the
primary visual cortex

In vivo recording in the visual cortex of a rat

Dept. of Psychology, Concordia and Montreal Universities, Montreal

Page 17
 Brain Machine Interface : Bioelectronics Based on 3D
Chip Stacking
-- Outline --
Introduction
I. Parallel sensing from the cortex
• Multi-channel, multi-chip neural sensors
• Microelectrodes arrays & Integration/assembly
II. Microstimulation and Monitoring (treatment example)
• Intracortical visual implant
III. Efficient energy delivery and bidirectional data transfer
IV. Other project
• Lab-on-chip - based devices for better diagnostics
V. Research team, labs & facilities (Polystim & ReSMiQ)
Summary
 The visual intracortical stimulator
-- Implementation results --
 Stimulation Module (4x4)
 CMOS 0.18 µm, ~60 000 Gates Downlink

 Downlink
 > 1 Mbps @ 13.56 MHz, D = 67%

 Uplink : 200 kb/s

 Power: <1mW/SM @ 1MHz
 > 100 mW load; P (err) < 10-6

DACs Monitoring
TEST
structures BIAS

MONITORING
R2R AMP

ELECTRODES
CTRL CONN / CTRL

Page 19
 Brain Machine Interface : Bioelectronics Based on 3D
Chip Stacking
-- Outline --
Introduction
I. Parallel sensing from the cortex
• Multi-channel, multi-chip neural sensors
• Microelectrodes arrays & Integration/assembly
II. Microstimulation and Monitoring (treatment example)
• Intracortical visual implant
III. Efficient energy delivery and bidirectional data transfer
IV. Other project
• Lab-on-chip - based devices for better diagnostics
V. Research team, labs & facilities (Polystim & ReSMiQ)
Summary
 Wireless inductive link
-- Power transfer efficiency --
Inductive link Rectifier
C1 R2 V rec
Voltage V DC
M
regulator
R1 * *
Vs ~
L1 C2 C3 Linear LOAD
L2
regulator

1
k 2V 2
C2
η = 2 DC

total
1
R 1C 1 P load + k 2 C 2 (V rec + 2V diode ) V
2 DC

η = ηrflink η rectifier η regulator ~ 12 %

total
Page 21
 Power transfer
-- Efficiency & safety --
External Controller Implant
C1 Skin
Data Rectifier
PA
Modulator
Vdd L2 Shunt
regulator To/From
L1 C2 Other
Battery Switching
Regulator parts
Load
Shift
Key Encoder
ASK Demodulator / (LSK)
DAC/Decoder
ASK/PSK Demodulator

Page 22
 Wireless dedicated links
-- The external interface --
Switching power amplifier (AP)
Power link
&
bi-
User Interface

Modulator Demodulator
directional
data
transfer
Frequency Control unit
generator - Power supply management by
- PA calibration external
- Inductive link coupling inductor
Power - Resonance frequency (antenna)
source - Extensive data processing

Page 23
 Wireless dedicated links
-- The internal interface --

Rectifier LDO Reg 1 VDD1

Switched
Capacitor LDO Reg 2 VDD2
Shunt
regulator DC/DC
Off chip inductor

LDO Reg n VDDn

Load
Shift

contacts
Key M

Tissues
Encoder ADC U Analog
(LSK) X Front-
Ends
(1..n)

ASK/PSK
Controller/
Demodulator
Stimulator
Start-up Protection Clock Generator
Circuit Circuit Circuit
Page 24
 RF LINK to Transfer Data
-- BPSK demodulation --
Gilbert multiplier
Arm I branch
LP Filter
m(t) cos(q1-q2) Data Requirements: 1) Fully integrated,
2 sin(w1t+q2)
Out 2) Low power consumption, 3) Fully
Data In VCO
Low Pass
differential
Filter
m(t) sin(w1t+q1)
m(t) = 1 or –1
Phase m(t) sin 2(q1-q2) Gilbert
Shifter 90
2 multiplier
2 cos (w1t+q2)
Arm m(t) sin(q1-q2)
LP Filter
Q branch
Gilbert multiplier Arm Filter I branch
Dout
Data in Clk
• Hard-limited Costas loop circuit Quadrature Loop Chopper
• Coherent : recover carrier / data signal VCO Filter multiplier
generator
in the same loop
Receiver Arm Filter
coil
Q branch

Digital domain Analog domain

Page 25
 Parallel recording from the cortex (Cont’d)
-- Results : High data rate wireless link --
QPSK LPF
Data Out A
sin(w1t +q2)
Input
V d(t) -
Signal
VCO LPF BPSK QPSK
Vs(t)
+
90 -
CMOS CMOS
Data Out B
Phase Shifter 0.18μm 0.18μm
cos(w1t +q2)
13.56 13.56
LPF MHz MHz
1.6 Mbps* 4Mbps*
1.2 Mbps** 2.2 Mbps**
8Mbps***
0.61 mW** 0.76 mW
540 um at 4Mbps

*Postlayout
Voltage Controlled Oscillator Comparator **Measured
***Matlab
BPSK QPSK
Page 26
 Testing Challenges
-- Engineering and Medical Validations --
 Functional tests (electrical, mechanical, ..)
 Circuits, Package, Heat, Reliability, Toxicity, ….

 Self-test and fault detection after implantation

 Noise considerations and grounding (multichannel aspect)
 Analog/digital blocks, Scan and BIST, overhead resources power/area

 In vivo measurement and validation

 Humidity, temperature, Ion concentration, pH, interface to tissues,…
 Experiments in animals and humans: spontaneous or evoked activity

 Ethics, experimental protocol and approvals.

Page 27
 Polystim neurotechnologies Laboratory
-- http: //[Link] --
 Founded in 1994
 Completed Degrees
 70 M.R. & 17 Ph.D.
 Currently supervised students
 12 M.R. (30% with scholarships), and 8 Ph.D. (50% with scholarships).
 Invited researchers, postdoctoral and research assistants
 1 Technician & 1 Secretary
 Collaborators (Colleagues from)
 Several medical institutes and research centers in hospitals
 Sciences and applied sciences programs
 Support:
 NSERC, CIHR, FQRNT, CMC µsystems, CRC - DMI, FCI-DMI
 Industry:
 Victhom HB, INLB, DALSA Semiconductor, Scanview, Biophage, etc.
Page 28
 Design, tests, assembly, packaging and in vitro
validation facilities
-- [Link] --

CFI Room A345

Page 29
 Un courant porteur pour le Québec

Université de Montréal
McGill University
[Link]
Université du Québec à Montréal Mohamad Sawan, Director
École Polytechnique de Montréal June 2009
École de technologie supérieure
Concordia University
Université Laval
Université du Québec à Chicoutimi
Université du Québec à Trois-Rivières
 Un courant porteur pour le Québec

M o m.
D e e d ic lec s
v ic a l Te ptic reles
es o Wi
Specification, Algorithms, &
Design architectures,
optimization synthesis &
In d u s tr & simulation r ity ,
Controial
co-design Secu imedia
l Design methods, Fabrication, M u lt
implementation, integration, R F ID
modeling Prototyping &
validation
n an o - SoC , A n
Micro & tronics

nf.
Test, diagnostic, Emerging signal Plaalog & M
elec tforms ixed-

Co
verification & Technologies &
characterization standards

S
CA
i d ic, T
R F e ch n

EW
c
o flu , et Signal C o IC , o l
ic r p tic Processing n v M E o g ie

.N
: M o er M s
to S ,

Int
o C rs, D
L
A c S e n s o rks

e tc a ta

V id io io n
to r ,
tu a o r s

a u d p lic t
.
s

Ap

eo
tw

s
Ne

&
 Summary
 Multi-chip multi-channel 3D neural sensing from the cortex
 Low-power, chip area, vertical integration and packaging
 Test challenges: Noise, design of in vivo experiments

 Reliability and safety are important facts.

 Typical SMD involve multi-disciplinary team : engineers, physicians,

surgeons, health care professionals, etc;
 Challenges at the level of intracortical microsystems are all important
(power issues, assembly, microelectrodes);
 Monitoring and recording permit to understand the accurate
functions at the CNS;
 Technology progresses will allow the creation of many more reliable
implantable devices;
 Diagnostic tools based on LoC (neurotransmitters detection) and
drug delivery.
 Brain Machine Interface : Bioelectronics Based on 3D Chip
Stacking
Acknowledgments
-- http: //[Link] --
T ha nk You

 Master & Ph.D. students

 Collaborators: Colleagues from different research centers
 Support: NSERC, CIHR, FQRNT, CMC µsystems, CRC-DMI, FCI-DMI
 Industry: Victhom, INLB, DALSA, Scanview, Clarovita.