Lecture # 6

PROGRAMMABLE INTERVAL TIMER 8254

The Intel 8254 is a counter/timer device which provides three independent 16-bit counters, each
capable of handling clock inputs up to 10 MHz, all modes are software programmable. The 8254
is a superset of the 8253 and is the timer used in the personal computer (PC). The 8254 uses
HMOS technology and comes in a 24-pin plastic package

The 8254 is a programmable interval timer/counter designed for use with Intel microcomputer
systems. It is a general purpose, multi-timing element that can be treated as an array of I/O ports
in the system software. The 8254 solves one of the most common problems in any
microcomputer system, the generation of accurate time delays under software control. Instead of
setting up timing loops in software, the programmer configures the 8254 to match his
requirements and programs one of the counters for the desired delay. After the desired delay, the
8254 will interrupt the CPU. This device is useful wherever the microprocessor must control
real-time events. Some examples of usage include real-time clock, events counter, and for motor
speed and direction control.

The timer appears in the personal computer decoded at ports 40H–43H to do the following:

1. Generate a basic timer interrupt that occurs at approximately 18.2 Hz.

2. Cause the DRAM memory system to be refreshed.
3. Provide a timing source to the internal speaker and other devices.

8254 Functional Description

Figure 1 shows the pin-out of the 8254, which is a higher-speed version of the 8253. Each timer
contains a CLK input, a gate input, and an output (OUT) connection. The CLK input provides
the basic operating frequency to the timer, the gate pin controls the timer in some modes, and the
OUT pin is where we obtain the output of the timer. The signals that connect to the
microprocessor are the data bus pins (D7–D0), and address inputs A1 and A0. The address inputs
are present to select any of the four internal registers used for programming, reading, or writing
to a counter.
 Figure 1: 8254 programmable interval timer. (a) Internal structure and (b) pin-out

Pin Definitions
Accessing the 8254 registers
8254 System Interface

The 8254 is a component of the Intel Microcomputer Systems and interfaces in the same manner
as all other peripherals of the family. It is treated by the system's software as an array of
peripheral I/O ports; three are counters and the fourth is a control register for MODE
programming. Basically, the select inputs A0, A1 connect to the A0, A1 address bus signals of
the CPU. The CS can be derived directly from the address bus using a linear select method. Or it
can be connected to the output of a decoder. Figure 2 shows 8254 System Interface

Figure 2: 8254 System Interface

Programming the control word of 8254

Each counter is individually programmed by writing a control word, followed by the initial
count. Figure 3 lists the program control word structure of the 8254. The control word allows the
programmer to select the counter, mode of operation, and type of operation (read/write). The
control word also selects either a binary or BCD count. Each counter may be programmed with a
count of 1 to FFFFH. A count of 0 is equal to FFFFH+l (65,536) or 10,000 in BCD. The
minimum count of 1 applies to all modes of operation except modes 2 and 3, which have a
minimum count of 2. Timer 0 is used in the personal computer with a divide-by count of 64K
(FFFFH) to generate the 18.2 Hz (18.196 Hz) interrupt clock tick. Timer 0 has a clock input
frequency of 4.77 MHz + 4 or 1.1925 MHz
 Figure 3: The control word for the 8254-2 timer

The control word uses the BCD bit to select a BCD count (BCD = 1) or a binary count (BCD =
0). The M2, M1, and M0 bits select one of the six different modes of operation (000–101) for the
counter. The RW1 and RW0 bits determine how the data are read from or written to the counter.
The SC1 and SC0 bits select a counter or the special read-back mode of operation. Each counter
has a program control word used to select the way the counter operates. If two bytes are
programmed into a counter, then the first byte (LSB) will stop the count, and the second byte
(MSB) will start the counter with the new count.

Programming the 8254

Counters are programmed by writing a Control Word and then an initial count. The Control
Words are written into the Control Word Register, which is selected when A1, A0 = 11. The
Control Word itself specifies which Counter is being programmed. By contrast, initial counts are
written into the Counters, not the Control Word Register. The A1, A0 inputs are used to select
the Counter to be written into. The format of the initial count is determined by the Control Word
used.

 Write Operations

The programming procedure for the 8254 is very flexible. Only two conventions need to be
remembered:
1) For each Counter, the Control Word must be written before the initial count is written.
2) The initial count must follow the count format specified in the Control Word (least significant
byte only, most significant byte only, or least significant byte and then most significant byte).
A new initial count may be written to a Counter at any time without affecting the Counter's
programmed Mode in any way. Counting will be affected as described in the Mode definitions.
The new count must follow the programmed count format. If a Counter is programmed to
read/write two-byte counts, the following precaution applies: A program must not transfer
control between writing the first and second byte to another routine which also writes into that
same Counter. Otherwise, the Counter will be loaded with an incorrect count.

 Read Operations

It is often desirable to read the value of a Counter without disturbing the count in progress. This
is easily done in the 8254.

There are three possible methods for reading the counters: a simple read operation, the Counter
Latch Command, and the Read-Back Command. Each is explained below. The first method is to
perform a simple read operation. To read the Counter, which is selected with the A1, A0 inputs,
the CLK input of the selected Counter must be inhibited by using either the GATE input or
external logic. Otherwise, the count may be in the process of changing when it is read, giving an
undefined result

 Counter Latch Command

The second method uses the ``Counter Latch Command''. Like a Control Word, this command is
written to the Control Word Register, which is selected when A1, A0 e 11. Also like a Control
Word, the SC0, SC1 bits select one of the three Counters, but two other bits, D5 and D4,
distinguish this command from a Control Word. The selected Counter's output latch (OL) latches
the count at the time the Counter Latch Command is received. This count is held in the latch
until it is read by the CPU (or until the Counter is reprogrammed). The count is then unlatched
automatically and the OL returns to ``following'' the counting element (CE). This allows reading
the contents of the Counters ``on the fly'' without affecting counting in progress. Multiple
Counter Latch Commands may be used to latch more than one Counter. Each latched Counter's
OL holds its count until it is read. Counter Latch Commands do not affect the programmed Mode
of the Counter in any way. The command is written into the Control Word Register and has the
format shown in Figure 4.
 Figure 4: Counter Latching Command Format

 Read-Back Command

The third method uses the Read-Back Command. This command allows the user to check the
count value, programmed Mode, and current states of the OUT pin and Null Count flag of the
selected counter(s). The read-back command may be used to latch multiple counter output
latches (OL) by setting the COUNT bit D5 = 0 and selecting the desired counter(s). This single
command is functionally equivalent to several counter latch commands, one for each counter
latched. Each counter's latched count is held until it is read (or the counter is reprogrammed).
The counter is automatically unlatched when read, but other counters remain latched until they
are read. If multiple count read-back commands are issued to the same counter without reading
the count, all but the first are ignored; i.e., the count which will be read is the count at the time
the first read-back command was issued. The read-back command may also be used to latch
status information of selected counter(s) by setting STATUS bit D4 = 0. Status must be latched
to be read; status of a counter is accessed by a read from that counter. The counter status format
shown in Figure 5.

Figure 5: Status Byte

Modes of Operation

Six modes (mode 0–mode 5) of operation are available to each of the 8254 counters. Figure 6
shows how each of these modes functions with the CLK input, the gate (G) control signal, and
OUT signal. A description of each mode follows:

Figure 6: The six modes of operation for the 8254-2 programmable interval timer. The G input
stops the count when 0 in modes 2, 3, and 4.

MODE 0: Allows the 8254 counter to be used as an event counter. In this mode, the output
becomes logic 0 when the control word is written and remains there until N plus the number of
programmed counts. For example, if a count of 5 is programmed, the output will remain a logic 0
for 6 counts beginning with N. Note that the gate (G) input must be a logic 1 to allow the counter
to count. If G becomes a logic 0 in the middle of the count, the counter will stop until G again
becomes a logic 1.

MODE 1: Causes the counter to function as a retriggerable, monostable multivibrator (one-shot).

In this mode the G input triggers the counter so that it develops a pulse at the OUT connection
that becomes logic 0 for the duration of the count. If the count is 10, then the OUT connection
goes low for 10 clocking periods when triggered. If the G input occurs within the duration of the
output pulse, the counter is again reloaded with the count and the OUT connection continues for
the total length of the count.

MODE 2: Allows the counter to generate a series of continuous pulses that are one clock pulse
wide. The separation between pulses is determined by the count. For example, for a count of 10,
the output is a logic 1 for nine clock periods and low for one clock period. This cycle is repeated
until the counter is programmed with a new count or until the G pin is placed at a logic 0 level.
The G input must be logic 1 for this mode to generate a continuous series of pulses.

MODE 3: Generates a continuous square wave at the OUT connection, provided that the G pin
is a logic 1. If the count is even, the output is high for one half of the count and low for one half
of the count. If the count is odd, the output is high for one clocking period longer than it is low.
For example, if the counter is programmed for a count of 5, the output is high for three clocks
and low for two clocks.

MODE 4: Allows the counter to produce a single pulse at the output. If the count is programmed
as a 10, the output is high for 10 clocking periods and low for one clocking period. The cycle
does not begin until the counter is loaded with its complete count. This mode operates as a
software triggered one shot. As with modes 2 and 3, this mode also uses the G input to enable the
counter. The G input must be a logic 1 for the counter to operate for these three modes.

MODE 5: A hardware triggered one-shot that functions as mode 4, except that it is started by a
trigger pulse on the G pin instead of by software. This mode is also similar to mode 1 because it
is retriggerable.

Example1: 8254 Control Word Register (CWR) include the binary format of (10010000)2 with
A1, A0=11. Specify the function of each part of 8245 timer interval.
Solution:

The CWR selects the following:

Counter: 2
Read / write: Load Least significant byte only
Mode: 0
Count type: Binary count
Example 2: Write code to set up three counters located at I/O address 40h as follows:
– Counter 0: Binary counter operating in mode 0 with a value of 1234h
– Counter 1: BCD counter operating in mode 2 with a value of 0100h
– Counter 2: Binary counter operating in mode 4 with a value of 1FFFh

Solution:
Mode word for counter 0 = 00 11 000 0 = 30h
Mode word for counter 1 = 01 11 010 1 = 75h
Mode word for counter 2 = 10 11 100 0 = B8h
MOV AL, 30H ; SET UP COUNTER 0 MODE
OUT 43H, AL
MOV AL, 75H ; SET UP COUNTER 1 MODE
OUT 43H, AL
MOV AL, 0B8H ; SET UP COUNTER 2 MODE
OUT 43H, AL
MOV AL, 34H ; LOAD COUNTER 0 by the vale 1234
OUT 40H, AL
MOV AL, 12H
OUT 40H, AL
MOV AL, 00H ; LOAD COUNTER 1 by the vale 0100
OUT 41H, AL
MOV AL, 01H
OUT 41H, AL
MOV AL, FFH ; LOAD COUNTER 2 by the vale 1FFF
OUT 42H, AL
MOV AL, 1FH
OUT 42H, AL

• Counter 0: Binary counter operating in mode 0 with a value of 1234h

– Output goes high after 1234h (4660d) clock cycles

• Counter 1: BCD counter operating in mode 2 with a value of 0100h

– Output pulses low (for one clock cycle) every 0100h (translated to BCD is 4 decimal) clock
cycles

• Counter 2: Binary counter operating in mode 4 with a value of 1FFFh

– One shot produced after a delay of 1FFFh (=8191d) cycles

Example 3: read the contents of counter 2 on the fly. The count is to be loaded into the
AX register. Assume that the 8254 is located at I/O address 40h.
Solution:
First, latch the contents of counter 2, and then its value can be read from a temporary storage
register.
MOV AL, 10000000b ; Latch counter 2
OUT 43h, AL
IN AL, 42h ; Read the lower byte
MOV BL, AL ; Store it temporarily
IN AL, 42h
MOV AH, AL
MOV AL, BL ; Counter contents now
; resides in AX

Example 4: Identify the port address of control register and counter 2, then write a subroutine to
initial counter 2 in mode 0 with the count of (50000) decimal. The subroutine should also include
reading count on the fly.

Solution: Port Address when chip select is enabled with A7=1(Assuming A6 to A3 all zeros),
then the port address of Control Reg. = 83 and Counter 2 = 82
(Note: (5000)10 = ( 1388)16 )

Example 5: Generating a Waveform with the 8254 shown in Figure below, the 8254 connected to
function at I/O ports 0700H, 0702H, 0704H, and 0706H. The addresses are decoded by using a
PLD that also generates a write strobe signal for the 8254, which is connected to the low-order
data bus connections. The PLD also generates a wait signal for the microprocessor that causes
two wait states when the 8254 is accessed. The wait state generator connected to the
microprocessor actually controls the number of wait states inserted into the timing.
The following program generates a 100 KHz square-wave at OUT0 and a 200 KHz continuous
pulse at OUT1. Counter 0 uses mode 3 and counter 1 uses mode 2. The count programmed into
counter 0 is 80 and the count for counter 1 is 40. These counts generate the desired output
frequencies with an 8 MHz input clock.

DC Motor Speed and Direction Control

One application of the 8254 timer is as a motor speed controller for a DC motor. Figure 7 shows
the schematic diagram of the motor and its associated driver circuitry. It also illustrates the
interconnection of the 8254, a flip-flop, and the motor and its driver.

The operation of the motor driver circuitry is straightforward. If the Q output of the 74ALS112 is
a logic 1, the base Q2 is pulled up to +12 V through the base pull-up resistor, and the base of Q2
is open circuited. This means that Q1 is off and Q2 is on, with ground applied to the positive lead
of the motor. The bases of both Q3 and Q4 are pulled low to ground through the inverters. This
causes Q3 to conduct or turn on and Q4 to turn off, applying ground to the negative lead of the
motor. The logic 1 at the Q output of the flip-flop therefore connects +12 V to the positive lead
of the motor and ground to the negative lead. This connection causes the motor to spin in its
forward direction. If the state of the Q output of the flip-flop becomes a logic 0, then the
conditions of the transistors are reversed and +12 V is attached to the negative lead of the motor,
with ground attached to the positive lead. This causes the motor to spin in the reverse direction.
If the output of the flip-flop is alternated between a logic 1 and 0, the motor spins in either
direction at various speeds. If the duty cycle of the Q output is 50%, the motor will not spin at all
and exhibits some holding torque because current flows through it.
Figure 8 shows some timing diagrams and their effects on the speed and direction of the motor.
Notice how each counter generates pulses at different positions to vary the duty cycle at the Q
output of the flip flop. This output is also called pulse width modulation.
 Figure 7: Motor speed and direction control using the 8254 timer.

Figure 8: Timing for the motor speed and direction control circuit of Figure 11–40. (a) No rotation, (b) high-speed
rotation in the reverse direction, and (c) high-speed rotation in the forward direction

The following example lists a procedure that controls the speed and direction of the motor. The
speed is controlled by the value of AH when this procedure is called. Because we have an 8-bit
number to represent speed, a 50% duty cycle, for a stopped motor, is a count of 128. By
changing the value in AH when the procedure is called, we can adjust the motor speed. The
speed of the motor will increase in either direction by changing the number in AH when this
procedure is called. As the value in AH approaches 00H, the motor begins to increase its speed
in the reverse direction. As the value of AH approaches FFH, the motor increases its speed in the
forward direction.