RAM is a combin, ational Circuit sequential cireuit ? CF) Whatis the modulus of the cow states Q. @, Q,= 000. @3 4 @5 @é6 [1990: 5 Marks] Find the maximum clock frequency at which the counter in figure, can be operated. Assume that the propagation delay through each flip-flop and AND gate is 10 ns. Also assume that the setup time for the JK inputs of the flip-flops is negligible. [199: 34 For the initial state of 000, the function performed by the arrangement of the J-K flip-flops in figure is: ©) Shift register ® Mod-3 counter © Mod-6counter @ Mod-2 counter [19941 Marky 86 Consider the synchronous sequential = the figure. (6) Given that the initial S,, identify the set of reachable. Scanned with CamScannerjal state of P, Qas00, 1 (respectively). clock cycles the output state P, Q is ) 1,2 : @ 0,1 [2000 : 2 Marks} the following circuit with initial state The D flip-flops are positive edged red and have set up time 20 ns and hold Clock, r the following timing diagrams of X the clock period of C 2 40 nanosecond. [2001 :2 Marks] ae Q. = 0. The state of the circuit is hevalue 4Q, +2Q, +Qy 3.10 3.11 Which one of the following is the correct state sequence of the circuit @) 1,3, 4,6, 7, 5,2 © 1,2,7,3,5,6,4 © 1,253,764 @ 1,6,5,7,2.3,4 [2001:2 Marks] ‘The finite state machine described by the following state diagram with Aas starting state, where an are label.x/y and xstands for L-bit input and y stands for 2-bit output (a) Outputs the sum of the present and the previous bits of the input. (&) Outputs 01 whenever the input sequence contains 11. (© Outputs 00 whenever the input sequence contains 10. (@ None of the above [2002 :2 Marks} ‘A L-input, 2-output synchronous sequential circuit behaves as follows: Let 2,, m, denote the number of 0's and 1's respectively in initial k bits of the input (%, + my, = 1p. The circuit outputs 00 until one of the following conditions holds. 1. 2,—n,=2. In this case, the output at the k-th and all subsequency clock ticks is 10. 2. n,-2,=2. In this case, the output at the k-th and all subsequent clock ticks is 01. What in the minimum number of states required in the state transition graph of the above circuit? @si @7 2003: 2 Marks! Scanned with CamScanner2 a B15, nan spy atch made by ep ; HAND keten itboth Sane e eeeeUBtNg to thon it will rewult in eee ™ Q50,Q=1 Qa LQs1 (D Indoterminate states (20041 Marky Consider the partial im i i plementation of a 2-bi counter using T flip-flops following the ae 0-2-8-1-0, ns shown below: LsB cu ‘Tocomplete tho cireuit, the input X should be @ QY © Q+Q © QOQy @ QAeQ [2004 : 2 Marks} ‘Tho flowing dingram represents a finite state machine which takes input a binary number from the least significant bit, 10 on, 170 mw @ a Which one of the following is TRUE? (@ It computes 1’s complement of the input number @) Tt computes 2's complement of the input number (© It increments the input number @ It decrements the input number [2005 : 2 Marks} How many pulses are needed to change the contents of a 8-bit upcounter from 10101100 to 00100111 (rightmost bit is the LSB)? (@) 134 © 133 © i @ 123 [2005 : 1 Mark] Which of the following input sequences will always generate a 1 at the output z at the end of the third cycle? 3.17 318 Consider the following. edge triggered D FF. — circuit involving a postin pony Consider the following timing diagram. Lit 4 represent the logic level on the line A in theith clock period. Let A’ represent the complement of A. The ex! output sequence on ¥ over the clock perio* through 6 is (@ AQALAYAQA, (0) ApA,AY AS OA AA/AA, @ A, Ay’ aap . a [2005 :2 Mark Consider the following circuit Bye | Q| cx a ‘The Mip-flops are positive edge trisse™" Each state is designated as.a twobit = state Let the initial state be 00. The =** sequence is — Scanned with CamScanner[2005 : 2 Marks] 1 the circuit in the diagram. The @ represents Ex-OR. The D flip-flops are lized to zero (cleared). }— Data cK [2006 : 2 Marks] given a free running clock with a duty 50% and a digital waveform f which s only at the negative edge of the clock. one of the following circuits (using clocked 3.22, 3.23 3.24 terms of the current state $ and the input variables x and y is @ St= © St= Vy +Sx Q) St=Sxy Styx’ oy @ St=S'y+Sx’ [2006 : 2 Marks] ‘Which of the following input sequences for a cross- coupled R-S flip-flop realized with two NAND gates may lead to an oscillation? @ 11,00 (b) 01, 10 © 10,01 @ 00,11 [2007 : 1 Mark] What is the final value stored in the linear feedback shift register if the input is 101101? 101101 & XOR (@) 0110 © 1101 (b) 1011 @ mu [2007 : 2 Marks) ‘The control signal functions of 4-bit binary counter are given below (where X is “don't care”) D flip-flops) will delay the phase of fby 180°? Clear | Clock | Load | Count [ Function S 1 x x x Clear to 0 > pa o 1X [0 | 0 | Nochange 0 T 1 X _| Load input o T 0 1 Count next [2006 : 1 Mark] "4 state machine with the following state am the expression for the next state S* in ‘The counter is connected as follows ool “Assume that the counter and gate del lays ares” cs negligible. Ifthe counter starts at 0, then cy through the following sequence f (@) 0,3,4 00345 % (@) 0,1, 2 3:45 © 0,1,2.3,4 [2007:2 Marks] Scanned with CamScannera GATE Previous Years Solved Papers: [YJ a ~My, 25 Consider the fo realization by a i eo110 lowing state IK flip flop. oo. Common Data Q.8.29 & Q.3.30 Consider the following cireuit involyi is ng three) {Alip-flops used in a certain type of count Ny ter confine @) x®yand ¥Oy @ x®yandx@y © x@yand yoy @ x@yandxro@y [2008 : 2 Marks 826 Given the following state tabl Ie of an FSM with two states A and B, one input and. one output: Ste | Saie3| tspae States | shite | Output OF ee oon a oO 1 0 1 0 0 ryo lo |o fa: |] o eo | ell 529 Ifat some instance prior tothe occurrence ft ommimol |H | o lenel G clock edge, P, Q and R have a value 0, tanto o a : cle : respectively, what shall be the valueofPQH ats, RET bo balla the clock edge? : (a) 000 &) 001 If the initial state is A = 0, B= 0, what is the @ un lati minimum length of an input string which will Ort: apiars take the machine to the state A=0, B= 1 with output=1? 3.30 Ifall the flip-flops were reset to 0 at power on @3 4 whatis the total number of distinct outputs(state) O5 @6 represented by PQR generated by the counter” [2009:2 Marks} @3 b) 4 327 In the sequential cireuit shown below, if the Ce @6 no initial value of the output Q,Q, is 00, what are a the next four values of Q, 331 Let k=2", A circuit is built by giving the ofan n-bit binary counter as input to an 1 a a bit decoder. This circuit is equivalent toa (@ k-bitbinary up counter. al Lt ©) k-bit binary down counter. (© k-bitring counter. _ : @ bit Johnson counter. . @ 11,10,01,00 ©) 10,11,01,00 [2014 (Get-2): 1 Ma" © 1000,01,11 @ 11,10,00,01 [2010:2Marks] 3.32 328 The minimum number of D. flip-flops needed to design a mod-258 counter is @9o © 512 os @ 258 The above synchronous sequential A [20111 Marky built using JK flip-flops is initialize eI ~~ Scanned with CamScanner‘The state sequence for this circuit gclock cyclesis 010, 012 () 111, 110, 101 10,111 @ 100,011,001 [2014 (Set-3) : 2 Marks] 4bitJohnson counter with an initial ‘000. The counting sequence of this oteris 1,37, 15, 14, 12, 8,0 0,1,3,5, 79, 11, 13; 15,0 9, 6,6, 8 10, 12, 14,0 0,8, 12,14, 15,7, 3, 1,0 j [2015 (Set-1): 1 Mark] sitive edge-triggered D flip-flop is connected veitive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to “uththe J and K inputs of the JK flip-flop, while ‘Qoutput of the JK flip-flop is connected to input of the D flip-flop. Initially, the output sD flip-lop is set to logic one and the output e JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q utof the JK flip-flop when the flip-flops are fed to a free-running common clock? the flip-flops have non-zero propagation ) ot1o1to. @) 0100100. OLL01110.._@_011001100. : [2015 (Set-1): 2 Marks] nimum number of JK flip-flops required struct a synchronous counter with the sequence (0,0, 1, 1, 2,23, 3, 0, 0,--)8— ¢ [2015 (Set-2):1 Mark] mplement this counter is . [2016 (Set-1) :1 Mark] combination of 1’ and D flip-flops Frets shown below. The ‘output of the D flop is connected to the input of the T Hip- the output of the T'flip-flop is connected iput of the D flip-flop. ms 3.38 3.39 in |* Fip-Fop Clock. Initially, both Q, and Q, are set to 1 (before the 1* clock cycle). The outputs (@) Q, Qyafter the 3" cycle are 11 and after ‘the 4" cycle are 00 respectively. ©) Q, Qyafter the 3" cycle are 11 and after the 4" cycle are 01 respectively. © Q, Qatter the 3" cycle are 00 and after the 4 cycle are 11 respectively. @ Q, Qoafter the 3% cycle are 01 and after the 4® cycle are 01 respectively. [2017 (Set-1) :2 Marks] ‘The next state table of a 2-bit saturating up- counter is given below: @ | % | a | @ Cn oi | uo rfofa]a 1a ft Lt ‘The counter is built as a synchronous: sequential circuit using T flip-flops. The expressions for T, and T, are @ T=A% te © T=, qT © T=QtQ N=A+% @ T=9Q, = A+ [2017 (Set-2) :2 Marks] Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops. n—-|D QED Qt ow os __|_ a ‘The number of states in the state transition diagram ofthe circuit that have a transition back tothe: same state on some value of in’ [2018:1 Marks] Scanned with CamScanner