Simple IO using LPC 21 xx boards
2102 PINS ELO
PIN SEL l
Port as 0 IP YP Pins
IODIR Reg
Letting the
Pinsetting register Pinclearing register
If 1Il is provided H to PIN set Sets Bit
P INclear Clears Bit
NAP to
glow LEDs connected b w P1 lb P 1.23 of
register LEDs connected to each pin should be
1013112
turned ON OFF with time in between Repeatproce
delay
Using LPC2129 target board
So.LI Algorithm
Data moved to IODIR E 0028018 to set pins as
Olp pins L
Bit set to turn ON the LED is moved to Pin
Setting
Register CE0028014
Provide Delay
Bit Set to turn OFF to Pin ClearingRegisterG002801
Glow all pins from 1.16 l 23
Loop once from 1 16
again
Progream
pinsash O
IODIR EDU OX 0028018 iA.dd.ro
controlre.gtoSetIOSETEgUOXEO0280l4
Iopin setting register
IOCLR EBU Ox 002801C IOpin
clearing register
A DR H IODIR
DR 80 0 00170000
STR ro Cri
ADR r2 IOSET
ADR r3 IOCLR
Top MOU 14 0 00010000
UP STR 84 r2 i set 171.16 in PINSET r.e.gg
LDR r5 0 00 FEFFFF
BI SUBS rs.rs I
BNE Bl
STR r3 i clear 19.16
ry in PINCLR.o.ge
Mov r4 r4 LSL 1
CMP fly 0 01000000 I Compare with
BNE UP
B TOP
Modify by LED is connected to alternate pins
1.10 to Pl 28
starting from P display 1 at a time
with a m x delay Repeat sequence
Flash all LEDs connected to Pl 08 to Pl 27
Program
1013112 Ego ox C XXXX
10SET EGO OX CXXXX
IOCLR EGO OXE xxxx
ADR rt IO DIR
MOV ro 0 1 FF FF COO
STR ro Cri
30 29 28 272625 24 23 2221 201IS 1817 16 15 1413 12 11 10 g 8 7 65 43210
o O I l l l l l l l l l ll l l l l l l l 0000000000
ADR R2 10SET
ADR BilocLR
Top MOV RG 0 00000400
UP STR RG r2 i set pin 1.10
LDR 85 OXFFFFFFFF
Bl S UBS r5 rs I
3 u r
B NE T1
STR r4 3
MOV ke r4 GL 2
CMP 84 0 20000000
B NE OP
B TOP
Interface 32 bit controller and write a to
program
run 32 bit counter
ring
Modify the above to run 32 bit JohnsonCounter
2 2 2020
Thumb 16 bit
1
High code density
Only relative ins.tn can be conditionally executed
to r7 is fully accessible low registers
58 r 12 accessible with ADD MovandCHIPhigh registers
compare all data processing in.st that operate
on low register update conditional flags in CPSR
Compare inst.in is the only one that can update
CPSR in high registers
CPSR only indirect access SPSR no access
MSR MRS aren't applicable To movevalue into
any
CPSR SPSR the state must be changed fromThumb to
ARM state
Other branch instruction
Only conditionally executed branch in.SI 25613 to 25413
without conf 2048 B to 204GB
BL I 4 MB DC loaded with label
It can't be conditionally erecated
Eu Cps R nzcvq IFT sve
rI 0 00 I
82 0 00 1
SUB ro r l r2
C PS R IF T
nZcvq src
0 0 00000000
fu 2 CPSR nzcvqIFT Svc
RIO 0 80000000
MI OX 8000 0000
A DD r g r lo r Il
CPSR nzcvqIFT s.ve
9 0 00000000
EX 3 r2 0 00000002
f4 0 0000 0001
SL Arc
Best
POST 0 0000 0001
r4
r2 0 0000
0004
r2 is leftshifted by the oftimes as specif
in
r4
Shingle register LDR
STR
Thumb suppfts CDR STR
L DR Load word into
register from memory RE
32C
Mem
STR Dave word from register into memory
LDRB Rd Mems Adar
STR B Rd Mems Adder
LD RH Rd Mem16 Adder
STR H Rd Mem It Adder
LDRSB Load signed byte into register
LDRSH Il halfword 11
Eu Lg Pre
them32 0 90000000 0 00000007
Mem 32 0 90000004 0 00000002
Mem 32 0 90000008 0 00000003
TO 0 00000000
fl 0 90000000
rly 0 00000004
LDR ro CRI rly LDR ro Cri 4
Post ro 0 00000002
M 0 90000000
0 00000004
fly
1st insta depends on value of r4
2nd ins.tn uses fined
Same result
offset
Multiple Load Store Thumb versions only increment
after addressing modes
D MIA
STMIA Only low registers are
applicable
En S rt 0 00000001
12 0 0000 0002
r3 0 0000 0003
fly 0 00009000
STMIA rg Ert r2 b
Post Mem32 0 00009000 rt
Mem32 0 00009004 r2
Mem32 0 00009008 r3
them 326 0000good
Getafe SP is r 13 fined in thumbop t
It is automatically updated No multiple load store
PUSH and POP
POP Pop register from stack
SP SP
14 10
PUSH Push
register onto stack
sp SP N
4
PUSH can include LR
pop can include PC
En PUSH Crl Ir
MOV ri M
POPCpc ft
1
12 is pushed to stack with register rt upon return
return adder to
goes pc
WAP to add 2 64 bit n.es using Thumb M 7 as
subroutine
PUSH Crs r6 ir
MOV r7 O i Carry holder
LDR RS Cro 64 bit 1
LDR r6 ri i 64 bit 2
ADD r 5 r G i 32 bit
STR r 5 Cro Crs Cros
LDR r5 Cro 4 Load neat word of 64 bit
LDR rf Cri gy l Il
ADC rs ro
STR r5 Cro i
4 n
ro valuedoesn't change storebyoffs
ADC M M Add if carry exists
store carry by offset of 8
STR RS ro 8
POPCPC rG.rs
