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2N6660/2N6661 N-Channel Enhancement-Mode Vertical Dmos Fets: Features General Description

The document describes Supertex's 2N6660 and 2N6661 N-channel enhancement-mode vertical DMOS FETs. These transistors utilize a vertical DMOS structure and silicon-gate process to produce devices with high power handling capabilities like bipolar transistors as well as high input impedance and positive temperature coefficient like MOS devices. Key features include being free from thermal runaway, low threshold voltage, high breakdown voltage, fast switching speeds, and suitability for applications requiring switching and amplification.

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0% found this document useful (0 votes)
192 views3 pages

2N6660/2N6661 N-Channel Enhancement-Mode Vertical Dmos Fets: Features General Description

The document describes Supertex's 2N6660 and 2N6661 N-channel enhancement-mode vertical DMOS FETs. These transistors utilize a vertical DMOS structure and silicon-gate process to produce devices with high power handling capabilities like bipolar transistors as well as high input impedance and positive temperature coefficient like MOS devices. Key features include being free from thermal runaway, low threshold voltage, high breakdown voltage, fast switching speeds, and suitability for applications requiring switching and amplification.

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2N6660/2N6661

N-Channel Enhancement-Mode
Vertical DMOS FETs

Features General Description


► Free from secondary breakdown The Supertex 2N6660 and 2N6661 are enhancement-
► Low power drive requirement mode (normally-off) transistors that utilizes a vertical
► Ease of paralleling DMOS structure and Supertex’s well-proven silicon-gate
► Low CISS and fast switching speeds manufacturing process. This combination produces devices
► Excellent thermal stability with the power handling capabilities of bipolar transistors,
and the high input impedance and positive temperature
► Integral Source-Drain diode
coefficient inherent in MOS devices. Characteristic of
► High input impedance and high gain
all MOS structures, these devices are free from thermal
► Complementary N- and P-Channel devices
runaway and thermally-induced secondary breakdown.
Applications
Supertex’s vertical DMOS FETs are ideally suited to a
► Motor controls wide range of switching and amplifying applications where
► Converters very low threshold voltage, high breakdown voltage, high
► Amplifiers input impedance, low input capacitance, and fast switching
► Switches speeds are desired.
► Power supply circuits
► Drivers (relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.)

Ordering Information
RDS(ON) ID(ON)
BVDSS/BVDGS
Device Package (max) (min)
(V)
(Ω) (A)
2N6660 TO-39 60 3.0 1.5
2N6661 TO-39 90 4.0 1.5

Absolute Maximum Ratings Pin Configuration


Parameter Value
Drain to source voltage BVDSS
Drain to gate voltage BVDGS
Gate to source voltage ±20V
Operating and storage temperature -55°C to +150°C
Soldering temperature1 +300°C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous DGS
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.

Note 1. Distance of 1.6mm from case for 10 seconds.


TO-39
Case: DRAIN
2N6660/2N6661
Electrical Characteristics (T C
= 25°C unless otherwise specified)

Symbol Parameter Min Typ Max Units Conditions

Drain-to-source break- 2N6660 60 - -


BVDSS V VGS = 0V, ID = 10µA
down voltage 2N6661 90 - -
VGS(th) Gate threshold voltage 0.8 - 2.0 V VGS = VDS, ID = 1.0mA
O
ΔVGS(th) VGS(th) change with temperature - -3.8 -5.5 mV/ C VGS = VDS, ID = 1.0mA
IGSS Gate body leakage current - - 100 nA VGS = ±20V, VDS = 0V
- - 10 VGS = 0V, VDS = Max rating
IDSS Zero gate voltage drain current µA VDS = 0.8 Max Rating,
- - 500
VGS = 0V, TA = 125OC
ID(ON) ON-state drain current 1.5 - - A VGS = 10V, VDS = 10V
All - - 5.0 VGS = 5.0V, ID = 0.3A
Static drain-to-source
RDS(ON) 2N6660 - - 3.0 Ω VGS = 10V, ID = 1.0A
ON-state resistance
2N6661 - - 4.0 VGS = 10V, ID = 1.0A
GFS Forward transconductance 170 - - mmho VDS = 25V, ID = 0.5A
CISS Input capacitance - - 50 VGS = 0V,
COSS Common source output capacitance - - 40 pF VDS = 24V,
CRSS Reverse transfer capacitance - - 10 f = 1.0MHz

t(ON) Turn-ON time - - 10 VDD = 25V, ID = 1.0A,


ns
t(OFF) Turn-OFF time - - 10 RGEN = 25Ω
VSD Diode forward voltage drop - 1.2 - V VGS = 0V, ISD = 1.0A
trr Reverse recovery time - 350 - ns VGS = 0V, ISD = 1.0A
Notes:
1.All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2.All A.C. parameters sample tested.

Thermal Characteristics
ID ID Power Dissipation
θjc θja IDR* IDRM
Device Package (continuous)* (pulsed) @TC = 25OC O O
( C/W) ( C/W) (mA) (A)
(mA) (A) (W)
2N6660 TO-39 410 3.0 6.25 20 125 410 3.0
2N6661 TO-39 350 3.0 6.25 20 125 350 3.0
Notes:
* ID (continuous) is limited by max rated TJ.

Switching Waveforms and Test Circuit VDD


10V
90%
RL
INPUT PULSE
0V 10% GENERATOR
OUTPUT
t(ON) t(OFF)
RGEN
td(ON) tr td(OFF) tF

VDD
10% 10% D.U.T.
OUTPUT INPUT

0V 90% 90%

2
2N6660/2N6661

TO-39 Package Outline

0.360 ± 0.010 0.325 ± 0.010


DIA DIA
(9.144 ± 0.254) (8.255 ± 0.254)

0.050
0.250 ± 0.010 (1.270)
MAX
(6.350 ± 0.254)

0.500 0.018 ± 0.002


MIN
(12.700) (0.4572 ± 0.0508)

0.200
TYP
(5.080)

90° NOM
0.100
0.035 ± 0.005
(2.540)
(0.889 ± 0.127) 2
1 3
0.100
0.033 ± 0.005 (2.540)
(0.8382 ± 0.127) 1-Source
2-Gate
45° 3-Drain
NOM

Dimensions in Inches
Measurement Legend =
(Dimensions in Millimeters)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)

Doc.# DSFP-2N6660_2N6661
A042507
3

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