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DC Response
 DC Response: Plot of Vout vs. Vin (i.e Voltage Transfer Curve [VTC]) for
a gate
DC Transfer  CMOS Inverter
Characteristics of – When Vin = 0 -> Vout = VDD
static CMOS – When Vin = VDD -> Vout = 0 VDD
Inverter – For input between 0 and VDD , Idsp
Vin Vout
Vout depends on transistor
Idsn
size and current
– By KCL, Idsn = |Idsp|

1 CMOS VLSI Design 4th Ed. 2

Transistor Operation in CMOS Inverter nMOS Operation

 For what Vin and Vout are nMOS and pMOS in Cutoff Linear Saturated
– Cutoff? Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
– Linear? Vin < Vtn Vin > Vtn Vin > Vtn
– Saturation? Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
 Current depends on region of transistor operation Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

CMOS VLSI Design 4th Ed. 3 CMOS VLSI Design 4th Ed. 4

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pMOS Operation Idsn and Idsp in terms of Vdsn and Vdsp for various values of Vgsn and
Vgsp

Cutoff Linear Saturated  Assume Vtn=|vtp| and pMOS is wider than nMOS such that bn = bp
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp Vgsn5

Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Idsn Vgsn4
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vgsn3
Vout > Vin - Vtp Vout < Vin - Vtp -Vdsp
Vgsn2
-VDD
Vgsp1 Vgsn1
Vgsp2 0 VDD
VDD
Vgsp3 Vdsn
Vgsp = Vin - VDD Vtp < 0 Idsp Vgsp4
Vin Vout -Idsp
Vdsp = Vout - VDD Idsn Vgsp5

CMOS VLSI Design 4th Ed. 5 CMOS VLSI Design 4th Ed. 6

Plot of Idsn and | Idsp| in terms of Vout for various values of

Plot of Idsn and | Idsp| in terms of Vout for various values of V in.
V in.

 Vin = 0  Vin = 0V
0.4V
0.6V
0.8V
.2V
DD DD
DD

Vin0 Vin5
in5

Vin1 Vin4
dsn, |Idsp
Idsn dsp
|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
in0
VDD
Vout
out
DD
The possible operating points of the inverter, marked with dots, are the
values of Vout where Idsn = | Idsp| for a given value of Vin.

CMOS VLSI Design 4th Ed. 7 CMOS VLSI Design 4th Ed. 8

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CMOS DC Transfer Curve Operating Regions of MOSFETs in CMOS Inverter

 Transcribe the operating points onto V in vs. Vout plot VDD

Vin Vout

Vin0 Vin1
VDD Vin2 Region nMOS pMOS
Vin0 Vin5
A B
A Cutoff Linear
VDD
Vout
Vin1 Vin4
C B Saturation Linear A B

Vin2 Vin3 C Saturation Saturation Vout

Vin3
C
Vin3 Vin2 D Vin4 Vin5 D Linear Saturation
Vin4 Vin1 E
0
VDD
Vtn VDD/2 VDD+Vtp
VDD E Linear Cutoff
Vout Vin D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

CMOS VLSI Design 4th Ed. 9 CMOS VLSI Design 4th Ed. 10

Summary of CMOS Inverter Operation The supply current IDD (= Idsn = | Idsp|) versus Vin

VDD
A B
The plot indicates
Vout that both transistors
C are momentarily ON
as Vin passes
D
through voltages
E between GND and
0 Vtn VDD/2 VDD+Vtp
VDD VDD, resulting in
Vin
a pulse of current
drawn from the
power supply.

CMOS VLSI Design 4th Ed. 11 CMOS VLSI Design 4th Ed. 12

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CMOS Inverter Input threshold voltage

CMOS Inverter Input threshold voltage contd.

 CMOS Inverter Input threshold voltage (Vinv) or mid-  KCL at the inverter output node, IDn = - Idp ------(1)
point voltage: It is the input voltage at which output changes  In the circuit,
from one state to another. VDD
Vgsn=Vin and Vgsp=Vin-VDD
 It corresponds to region C on the DC characteristics at which
Vin= Vout = Vinv and Vin = Vinv Idsp
Vin Vout
– Intersection of DC characteristic with Vin= Vout
Idsn
characteristic.
 In region C, both PMOSFET and NMOSFET are in Saturation

Substitute in eqn (1) and solve for Vinv.

CMOS VLSI Design 4th Ed. 13 CMOS VLSI Design 4th Ed. 14

CMOS Inverter Input threshold voltage contd. Symmetric VTC

𝛽𝑛 𝛽𝑝
VDD+Vtp+V tn
𝛽𝑝 VDD+Vtp+Vtn 1
 For symmetric VTC, =1
 Vinv =  Vinv = 𝑟 𝛽𝑛
𝛽 1
1 + 𝛽𝑛 1+ 𝑟
kp’ (W/L)𝑝 µp Cox (W/L)P
𝑝
i.e =1  =1
𝛽𝑝 kn’ (W/L)𝑛 µn Cox (W/L)𝑛
Where r =
𝛽𝑛  µn Cox (W/L)n = µp Cox (W/L)P
𝛽
 Vinv depends on 𝛽𝑝 =kp’ (W/L)𝑝
kn’ (W/L)𝑛  µn (W/L)n = µp (W/L)P
𝑛

i.e. Vinv depends on ratios of aspect ratios.(Aspect ratio->W/L ratio)  3 µp (W/L)n = µp (W/L)P
 With Vtn= -Vtp and
𝛽𝑝
= 1, Vinv= VDD/2 -- Symmetric VTC i.e  (W/L)p = 3( W/L)n
𝛽𝑛
Logic LOW input range: From 0 to VDD/2 and, i.e. PMOSFET should be 3 times bigger in size than
Logic HIGH input range: From VDD/2 to VDD NMOSFET => Keep Lp=Ln=L and Wp=3 Wn

CMOS VLSI Design 4th Ed. 15 CMOS VLSI Design 4th Ed. 16

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Dependence of inverter threshold voltage on Beta Ratio Numerical on inverter threshold voltage

 If bp / bn  1, switching point will move from V DD/2

βp > βnPMOS bigger than
NMOS Vinv>VDD/2

βp = βn PMOS is 3 times

(approx.) bigger than NMOS
Vinv=VDD/2

βp < βn PMOS smaller than

NMOS Vinv<VDD/2

CMOS VLSI Design 4th Ed. 17 CMOS VLSI Design 4th Ed. 18