Unit 12

Registers and Counters

By
Ruba A. Salamah
1 241-208 CH9
Objectives
1. Explain the operation of registers. Show how to transfer data
between registers using a tri-state bus.

2. Explain the operation of shift registers, show how to build

them using flip-flops, and analyze their operation. Construct a
timing diagram for a shift register.

3. Explain the operation of binary counters, show how to build

them using flip-flops and gates, and analyze their operation.

4. Given the present state and desired next state of a flip-flop,

determine the required flip-flop inputs.
Objectives cont…

5. Given the desired counting sequence for a

counter, derive the flip-flop input equations.

6. Explain the procedures used for deriving

flip-flop input equations.

7. Construct a timing diagram for a counter

by tracing signals through the circuit.

3
12.1 Registers and Register Transfers
 Several D flip-flops may be grouped together with a common
clock to form a register
12.1 Registers and Register Transfers
bus notation

4Bit D Flip-Flop
Registers with
Data,
Load, Clear, and
Clock Inputs
 Data Transfer Between Registers
 Transferring data between registers is a common operation in
digital systems.
12.1 Registers and Register Transfers
 Because each flip-flop can store one bit of information, this
register can store four bits of information
 This register has a load signal that is ANDed with the clock.
When Load = 0, the register is not clocked, and it holds its
present value.
 When it is time to load data into the register, Load is set to 1 for
one clock period.
 The flip-flops in the register have asynchronous clear inputs
that are connectedto a common clear signal, ClrN (active low).
 A group of wires that perform a common function is often
referred to as a bus. A heavy line is used to represent a bus, and
a slash with a number beside it indicates the number of bits in
the bus.
Logic Diagram for 8-Bit Register with Tri-State
Output
8
Data Transfer Using a Tri-State Bus
9
Parallel Adder with Accumulator

10
 Register
• A register is a memory device that can be used to store
more than one-bit information

• A register is usually realized as several flip-flops with

common control signals that control the movement of
data to and from the register. (shifting data 1s and 0s)

• A register can consist of one or more FF is used to store

and shift data.

• A register in digital circuit with 2 basic function : data

storage and data movement
 Basic Shift Register Function
 Shift Register consists of an arrangement of Flip-flop.

 Important in applications involving storage and

transfer data in digital system.

 Has no specified sequence of states.

 D flip-flop is used
 Shift Registers
 Multi-bit register that moves stored data bits
left/right ( 1 bit position per clock cycle)
 Shift Left is towards MSB
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0 1 1 1 LSI 1 1 1 LSI

 Shift Right (or Shift Up) is towards MSB

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
RSI 0 1 1 1 RSI 0 1 1
Basic data movement in shift registers
(Four bits are used for illustration. The bits
move in the direction of the arrows.)
 Type of register

i. Serial In / Serial Out Shift Registers (SISO)

ii. Serial In /Parallel Out Shift Registers (SIPO)
iii. Parallel In / Serial Out Shift Registers (PISO)
iv. Parallel In / Parallel Out Shift Registers (PIPO)
 Serial-in/Serial out Shift Register

 5-bit serial in/serial out shift register

implemented with D flip-flops.

FF0 FF1 FF2 FF3 FF4

Serial 1 1 1 1 1 1 Serial
data D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 data
input output

C C C C C

CLK
CLK

16
4- bit (1010) being entered serially into Serial In, Serial Out Shift Register (SISO)
Show state of 5-bit register for specified data input and clock waveform.
Assume register initially clear all (0s)  SISO
Serial In, Parallel Out Shift register (SIPO)

• Data bits entered serially (right-most bit first)

• Difference from SISO is the way data bits are taken
out of the register – in parallel.
• Output of each stage is available
 Serial In/Parallel Out Shift Registers
SI/SO
 4-bit serial in/parallel out shift register
 For example, assume the binary number
1011 is loaded sequentially, one bit at each
clock pulse.
FF0 FF1 FF2
FF2 FF3
FF3
Serial 1
X
0 1
0 10 10 1
data D00
D Q00
Q D11
D Q11
Q D22
D Q22
Q D33
D Q33
Q
input
C
C C
C C
C C
C

CLK
CLK

21
Example :

Show the states of 4-bit register (SRG 4) for the data input and clocks
waveforms. The register initially contains all (1s).

Assume the register initially contains all 1s ~ HIGH.

The register have 0110 after 4 clock pulse…
Parallel In, Parallel Out Shift Register (PIPO)

 Immediately following simultaneous entry of all data bits,

it appear on parallel output.
4-bit parallel in/serial out shift register (PISO)
(logic symbol)
 4-bit parallel in/serial out shift register (PISO)

When signal = 1,
SHIFT

When signal = 0,
 LOAD
 4-bit parallel in/serial out shift register (PISO)

When signal = 0,
LOAD

G1 – G3
enabled
 4-bit parallel in/serial out shift register (PISO)

When signal = 1,
SHIFT

G4 – G6
enabled
Example : Show the data input waveform for 4-bit register with parallel input
and clock shift/load waveform…4-bit parallel in/serial out shift register (PISO)
Universal Shift Register

PI/PO
PI/SO
SI/PO
SI/S0
SHIFT RIGHT
SHIFT LEFT
Parallel-In, Parallel-Out Right-Shift
Register

PI/PO
PI/SO
SI/PO
SI/S0
JUST SHIFT RIGHT
Register
 See problems 12-2, 12-3
 Shift Register Counters
▪ Shift registers can form useful counters by
recirculating a pattern of 0’s and 1’s.
▪ Two important shift register counters are the Johnson
counter and the ring counter.
FF0 FF1 FF2 FF3
Q3
D0 Q0 D1 Q1 D2 Q2 D3 Q3

C C C C

CLK

FF0 FF1 FF2 FF3

D0 Q0 D1 Q1 D2 Q2 D3 Q3

C C C C

Q3 Q3

34 CLK
 Ring Counter and timing signals

 Timing signals that

control the sequence
of operations in a
digital system can be
generated by a ring
counter

35
Timing signals

 For an alternative
design, the timing
signals can be
generated by a
two‐bit counter
that goes through
four distinct states.
Timing signals
 To generate 2n timing signals, we need
either a shift register with 2n flip‐flops or
an n ‐bit binary counter together with an
n ‐to‐2 n ‐line decoder.
 For example, 16 timing signals can be
generated with a 16‐bit shift register
connected as a ring counter or with a
4‐bit binary counter and a 4‐to‐16‐line
decoder.
 Johnson counter
• A k ‐bit ring counter circulates a single bit among
the flip‐flops to provide k distinguishable states.
• The number of states can be doubled if the shift
register is connected as a switch‐tail ring counter.

CLK Q0 Q1 Q2 Q3
0 0 0 0 0
FF0 FF1 FF2 FF3
1 1 0 0 0
D0 Q0 D1 Q1 D2 Q2 D3 Q3
2 1 1 0 0
C C C C 3 1 1 1 0
4 1 1 1 1
Q3 Q3
5 0 1 1 1
CLK 6 0 0 1 1
38 7 0 0 0 1
 A Johnson counter is a k ‐bit switch‐tail ring
counter with 2 k decoding gates to provide
outputs for 2 k timing signals. The decoding gates
are not shown in Fig. 6.18 , but are specified in the
last column of the table.
 COUNTERS
 An n ‐bit binary counter consists of n flip‐flops and
can count in binary from 0 through 2n - 1.
 Counters are available in two categories: ripple
counters and synchronous counters.
 In a ripple (asynchronous) counter, a flip‐flop output
transition serves as a source for triggering other
flip‐flops. In other words, the C input of some or all
flip‐flops are triggered, not by the common clock
pulses, but rather by the transition that occurs in
other flip‐flop outputs.
 In a synchronous counter, the Clock inputs of all
flip‐flops receive the common clock.
Binary Ripple Counter
4 bit ripple binary up counter
Up Ripple Counters
Down Ripple Counters
 BCD Ripple Counters
 A decimal counter follows a sequence of 10 states and
returns to 0 after the count of 9.
BCD Ripple Counters
SYNCHRONOUS COUNTERS
 Synchronous counters are different from ripple
counters in that clock pulses are applied to the
inputs of all flip‐flops. A common clock triggers all
flip‐flops simultaneously, rather than one at a
time in succession as in a ripple counter.
 The decision whether a flip‐flop is to be
complemented is determined from the values of
the flip flop inputs, such as T or J and K at the
time of the clock edge.
 The problem is to determine the flip-flop inputs
Design of 3-bit binary counter

Transition Table for Binary Counter

 Excitation Tables

• When D -type flip-flops are employed, the input equations are obtained
directly from the next state.
 Design of 3-bit binary counter (cont..)

Transition Table for Binary Counter

Design of 3-bit binary counter
4-bit binary UP counter with JK Flip-Flop
4-bit binary Down counter with JK Flip-Flop
Up-Down
Counter
up-down binary counter D Flip-Flop

Transition Graph and Table for Up-Down Counter

 up-down binary counter

 When U = 1, the counter counts up in the sequence 000,

001, 010, 011, 100, 101, 110, 111, 000 . . .
 When D = 1, the counter counts down in the sequence
000, 111, 110, 101, 100, 011, 010, 001, 000 . . .
 When U = D = 0, the counter state does not change.
 U = D = 1 is not allowed.
Binary counter
with count
enable
Loadable Counter with Count Enable
Loadable Counter with Count Enable
 Counters for Other Sequences
 Counters can be designed to generate any desired sequence
of states.
 A divide‐by‐ N counter (also known as a modulo‐ N counter)
is a counter that goes through a repeated sequence of N
states. The sequence may follow the binary count or may be
any other arbitrary sequence.
 A circuit with n flip‐flops has 2n binary states. There are
occasions when a sequential circuit uses fewer than this
maximum possible number of states.
 States that are not used may be treated as don’t‐care
conditions or may be assigned specific next states.
 Counters for Other Sequences
 it is necessary to ensure that if the circuit enters one of
the unused states the circuit eventually goes into one of
the valid states so that it can resume normal operation.
 Otherwise, if the sequential circuit circulates among
unused states, there will be no way to bring it back to its
intended sequence of state transitions.
 If the unused states are treated as don’t‐care conditions,
then once the circuit is designed, it must be investigated
to determine the effect of the unused states.
 The next state from an unused state can be determined
from the analysis of the circuit after it is designed.
Example
Design with T
Flip-Flop
FIGURE 12-24
Counter Using T Flip-Flops
FIGURE 25-12
Timing Diagram for Figure 24-12
 self‐correcting counter
 Although the original transition table for the counter (Table
12-3) is not completely specified, the next states of states
001, 101, and 110 have been specified in the process of
completing the circuit design.
 For example, if the flip-flops are initially set to C = 0, B = 0,
and A = 1, tracing signals through the circuit shows that TC =
TB = 1 and TA = 0, so that the state will change to 111 when a
clock pulse is applied.
Can you test the other two
unused states????

Is this a self‐correcting
counter????
 self‐correcting counter
 In a self‐correcting counter, if the counter happens to be
in one of the unused states, it eventually reaches the
normal count sequence after one or more clock pulses.
 An alternative design could use additional logic to direct
every unused state to a specific next state.
 For this reason, all of the don’t-care states in a counter
should be checked to make sure that they eventually
lead into the main counting sequence
 If a power-up reset is provided, the counter is
sometimes called self-starting.
Example Continue… Design Using D Flip-Flops
Example Continue… Design Using D Flip-Flops
Counters for Other Sequences
 Counters and shift registers with clear, preset, or parallel
load capability can also be used to generate nonbinary
count cycles.
 Consider a 4 bit binary counter with a clear input. The
binary counter (N = 4) can be converted to a BCD decade
(decimal) counter if the gate logic causes the counter to
transfer from a count of 9 to a count of 0 (rather than
10). If the clear input is a synchronous clear, then the
logic required is
 If the clear input is an asynchronous input, then the logic
required is
 Two ways to achieve a BCD counter using a
counter with parallel load
 A momentary spike occurs in
 output A0 as the count goes from 1010 to 1011 and
immediately to 0000. The spike may
 be undesirable, and for that reason, this configuration
is not recommended.

A momentary spike occurs in output A1as the count goes from 1001
to 1010 and immediately to 0000. The spike may be undesirable, and
for that reason, this configuration is not recommended.
Counter Design Using S-R Flip-Flops
Example
Example Continue….
Example Continue….
Example Continue….
Counter Design Using J-K Flip-Flops
Example
Example continue…….
Derivation of Flip-Flop Input
Equations—Summary
EXAMPLES
 THE END

Any Questions
?