2 Bit Alu

The document describes a 2-bit ALU (Arithmetic Logic Unit) implemented in VHDL, which takes two 2-bit inputs and a 2-bit selector to perform various operations including addition, subtraction, NAND, and NOR. The architecture is defined behaviorally with a process that uses a case statement to determine the output based on the selector input. The document also includes references to simulation and block/logic diagrams, although these diagrams are not provided.

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Mahesh Nandurkar

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2 Bit Alu

Uploaded by

Mahesh Nandurkar

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2 BIT ALU

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity alllllll is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
res : out STD_LOGIC_VECTOR (1 downto 0));
end alllllll;

architecture Behavioral of alllllll is

begin
process(a,b,sel)
begin
case sel is
when"00"=>
res<=a+b;
when"01"=>
res<=a-b;
when"10"=>
res<=a nand b;
when "11"=>
res<=a nor b;
when others=>
res<="XX";
end case;
end process;
end Behavioral;
SIMULATION

BLOCK DIAGRAM
LOGIC DIAGRAM

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2 Bit Alu

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2 Bit Alu

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2 BIT ALU

---- Uncomment the following library declaration if instantiating

architecture Behavioral of alllllll is

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