Scribd
Upload
49 views4 pages

Mux 1

This document describes a multiplexer entity with 4 inputs (A, B, C, D) and 2 select lines (S0, S1). Based on the values of the select lines, the multiplexer will output one of the 4 inputs on the output Z. The document also includes a testbench that applies different combinations of inputs to the multiplexer entity and observes the output.

Uploaded by

Jyoti Sahoo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
49 views4 pages

Mux 1

This document describes a multiplexer entity with 4 inputs (A, B, C, D) and 2 select lines (S0, S1). Based on the values of the select lines, the multiplexer will output one of the 4 inputs on the output Z. The document also includes a testbench that applies different combinations of inputs to the multiplexer entity and observes the output.

Uploaded by

Jyoti Sahoo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

----------------------------------------------------------------------------------

-- Create Date: [Link] 11/23/2021

-- Design Name:

-- Module Name: mux1_entity - Behavioral

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mux1_entity is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

C : in STD_LOGIC;

D : in STD_LOGIC;

S0 : in STD_LOGIC;

S1 : in STD_LOGIC;

Z : out STD_LOGIC);

end mux1_entity;

architecture Behavioral of mux1_entity is

begin

process (A,B,C,D,S0,S1) is

begin

if (S0 ='0' and S1 = '0') then

Z <= A;

elsif (S0 ='1' and S1 = '0') then

Z <= B;

elsif (S0 ='0' and S1 = '1') then

Z <= C;

else

Z <= D;

end if;

end process;

end Behavioral;
--------------------------------------------------------------------------------

-- Create Date: [Link] 11/23/2021

-- Design Name:

-- Module Name: /home/ise/mux1/mux1_tb.vhd

-- Project Name: mux1

ENTITY mux1_tb IS

END mux1_tb;

ARCHITECTURE behavior OF mux1_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT mux1_entity
PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

D : IN std_logic;

S0 : IN std_logic;

S1 : IN std_logic;

Z : OUT std_logic

);

END COMPONENT;

--Inputs

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

signal S0 : std_logic := '0';

signal S1 : std_logic := '0';

--Outputs

signal Z : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: mux1_entity PORT MAP (

A => A,

B => B,

C => C,

D => D,

S0 => S0,

S1 => S1,

Z => Z

);
-- Stimulus process

stim_proc: process

begin

wait for 1 ps;

A <= '1';

B <= '0';

C <= '1';

D <= '0';

S0 <= '0'; S1 <= '0';

wait for 1 ps;

S0 <= '1'; S1 <= '0';

wait for 1 ps;

S0 <= '0'; S1 <= '1';

wait for 1 ps;

S0 <= '0'; S1 <= '1';

wait for 1 ps;

end process;

END;

You might also like