A4960

Sensorless BLDC Controller

Features and Benefits Description

• 3-phase BLDC sensorless start-up and commutation The A4960 is a three-phase, sensorless, brushless DC (BLDC)
• Gate drive for N-channel MOSFETs motor controller for use with external N-channel power
• Integrated PWM current limit MOSFETs.
• 7 to 50 V supply voltage operating range
The motor is driven using block commutation (trapezoidal
• Compatible with 3.3 V and 5 V logic
drive) where phase commutation is determined, without the
• Cross-conduction protection with adjustable dead time
need for independent position sensors, by monitoring the motor
• Charge pump for low supply voltage operation
back-EMF. A programmable motor start-up scheme allows
• Extensive diagnostics output
the A4960 to be adjusted for a wide range of motor and load
• Low current sleep mode
combinations.
Applications: An external bootstrap capacitor is used to provide the above
battery supply voltage required for N-channel MOSFETs.
• Pumps An automatic internal bootstrap charge management scheme
• Fans ensures that the bootstrap capacitor is always sufficiently
• Blowers charged for safe operation of the power MOSFETs. The power
MOSFETs are protected from shoot-through by integrated
crossover control and adjustable dead time.
Package: 32-pin LQFP with exposed
Integrated diagnostics provide indication of undervoltage,
thermal pad (suffix JP)
overtemperature, and power bridge faults and can be configured
to protect the power MOSFETs under most short circuit
conditions. Detailed diagnostics are available as a serial data
word.
The A4960 is supplied in a 32-pin LQFP with exposed pad
for enhanced thermal dissipation (suffix JP). This package
is lead (Pb) free, with 100% matte-tin leadframe plating
(suffix –T).
Not to scale

Typical Application

VBAT
VBAT A8450
Regulator

SPI

3-Phase
A4960 BLDC
PWM Motor
Micro- TACHO
controller
RESET

FAULT

A4960S-DS, Rev. 4 April 27, 2022

MCO-0000175
A4960 Sensorless BLDC Controller

Selection Guide
Part Number Packing*
A4960SJPTR-T 1500 pieces per 13-in. reel
*Contact Allegro™ for additional packing options

Absolute Maximum Ratings1,2

Characteristic Symbol Notes Rating Unit
Load Supply Voltage VBB –0.3 to 50 V
Logic Supply Voltage VDD –0.3 to 6 V
Terminal VREG VREG –0.3 to 16 V
Terminal CP1 VCP1 –0.3 to 16 V
VCP1 – 0.3 to
Terminal CP2 VCP2 V
VREG + 0.3
Terminals STRN, SCK, SDI, PWM –0.3 to 6 V
Logic Inputs VI Terminal RESETN – can be pulled to VBB with
–0.3 to 6 V
>22 kΩ
Logic Outputs VO Terminals SDO, TACHO –0.3 to VDD + 0.3 V
Terminal DIAG VDIAG –0.3 to VDD + 0.3 V
Terminal VBRG VBRG –5 to 55 V
Terminals CA, CB, CC VCx –0.3 to VREG + 50 V
VCX – 16 to
Terminals GHA, GHB, GHC VGHx V
VCX + 0.3
VCX – 16 to
Terminals SA, SB, SC VSx V
VCX + 0.3
Terminals GLA, GLB, GLC VGLx VREG – 16 to 18 V
Terminal LSS VLSS VREG – 16 to 18 V
Terminal REF VREF –0.3 to 6.5 V
Terminals CSP, CSM VCSx –0.3 to 1 V
Terminal AGND Connect directly to GND
Ambient Operating Temperature Temperature Range S; limited by power
TA –20 to 85 °C
Range dissipation
Maximum Continuous Junction
TJ(max) 150 °C
Temperature
Storage Temperature Range Tstg –55 to 150 °C
1With respect to GND. Ratings apply when no other circuit operating constraints are present.
2Small “x” in pin names and symbols indicates a variable sequence character.

Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Unit

Package Thermal Resistance, Junction On 4-layer PCB based on JEDEC standard 23 ºC/W
RθJA
to Ambient On 2-layer PCB with 3 in.2 copper each side 44 ºC/W
Package Thermal Resistance, Junction
RθJP 2 ºC/W
to Pad
*Additional thermal information available on the Allegro website

2
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A4960 Sensorless BLDC Controller

Table of Contents

Specifications 2 Diagnostics 19
Pin-out Diagram and Terminal List 4 DIAG pin 19
Functional Block Diagram 5 Serial interface fault output 19
Electrical Characteristics Table 6 Fault response action 20
Timing Diagrams 10 Fault Mask register 20
Operation Timing Diagrams 10 Chip-level diagnostics 20
Functional Description 12 Chip Fault States: Temperature Thresholds 20
Functional Description 12 Chip Fault State : VREG Undervoltage 21
Input and Output Terminal Functions 12 Chip Fault State: VDD Undervoltage 21
Motor Drive System 13 Bootstrap Undervoltage Fault State 21
Rotor position sensing using motor BEMF 13 MOSFET fault detection 21
Commutation Blank Time 14 MOSFET fault blank time 22
BEMF Window 14 Short fault operation 22
BEMF Hysteresis 14 MOSFET Fault State: Short to Supply 22
Start-up 14 MOSFET Fault State: Short to Ground 22
Motor control 15 MOSFET Fault State: Shorted Winding 22
Phase advance 15 Serial Interface Description 23
Power Supplies 16 Configuration and control registers 24
Gate Drives 16 Diagnostic register 25
Gate drive voltage regulation 16 Applications Information 31
Bootstrap charge management 16 Control Timing Diagrams 31
Low-side gate drive 16 Input/Output Structures 32
High-side gate drive 17 Package Outline Drawing 33
Dead Time 17
Sleep Mode and RESETN 17
Current Limit 18
Current sense amplifier 18
Fixed off-time 18
Blank time 19

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A4960 Sensorless BLDC Controller

Pin-out Diagram

AGND

VREG
GND
VBB

CP1

CP2

CA

SA
32

31

30

29

28

27

26

25
VBRG 1 24 GHA

RESETN 2 23 GLA

REF 3 22 CB

VDD 4 PAD 21 SB

DIAG 5 20 GHB

PWM 6 19 GLB

TACHO 7 18 GHC

SDO 8 17 CC
10

11

12

13

14

15

16
9

SC
SCK

SDI

CSM

CSP

LSS
STRN

GLC

Terminal List Table

Name Number Function Name Number Function
AGND 31 Reference ground LSS 14 Low-side source
CA 26 Bootstrap capacitor, Phase A PAD – Exposed thermal pad
CB 22 Bootstrap capacitor, Phase B PWM 6 PWM Input
CC 17 Bootstrap capacitor, Phase C REF 3 Reference voltage input
CP1 29 Pump capacitor RESETN 2 Standby mode control
CP2 28 Pump capacitor SA 25 Motor connection, Phase A
CSM 12 Sense amplifier negative input SB 21 Motor connection, Phase B
CSP 13 Sense amplifier positive input SC 16 Motor connection, Phase C
DIAG 5 Programmable diagnostic output SCK 9 Serial clock input
GHA 24 High-side gate drive, Phase A SDI 10 Serial data input
GHB 20 High-side gate drive, Phase B SDO 8 Serial data output
GHC 18 High-side gate drive, Phase C STRN 11 Serial Strobe (chip select) input
GLA 23 Low-side gate drive, Phase A TACHO 7 Speed output
GLB 19 Low-side gate drive, Phase B VBB 32 Main power supply
GLC 15 Low-side gate drive, Phase C VBRG 1 High-side drain voltage sense
GND 30 Power ground VDD 4 Logic supply
VREG 27 Regulated voltage, above supply

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A4960 Sensorless BLDC Controller

Functional Block Diagram

Battery +
CP

VDD CP1 CP2 VBB

STRN Charge VBAT

SCK Serial Start Config Pump VREG
SDI Interface Registers Registers CREG
Regulator
SDO

REF Ref Start VBRG

DAC Sequencer
Phase A shown
(Repeated for B and C)
PWM
CA
CBOOTA
Bootstrap
Monitor
High-Side GHA
TACHO Drive RGATE

VDS
Monitor
SA
Run Motor Bridge Gate
RESETN State Control Drive VDS
Control VREG Monitor
Sequencer Control

Phase C
Low-Side GLA
Drive RGATE
Phase B

Diagnostics
DIAG and
Protection Blank Dead
Comm Blank
Time Time LSS
Timer Time

CSP
Zero X
Detect
CSM
VRI

AGND GND

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A4960 Sensorless BLDC Controller

ELECTRICAL CHARACTERISTICS Valid at TA = 25°C, VDD = 5 V, VBB = 7 to 28 V; unless otherwise specified

Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Supply and Reference
Operating, outputs active 6 – 50 V
VBB Functional Operating Range1 VBB Operating, outputs disabled 5.5 – 50 V
No unsafe states 0 – 50 V
IBBQ RESETN = high; GHx, GLx = low, VBB = 12 V – 10 14 mA
VBB Quiescent Current
IBBS RESETN = low, sleep mode, VBB = 12 V – – 10 µA
VDD Logic Supply VDD 3.0 – 5.5 V
IDDQ RESETN = high, outputs low – 6 16 mA
VDD Quiescent Current
IDDS RESETN = low – – 15 µA
VBB > 9 V, IREG = 0 to 8 mA 12.4 13 13.8 V
7.5 V < VBB ≤ 9 V, IREG = 0 to 6 mA 12.4 13 13.8 V
VREG Output Voltage VREG
2×VBB
6 V < VBB ≤ 7.5 V, IREG = 0 to 5 mA – – V
– 2.5
ID = 10 mA 0.4 0.7 1.0 V
Bootstrap Diode Forward Voltage VfBOOT
ID = 100 mA 1.5 2.2 2.8 V
rD(100mA) = (VfBOOT(150mA) – VfBOOT(50mA)) /
Bootstrap Diode Resistance rD 6.5 15.0 22.5 Ω
100 (mA)
Bootstrap Diode Current Limit IDBOOT 250 500 750 mA
System Clock Period tOSC 42.5 50 57.5 ns
Gate Output Drive
Turn-On Time tr CLOAD = 500 pF, 20% to 80% – 35 – ns
Turn-Off Time tf CLOAD = 500 pF, 80% to 20% – 20 – ns
Pull-Up On-Resistance2 RDS(on)UP IGHx = –150 mA 9 13 17 Ω
Pull-Down On-Resistance RDS(on)DN IGLx = 150 mA 1.8 3.0 5.0 Ω
GHx Output Voltage High VGHH Bootstrap capacitor fully charged VC – 0.2 – – V
GHx Output Voltage Low VGHL –10 µA < IGH < 10 µA – – VSx + 0.3 V
GLx Output Voltage High VGLH –10 µA < IGL < 10 µA VREG – 0.2 – – V
GLx Output Voltage Low VGLL –10 µA < IGL < 10 µA – – VLSS + 0.3 V
GHx Passive Pull-Down RGHPD VGSH = 1 V – 350 – kΩ
GLx Passive Pull-Down RGLPD VGSL = 1 V – 350 – kΩ
Input change to unloaded gate output change,
Turn-Off Propagation Delay tP(off) 200 250 300 ns
see figure 3
Input change to unloaded gate output change,
Turn-On Propagation Delay tP(on) 200 250 300 ns
see figure 3
Dead Time (Turn-Off to Turn-On delay) tDEAD Default power–up state, see figure 3 0.85 1.0 1.15 µs
Current Limiting
Differential Input Voltage VID VID = VCSP – VCSM 0 – 200 mV
Reference Input Voltage VREF 0.8 – 2.0 V

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A4960 Sensorless BLDC Controller

ELECTRICAL CHARACTERISTICS (continued) Valid at TA = 25°C, VDD = 5 V, VBB = 7 to 28 V;

unless otherwise specified
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Reference Clamp Voltage VREFC REF tied to VDD 1.84 2 2.16 V
Reference Input Current2 IREF –3 0 3 µA
Internal Reference Voltage VRI Default power–up state – VREF – V
Current Trip Point Error3 EITRIP VREF = 2 V –5% – +5% %FS
Fixed Off-Time tOFF Default power–up state 30.3 35.6 40.9 µs
Blank Time tBL Default power–up state 2.72 3.2 3.68 µs
Logic Inputs and Outputs
Terminals PWM, SDI, SCK, STRN – – 0.3VDD V
Input Low Voltage VIL
Terminal RESETN – – 0.25VDD V
Input High Voltage VIH 0.7VDD – – V
Terminals PWM, SDI, SCK, STRN 150 550 – mV
Input Hysteresis VIhys
Terminal RESETN 150 370 – mV
Terminals PWM, SDI, SCK 30 50 70 kΩ
Input Pull-Down Resistor RPD
Terminal RESETN 45 80 110 kΩ
Input Pull-Up Resistor RPU Terminal STRN 30 50 70 kΩ
Output Low Voltage VOL IOL = 1 mA – 0.2 0.4 V
Output High Voltage2 VOH IOL = –1 mA VDD – 0.4 VDD – 0.2 – V
Output Leakage (SDO)2 IO 0 V < VO < VDD, STRN = 1 –1 – 1 µA
Logic Inputs and Outputs – Dynamic Parameters
RESETN Pulse Width tRES 0.2 – 4.5 µs
RESETN Shutdown Width tRSD 10 – – µs
Input Pulse Filter Time (PWM) tPIN – 35 – ns
PWM Brake Time tBRK 500 – – µs
Clock High Time tSCKH A in figure 1 50 – – ns
Clock Low Time tSCKL B in figure 1 50 – – ns
Strobe Lead Time tSTLD C in figure 1 30 – – ns
Strobe Lag Time tSTLG D in figure 1 30 – – ns
Strobe High Time tSTRH E in figure 1 300 – – ns
Data Out Enable Time tSDOE F in figure 1 – – 40 ns
Data Out Disable Time tSDOD G in figure 1 – – 30 ns
Data Out Valid Time from Clock Falling tSDOV H in figure 1 – – 40 ns
Data Out Hold Time from Clock Falling tSDOH I in figure 1 5 – – ns
Logic I/O – Dynamic Parameters (continued)
Data In Set-up Time to Clock Rising tSDIS J in figure 1 15 – – ns
Data In Hold Time from Clock Rising tSDIH K in figure 1 10 – – ns

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A4960 Sensorless BLDC Controller

ELECTRICAL CHARACTERISTICS (continued) Valid at TA = 25°C, VDD = 5 V, VBB = 7 to 28 V;

unless otherwise specified
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Wake Up from Sleep Mode tEN RESETN rising to undervoltage faults cleared – – 2 ms
Motor Start-up Parameters
Hold Torque Internal Reference VHQ Default power–up level: IDS = 0 33.7 37.5 41.3 %VREF
Hold Torque Duty Cycle DHQ Default power–up level: IDS = 1 33.7 37.5 41.3 %
Hold Time tHOLD Default power–up level 28.9 34.0 39.1 ms
Start Commutation Time tCOMS Default power–up level 34 40 46 ms
End Commutation Time tCOME Default power–up level 2.72 3.20 3.68 ms
Ramp Torque Internal Reference VRQ Default power–up level: IDS = 0 50.6 56.25 61.9 %VREF
Ramp Torque Duty Cycle DRQ Default power–up level: IDS = 1 50.6 56.25 61.9 %
Ramp Rate (Change in commutation
ΔtCOM RR[3:0] = 1001 1.7 2.0 2.3 ms
time)
Motor Run Parameters
Denominated in electrical degrees,
Phase Advance θADV 12 15 18 deg
PA[3:0] = 1000
BEMF Hysteresis – High VBHYSH – 240 – mV
BEMF Hysteresis – Low VBHYSL – 60 – mV
BEMF Window Time tBW Default power–up level 5.4 6.4 7.4 µs
Commutation Blank Time tCB Default power–up level 42.5 50 57.5 µs
Protection
VREGUVON VREG rising 7.5 8 8.5 V
VREG Undervoltage Threshold
VREGUVOFF VREG falling 6.6 7.1 7.6 V
Bootstrap Undervoltage VBOOTUV VBOOT falling, VCx – VSx 58 – 71 %VREG
Bootstrap Undervoltage Hysteresis VBOOTUVHys – 13 – %VREG
VDD Undervoltage Threshold VDDUV VDD falling 2.45 2.7 2.85 V
VDD Undervoltage Hysteresis VDDUVHys 50 100 150 mV
Drain-Source Threshold Voltage VDSTH Default power–up level 720 800 880 mV
VBRG Input Voltage VBRG When VDS monitor is active VBB – 1 VBB VBB + 1 V
VBRG Input Current IVBRG VDSTH = default, VBB = 12 V, 0 V < VBRG < VBB – – 250 µA
High side on, VDSTH ≥ 1 V – ±100 – mV
Short-to-Ground Threshold Offset4 VSTGO
High side on, VDSTH < 1 V –150 ±50 +150 mV
Low side on, VDSTH ≥ 1 V – ±100 – mV
Short-to-Battery Threshold Offset5 VSTBO
Low side on, VDSTH < 1 V –150 ±50 +150 mV
Protection (continued)
DIAG Output Clock Division Ratio ND DGx = 01 400 – – –
DIAG Output VDS Threshold Error EVTHD DGx = 10 –10 – 10 mV

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A4960 Sensorless BLDC Controller

ELECTRICAL CHARACTERISTICS (continued) Valid at TA = 25°C, VDD = 5 V, VBB = 7 to 28 V;

unless otherwise specified
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Temperature Warning Threshold TJW Temperature increasing 125 135 145 ºC
Temperature Warning Hysteresis TJWHys – 15 – ºC
Overtemperature Threshold TJF Temperature increasing 155 170 – ºC
Overtemperature Hysteresis TJFHys Recovery = TJF – TJHys – 15 – ºC
1Function is correct but parameters are not guaranteed above or below the general limits (7 to 28 V).
2For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device terminal.
3Current Trip Point Error is the difference between the actual current trip point and the target current trip point, referred to maximum full scale (100%)
current: EITRIP = 100 × (ITRIP(Actual) – ITRIP(Target)) / IFullScale (%) .
4As V
Sx decreases, a fault occurs if VBAT – VSx > VSTG . STG threshold, VSTG = VDTSTH + VSTGOFF .
5As V
Sx increases, a fault occurs if VSx – VLSS > VSTB . STB threshold, VSTB = VDTSTH + VSTBOFF .

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A4960 Sensorless BLDC Controller

Operation Timing Diagrams

STRN

C A B D E

SCK

J K

SDI X D15 X D14 X X D0 X

F
I G
SDO Z D15’ D14’ D0’ Z

H
X=don’t care, Z=high impedance (tri-state)

Figure 1. Serial Interface Timing (letters A through K are referenced in the Electrical Characteristics table, Logic
Inputs and Outputs – Dynamic Parameters section)

PWM
PWM
tP(off) tDEAD
tBRK
GHx
Run PWM Off Brake
GLx

tDEAD tP(off)

Figure 2. Gate Drive Output Timing – PWM Input Figure 3. PWM Brake Timing

PWM
tP(off)

GHx
tDEAD tBL

HS VDS Monitor Action Disabled Active Disabled

tP(off)

GLx
tDEAD tBL

LS VDS Monitor Action Active Active Disabled

Figure 4. VDS Fault Blanking

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A4960 Sensorless BLDC Controller

Phase

TACHO

Phase Internal or
External
PWM

tBW tBW
tCB tCB
Phase BEMF BEMF BEMF BEMF
Voltage ignored monitored ignored monitored
TACHO

Figure 5. Commutation Blank Time Figure 6. BEMF Window

Phase Phase

TACHO TACHO

VBHYSL

Normal Zero-Crossing with high hysteresis

with low hysteresis VBHYSL
VBHYSH VBHYSH
with low hysteresis
with high hysteresis Normal Zero-Crossing

High hysteresis High hysteresis

TACHO Low hysteresis TACHO Low hysteresis
when when
No hysteresis No hysteresis

Figure 7. BEMF Hysteresis – Falling Phase Voltage Figure 8. BEMF Hysteresis – Rising Phase Voltage

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A4960 Sensorless BLDC Controller

Functional Description
The A4960 is a three-phase, sensorless, brushless DC (BLDC) to provide the transient charging current.
motor controller for use with external N-channel power
REF Voltage reference input to internal reference DAC. Connect
MOSFETs and is specifically designed for high-power indus-
trial applications. The motor is driven using block commutation to VDD to use the internal 2 V reference.
(trapezoidal drive), where phase commutation is determined by GND Analog reference, digital and power ground. Connect to
a proprietary, motor back-EMF (BEMF) sensing technique. The supply ground.
motor BEMF is sensed to determine the rotor position without
any requirement for independent position sensors. VBRG Sense input to the top of the external MOSFET bridge.
Allows accurate measurement of the voltage at the drain of the
Motor current is provided by six external N-channel power
high-side MOSFETs.
MOSFETs arranged as a three-phase bridge. The A4960 provides
six high current gate drives, three high-side and three low-side, CA, CB, CC High-side connections for the bootstrap capacitors
capable of driving a wide range of MOSFETs. It includes all the and positive supply for high-side gate drivers.
necessary circuits to ensure that the gate-source voltage of both
GHA, GHB, GHC High-side, gate-drive outputs for external
high-side and low-side MOSFETs are above 10 V at motor sup-
ply voltages down to 7 V. N-channel MOSFETs.

An integrated start-up scheme can be configured with program- SA, SB, SC Motor phase connections. These terminals sense the
mable parameters through a serial interface allowing the A4960 voltages switched across the load. They are also connected to the
to be adjusted for a wide range of motor and load combinations. negative side of the bootstrap capacitors and are the negative sup-
The serial interface also provides the ability to program various ply connections for the floating high-side drivers.
gate drive and diagnostic parameters.
GLA, GLB, GLC Low-side, gate-drive outputs for external
Integrated diagnostics provide indication of undervoltage, over- N-channel MOSFETs.
temperature, and power bridge faults. They can be configured to
protect the power MOSFETs under most short circuit conditions. LSS Low-side return path for discharge of the capacitance on the
Detailed diagnostic information is available through the serial MOSFET gates, connected to the common sources of the low-
interface. side external MOSFETs through a low impedance track.

Specific functions are described more fully in following sections. CSP, CSM Current sense amplifier inputs. Connect directly to
each end of the sense resistor using separate PCB traces.

Input and Output Terminal Functions PWM PWM input to control high-side switching. When pulsed
low, this turns off any active high-side drivers and turns on the
VBB Main power supply for internal regulators and charge pump. complementary low-side drivers. When held low for longer than
The main power supply should be connected to VBB through a
the PWM brake time, this turns off all high-side drivers and turns
reverse voltage protection circuit and should be decoupled with
on all low-side drivers, when RUN (bit 0 in the Run register) is
ceramic capacitors connected close to the supply and ground
set to 1.
terminals.
RESETN Resets faults when pulsed low. Forces low-power
VDD Logic supply. Compatible with 3.3 V and 5 V logic. This
should be decoupled to ground with a 100 nF capacitor. shutdown (sleep mode) when held low for more than the reset
shutdown width, tRSD . Can be pulled to VBB with 22 kΩ resistor.
CP1, CP2 Pump capacitor connections for charge pump. Connect
a 220 nF ceramic capacitor between CP1 and CP2. SDI Serial data input. 16-bit serial word input, MSB first.

VREG Regulated voltage, nominally 13 V, used to supply the low SDO Serial data output. High impedance when STRN is high.
side gate drivers and to charge the bootstrap capacitors. A suffi- Outputs FF (bit 15 of the Diagnostic register), the Fault flag, as
ciently large storage capacitor must be connected to this terminal soon as STRN goes low.

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A4960 Sensorless BLDC Controller

SCK Serial clock. Data is latched in from SDI on the rising edge Rotor position sensing using motor BEMF
of SCK. There must be 16 rising edges per write and SCK must Determining the rotor position using BEMF sensing relies on
be held high when STRN changes. the accurate comparison of the voltage on the undriven (tri-state)
motor phase (indicated by Z in table 1) to the voltage at the
STRN Serial data strobe and serial access enable. When STRN
centertap of the motor, approximated using a reference voltage at
is high any activity on SCK or SDI is ignored, and SDO is high
half the supply voltage. The BEMF zero crossing, the point where
impedance allowing multiple SDI slaves to have common SDI,
the tri-stated motor winding voltage crosses the reference voltage,
SCK, and SDO connections.
is used as a positional reference. When the motor is running at a
DIAG Diagnostic output. Programmable output to provide four constant speed, this zero crossing occurs approximately halfway
alternative functions: Fault output flag (default), Sensorless through one commutation cycle. Adaptive commutation circuitry
Operation Indicator, internal timer, and VDS threshold. and programmable timers then determine the optimal commuta-
tion points.
TACHO Motor speed output. Provides a pulse signal with a
frequency proportional to the motor speed. TACHO remains low Zero crossings are indicated by the output at the TACHO termi-
until the first BEMF zero-crossing is detected. nal, which goes high at each valid zero crossing and low at the
next commutation point, as shown in figure 9. In each state, the
BEMF detector looks for the first correct polarity (low-to-high
Motor Drive System
The motor drive system consists of three half bridge gate drive State 1 2 3 4 5 6 1 2 3 4 5 6
outputs, each driving one leg of an external 3-phase MOSFET
power bridge. The state of the gate drive outputs is determined
SA
by a state sequencer with six possible states. These states are
shown in table 1 and change in a set sequence depending on the
required direction of rotation. For the A4960, forward is defined
as the state sequence shown in table 1, DIR (Run bit 1) set to 0, SB
incrementing in steps of one from 1 to 6, then repeating from 1.
Reverse (DIR set to 1) is decrementing in steps of one from 6 to
1, then repeating from 6. The effect of these states on the motor
SC
phase voltage is illustrated in figure 11. The point at which the
state of the gate outputs changes is defined as the commutation
point and must occur each time the magnetic poles of the rotor
reach a specific point in relation to the poles of the stator. This TACHO
point is determined by a complete self contained BEMF sensing
scheme with an adaptive commutation timer. Figure 9. Motor phase state sequence, DIR = 0

Table 1. Control and Phase Sequence Table

Control Bits Motor Phase Gate Drive Outputs
State Mode
RUN BRK DIR = 1 DIR = 0 SA SB SC GHA GLA GHB GLB GHC GLC
1 0 1 HI Z LO HI LO LO LO LO HI
1 0 2 Z HI LO LO LO HI LO LO HI
1 0 3 LO HI Z LO HI HI LO LO LO
Run
1 0 4 LO Z HI LO HI LO LO HI LO
1 0 5 Z LO HI LO LO LO HI HI LO
1 0 6 HI LO Z HI LO LO HI LO LO
0 x x x x Z Z Z LO LO LO LO LO LO Coast
1 1 x x x LO LO LO LO HI LO HI LO HI Brake
x: don’t care; HI: high-side MOSFET active; LO: low-side MOSFET active; Z: high impedance, both MOSFETs off

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A4960 Sensorless BLDC Controller

or high-to-low) zero crossing and latches it until the next state BEMF detection but permits the motor to run slower or at a lower
change. This latching action, combined with precise comparator voltage when BEMF detection is achieved.
hysteresis, provides a robust sensing system.
Start-up
There are three variables that effect the BEMF sensing, these are: In order to correctly detect the zero crossing, the changing motor
BEMF on any phase must be detectable when that phase is not
• Commutation Blank Time, tCB
being driven. When the motor is running at a relatively constant
• BEMF Hysteresis, VBHYS speed, this is ensured by the adaptive commutation scheme used.
• BEMF Window, tBW However, during start-up, particularly when the motor load has a
high friction component, the motor must be accelerated from rest
Commutation Blank Time in such a way that the BEMF zero crossing can be detected. Ini-
The BEMF detectors are inhibited for tCB following a commuta- tially, as the motor is started, there is no rotor position informa-
tion event. This prevents any commutation transients and winding tion from the BEMF sensor circuits and the motor must be driven
demagnetization periods from disturbing the BEMF sensing in an open loop 3-phase stepper mode. Unlike a true stepper
system. The commutation blank time is shown in figure 5 and is motor, which is designed for open loop operation, most 3-phase
selected by CB[1:0] (Config0 bits 11:10 ). BLDC motors are unstable when driven in this way and will
overshoot the intended step point by a large margin. To overcome
BEMF Window this limitation the motor must be accelerated such that the motor
The BEMF window is the length of time after any PWM change, movement and the phase step sequence can synchronize to allow
low-to-high or high-to-low, during which the phase voltage and correct BEMF zero crossing detection.
the output of the BEMF comparator is ignored, as shown in
figure 6. It is selected using BW[2:0] (Run bits 9:7). The BEMF The initial start speed, the acceleration rate, and the accelerat-
window is effectively the BEMF comparator blank time. ing torque must be adjusted for each combination of motor and
mechanical load. These parameters can be programmed in the
If the PWM-on time is less than the BEMF window, then the A4960 through the serial interface. Configuration registers Con-
phase voltage is ignored for the whole PWM-on time. If the fig4 and Config5 provide the following programmable param-
PWM-off time is less than the BEMF window, then the phase eters:
voltage is ignored for the whole PWM-off time.
• Config4 bits SC[3:0] – set the start of ramp speed
BEMF Hysteresis
The BEMF hysteresis is the amount by which the BEMF voltage, • Config4 bits EC[3:0] – set the end of ramp speed
measured on the undriven phase, must exceed the normal zero- • Config5 bits RR[3:0] – set the ramp rate
crossing value before zero crossing is detected and TACHO goes
• Config5 bits RQ[3:0] – set the acceleration torque
high. This is illustrated in figures 7 and 8.
To ensure that the motor start-up and sensorless BEMF capture
If the BEMF is falling, then the zero crossing will be detected
is consistent, the start sequencer always forces the motor to a
when the BEMF voltage is lower than the normal zero-crossing
known start position. The time during which the motor is forced
value minus the BEMF hysteresis (figure 7).
into the start position can be programmed through the serial inter-
If the BEMF is rising, then the zero crossing will be detected face using the four hold time bits, HT[3:0] (Config3 bits 3:0).
when the BEMF voltage is higher than the normal zero-crossing The torque applied during this hold time is programmed using
value plus BEMF hysteresis (figure 8). the four hold torque bits, HQ[3:0], (Config3 bits 7:4). These two
variables allow a stable start condition to be achieved for differ-
The BEMF hysteresis is selected using BH[1:0] (Run bits
ent motor and attached mechanical loads.
11:10). It can be set to zero, low (typically 60 mV), high (typi-
cally 240 mV) or Auto. Auto sets the hysteresis to the high level As soon as a valid BEMF zero crossing is detected during the
during start-up and reduces it to the low level during running. start sequence, the A4960 will transition to full BEMF commuta-
This provides added security during start-up in achieving a stable tion and the start sequencer will be reset. The TACHO output

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A4960 Sensorless BLDC Controller

will remain low until the first BEMF zero crossing is detected. braking and no current control is available. Care must be taken to
TACHO will then go high at each BEMF zero crossing and will ensure that the braking current does not exceed the capability of
go low at each commutation point. Sensorless operation is also the low-side MOSFETs.
indicated by a zero in LOS (Diagnostic bit 9), and by a high level
When RUN is set to 1, automatically LOS (Diagnostic bit 9)
when the Sensorless Operation Indicator option is selected on the
is set to 1 and the Sensorless Operation Indicator option on the
DIAG pin output.
DIAG pin output, if selected, is set low until sensorless operation
If sensorless operation cannot be achieved by the end of the is achieved. When RUN is set to 0, or BRK is set to 1, the LOS
acceleration ramp, then the sequencer will reset and retry if RSC bit and the Sensorless Operation Indicator are inactive (LOS set
(Run bit 3) is set to 1. This will continue until stopped by pulling to 0 and DIAG set high).
PWM or RESETN low, or by control via the serial interface. If When the motor is running, the motor speed can be varied by
RSC is set to 0, then the retry will not take place, and the outputs applying a variable duty cycle input to the PWM terminal. The
will remain off and the LOS bit will be set. motor speed will be proportional to the duty cycle of this signal
but will also vary with the mechanical load and the supply volt-
Motor control age. Precise speed control requires an external control loop which
The running state, direction, and speed of the motor are con- can use the PWM input to vary the motor speed within the overall
trolled by a combination of commands through the serial inter- closed loop speed controller. The motor speed can be determined
face and by signals on specific terminals (see Applications by monitoring the TACHO output. When the A4960 is running
Information section). The serial interface provides three control with sensorless commutation, the TACHO output provides a
bits: RUN, DIR, and BRK (Run bits 2:0). square wave output with a frequency proportional to the motor
When RUN is set to 1, the A4960 is allowed to run the motor or speed.
to commence the start-up sequence. When RUN is set to 0 all The PWM input can be driven from 3.3 V or 5 V logic, and
gate drive outputs go low, no commutation takes place, and the has hysteresis and a filter to improve noise performance. When
motor is allowed to coast. Setting RUN to 0 overrides all other pulsed low, any active high-side drivers will be turned off and the
control inputs. complementary low-side drivers will be turned on. This provides
The DIR bit determines the direction of rotation. Forward is high-side chopped, slow-decay PWM with synchronous rectifica-
defined as the state sequence shown in table 1, DIR (Run bit 1) tion.
set to 0, incrementing in steps of one from 1 to 6, then repeating Holding the PWM input low for longer than the PWM brake
from 1. Reverse (DIR set to 1) is decrementing in steps of one time, tBRK , will force a brake condition in the same way as the
from 6 to 1, then repeating from 6. BRK bit in the Run register. The brake will only be active when
The BRK bit can be set to apply an electrodynamic brake which RUN is set to 1.
will decelerate a rotating motor. It also can provide some holding Except for the PWM brake function, the PWM input will be
torque for a stationary motor. When RUN and BRK are both set ignored during start-up, until sensorless commutation is achieved.
to 1, all low-side MOSFETs will be turned on and all high-side It also will also be ignored when BRK is set to 1.
MOSFETs turned off, effectively applying a short between the
motor windings. This allows the reverse voltage generated by Phase advance
the rotation of the motor (motor BEMF) to set up a current in the In some motor control systems, improved motor performance can
motor phase windings that will produce a braking torque. This be achieved by starting to energize the phase windings in advance
braking torque will always oppose the direction of rotation of the of the timing defined by the rotor position. This ensures that the
motor. The strength of the braking or holding torque will depend phase windings have reached the required current level at the
on the motor parameters. No commutation takes place during point where the resulting forward torque on the rotor will be most

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A4960 Sensorless BLDC Controller

effective. It also ensures that the current in the phase windings MOSFET during switching. The charge current for the high-side
will start to decay in time to ensure that the torque produced by drives is provided by the bootstrap capacitors connected between
the decaying phase current will not cause any rotor drag. If cor- the Cx and Sx terminals, one for each phase. The charge and dis-
rectly set up, phase advance can result in greater motor efficiency. charge rate can be controlled using an external resistor in series
In motors that use Hall sensors or rotary decoders this can be with the connection to the gate of the MOSFET.
achieved by a mechanical offset in the sensor position. However
this is only valid for one direction of rotation. Gate drive voltage regulation
The gate drives are powered by an internal regulator which limits
The A4960 overcomes this mechanical limitation by providing a
the supply to the drives and therefore the maximum gate voltage.
programmable electronic method of setting the phase advance in
When the VBB supply is greater than approximately 16 V, the
either direction of rotation. The PA[3:0] (Config5 bits 11:8 ) set-
regulator is a simple linear regulator. Below 16 V, the regulated
ting provides phase advance in electrical commutation angle from
supply is maintained by a charge pump boost converter, which
0° to 28° in steps of 1.9°. This is equivalent to a phase advance up
requires a pump capacitor connected between the CP1 and CP2
to almost half of the commutation period on any one phase. The
pins. This capacitor must have a minimum value of 220 nF, and is
phase advance is automatically always in relation to the motor
typically 470 nF.
direction. There is no need to change the value with a direction
change. The regulated voltage, nominally 13 V, is available on the VREG
pin. A sufficiently large storage capacitor must be connected to
this pin to provide the transient charging current to the low-side
Power Supplies drives and the bootstrap capacitors.
Two power supply voltages are required, one for the logic inter-
face and control, and another one for the analog and output drive Bootstrap charge management
sections. The logic supply, connected to VDD, is a 5 V nominal The A4960 monitors the individual bootstrap capacitor charge
supply, but the TTL threshold logic inputs allow the inputs to be voltages to ensure sufficient high-side drive. Before a high-side
driven from a 3.3 V or 5 V logic interface. drive can be turned on, the bootstrap capacitor voltage must be
higher than the turn-on voltage limit. If this is not the case, then
The normal operating voltage range of the A4960, where the the A4960 will attempt to charge the bootstrap capacitor by acti-
electrical parameters are fully defined, is 7 to 28 V. However, it vating the complementary low-side drive. Under normal circum-
is designed to function correctly up to 50 V during load dump stances this will charge the capacitor above the turn-on voltage in
conditions, and will maintain full operation down to 6 V. Below a few microseconds and the high-side drive will then be enabled.
7 V and above 28 V some parameters may exceed the limits The bootstrap voltage monitor remains active while the high-side
specified for the normal supply voltage range. The A4960 will drive is active, and if the voltage drops below the turn-off volt-
function correctly with a VBB supply down to 5.5 V. However, age, a charge cycle is initiated also.
full sensorless start-up and commutation may not be possible.
The bootstrap charge management circuit may actively charge
The main power supply should be connected to VBB through the bootstrap capacitor regularly when the PWM duty cycle is
a reverse voltage protection circuit. Both supplies should be very high, particularly when the PWM off-time is too short to
decoupled with ceramic capacitors connected close to the supply permit the bootstrap capacitor to become sufficiently charged.
and ground terminals. If, for any reason, the bootstrap capacitor cannot be sufficiently
charged a bootstrap fault will occur. See the Diagnostics section
for further details.
Gate Drives
The A4960 is designed to drive external, low on-resistance, Low-side gate drive
power N-channel MOSFETs. It supplies the large transient The low-side gate drive outputs GLA, GLB, and GLC are refer-
currents necessary to quickly charge and discharge the external enced to the LSS terminal. These outputs are designed to drive
MOSFET gate capacitance in order to reduce dissipation in the external N-channel power MOSFETs. External resistors between

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A4960 Sensorless BLDC Controller

each gate drive output and the gate connection to the respective high-side MOSFET gate capacitance flows through these con-
MOSFET (as close as possible to the MOSFET) can be used to nections which should have low impedance circuit board traces
control the slew rate seen at the gate, thereby providing some to the MOSFET bridge. These terminals also provide the phase
control of the di/dt and dv/dt of the voltage at the SA, SB, and SC voltage feedback to used to determine the rotor position.
terminals. When GLx is set high, the upper half of the driver is
turned on and the drain sources current to the gate of the respec-
tive low-side MOSFET in the external power bridge, turning on Dead Time
the MOSFET. When GLx is set low, the lower half of the driver is To prevent cross conduction (shoot through) in any phase of the
turned on and the drain sinks current from the external MOSFET power MOSFET bridge, it is necessary to have a dead-time delay
gate circuit to the LSS terminal, turning off the MOSFET. LSS is between a high- or low-side turn-off and the next complementary
the low-side return path for discharge of the capacitance on the turn-on event. The potential for cross conduction occurs when
MOSFET gates. It should be connected to the common sources of any complementary high-side and low-side pair of MOSFETs
the low-side external MOSFETs through a low-impedance circuit are switched at the same time, for example, at the PWM
board trace. switchpoints. In the A4960, the dead time for all three phases is
set by the contents of DT[5:0] (Config0 bits 5:0 ). These six bits
High-side gate drive contain a positive integer that determines the dead time by divi-
The high-side gate drive outputs GHA, GHB and GHC are ref- sion from the system clock.
erenced to the SA, SB, and SC pins respectively. These outputs
are designed to drive external N-channel power MOSFETs. The dead time is defined as:
External resistors between each gate drive output and the gate tDEAD = n × 50 ns (1)
connection to the respective MOSFET (as close as possible to the
MOSFET) can be used to control the slew rate seen at the gate,
where n is a positive integer defined by DT[5:0] and tDEAD has a
thereby controlling the di/dt and dv/dt of the voltage at the SA,
minimum programmable value of 100 ns.
SB, and SC terminals. When GHx is set high, the upper half of
the driver is turned on and the drain sources current to the gate of For example, when DT[5:0] contains 011000 (24 in decimal),
the respective high-side MOSFET in the external motor-driving then tDEAD = 1.2 µs (typical).
bridge, turning on the MOSFET. When GHx is set low, the lower
The accuracy of tDEAD is determined by the accuracy of the
half of the driver is turned on and the drain sinks current from the
system clock, as defined in the Electrical Characteristics table,
external MOSFET gate circuit to the respective Sx terminal, turn-
tOSC . A DT[5:0] value of 000000, 000001, or 000010 (0, 1, or 2
ing off the MOSFET.
in decimal) sets the minimum programmable tDEAD of 100 ns.
The CA, CB, and CC pins are the positive supplies for the float-
ing high-side gate drives. The bootstrap capacitors are connected Sleep Mode and RESETN
between the Cx and Sx terminals of the same phase. The boot- RESETN is an active-low input which allows the A4960 to enter
strap capacitors are charged to approximately VREG when the sleep mode, in which the current consumption from the VBB and
associated output Sx terminal is low. When the Sx output swings VDD supplies is reduced to its minimum level. When RESETN
high, the charge on the bootstrap capacitor causes the voltage at is held low for longer than the reset pulse time, tRES , the inter-
the corresponding Cx terminal to rise with the output to provide nal pump regulator and all internal circuitry is disabled and the
the boosted gate voltage needed for the high-side MOSFETs. A4960 enters sleep mode. In sleep mode the latched faults and
corresponding fault flags are cleared.
The SA, SB, and SC terminals are connected directly to the motor
phase connections. These terminals sense the voltages switched When coming out of sleep mode, the protection logic ensures
across the load. They are also connected to the negative side of that the gate drive outputs are off until the charge pump reaches
the bootstrap capacitors and are the negative supply connections its correct operating condition. The charge pump will stabilize in
for the floating high-side drives. The discharge current from the approximately 3 ms under typical conditions. To allow the A4960

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A4960 Sensorless BLDC Controller

to start-up without requiring external logic input, the RESETN where n is a positive integer defined by VR[3:0] (Config1 bits
terminal can be pulled to VBB with an external pull-up resistor. 9:6).
The resistor value should be between 20 and 33 kΩ.
For example, when VR[3:0] contains 1100 (12 in decimal), then
RESETN can also be used to clear any fault conditions without VRI = 81.25%VREF .
entering sleep mode by taking it low for the reset pulse time, VRI is generated by a digital-to-analog converter (DAC) with
tRES . Latched short fault conditions, which disable the outputs, VREF as the reference input to the DAC. VRI will therefore scale
will be cleared as will the serial fault register. directly with VREF .
With the PWM input high, or during start-up when PWM is
Current Limit ignored, when the outputs of the MOSFETs are turned on, current
increases in the motor winding until it reaches a value given by
An integrated fixed off-time PWM current control circuit is
approximately:
provided to limit the motor current during periods when the
torque demand exceeds the normal operating range. It is also VRI
available at start-up to set the hold torque and the ramp torque ITRIP ≈ (3)
AV × RSENSE
if IDS (Config3 bit 8) is set to 0. The fixed off-time is program-
mable through the serial interface and the current limit is set by where
an external sense resistor and a programmable reference voltage
VRI is defined as above,
derived from the voltage at the REF input. During normal run-
ning, the internal current control can be used in conjunction with AV is the gain of the sense amplifier, typically 10, and
any external PWM control on the PWM input by ensuring that RSENSE is the value of the sense resistor.
the programmable off-time of the internal control circuit is longer
than the maximum off-time of the external PWM signal. At the trip point, the sense comparator switches off any active
high-side MOSFETs and switches on the complementary low-
During the start-up sequence, the PWM input is ignored, unless side MOSFETs. This makes the bridge switch from a drive
it is held low in the brake condition. If IDS is set to 0, the current configuration, where the current is forced to increase, into a recir-
limit circuit provides full control over the hold torque and accel- culation configuration, where the motor inductance causes the
eration torque. current to recirculate for a fixed duration defined as the off-time.
During this off-time the current will decay at a rate defined by
Current sense amplifier the motor inductance and the impedance of the MOSFET bridge.
A differential sense amplifier with a gain of 10 is provided to This is classic slow decay PWM current control.
allow the use of low-value sense resistors or a current shunt as
the current sensing element. Fixed off-time
The duration of the fixed off-time is set by the contents of
The output of the sense amplifier is compared to an internally
PT[4:0] (Config2 bits 4:0). These five bits contain a positive
generated reference voltage, VRI , the value of which is pro- integer that determines the off-time derived by division from the
grammed through the serial interface as a ratio of the voltage, system clock.
VREF , at the reference input terminal, REF. When the REF ter-
minal is connected to VDD, VREF is then limited to the reference The off-time is defined as:
clamp voltage, VREFC . tOFF = 10 µs + (n × 1.6 µs) (4)
VRI can have a value between 6.25%VREF and 100%VREF where n is a positive integer defined by PT[4:0].
defined as:
For example, when PT[4:0] contains 11010 (26 in decimal), then
VRI = [(n + 1) × 6.25%] × VREF (2) tOFF = 51.6 µs typically.

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A4960 Sensorless BLDC Controller

The accuracy of tOFF is determined by the accuracy of the system DIAG pin
clock, tOSC , as defined in the Electrical Characteristics table. A The DIAG terminal is a diagnostic output that can be pro-
value of 00000 in PT[4:0] sets the minimum off-time of 10 µs. grammed through the serial interface DG[1:0](Run bits 5:4) to
provide any one of four alternative dedicated diagnostic signals:
Blank time
• the general fault output flag
When the bridge is switched into the drive configuration, a
current spike occurs due to the reverse-recovery currents of • the Sensorless Operation Indicator
the clamp diodes and switching transients related to distributed • the programmed VDS threshold voltage
capacitance in the load. To prevent this current spike from being • a clock signal derived from the internal chip clock
detected as a current limit trip, the current-control compara-
After a power-on reset the DIAG output defaults to the fault out-
tor output is blanked for a short period of time when the source
put flag. The general logic-level fault output flag outputs a low
driver is turned on. The length of the blanking time is set by the
on the DIAG pin to indicate a fault is present. This fault output
contents of BT[3:0] (Config0 bits 9:6). These four bits contain a
flag remains low while an unlatched fault is present or if one of
positive integer that determines the blank time derived by divi-
the latched faults has been detected and the outputs are disabled.
sion from the system clock.
(Note there also is a common Fault flag, described in the Serial
The blank time is defined as: fault output section.)
tBL = n × 400 ns (5) The Sensorless Operation Indicator is a logic level signal that is
set high when the A4960 has achieved sensorless commutation.
where n is a positive integer defined by BT[3:0].
The Sensorless Operation Indicator is set low before sensorless
For example, when BT[3:0] contains 1011 (11 in decimal), then operation is achieved at start-up, or if sensorless operation is lost
tBL = 4.4 µs typically. while the motor should be operating. This indicator is held high
even when the motor is stopped, by setting RUN (Run bit 0) to 0
The accuracy of tBL is determined by the accuracy of the system
or BRK (Run bit 2) to 1.
clock, tOSC , as defined in the Electrical Characteristics table.
The VDS threshold output provides access to the internal thresh-
The blank time is also used with the MOSFET drain-source
old voltage to allow more precise calibration of the MOSFET
monitors, which are used to determine MOSFET short faults.
fault monitor threshold if required.
The blank time is used in these circuits, as shown in figure 4, to
mask the effect of any voltage or current transients caused by any The clock output provides a logic-level square wave output to
PWM switching action. allow more precise calibration of the timing settings if required.
The user must ensure that blank time is long enough to mask any Serial interface fault output
current transient seen by the internal sense amplifier and mask The serial interface allows detailed diagnostic information to be
any voltage transients seen by the drain-source monitors. read from the Diagnostic register at any time.
The first bit (bit 15) of the Diagnostic register contains the com-
Diagnostics mon Fault flag, FF, which is set high when any of the fault bits in
Several diagnostic features are integrated into the A4960 to the Diagnostic register have been set. This allows fault conditions
provide indication of fault conditions. In addition to system-wide to be detected using the serial interface by simply taking STRN
low. As soon as STRN goes low the fist bit in the Diagnostic
faults such as undervoltage and overtemperature, the A4960
register can be read to determine if a fault has been detected at
integrates individual drain-source monitors for each external
any time since the last Diagnostic register reset. In all cases the
MOSFET, to provide short circuit detection.
fault bits in the Diagnostic register are latched and only cleared
The fault status is available from two sources, the DIAG output after a Diagnostic register reset (see Diagnostic Register section
terminal and the serial interface. on serial access).

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A4960 Sensorless BLDC Controller

Note that FF does not provide the same function as the general register, then the corresponding diagnostic will be completely
fault output flag output on the DIAG pin (described above). The disabled. No fault states for the disabled diagnostic will be gener-
fault output on the DIAG pin provides an indication that certain ated and neither the general fault output flag (DIAG pin) nor bits
types of faults are present and in some cases that the outputs have in the Diagnostic register will be set.
been disabled. FF provides an indication that certain types of
The VDD Undervoltage and VREG Undervoltage faults can-
faults have occurred since the last Diagnostic register reset and
not be masked. VDD undervoltage detection cannot be disabled
the respective fault bit has been set.
because the diagnostics and the output control depend on VDD
to operate correctly. VREG undervoltage detection cannot be
Fault response action
For certain fault conditions, the response of the A4960 is deter- disabled because it is safe to turn on the gate drive outputs only
mined by the state of the Enable Stop on Fault bit, ESF (Run when VREG is at a sufficiently high voltage.
bit 6), as shown in table 2. When a short fault or overtemperature Note: Care must be taken when diagnostics are disabled to avoid
condition is detected, if ESF is set to 1 the A4960 disables all potentially damaging conditions.
the gate drive outputs and coasts the motor. For short faults, this
disabled state will be latched until RESETN goes low, a serial Chip-level diagnostics
interface read is completed, or a power-on reset occurs. For Parameters critical for safe operation of the A4960 and the
undervoltage fault conditions, the outputs will always be dis- external MOSFETs are monitored. These include: maximum
abled, regardless of the ESF bit setting. chip temperature, minimum logic supply voltage, and the vari-
When ESF is set to 0, although the general fault output flag ous minimum voltages required to drive the external MOSFETs
(DIAG pin) is still activated (low), the A4960 will not disrupt (VREG and each of the bootstrap voltages). Note that the main
normal operation under most conditions, and will therefore not supply voltage, VBB , is not monitored for minimum voltage. This
protect the motor or the drive circuit from damage. It is impera- is because the critical minimum voltages are generated by the
tive that the application master control circuit or other external charge pumps internal to the A4960. When a fault is present, the
circuit takes any necessary action when a fault occurs, to prevent general fault output flag (DIAG pin) will be active (low).
damage to components. Chip Fault States: Temperature Thresholds
Two temperature threshold actions are provided: a high tempera-
Fault Mask register ture warning and an overtemperature shutdown.
Certain individual diagnostics can be disabled by setting the cor-
responding bit in the Mask register. If a bit is set to 1 in the Mask • If the chip temperature rises above the Temperature Warning
Threshold, TJW , the general fault output flag (DIAG pin) goes
low and the High Temperature Warning bit, TW (Diagnostic
Table 2: Fault Response Actions bit 11) and the common Fault flag bit, FF (bit 15), are set to 1. No
Disable Outputs Fault other action is taken by the A4960. When the temperature drops
Fault Description
ESF = 0 ESF = 1 Latched below TJW by more than the hysteresis value, TJWHys , the general
No fault No No n.a. fault output flag (DIAG pin) goes high, but TW and FF remain
VDD Undervoltage Yes* Yes* No set in the Diagnostic register until a register reset.
VREG Undervoltage Yes* Yes* No • If the chip temperature rises above the Overtemperature Thresh-
Bootstrap Undervoltage Yes* Yes* Yes old, TJF , the general fault output flag (DIAG pin) goes low and
Temperature Warning No No No the overtemperature bit, TS (Diagnostic bit 10) and the common
Overtemperature No Yes* No Fault flag bit, FF (bit 15), are set to 1. When ESF (Run bit 6) is
Short to Ground No Yes*
set to 1, if an overtemperature is detected, all gate drive outputs
Only will be disabled automatically. If an overtemperature condition
Short to Supply No Yes* when
ESF = 1 occurs when ESF is set to 0, then no circuitry will be disabled
Shorted Load No Yes*
and action must be taken by the user to limit the power dissipa-
* All gate drives low, all MOSFETs off

20
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A4960 Sensorless BLDC Controller

tion in some way, so as to prevent overtemperature damage to the Bootstrap Undervoltage Fault State
chip and unpredictable device operation. When the temperature In addition to a monitor on VREG , the A4960 also monitors the
drops below TJF by more than the hysteresis value, TJFHys , the individual bootstrap capacitor charge voltages to ensure sufficient
general fault output flag (DIAG pin) goes high, but the overtem- high-side drive. Before a high-side drive can be turned on, the
perature bit, TS, and FF remain set in the Diagnostic register until bootstrap capacitor voltage must be higher than the turn-on volt-
cleared. age limit, VBOOTUV + VBOOTUVHys . If this is not the case, then the
Chip Fault State : VREG Undervoltage A4960 will attempt to charge the bootstrap capacitor by activat-
The internal charge-pump regulator supplies the low-side gate ing the complementary low-side drive. Under normal circum-
driver and the bootstrap charge current. Before enabling any stances this will charge the capacitor above the turn-on voltage in
of the outputs, it is critical to ensure that the regulated voltage, a few microseconds and the high-side drive will then be enabled.
VREG , at the VREG terminal is sufficiently high. The bootstrap voltage monitor remains active while the high-
If VREG goes below the VREG Undervoltage Threshold, side drive is active, and if the voltage drops below the turn-off
VREGUVOFF , the general fault output flag (DIAG pin) goes low voltage, VBOOTUV , a charge cycle is also initiated. In either case,
and the VREG undervoltage bit, VR (Diagnostic bit 13) and the if there is a fault that prevents the bootstrap capacitor charg-
common Fault flag bit, FF (bit 15), are set to 1. All gate drive ing, then the charge cycle will time out, the general fault output
outputs go low, the motor drive is disabled, and the motor coasts. flag (DIAG pin) will go low, and the outputs will be disabled.
When VREG rises above VREGUVON, the gate drive outputs are re- The appropriate bit (VA, VB, or VC, according to the phase) in
enabled and the general fault output flag (DIAG pin) goes high. the Diagnostic register will be set to allow the faulty bootstrap
The fault bit, VR, and FF remain set in the Diagnostic register capacitor to be determined by reading the serial data word from
until cleared. the Diagnostic register.

The VREG undervoltage monitor circuit is active during power- The bootstrap undervoltage fault state will be latched until
up. The general fault output flag (DIAG pin) is low and all gate RESETN is set low, a serial interface read is completed, or a
drives will be low until VREG is greater than approximately 8 V. power-on reset occurs due to a VDD undervoltage on the logic
Note that this is sufficient to turn on standard-threshold, external supply.
power MOSFETs at a battery voltage as low as 5.5 V, but the
on-resistance of the MOSFET may be higher than its specified MOSFET fault detection
maximum. Faults on external MOSFETs are determined by measuring the
drain-source voltage of the MOSFET and comparing it to the
Chip Fault State: VDD Undervoltage Drain-Source Threshold Voltage, VDSTH , defined by VT[5:0]
The logic supply voltage, VDD , at the VDD terminal is monitored (Config1 bits 5:0). These bits provide the input to a 6-bit DAC
to ensure correct logical operation. If VDD drops below the VDD with a least significant bit value of typically 25 mV. The output of
Undervoltage Threshold, VDDUV , then the logical function of the DAC produces VDSTH , defined as approximately:
the A4960 cannot be guaranteed and the outputs will be imme-
diately disabled. The A4960 will enter a power-down state and VDSTH ≈ n × 25 mV (6)
all internal activity, other than the VDD voltage monitor, will be
suspended. where n is a positive integer defined by VT[5:0].
When VDD rises above the rising undervoltage threshold, VDDUV For example, when VT[5:0] contains 101000 (40 in decimal),
+ VDDUVHys , the A4960 will perform a power-on reset. All serial then VDSTH = 1 V typically. The accuracy of VDSTH is defined in
control registers will be reset to their power-on state, all fault the Electrical Characteristics table.
conditions and fault-specific bits in the Diagnostic register will be
The low-side drain-source voltage for any MOSFET is mea-
reset, and the general fault output flag (DIAG pin) will go high.
sured between the LSS terminal and the appropriate Sx terminal.
The FF bit and the POR bit (Diagnostic bits 15 and 14) will be set
Using the LSS terminal rather than the ground connection avoids
to 1 to indicate that a power-on reset has taken place.
adding any low-side current sense voltage to the real low-side
The same power-on reset sequence occurs for initial power-on, drain-source voltage. The high-side drain-source voltage for
and also for a VDD “brown-out,” where VDD drops below VDDUV any MOSFET is measured between the VBRG terminal and the
only momentarily. appropriate Sx terminal. Using the VBRG terminal rather than the

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A4960 Sensorless BLDC Controller

bridge supply avoids adding any high-side current sense voltage fault will be detected. If ESF (Run bit 6) is set to 1 this fault will
to the real high-side drain-source voltage. be latched and the MOSFET disabled until there is an A4960
Diagnostic register reset.
The VBRG terminal is a low-current sense input to the top of
the external MOSFET bridge. It should be connected directly to If a short circuit fault occurs when ESF is set to 0, then the
the common connection point for the drains of the power bridge external MOSFETs are not disabled by the A4960. To limit any
MOSFETs at the positive supply connection point. The input damage to the external MOSFETs or the motor, the A4960 should
current to the VBRG terminal is proportional to the drain-source either be fully disabled by the RESETN input or all MOSFETs
threshold voltage, VDSTH , and is approximately: switched off by setting RUN (bit 0 in the Run register) to 0,
IVBRG = 72 × VVBRG + 52 (7) through a serial interface write. Alternatively, setting the ESF bit
to 1will allow the A4960 to disable the MOSFETs as soon as a
where IVBRG is the current into the VBRG terminal in µA and fault is detected.
VDSTH is the Drain-Source Threshold Voltage, described above. MOSFET Fault State: Short to Supply
Note that the VBRG terminal can withstand a negative voltage A short from any of the motor phase connections to the battery
as great as –5 V. This allows the terminal to remain connected or VBB connection is detected by monitoring the voltage across
directly to the top of the power bridge during negative transients the low-side MOSFETs in each phase using the respective Sx
where the body diodes of the power MOSFETs are used to clamp terminal and the LSS terminal. This drain-source voltage is then
the negative transient. The same applies to the more extreme case compared to the Drain-Source Threshold Voltage, VDSTH , after
where the MOSFET body diodes are used to clamp a reverse bat- a blank time. While the drain source voltage exceeds VDSTH , the
tery connection. general fault output flag (DIAG pin) will be low and, when ESF
MOSFET fault blank time is set to 1, it will be latched low and the outputs will be disabled.
To avoid false MOSFET fault detection during switching tran- MOSFET Fault State: Short to Ground
sients the VDS-to-VDSTH comparison is delayed, following a A short from any of the motor phase connections to ground
MOSFET turn-on, by the internal blank timer. This is the same is detected by monitoring the voltage across the high-side
blank time as used for current sensing phase voltage monitoring. MOSFETs in each phase using the respective Sx terminal and the
The length of the blanking time is set by the contents of BT[3:0] voltage at VBRG. This drain-source voltage is then compared to
(Config0 bits 9:6 ). These four bits contain a positive integer that the Drain-Source Threshold Voltage, VDSTH , after a blank time.
determines the blank time derived by division from the system While the drain source voltage exceeds VDSTH the general fault
clock. output flag on the DIAG pin will be low and, when ESF is set to
The blank time is defined as in equation 5: 1, it will be latched low and the outputs will be disabled.
tBL = n × 400 ns Note: The distinction between short to ground and short to supply
where n is a positive integer defined by BT[3:0]. can only be made by examining the serial Diagnostic register.
The general fault output flag (DIAG pin) simply indicates the
For example, when BT[3:0] contains 1001 (9 in decimal), then presence of a probable short circuit.
tBL = 3.6 µs typically.
MOSFET Fault State: Shorted Winding
The accuracy of tBL is determined by the accuracy of the system The short to ground and short to supply detection circuits will
clock, tOSC , as defined in the Electrical Characteristics table. also detect a short across a motor phase winding. In most cases
Short fault operation a shorted winding will be indicated by a high-side and low-side
Power MOSFETs take a finite time to reach the rated on-resis- fault latched at the same time in the Diagnostic register. In some
tance, so the measured drain-source voltages may show a fault as cases the relative impedances may only permit one of the shorts
the phase switches. To overcome this and avoid false short fault to be detected. In any case when a short of any type is detected
detection, the voltages are not sampled until a blank time elapses the general fault output flag (DIAG pin) will go low and, when
after the external MOSFET is turned on. If the drain-source volt- ESF is set to 1, it will be latched low and the outputs
age remains above the threshold after the blank time, then a short will be disabled.

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A4960 Sensorless BLDC Controller

Serial Interface Description SCK, and SDO connections. Each slave then requires an indepen-
dent STRN connection.
A three wire synchronous serial interface, compatible with SPI,
is used to control the features of the A4960. A fourth wire can When 16 data bits have been clocked into the shift register,
be used to provide diagnostic feedback and read back of register STRN must be taken high to latch the data into the selected regis-
contents. ter. When this occurs, the internal control circuits act on the new
data and the Diagnostic register is reset.
The A4960 can be started only by using the serial interface to set
the RUN bit (Run bit 0) to 1. Application specific settings are If there are more than 16 rising edges on SCK, or if STRN goes
configured by setting the appropriate register bits through the high and there are fewer than 16 rising edges on SCK, the write
serial interface. will be cancelled without writing data to the registers. In addition
the Diagnostic register will not be reset and the FF bit (Diagnotic
The serial interface timing requirements are specified in the
bit 15) will be set to 1 to indicate a data transfer error.
Electrical Characteristics table, and illustrated in figure 1. Data is
received on the SDI terminal and clocked through a shift register Diagnostic information or the contents of the configuration and
on the rising edge of the clock signal input on the SCK terminal. control registers is output on the SDO terminal, MSB first, while
STRN is normally held high, and is brought low only to initiate a STRN is low. The output stream changes to the next bit on each
serial transfer. No data is clocked through the shift register when falling edge of SCK. The first bit, which is always the FF bit, is
STRN is high, allowing multiple slave units to use common SDI, output as soon as STRN goes low.

Table 3. Serial Registers Definition

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CB1 CB0 BT3 BT2 BT1 BT0 DT5 DT4 DT3 DT2 DT1 DT0
Config 0 (Blank,Dead) 0 0 0 WR
0 0 1 0 0 0 0 1 0 1 0 0

VR3 VR2 VR1 VR0 VT5 VT4 VT3 VT2 VT1 VT0
Config 1 (VREF,VDSTH) 0 0 1 WR
0 0 1 1 1 1 1 0 0 0 0 0

PT4 PT3 PT2 PT1 PT0

Config 2 (PWM) 0 1 0 WR
0 0 0 0 0 0 0 1 0 0 0 0

IDS HQ3 HQ2 HQ1 HQ0 HT3 HT3 HT1 HT0

Config 3 (Hold) 0 1 1 WR
0 0 0 0 0 1 0 1 0 1 0 0

EC3 EC2 EC1 EC0 SC3 SC2 SC1 SC0

Config 4 (Start Com) 1 0 0 WR
0 0 0 0 1 1 1 1 0 1 0 0

PA3 PA2 PA1 PA0 RQ3 RQ2 RQ1 RQ0 RR3 RR2 RR1 RR0
Config 5 (Ramp) 1 0 1 WR
0 0 0 0 1 0 0 0 0 0 0 0

TW TS LOS VA VB VC AH AL BH BL CH CL
Mask 1 1 0 WR
0 0 0 0 0 0 0 0 0 0 0 0

BH1 BH0 BW2 BW1 BW0 ESF DG1 DG0 RSC BRK DIR RUN
Run 1 1 1 WR
0 0 1 0 0 0 0 0 0 0 0 0

FF POR VR TW TS LOS VA VB VC AH AL BH BL CH CL
Diagnostic
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*Power-on reset value shown below each input register bit.

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A4960 Sensorless BLDC Controller

Each of the 8 configuration and control registers has a write bit, Config2 Configuration Register 2 contains PWM settings:
WR (bit 12), as the first bit after the register address (bits 15:13). PT[4:0], a 5-bit integer to set the off-time for the PWM cur-
This bit must be set to 1 to write the subsequent bits into the rent control used to limit the motor current during start-up and
selected register. If WR is set to 0 then the remaining data bits normal running
(bits 11:0) are ignored.
Config3 Configuration Register 3 contains start-up hold settings:
The state of the WR bit also determines the data output on SDO.
By setting the WR bit to 1, writing to any register will allow the • IDS, to select between current control and duty cycle control to
Diagnostic register to be read at the SDO output. If WR is set set the initial holding torque.
to 0, then the output is the contents of the register addressed by • HQ[3:0], a 4-bit integer to set the holding torque for the initial
the first three input bits. In all cases the first three bits output on start position. The holding torque is set by an internally gener-
SDO will always be the FF, POR, and VR bits from the Diagnos- ated PWM duty cycle or by internal PWM current control.
tic register. ▫ If IDS is set to zero then HQ[3:0] selects the hold current in
increments of 6.25%.
Configuration and control registers
The serial data word is 16 bits, input MSB first, with the first ▫ If IDS is set to one then HQ[3:0] selects the duty cycle in
three bits defined as the register address. This provides eight writ- increments of 6.25%.
able registers: • HT[3:0], a 4-bit integer to set the hold time of the initial start
• Six registers are used for configuration: one for blank time and position in increments of 8 ms from 2 ms.
dead time programming, one for current and voltage limits, one Config4 Configuration Register 4 contains start-up timing set-
for PWM set-up parameters, and three for start-up parameters. tings:
• The seventh register is the fault Mask register, which provides • EC[3:0], a 4-bit integer to set the end commutation time in
the ability to disable individual diagnostics. increments of 200 µs.
• The eighth register is the Run register, containing motor control • SC[3:0], a 4-bit integer to set the start commutation time in
inputs. increments of 8 ms.
Config0 Configuration register 0 contains basic timing
Config5 Configuration Register 5 contains start-up ramp settings:
settings:
• PA[3:0], a 4-bit integer to set the phase advance in increments
• CB[1:0], 2 bits to select the commutation blank time, tCB of 1.875° (electrical degrees)
• BT[3:0], a 4-bit integer to set the blank time, tBL , in 400 ns
• RQ[3:0], a 4-bit integer to set the torque during ramp-up. The
increments
ramp torque is set by an internally generated PWM duty cycle
• DT[5:0], a 6-bit integer to set the dead time, tDEAD , in 50 ns or by internal PWM current control.
increments
▫ If ISD is set to zero then RQ[3:0] selects the hold current in
Config1 Configuration Register 1 contains basic voltage increments of 6.25%.
settings:
▫ If ISD is set to one then RQ[3:0] selects the duty cycle in
• VR[3:0], a 4-bit integer to set the current limit reference volt- increments of 6.25%.
age, VRI , as a ratio of the voltage at the REF terminal, VREF • RR[3:0], a 4-bit integer to set the acceleration rate during the
• VT[5:0], a 6-bit integer to set the Drain-Source Threshold Volt- forced commutation ramp up. Sets the reduction in commuta-
age, VDSTH , in 25 mV increments tion time, in 200 µs steps, at each commutation change.

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A4960 Sensorless BLDC Controller

Mask This register contains a fault masking bit for each fault Diagnostic register
bit in the Diagnostic register. If a bit is set to one in the Mask There is one diagnostic register in addition to the eight writable
register then the corresponding diagnostic will be completely registers. Each time a register is written, the Diagnostic register
disabled. No fault states for the disabled diagnostic will be gener- can be read, MSB first, on the serial output terminal, SDO (see
ated and no fault flags or diagnostic bits will be set. serial timing diagram, figure 1). The Diagnostic register contains
fault flags for each fault condition and a general fault flag. When-
Run This register contains various bits to set running conditions: ever a fault occurs, the corresponding flag bit in the Diagnostic
• BH[1:0], 2 bits to select the BEMF hysteresis. register will be set and latched.

• BW[2:0], 3 bits to select the BEMF window. The fault flags in the Diagnostic register are reset only on the
completion of a serial interface access, or when the RESETN
• ESF, the Enable Stop on Fault bit; defines the action taken input is low for the Reset Pulse Width, tRES. Resetting the
when a short is detected. See Diagnostics section for details of Diagnostic register only affects latched faults that are no longer
fault actions. present. For any static faults that are still present, for example
• DG[1:0], 2 bits to select the output routed to the DIAG termi- overtemperature, the fault flag will remain set after the register
nal. The default output is the general fault output flag, which reset.
is a low true (active low) signal that is active anytime a fault At power-up or after a power-on reset, the FF bit and the POR bit
is present or a fault state has been latched. The second option are set and all other bits are reset. This indicates to the external
sets the DIAG output high whenever the A4960 is running with controller that a power-on reset has taken place and all registers
sensorless commutation. The other two outputs provide an ex- have been reset. Note that a power-on reset only occurs when the
ternal controller with the facility to read back the drain-source VDD supply rises above its undervoltage threshold. Power-on
threshold voltage, or to measure the system clock frequency for reset is not affected by the state of the VBB supply or VREG.
calibration. The first bit in the register is the diagnostic register flag, FF. This
• RSC, the Restart control bit. is high if any bits in the diagnostic register are set or if a serial
▫ When set to 1 allows restart after loss of BEMF synchroniza- write error has occurred. When STRN goes low to start a serial
write SDO comes out of its high impedance state and outputs
tion if RUN is 1 and BRK is 0.
the serial register fault flag. This allows the main controller to
▫ When set to 0 the motor will coast to a stop when bemf syn- poll the A4960 through the serial interface to determine if a fault
chronization is lost. has been detected. If no faults have been detected then the serial
• BRK, brake control. transfer may be terminated without generating a serial read fault
by ensuring that SCK remains high while STRN is low. When
• DIR, direction control. STRN goes high the transfer will be terminated and SDO will go
• RUN, enables the A4960 to start and run the motor. into its high impedance state.

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A4960 Sensorless BLDC Controller

Serial Register Reference

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CB1 CB0 BT3 BT2 BT1 BT0 DT5 DT4 DT3 DT2 DT1 DT0
Config 0 0 0 0 WR
0 0 1 0 0 0 0 1 0 1 0 0

VR3 VR2 VR1 VR0 VT5 VT4 VT3 VT2 VT1 VT0
Config 1 0 0 1 WR
1 1 1 1 1 0 0 0 0 0
*Power on reset value shown below each input register bit.

Configuration Register 0 Configuration Register 1

CB[1:0] Commutation blank time VR[3:0] Current sense reference ratio for normal running
CB1 CB0 Blank Time Default conditions.
0 0 50µs D
0 1 100µs Typically:
1 0 400µs
V RI = (n +1) × 6 . 25 %V REF
1 1 1ms
where n is a positive integer defined by VR[3:0]
The accuracy of tCB is determined by the system clock
e.g. for the power-on-reset condition
frequency as defined in the electrical characteristics table.
VR[3:0] = [1 1 1 1] then VRI=VREF
BT[3:0] Blank time If the REF terminal is connected to VDD then VREF is
t BL = n × 400 ns clamped to VREFC.
where n is a positive integer defined by BT[3:0] The range of VRI is 6.25% VREF to 100%VREF.
e.g. for the power-on-reset condition
BT[3:0] = [1 0 0 0] then tBL=3.2µs VT[5:0] VDS Threshold.
The range of tBL is 0 to 6µs. Typically:
The accuracy of tBL is determined by the system clock
V DSTH = n × 25 mV
frequency as defined in the electrical characteristics table. where n is a positive integer defined by VT[5:0]
e.g. for the power-on-reset condition
DT[5:0] Dead time VT[5:0] = [1 0 0 0 0 0] then VDSTH=800mV
t DEAD = n × 50 ns
The range of VDSTH is 0 to 1.575V.
where n is a positive integer defined by DT[5:0]
e.g. for the power-on-reset condition
DT[5:0] = [0 1 0 1 0 0] then tDEAD=1µs
The range of is 100ns to 3.15µs. Selecting a value of 0, 1
or 2 will set the dead time to 100ns.
The accuracy of tDEAD is determined by the system clock
frequency as defined in the electrical characteristics table.

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A4960 Sensorless BLDC Controller

Serial Register Reference

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PT4 PT3 PT2 PT1 PT0

Config 2 (PWM) 0 1 0 WR
1 0 0 0 0

IDS HQ3 HQ2 HQ1 HQ0 HT3 HT3 HT1 HT0

Config 3 (Hold) 0 1 1 WR
0 0 1 0 1 0 1 0 0
*Power on reset value shown below each input register bit.

Configuration Register 2 Configuration Register 3

PT[4:0] Fixed off time IDS Start-up Torque control method
t OFF = 10 µs +( n × 1 .6 µs ) IDS Start-up Torque control Default
0 Current limited D
where n is a positive integer defined by PT[4:0]
1 Duty cycle limited
e.g. for the power-on-reset condition
PT[4:0] = [1 0 0 0 0] then tOFF=35.6µs HQ[3:0] Current sense reference ratio or duty cycle ratio
The range of tOFF is 10µs to 59.6µs. for hold torque during initial start sequence.
The accuracy of tOFF is determined by the system clock If IDS is 0 then HQ[3:0] sets the hold current.
frequency as defined in the electrical characteristics table. If IDS is 1 then HQ[3:0] sets the hold duty cycle.
Typically:
V RH = ( n + 1)× 6 . 25 %V REF ...... when IDS=0
D H = (n + 1 )× 6 . 25 % ............... when IDS=1
where n is a positive integer defined by HQ[3:0]
e.g. for the power-on-reset condition
HQ[3:0] = [0 1 0 1] then
VRH=37.5%VREF ...................... when IDS=0
DH=37.5% ............................... when IDS=1
The range of VRH is 6.25% VREF to 100%VREF.
The range of DH is 6.25% to 100%.
The accuracy of VRH and DH is defined in the electrical
characteristics table.
HT[3:0] Hold Time.
t HOLD = 2 ms + (n × 8 ms)
where n is a positive integer defined by HT[3:0]
e.g. for the power-on-reset condition
HT[3:0] = [0 1 0 0] then tHOLD=34ms
The range of tHOLD is 2ms to 122ms.
The accuracy of tHOLD is determined by the system clock
frequency as defined in the electrical characteristics table.

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A4960 Sensorless BLDC Controller

Serial Register Reference

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EC3 EC2 EC1 EC0 SC3 SC2 SC1 SC0

Config 4 (Start Com) 1 0 0 WR
1 1 1 1 0 1 0 0

PA3 PA2 PA1 PA0 RQ3 RQ2 RQ1 RQ0 RR3 RR2 RR1 RR0
Config 5 (Ramp) 1 0 1 WR
0 0 0 0 1 0 0 0 0 0 0 0
*Power on reset value shown below each input register bit.

Configuration Register 4
RQ[3:0] Current sense reference ratio or duty cycle ratio
EC[3:0] End Commutation time for torque during forced commutation ramp-up.
t COME = ( n + 1 )× 0 .2 ms If IDS is 0 then RQ[3:0] sets the ramp current.
where n is a positive integer defined by EC[3:0] If IDS is 1 then RQ[3:0] sets the ramp duty cycle.
e.g. for the power-on-reset condition Typically:
EC[3:0] = [1 1 1 1] then tCOME=3.2ms
V RR = ( n + 1)× 6 . 25 % V REF ........ when IDS=0
The range of tCOME is 0.2ms to 3.2ms.
The accuracy of tCOME is determined by the system clock D R = ( n +1 )× 6 .25 % ................. when IDS=1
frequency as defined in the electrical characteristics table.
where n is a positive integer defined by RQ[3:0]
SC[3:0] Start commutation time e.g. for the power-on-reset condition
t COMS = ( n + 1) × 8 ms RQ[3:0] = [1 0 0 0] then
VRH=56.25%VREF .................... when IDS=0
where n is a positive integer defined by SC[3:0]
DH=56.25% ............................. when IDS=1
e.g. for the power-on-reset condition
The range of VRR is 6.25% VREF to 100%VREF.
SC[3:0] = [0 1 0 0] then tCOMS=40ms
The range of DR is 6.25% to 100%.
The range of is 8ms to 128ms.
The accuracy of VRR and DR is defined in the electrical
The accuracy of tCOMS is determined by the system clock
characteristics table.
frequency as defined in the electrical characteristics table.
RR[3:0] Ramp rate.
Decrease in commutation time at each
commutation change.
Configuration Register 5
Typically at each commutation change:
PA[3:0] Phase Advance.
t COM ( next ) = t COM – (n + 1)× 0.2ms
Typically:
where tCOM(next) is the next commutation time in ms,
θ ADV = n × 1 .875 ° ( electrical )
tCOM is the present commutation time in ms,
where n is a positive integer defined by PA[3:0] and n is a positive integer defined by RR[3:0]
e.g. for the following condition e.g. for the condition RR[3:0] = [0 1 1 1]
PA[3:0] = [1 0 0 0] then θADV=15° the commutation time will be reduced by 1.6ms at
The range of θADV is 0 to 28.125° (electrical) each commutation change.
The accuracy of θADV is defined in the electrical The range of RR is 0 to 15.
characteristics table. The range of the commutation change is 0.2ms to 3.2ms.
The accuracy of RR is determined by the system clock
frequency as defined in the electrical characteristics table.

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A4960 Sensorless BLDC Controller

Serial Register Reference

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BH1 BH0 BW2 BW1 BW0 ESF DG1 DG0 RSC BRK DIR RUN
Run 1 1 1 WR
0 0 1 0 0 0 0 0 0 0 0 0
*Power on reset value shown below each input register bit.

Run Register
BH[1:0] BEMF Hysteresis. RSC Restart control
BH1 BH0 Hysteresis Default RSC Restart Default
0 0 Auto High Start/Low Run D 0 No restart D
0 1 None 1 Allow restart after loss of sync
1 0 High
1 1 Low BRK Brake
BRK Recirculation Default
BW[2:0] BEMF Window. 0 Brake off – normal operation D
BW2 BW1 BW0 Window Default 1 Brake on – slow decay recirculation
0 0 0 0.4µs
0 0 1 0.8µs DIR Direction of Rotation
0 1 0 1.6µs DIR Direction Default
0 1 1 3.2µs 0 Forward (Table 1 states 1to 6) D
1 0 0 6.4µs D 1 Reverse (Table 1 states 6 to 1)
1 0 1 12.8µs
RUN Run enable
1 1 0 25.6µs
RUN Recirculation Default
1 1 1 51.2µs
0 Disable outputs, coast motor D
ESF Enable Stop on Fail 1 Start and run motor
ESF Recirculation Default
1 Stop on fail. Report fault.
0 No stop on fail, Report fault. D

DG[1:0] Selects signal routed to DIAG output.

DG1 DG0 Signal on DIAG pin Default
0 0 Fault– low true D
0 1 LOS – low true
1 0 VDSTH
1 1 Clock

29
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4960 Sensorless BLDC Controller

Serial Register Reference

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TW TS LOS VA VB VC AH AL BH BL CH CL
Mask 1 1 0 WR
0 0 0 0 0 0 0 0 0 0 0 0

FF POR VR TW TS LOS VA VB VC AH AL BH BL CH CL
Diagnostic
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*Power on reset value shown below each input register bit.

Mask Register Diagnostic Register

FF General Fault flag
POR Power-on-reset
VR Undervoltage
TW Temperature warning TW High temperature warning
TS Thermal shutdown TS Over temperature shutdown
LOS Loss of bemf synchronization LOS bemf synchronization lost
VA Bootcap A fault VA Fault on bootcap A
VB Bootcap B fault VB Fault on bootcap B
VC Bootcap B fault VC Fault on bootcap C
AH Phase A high-side VDS AH VDS fault detected on Phase A high-side
AL Phase A low-side VDS AL VDS fault detected on Phase A low-side
BH Phase B high-side VDS BH VDS fault detected on Phase B high-side
BL Phase B low-side VDS BL VDS fault detected on Phase B low-side
CH Phase C high-side VDS CH VDS fault detected on Phase C high-side
CL Phase C low-side VDS CL VDS fault detected on Phase C low-side

xx Fault mask Default xx Fault

0 Fault detection permitted D 0 No fault detected
1 Fault detection disabled 1 Fault detected

30
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4960 Sensorless BLDC Controller

Applications Information

Control Timing Diagrams

RUN

BRK

Motor State Coast Hold Ramp Run Coast Brake

tHOLD
TACHO

DIAG

LOS

Figure 9. Control example: Start from coast, coast, then brake to stop

PWM PWM duty cycle ignored PWM duty cycle used to vary speed

RUN
tBRK
BRK

Motor State Coast Brake Hold Ramp Run pwm off Brake

tHOLD
TACHO

DIAG

LOS

Figure 10. Control example: Start from brake, PWM brake to stop

PWM PWM duty cycle ignored PWM duty cycle used to vary speed

RUN tBRK tBRK

Motor State Coast Brake Hold Ramp Run Coast Brake

tHOLD
TACHO

DIAG

LOS

Figure 11. Control example: Start from PWM, coast, then PWM brake to stop

31
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4960 Sensorless BLDC Controller

Input/Output Structures

(a) Gate Drive Outputs (b) Supplies

Cx

18V VBRG VBB

18V
GHx
18V 7.5V

14V CP1 CP2 VDD VREG

Sx

VREG
18V 18V

18V 18V 18V 6V 18V

18V
18V GLx
14V 14V

LSS

(c) PWM, SDI, and SCK Inputs (d) STR Inputs (e) RESETN Inputs
VDD VDD VDD VDD

50 kΩ

PWM 2 kΩ 2 kΩ 2 kΩ
SDI STR RESET
SCK
50 kΩ 80 kΩ
6V 6V 6V 6V 7.5V 7.5V

(f) Sense Inputs (g) REF Inputs (h) Logic Outputs

VDD
VREG

18V
80 kΩ 25 Ω SDO
5 kΩ REF TACHO
CSP
CSM DIAG

6V
6V 6V 6V

32
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4960 Sensorless BLDC Controller

Package JP, 32-Pin LQFP

With Exposed Thermal Pad

For Reference Only – Not for Tooling Use

(Reference Allegro DWG-0000386, Rev. 5 or JEDEC MS-026 BBAHD)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

9.00 BSC 0.55 0.80

1.65
7.00 BSC 7º
3.5° ±3.5
0º
0.20 MAX
0.09 MIN

B
9.00 BSC 7.00 BSC
5.00 NOM 5.00 8.60

0.60 ±0.15
1.00
32 A REF 32

1 2
0.25 BSC 1 2
5.00 NOM
SEATING PLANE
5.00
GAUGE PLANE
Branded Face 8.60
C PCB Layout Reference View
32× C
SEATING
0.10 C PLANE
+0.08
0.37 –0.07 0.80 BSC
1.50 ±0.10
1.40 ±0.05
XXXXXXXXX
0.10 ±0.05
Date Code
Lot Number

A Terminal #1 mark area

B Exposed thermal pad (bottom surface); exact dimensions may vary with device
C Reference land pattern layout (reference IPC7351
QFP80P900X900X160-32BM); adjust as necessary to D Standard Branding Reference View
meet application process requirements and PCB layout Line 1, 2, 3: Maximum 9 characters per line
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal Line 1: Part Number
dissipation (reference EIA/JEDEC Standard JESD51-5) Line 2: Logo A, 4-digit Date Code
D Branding scale and appearance at supplier discretion Line 3: Assembly Lot Number

33
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A4960 Sensorless BLDC Controller

Revision Table
Revision Number Revision Date Description
– October 6, 2011 Initial Release
1 September 9, 2015 Corrected Figure 10 (page 31) DIAG and LOS signals
2 April 24, 2017 Corrected pinout diagram typo (page 4)
3 April 25, 2019 Minor editorial updates
4 April 27, 2022 Updated package drawing (page 33)

Copyright 2022, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

www.allegromicro.com

34
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com