User Manual

Pluto 5 Casino Controller

Document No. 80-15744 Issue 5 HEBER LTD

Current Issue :- Issue 5 - 12th August, 2003

Previous Issues :- Issue 1 - 8th June, 1999

Issue 2 - 4th January, 2000
Issue 3 – 5th February 2002
Issue 4 - 8th October, 2002

©HEBER Ltd. 2003. This document and the information contained therein is the intellectual property of
HEBER Ltd and must not be disclosed to a third party without consent. Copies may be made only if
they are in full and unmodified.

File Name: H:\pluto5\manuals\pluto_5_casino.doc HEBER LTD

Document No. 80-15744 Issue 5
 HEBER LTD
Belvedere Mill
Chalford
Stroud
Gloucestershire
GL6 8NT
England

Tel: +44 (0) 1453 886000

Fax: +44 (0) 1453 885013
Email: [email protected]
http://www.heber.co.uk

File Name: H:\pluto5\manuals\pluto_5_casino.doc HEBER LTD

Document No. 80-15744 Issue 5
 Page i

CONTENTS
1 INTRODUCTION.................................................................................................................... 1

2 NEW IN THIS RELEASE ....................................................................................................... 1

3 OVERVIEW ............................................................................................................................ 1

4 DIFFERENCES FROM PLUTO 5 .......................................................................................... 1

5 CIRCUIT SCHEMATIC DESCRIPTION ................................................................................ 2

5.1 SHEET 1 .................................................................................................................................. 2
5.2 SHEET 2 .................................................................................................................................. 2
5.3 SHEET 3 .................................................................................................................................. 2
5.4 SHEET 4 .................................................................................................................................. 2
5.5 SHEET 5 .................................................................................................................................. 2
5.6 SHEET 6 .................................................................................................................................. 2
5.7 SHEET 7 .................................................................................................................................. 2
5.8 SHEET 8 .................................................................................................................................. 3
5.9 SHEET 9 .................................................................................................................................. 3
5.10 SHEET 10 ................................................................................................................................ 3
5.11 SHEETS 11, 12 & 13 ................................................................................................................ 3
5.12 SHEETS 14............................................................................................................................... 3
5.13 SHEETS 15............................................................................................................................... 4
5.14 SHEETS 16............................................................................................................................... 4
5.15 SHEETS 17............................................................................................................................... 4
5.16 SHEETS 18............................................................................................................................... 4
6 CIRCUIT OPERATION .......................................................................................................... 5
6.1 POWER SUPPLIES..................................................................................................................... 5
6.2 RESET AND POWER FAIL DETECTION ......................................................................................... 5
6.3 PRIMARY BATTERY BACKUP ...................................................................................................... 6
6.4 THE MC68340 PROCESSOR ..................................................................................................... 6
6.4.1 CPU32 Processor Module ................................................................................................. 7
6.4.2 SIM40 System Integration Module..................................................................................... 7
6.4.3 DMA Controller Module ..................................................................................................... 9
6.4.4 Serial Module ..................................................................................................................... 9
6.4.5 Timer Module ................................................................................................................... 10
6.5 FPGA.................................................................................................................................... 11
6.6 EPROM SOCKETS / EPROM AUTOSELECT FEATURE ............................................................. 11
6.7 EPROM ADDRESS LINE SCRAMBLING IN 16 BIT MODE ............................................................ 12
6.7.1 2*27C040 EPROMs ......................................................................................................... 12
6.7.2 2*27C801 EPROMs ......................................................................................................... 13
6.8 MEMORY EXPANSION.............................................................................................................. 14
6.9 OPEN DRAIN OUTPUTS, OP0-63............................................................................................. 14
6.10 AUX OUTPUTS, AUX0-7 ........................................................................................................ 15
6.11 INPUTS, IP0-31 ...................................................................................................................... 15
6.12 DIL SWITCHES ....................................................................................................................... 16
6.13 SOFTWARE CONTROLLED INDICATOR LED............................................................................... 16
6.14 ON-BOARD PUSH BUTTON ...................................................................................................... 16
6.15 MULTIPLEXER ......................................................................................................................... 16
6.16 MULTIPLEXED LAMP CURRENT SENSE ..................................................................................... 17
6.17 SOUND GENERATION .............................................................................................................. 18
6.18 STEREO AMPLIFIER AND VOLUME CONTROLS........................................................................... 18
6.19 SERIAL I/O ............................................................................................................................. 19
2
6.20 INTERNAL I C BUS .................................................................................................................. 19
6.20.1 Real Time Clock............................................................................................................... 19
2
6.20.2 E PROM........................................................................................................................... 19

Document No. 80-15744 Issue 5 HEBER LTD

 Page ii

6.21 SERIAL CHANNELS C-H .......................................................................................................... 20

6.21.1 Mapping of DUART Lines ................................................................................................ 21
6.21.2 DUART Interrupts ............................................................................................................ 22
6.22 SECONDARY RAM.................................................................................................................. 22
6.23 SECURITY PIC MICROCONTROLLER ........................................................................................ 22
7 MACHINE OPERATION ...................................................................................................... 23
7.1 DRIVING REELS ...................................................................................................................... 23
7.2 READING THE DIL SWITCHES .................................................................................................. 23
7.3 READING THE SWITCH INPUTS ................................................................................................. 23
7.4 INTERFACING TO COIN & NOTE ACCEPTORS ............................................................................ 24
7.5 INTERFACING TO COIN PAYOUT MECHANISMS .......................................................................... 24
7.6 DRIVING VACUUM FLUORESCENT DISPLAYS (VFD) .................................................................. 24
2
7.7 USING THE EXTERNAL I C BUS ............................................................................................... 24
7.8 DRIVING METERS ................................................................................................................... 24
7.9 MAKING SOUNDS .................................................................................................................... 25
7.9.1 Single Channel/Single Speaker (Mono) Mode ................................................................ 25
7.9.2 Single Channel/Dual Speaker Mode................................................................................ 25
7.9.3 Dual Channel/Dual Speaker (Stereo) Mode .................................................................... 25
7.9.4 Dual Channel/Single Speaker Mode................................................................................ 25
7.10 USING MULTIPLEXED LAMPS ................................................................................................... 26
7.11 USING MULTIPLEXED LEDS .................................................................................................... 26
7.12 USING THE MULTIPLEX EXPANSION CONNECTOR ..................................................................... 26
7.13 ADDING VIDEO CAPABILITIES................................................................................................... 26
8 SOFTWARE DEVELOPMENT ............................................................................................ 27

9 CONNECTOR TYPES AND PIN OUTS .............................................................................. 28

9.1 SCHEDULE OF CONNECTOR TYPES.......................................................................................... 28
9.2 P1 – RS232 CHANNEL A ....................................................................................................... 29
9.3 P2 – DATAPORT (RS232 CHANNEL B).................................................................................... 30
9.4 P3 – POWER INPUT ................................................................................................................ 31
9.5 P4 – MULTIPLEXED LAMP SINKS ............................................................................................. 31
9.6 P5 ULTREX – MULTIPLEXED LEDS .......................................................................................... 32
9.7 P5 BOX HEADER – MULTIPLEXED LEDS .................................................................................. 32
9.8 P6 – MULTIPLEXED LAMPS SOURCES...................................................................................... 33
9.9 P7 ULTREX – REELS .............................................................................................................. 34
9.10 P7 BOX HEADER – REELS ...................................................................................................... 35
9.11 P8 ULTREX – GENERAL I/O #1 ............................................................................................... 36
9.12 P8 BOX HEADER – GENERAL I/O #1 ....................................................................................... 37
9.13 P9 ULTREX – GENERAL I/O #2 ............................................................................................... 38
9.14 P9 BOX HEADER – GENERAL I/O #2 ....................................................................................... 38
9.15 P10 – LOUDSPEAKERS ........................................................................................................... 39
9.16 P11 – MULTIPLEX EXPANSION ................................................................................................ 39
9.17 P12 – AUX OUTPUTS ............................................................................................................. 39
2
9.18 P13 – EXTERNAL I C BUS ...................................................................................................... 40
9.19 P14 – IO EXPANSION CARD CONNECTOR ............................................................................... 40
9.20 P15 – MEMORY EXPANSION CARD CONNECTOR...................................................................... 41
9.21 P16 – BACKGROUND DEBUG MODE CONNECTOR .................................................................... 41
9.22 P17 – RS232 CHANNEL C ..................................................................................................... 42
9.23 P18 - RS232 CHANNELS D, E, F & G. .................................................................................. 42
9.24 P19 – CHANNEL H – TTL SERIAL PORT .................................................................................. 43
9.25 P20 – POWER-OFF SECURITY MONITOR ................................................................................. 43

Document No. 80-15744 Issue 5 HEBER LTD

 Page iii

LIST OF TABLES
Table 1. Allocation of MC68340 Pins Controlled by SIM40 Module........................................................ 8
Table 2. Allocation of MC68340 Pins Controlled by DMA Module .......................................................... 9
Table 3. Allocation of MC68340 Pins Controlled by Serial Module....................................................... 10
Table 4. Allocation of MC68340 Pins Controlled by Timer Module....................................................... 10
Table 5. Possible EPROM Configurations ............................................................................................ 11
Table 6. Re-Mapping of Address Lines in 2*27C040 Mode .................................................................. 12
Table 7. Re-Mapping of EPROM Contents in 2*27C040 Mode ............................................................ 12
Table 8. Re-Mapping of Address Lines in 2*27C801 Mode .................................................................. 13
Table 9. Re-Mapping of EPROM Contents in 2*27C801 Mode ............................................................ 13
Table 10. Mapping of Open Drain Outputs (OP0-63) to TPIC6259 Devices ........................................ 14
Table 11. Mapping of Inputs IP0-31 ...................................................................................................... 15
Table 12. Mapping of DIL Switch Inputs................................................................................................ 16
2
Table 13. I C Slave Addresses for RTC, U40 ....................................................................................... 19
2 2
Table 14. I C Slave Addresses for E PROM, U37 ................................................................................ 20
Table 15 - Mapping of DUART U53 I/O Pins......................................................................................... 21
Table 16 - Mapping of DUART U54 I/O Pins......................................................................................... 22
Table 17 - Mapping of DUART U55 I/O Pins......................................................................................... 22
Table 18. Recommended Reel Stepper Motor Drive Connections ....................................................... 23
Table 19. AMP Ultrex Connector Part Numbers ................................................................................... 28
Table 20. Tyco Box Header Connector Part Numbers.......................................................................... 28
Table 21. AMP MTA-100 Connector Part Numbers .............................................................................. 29
Table 22. AMP MTA-156 Connector Part Numbers .............................................................................. 29

LIST OF FIGURES
Figure 1 – Schematic Sheet 1 - Root Sheet.......................................................................................... 44
Figure 2 - Schematic Sheet 2 - CPU ..................................................................................................... 45
Figure 3 - Schematic Sheet 3 - FPGA................................................................................................... 46
Figure 4 - Schematic Sheet 4 - Memory................................................................................................ 47
Figure 5 - Schematic Sheet 5 - Sound .................................................................................................. 48
Figure 6 - Schematic Sheet 6 – Open Drain Outputs............................................................................ 49
Figure 7 - Schematic Sheet 7 - Inputs................................................................................................... 50
Figure 8 - Schematic Sheet 8 - Power Supply ...................................................................................... 51
Figure 9 - Schematic Sheet 9 – IO Connectors..................................................................................... 52
Figure 10 - Schematic Sheet 10 - Reset/Battery/RS232 Channels A & B ............................................ 53
Figure 11- Schematic Sheet 11 - Lamp Column/LED Digit Drives........................................................ 54
Figure 12 - Schematic Sheet 12 - Lamp Row Drives ............................................................................ 55
Figure 13 - Schematic Sheet 13 - LED Segment Drives....................................................................... 56
Figure 14 - Schematic Sheet 14 – Root Sheet 2................................................................................... 57
Figure 15 - Schematic Sheet 15 – DUARTS, Channels C-H ................................................................ 58
Figure 16 - Schematic Sheet 16 – RS232 Buffers Channels C-H......................................................... 59
Figure 17 - Schematic Sheet 17 – Port H, TTL Buffers......................................................................... 60
Figure 18 - Schematic Sheet 18 – Secondary NV RAM, Security PIC Microcontroller......................... 61
Figure 19 – Pluto 5 Casino with Ultrex connectors (Pluto 5CU) Photograph........................................ 62
Figure 20 - Pluto 5 Casino Component Ident ........................................................................................ 63

Document No. 80-15744 Issue 5 HEBER LTD

 Page 1

1 INTRODUCTION
The Pluto 5 Casino Controller board is a natural progression in the Pluto family of products. It builds
on the proven reliability and technical excellence of previous Pluto boards and provides improved
performance and flexibility at lower cost. This manual covers the detail of the hardware operation of
Pluto 5 Casino Controller board, other boards in the system have their own manuals.

2 NEW IN THIS RELEASE

• Section 7.13 includes information about the Calypso 16 Video Card.
• Section 9.1 includes information about Box Header type connectors and their corresponding part
numbers.
• Schematic drawings have been updated to reflect hardware changes.

3 OVERVIEW
The Pluto 5 Casino Controller board is a low cost, high performance single board controller for
amusement machines. An 8 reel machine with 256 lamps, 32 LED digits, Linewriter display, Coin
Acceptors, Note Acceptors and Payout Hoppers can be controlled without any additional boards.

Single channel sound can be played through one or two speakers. Two Channel (mono or stereo)
sound is available by plugging in an additional IC.

Pluto 5 Casino boards are supplied with either Ultrex or Box Header connectors.
Pluto 5 Casino with Ultrex connectors is referred to as Pluto 5CU.
Pluto 5 Casino with Box Header connectors is referred to as Pluto 5CB.
These connectors and all the other connectors on the Pluto 5 Casino board are documented in section
9 - Connector Types and Pin Outs in this user manual.

4 DIFFERENCES FROM PLUTO 5

The Pluto 5 Casino Controller is basically an upgrade to the standard Pluto 5 Controller with the
following additional functionality added:

1. Provision for up to 6 extra serial communication ports, Channels3 C-H, by fitting DUARTs U53,
U54 & U55.
2. Additional 32Kbyte RAM with independent battery backed supply.
3. Provision for a battery powered PIC Microcontroller which allows power-down monitoring of up to
7 external switches.

To allow the above additions, the following changes have been made to the operation of the controller:

1. A standard Pluto 5 FPGA will not work in the Pluto 5 Casino Controller (the functions of pins 48 &
54 are changed).
2. The Multiplex Expansion (MPX2) facility offered on Pluto 5 has been lost
2
3. The General Purpose TTL outputs and external I C Bus on connectors P12 & P13 have been
remapped.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 2

5 CIRCUIT SCHEMATIC DESCRIPTION

This section is a walk through of the Pluto 5 Casino Controller board (56-15741) circuit schematics,
Figures 1-13 of this document. A detailed description is given in Section 4 “CIRCUIT OPERATION”.

5.1 Sheet 1

This sheet shows the interconnection between the remaining sheets of this drawing.

5.2 Sheet 2

This sheet shows the following items:

• Motorola MC68340 Processor.

• Pull-up resistors on Address Bus, Data Bus and other Control Signals.
• Push Button Switch, SW3.
• P16 “BACKGROUND DEBUG MODE” connector.

5.3 Sheet 3
This sheet shows the FPGA.

5.4 Sheet 4

This sheet shows the following memory related circuits:

• Sockets for 1 or 2 EPROMs, U1 and U2

• 64Kbytes Battery backed RAM, U3 and U4
• P15 “MEMORY EXPANSION” connector for plug-in Memory Cards

5.5 Sheet 5

This sheet shows the following sound related circuits:

• Standard Sound Channel #1, U8 (OKI MSM6585).

• Optional Sound Channel #2, U39 (OKI MSM6585).
• TDA7057AQ Stereo Audio Amplifier.
• P10, “LS” connector for loudspeakers.

5.6 Sheet 6

This sheet shows the 64 Open Drain Outputs, OP0-63.

5.7 Sheet 7
This sheet shows the following circuits:

• External inputs, IP0-31

• Two 8 way DIL switches, SW1 and SW2

Document No. 80-15744 Issue 5 HEBER LTD

 Page 3

5.8 Sheet 8

This sheet shows various Power Supply related functions:

• Current sensing +12V Meter supply

• Power fail detection.
• Current sensing from Lamp Multiplex.
• Fuse and +5V regulator.
• Voltage rail overvoltage and transient protection.
• P3 “PWR IN” power input connector

5.9 Sheet 9
This sheet shows the following I/O connectors.

• P7 “REELS” carries enough I/O lines to run 6 reels, including a sub set of the lamp multiplexer and
power supplies for the motors.
• P8 “I/O 1” and P9 “I/O 2” are general purpose I/O.
• P11 “MULTIPLEX EXPANSION” provides signals for the connection of Multiplex Expansion
boards.
• P12 “AUX OUTPUTS” provides 6 open drain TTL outputs, typically for driving VFD displays.
2 2 2
• P13 “I C” provides a connector for external I C expansion, e.g. E PROM modules. Note that the
2
lines used to implement this connector are different to the lines allocated for the internal I C bus to
U40 and U37.
• P14 “I/O EXPANSION” is a position for a daughter board for I/O expansion.

5.10 Sheet 10

This sheet shows the following circuits and connectors:

• Reset circuit and LED.

• Battery Backup for RAM and optional Real Time Clock.
2
• Optional I C Real Time Clock socket, U40, PCF8583.
2 2
• Optional I C E PROM socket, U37, 24C04 (512 bytes) or 24C08 (1024 bytes).
• RS232 buffers.
• P1 “RS232” is a general purpose RS232 serial communication port.
• P2 “DATAPORT” is the BACTA standard Dataport.

5.11 Sheets 11, 12 & 13

These sheets show the Multiplex Lamp and LED drive circuits and connectors.

• Sheet 11 shows the Lamp Columns/Digits Sink drivers.

• Sheet 12 shows the Lamp Row/Source drivers
• Sheet 13 shows the LED Segment drivers
• P4 “LAMP SINKS” is the Lamp Array Column/Sink outputs
• P5 “LED” is the connector for the 32 or 16 LED digits.
• P6 “LAMP SRC” is the Lamp Array Row/Source outputs

5.12 Sheets 14
Sheets 1-13 are identical to the standard Pluto 5 Board. This sheet is a secondary Root Sheet
showing the extra 4 schematics (Sheets 15-18) that have been added to make the Pluto 5 Casino.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 4

5.13 Sheets 15

This sheet shows the three 68681 DUARTs (U53-U55) that provide serial comms channels C-H.

5.14 Sheets 16
This sheet shows the following:
• Buffers for the 5 RS232 channels, C-G.
• Connector P17 for RS232 Channel C
• Connector P18 for RS232 Channels D, E, F & G.

5.15 Sheets 17

This sheet shows the Channel H Interface. This is at TTL levels and may connect directly, via P19, to
a variety of different format Interface Cards, eg RS422, RS485, Opto-Isolated RS485, etc.

5.16 Sheets 18

This sheet shows the following:

• Optional security PIC Microcontroller, U51.

• Security switch connector, P20.
• Second non-volatile (battery-backed), 32Kbyte RAM, U50.
• Second battery and back-up circuit for U51 and U50

Document No. 80-15744 Issue 5 HEBER LTD

 Page 5

6 CIRCUIT OPERATION
This section describes how some elements of the circuit operate and their capabilities and limitations.
A subsequent section deals with how the various capabilities of the board are used to implement
specific amusement machine functions.

6.1 Power Supplies

The Power Input to the board is on P3. There are 3 input voltages required, +12V, -12V and 36V or
48V for the lamp multiplex.

The +12V supply is fused by F1 (3.15A) as it comes on the board. From the unfused (input) side, the
+12V is distributed to the Reel Connector, P7 where it may be used to provide the supply for the
Stepper Motors.

From the fused side, the +12V is used for the following:

• Regulated via U15 to provide the Vcc (+5V) supply for the board. This will draw up to 250mA from
the +12V rail.
• To provide the Power Supply for the Stereo Audio Amplifier, U32. The load current drawn by this
will depend on the audio volume, etc. but is not likely to exceed an average of about 200mA.
• Monitored by U16B to detect imminent failure of the +5V supply and cause a Level 7 (Non-
Maskable) Interrupt, NMI-. The interrupt will occur if the +12V supply drops below approximately
7.8V.
• To provide the Power Supply for the multiplexed LED drive circuits. With 32 LED digits fitted and
all having all segments illuminated, the current drain is likely to be between 400mA and 550mA.
• Distributed to various connectors, P1, P2, P8, P9, P12 and P14 for optional use by external
circuits.

When connecting external loads to the Fused +12V outputs on P1, P2, P8, P9, P12 and P14 make
sure that the total current drawn is within the rating of fuse F1 (3.15A), making due allowances for the
other loads as described above.

The –12V supply input provides the negative supply for the 1488 RS232 Transmitter Buffers, U33,
U41, U43 & U46, and the –12V supply required on the DATAPORT Connector, P2.

The Lamp Multiplex supply should be +36V or +48V, depending upon the duty cycle employed by the
software. See Section 6.15, “Multiplexer” for more information.

Transient suppressers (Tranzorbs) are fitted on the +12V supply (fused side), -12V supply and Vcc to
protect these lines against any overvoltage.

6.2 Reset and Power Fail Detection

TL7705 device, U17, on Schematic Sheet 10, provides the system reset. At power up, the system is
held in a reset state (RESET- low, RESET high) for about 5 seconds. This time is determined by C14.
The processor may initiate a full hardware reset at any time by asserting Port B, pin 0 (PB0) low,
which will trigger the TL7705 via the RESIN- pin. The RESET lines will also be immediately asserted
by the TL7705 if the Vcc line drops below 4.75V.

While the system is in a reset state, i.e. RESET- is low, a red LED, LD1, is illuminated.

The power fail detection is a simple threshold detection on the 12V rail using one section of the quad
comparator LM339 (U16B) on Schematic Sheet 9.

When the +12V input falls below a threshold of approximately 7.8V, the output of the comparator goes
low which causes a Level 7 interrupt (NMI) to the processor. This will occur BEFORE the 7805
regulator drops out of regulation and the Vcc line starts to drop, thus giving the processor a period of
time to react before the RESET is asserted by the TL7705, U17. The main purpose of giving the

Document No. 80-15744 Issue 5 HEBER LTD

 Page 6

processor the NMI in advance of the RESET is to avoid the risk of an incomplete RAM write operation
occurring if the RESET were to be asynchronously asserted while such an operation was being
carried out.

The time available between the assertion of NMI and the assertion of RESET will depend on the rate
of fall of the +12V line, which will obviously be dependent upon the power supply and the loading on
the +12V, but will typically be several milliseconds.

6.3 Primary Battery Backup

A backup battery, BT1, is provided (Schematic Sheet 10) to allow the two RAMs U3 and U4 to retain
data while the board is powered down and to keep the optional Real Time Clock chip, U40, running.

BT1 is a two cell rechargeable NiMH (Nickel Metal Hydride) battery, capacity 70mA/hr. The circuit
comprising BT1, Q2, R43 and R132 provides the battery trickle charge and switchover of the secured
power supply rail, Vbatt.

While Vcc is at 5V, current flows through the base-emitter junction of Q2 through R43 into the battery.
On charge, the voltage on BT1 will be about 2.6V so the current through R43 will be (5-VBE-2.6)/3300,
about 0.5mA. Thus Q2 will be turned ON and Vbatt will be a VCEsat below Vcc. Current will therefore
also flow through R132 into Vbatt, (5-VCEsat-2.6)/3300, about 0.7mA. Total trickle charge current is
therefore 0.5 + 0.7 = 1.2mA. The specification of the cells calls for a trickle charge of between .01C
and .03C. C is 70mA, so the acceptable range is between .7mA and 2.1mA.

When power is removed, Vcc collapses to ground. The base-emitter junction of Q2 is now reverse
biased and therefore no current flows through R43 and Q2 is OFF. Vbatt is now connected to the
positive end of BT1 via R132. The discharge current into the RAMs and RTC should not exceed 40µA,
which will result in a voltage drop in R132 of less than 0.15V. This gives a worst case battery life in
excess of two months, and in practice much higher.

When on battery backup it is vital that the RAMs are placed in the standby state by ensuring that the
CS- line is high. Q1 and R42 achieve this. When the RESET- line goes low, which may occur either as
a result of a Reset occurring or Vcc collapsing, Q1 turns OFF causing the CS- lines to the RAMs to be
pulled to Vbatt by R42.

6.4 The MC68340 Processor

Full details of the operation of the processor is given in the Motorola MC68340 User Manual [see
Adobe Acrobat File 68340um.pdf, plus Addenda files 68340um_ad.pdf and 68340um_ad2.pdf]

The MC68340 contains the following functional blocks:

Document No. 80-15744 Issue 5 HEBER LTD

 Page 7

6.4.1 CPU32 Processor Module

The CPU32 is a processing core which is basically 68000 code compatible but with a number of
enhancements. For full details of operation please refer to both the Motorola MC68340 User Manual
and the Motorola M68000 Family Programmers Reference Manual [see Adobe Acrobat File
68kprm.pdf].

All modern 68000 Compilers and Assemblers have various options for the target CPU. When
generating code for the Pluto System, the CPU32 option should be used.

If the Compiler/Assembler is old it is possible that it may not have a CPU32 option. In this case, the
Compiler (if used) should be run with the 68000 option set. The assembler may be run in 68020 mode
which will allow the use of the MOVES command which is required during initialisation to set up the
Module Base Address Register (MBAR) in the MC68340. Care must be taken not to write code that
calls any other 68020 instructions that may not be implemented on the CPU32.

The Pluto 5 Development Kit includes a suitable C Compiler and Assembler.

6.4.2 SIM40 System Integration Module

This module controls various aspects of the operation of the processor, such as configuration, clock,
external bus, etc.

When used in the Pluto System, the main considerations in the use of this module are:

6.4.2.1 Module Base Address Register

Set the Module Base Address Register, MBAR, to a suitable address during initialisation.
This sets the base address of all the internal module registers. In the example code it is set
in Module “except.asm” to value 0xffff f000. There is nothing magic about this value, but
obviously it must be set to an address that is clear of any other devices in the processor
memory map. This register must be set before any other module initialisation is attempted.

6.4.2.2 Chip Selects

Set-up the 4 Chip Select outputs, CS0- to CS3-. The Pluto 5 System allocates these as
follows:

CS0 - is used to map the system programme memory. This consists of any EPROM fitted to
the on-board EPROM sockets, U1 and U2 plus any extra EPROM or FLASH devices fitted to
the Memory Expansion Connector, P14. Exact mapping, within the area defined by CS0-, is
carried out be the system FPGA.

CS1 - is used to map the on-board, battery backed RAM and, if fitted, any external RAM on
a memory card on connector P15.

CS2 - is used to map both the internal registers of the FPGA and the on-board I/O,

CS3 - is normally spare and is available on the I/O expansion connector, P14. Its main use is
for the selection of the optional add-on CGA/VGA Video Card.

After hardware reset, CS0- will be asserted for memory accesses anywhere in the memory
map which allows the processor to boot. However, the chip selects must be programmed
immediately after Reset and prior to any function or subroutine calls, because until they are,
CS1- will not be active and therefore it will not be possible for the processor to access RAM.

Example code for setting up the 4 pairs of Chip Select Base and Mask registers is given in
Module except.asm

6.4.2.3 Periodic Interrupt Timer

The “sim40_m.c” Module in the Sample Software sets this timer to provide a high priority
1mS interrupt which is normally used by the software to provide basic system timing. This
function is controlled by the PICR and the PITR.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 8

6.4.2.4 Clock Synthesiser Control

The SYNCR controls the operation of the main processor clock. The MC68340 is provided
with a 32.768KHz reference to which the main clock is phase locked. After reset, the main
clock defaults to 8.39MHz. The maximum clock frequency of the standard MC68340 is
16.77MHz.

6.4.2.5 System Protection

The SYPCR controls the bus monitors and software watchdog. Other safeguards in the
design give adequate protection against programme malfunction as a result of noise, etc.
The Software Watchdog feature is disabled, however, it could be used if required.

The Bus Monitor should be enabled and may be left set at its default of 64 clock cycles time-
out.

6.4.2.6 SIM40 Module Pin Allocations

Pins under the control of the SIM40 module are allocated as follows.

Table 1. Allocation of MC68340 Pins Controlled by SIM40 Module

NAME PIN I/O FUNCTION
PA0/A24- 123 O To I/O Expansion Connector P14, Pin b1, 3K3 pull-up &
RESET to Sound Channel #1, U8
PA1/A25/IACK1- 122 O To I/O Expansion Connector P14, Pin b2, 3K3 pull-up &
RESET to Sound Channel #2, U39
PA2/A26/IACK2- 121 O To I/O Expansion Connector P14, Pin b3, 3K3 pull-up &
Drive for Indicator LED LD2
PA3/A27/IACK3- 120 I To I/O Expansion Connector P14, Pin b4, 3K3 pull-up &
Push Button SW3 Input
PA4/A28/IACK4- 117 I/O To I/O Expansion Connector P14, Pin b5, 3K3 pull-up &
2 2
SCL line (I C) to RTC, U40 and E PROM, U37
PA5/A29/IACK5- 116 I/O To I/O Expansion Connector P14, Pin b6, 3K3 pull-up &
2 2
SDA line (I C) to RTC, U40 and E PROM, U37
PA6/A30/IACK6- 115 I/O Drives S1 pin on SFX Channel #2 (U39) 3K3 pull-up &
MPX Lamp Current Sense Input
PA7/A31/IACK7- 114 I/O Drives S2 pin on SFX Channel #2 (U39) 3K3 pull-up &
MPX Lamp Short Circuit Sense Input
PB0/MODCK 87 O Drive LOW to initiate hardware reset.
PB1/IRQ1-/CS1- 2 O CS1- Maps RAM
PB2/IRQ2-/CS2- 3 O CS2- Maps FPGA registers and I/O
PB3/IRQ3- 4 I Vmeter current sense input.
PB4/IRQ4-/CS3- 5 I/O To I/O Expansion Connector P14, Pin a3
PB5/IRQ5- 8 I/O To I/O Expansion Connector P14, Pin b15, 3K3 pull-up
PB6/IRQ6- 9 I/O To I/O Expansion Connector P14, Pin b16, 3K3 pull-up
PB7/IRQ7- 10 I IRQ7-/NMI input from Power Fail Detection Circuit
CS0-/AVEC- 1 O CS0- Maps ROM, both on-board U1/U2 and on Memory
Expansion Connector (via FPGA).

Document No. 80-15744 Issue 5 HEBER LTD

 Page 9

6.4.3 DMA Controller Module

The DMA Module provides 2 DMA Channels. On the Pluto 5 these are used for sending sound data
from the Programme Memory to the OKI MSM6585 Sound Chip(s). DMA Channel 1 is used to send
data to Sound Channel #1, which is fitted as standard to the Pluto 5 Board. DMA Channel 2 is used for
the optional add-on Sound Channel #2 if fitted (IC39).

The DMA channel should be set to work in following modes:

• External request
• Dual address
• Source address incrementing (Memory)
• Destination address not incrementing (FPGA sound register)
• Transfer size = byte
• Interrupt on completion

Pins controlled by the DMA module are allocated as follows:

Table 2. Allocation of MC68340 Pins Controlled by DMA Module

PIN NO. I/O FUNCTION
DREQ1- 16 I SFX Channel 1 DMA request
DACK1- 15 O No connection
DONE1- 14 IO Not used, 3K3 pull-up
DREQ2- 13 I SFX Channel 2 DMA request
DACK2- 12 O No connection
DONE2- 11 IO Not used, 3K3 pull-up

6.4.4 Serial Module

The Serial Module provides Asynchronous Comms on 2 Channels, Channel A and Channel B. It is
functionally very similar to the 1681/68681 range of DUARTs.

Channel A is buffered to RS232 levels and connected to connector P1. Signals RX, TX, RTS and CTS
are provided.

Channel B is buffered to RS232 levels and connected to DATAPORT connector P2. Signals RX, TX,
RTS and CTS are provided.

The 4 Channel A signals are also made available on the TTL Expansion Connector, P14, at TTL
levels. Thus, alternative interfaces may be provided on an Add-on Board to allow, say, RS485 or Mars
HII interfaces to be implemented.

The exact set up of the Serial Module will obviously depend upon the functionality required.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 10

Pins controlled by the Serial module are allocated as follows:

Table 3. Allocation of MC68340 Pins Controlled by Serial Module

PIN NO. I/O FUNCTION
RXDA 33 I RX DATA Channel A, P1, Pin 2 (RS232 level) &
To IO Expansion Connector P14, Pin c9 (TTL level)
TXDA 32 O TX DATA Channel A, P1, Pin 3 (RS232 level) &
To IO Expansion Connector P14, Pin c10 (TTL level)
RXDB 25 I RX DATA Channel B, DATAPORT P2 (RS232 level)
TXDB 24 O TX DATA Channel B, DATAPORT P2 (RS232 level)
OP0/RTSA- 29 O RTS Channel A, P1, Pin 5 (RS232 level) &
To IO Expansion Connector P14, Pin c12 (TTL level)
OP1/RTSB- 23 O RTS Channel B, DATAPORT P2 (RS232 level)
OP4/RXRDYA- 27 O SFX Channel #1 – U8, Pin S1 (Select Sample Rate)
OP6/TXRDYA- 26 O SFX Channel #1 – U8, Pin S2 (Select Sample Rate)
CTSA- 28 I CTS DUART Channel A, P1, Pin 4 (RS232 level) &
To IO Expansion Connector P14, Pin c11 (TTL level)
CTSB- 22 I CTS Channel B, DATAPORT P2 (RS232 level)

6.4.5 Timer Module

The Timer Module provides 2 General Purpose Timers.

The Pluto 5 Board uses these to provide a variable duty-cycle signals on TOUT1 and TOUT2 that is
used to control the volume setting on each channel of the TDA7057AQ Stereo Audio Amplifier.

Timer 1 (TOUT1) controls the volume of Sound Channel #1. Timer 2 TOUT2) controls the volume of
Sound Channel #2 if it is fitted. If Sound Channel #2 is not fitted, then Timer 2 may be used for other
purposes.

See Section 7.9, “Making Sounds” for detailed information on the operation of the Volume Controls.

Pins TGATE1- and TGATE2- are allocated as general purpose inputs which are used to read the SCL
2
and SDA lines on the External I C Connector, P13.

Pins controlled by the Timer Module are allocated as follows:

Table 4. Allocation of MC68340 Pins Controlled by Timer Module

PIN NO. I/O FUNCTION
2
TGATE1- 79 I Read External I C line SCL on P13, Pin 3 (inverted)
TIN1 81 I Not Used – Strapped To Vcc
TOUT1 80 O Variable Duty Cycle Volume Control SFX Channel #1
2
TGATE2- 36 I Read External I C Line SDA on P13, Pin 2 (inverted)
TIN2 34 I Not Used - Strapped To Vcc
TOUT2 35 O Variable Duty Cycle Volume Control SFX Channel #2

Document No. 80-15744 Issue 5 HEBER LTD

 Page 11

6.5 FPGA

The Pluto 5 Casino Controller is fitted with an 84 lead PLCC socket, position U6, into which is plugged
an FPGA. The standard FPGA type used is an Actel A40MX04-PL84. The purpose of fitting an FPGA
to the system is twofold. First, to allow the Pluto 5 Casino Controller to be uniquely configured for each
user of the system to give commercial and software security (see FPGA SECURITY MANUAL).
Secondly, it allows particular advanced features, for example, the EPROM Autoselect and Multiplex
dimming, to be economically implemented.

The following main functions are carried out by the FPGA:

• Control automatic EPROM mode selection

• Generate control signals for on-board EPROM and RAM
• Generate control signals for Memory Expansion Connector P15.
• Generate DMA requests and multiplex data for Sound Channels 1 & 2.
• Control and drive of data to Multiplex Arrays, both on-board MPX1 and expansion MPX2.
• Provide various levels of Software Security.
• Form an oscillator with 14.75MHz resonator:
• Generate Main Clock, EXTAL for MC68340 Processor @32.768kHz.
• Generate clock for MC68340 Serial Module @3.6864MHz.
• Generate clock for OKI MSM6585 devices, U8/39 @640KHz.

6.6 EPROM Sockets / EPROM Autoselect Feature

The 2 EPROM positions, U1 and U2, are configured such that 4 possible configurations of programme
memory are possible (assuming no external memory expansion via P15):

Table 5. Possible EPROM Configurations

U1 U2 Mode Configuration Total Size Addresses
scrambled
27C040 omit 8 bit 512k*8 512Kbyte no
27C040 27C040 16 bit 512K*16 1Mbyte yes
27C801 omit 8 bit 1024k*8 1Mbyte no
27C801 27C801 16 bit 1024k*16 2Mbyte yes

It is not necessary to change any links on the board in order to switch between different memory
configurations. All relevant switching is carried out within the FPGA, which contains an “EPROM
Autoselect” feature. After Power-up, during the reset period, the FPGA reads the top byte address of
U1. Data contained in this byte defines the memory configuration required and the FPGA
sets up the control lines to the EPROM sockets accordingly, so that, at the end of reset, the
processor is able to read the EPROM(s) correctly.

Thus, after the final linked EPROM software module has been created, prior to being blown into
EPROM, the top location of the memory must be overwritten with suitable data to signify the EPROM
configuration that will be used.

This is the feature referred to as EPROM Autoselect. A full operational description of this feature is
given in the User manual for the FPGA in use on the Pluto 5 Casino Controller Board.

As with the Pluto 1 System, in order to facilitate the option to use either 1 or 2 EPROMs, i.e. run in 8
bit or 16 bit mode, it is necessary to have some scrambling of the address lines to the EPROMs when
operating in 16 bit mode. Therefore, prior to blowing 16 bit EPROMs, the data must be re-arranged to
compensate. A software utility is provided with the Pluto 5 Development Kit to carry this out.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 12

Note that this scrambling of address lines is applicable ONLY to sockets U1 and U2 on the Pluto 5
Casino Controller Board. Any EPROM sockets on Memory Expansion Cards are connected 1:1 to
the address bus and do NOT require any special processing.

6.7 EPROM Address Line Scrambling in 16 Bit Mode

6.7.1 2*27C040 EPROMs

In 16 bit mode, running with 2 * 27C040 EPROMs, the scrambling of the address lines cause the
following effect on the memory mapping in the EPROMs. Note that this table applies to the re-mapping
that occurs to the EPROM contents, rather than the actual address lines.

Table 6. Re-Mapping of Address Lines in 2*27C040 Mode

68340 Address Bus EPROM Address
A0 Not Used in 16 Bit Mode
A1-A18 A2-A19
A19 A1

Thus, for example, addresses will be translated as follows so the contents of the EPROM must be re-
arranged to compensate:

Table 7. Re-Mapping of EPROM Contents in 2*27C040 Mode

68340 Access Address Will Read From This Location in
EPROM
0000 0000 0000 0000
0000 0002 0000 0004
0000 0004 0000 0008
0000 0006 0000 000C
0000 0008 0000 0010
| |
0007 FFFC 000F FFF8
0007 FFFE 000F FFFC
0008 0000 0000 0002
0008 0002 0000 0006
| |
000F FFFC 000F FFFA
000F FFFE 000F FFFE

Document No. 80-15744 Issue 5 HEBER LTD

 Page 13

6.7.2 2*27C801 EPROMs

In 16 bit mode, running with 2 * 27C801 EPROMs, the scrambling of the address lines cause the
following effect on the memory mapping in the EPROMs. Note that this table applies to the re-mapping
that occurs to the EPROM contents, rather than the actual address lines.

Table 8. Re-Mapping of Address Lines in 2*27C801 Mode

68340 Address Bus EPROM Address
A0 Not Used in 16 Bit Mode
A1-A18 A2-A19
A19 A1
A20 A20

Thus, for example, addresses will be translated as follows so the contents of the EPROM must be
re-arranged to compensate:

Table 9. Re-Mapping of EPROM Contents in 2*27C801 Mode

68340 Access Address Will Read From This Location in
EPROM
0000 0000 0000 0000
0000 0002 0000 0004
0000 0004 0000 0008
| |
0007 FFFC 000F FFF8
0007 FFFE 000F FFFC
0008 0000 0000 0002
0008 0002 0000 0006
| |
000F FFFC 000F FFFA
000F FFFE 000F FFFA
0010 0000 0010 0000
0010 0002 0010 0004
0010 0004 0010 0008
| |
0017 FFFC 001F FFF8
0017 FFFE 001F FFFC
0018 0000 0010 0002
0018 0002 0010 0006
| |
001F FFFC 001F FFFA
001F FFFE 001F FFFA

Document No. 80-15744 Issue 5 HEBER LTD

 Page 14

6.8 Memory Expansion

Various optional memory cards may be fitted to the Memory Expansion Connector P15. Seven lines
from the FPGA are included along with 16 data lines and 21 address lines.

The default functionality of the FPGA lines allows memory cards fitted with up to 4 EPROM or FLASH
devices to be accommodated along with a pair of RAM devices with no additional mapping
components.

If a memory card is fitted with 5V FLASH devices, then Write facilities are available. EPROM
Autoselect is also available with devices fitted on a Memory Card.

6.9 Open Drain Outputs, OP0-63

A block of 64 Open Drain Outputs, OP0-63, are provided by 8 off TPIC6259 devices U22-U29 (see
Figure 6 - Schematic Sheet 6 – Open Drain Outputs)

These are memory mapped as the least significant byte of a block of 8 words of address space. The
chip select for these devices, CS_OP-, is provided by the FPGA. Consult the User Manual of the
FPGA being used for exact mapping.

Please note that the chips are bit wide, not byte wide. Thus, Bit 0 of each word drives one device,
U22: Bit 1 drives U23, etc.

Table 10. Mapping of Open Drain Outputs (OP0-63) to TPIC6259 Devices

Bit D7 D6 D5 D4 D3 D2 D1 D0
Pin U29 U28 U27 U26 U25 U24 U23 U22 Addr.
Q7 OP63 OP62 OP61 OP60 OP59 OP58 OP57 OP56 Base+14
Q6 OP55 OP54 OP53 OP52 OP51 OP50 OP49 OP48 Base+12
Q5 OP47 OP46 OP45 OP44 OP43 OP42 OP41 OP40 Base+10
Q4 OP39 OP38 OP37 OP36 OP35 OP34 OP33 OP32 Base+8
Q3 OP31 OP30 OP29 OP28 OP27 OP26 OP25 OP24 Base+6
Q2 OP23 OP22 OP21 OP20 OP19 OP18 OP17 OP16 Base+4
Q1 OP15 OP14 OP13 OP12 OP11 OP10 OP9 OP8 Base+2
Q0 OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Base+0

Basically, the drive capability of these devices is 250mA per output, continuous, with all outputs ON. If
less than 8 outputs are ON in any one package, or any outputs are operating with a small load, the
capacity of the other outputs increases. For example, at 25°C, the TPIC6259 can sink 400mA
continuously from 3 outputs. Please refer to the data sheet for the TPIC6259 (tpic6259.pdf) for
details.

When allocating any output to a load greater than 250mA, consideration should be given to the
loading on each device. See Section 5.1, “Driving Reels” for details on driving standard reel
mechanism stepper motors.

Note also that, because they are MOSFETs, the outputs are resistive (<2Ω) and do not suffer from the
minimum saturation voltage of about 1V which would be the case if they were darlingtons. Therefore,
at low currents, they pull down close to Gnd and may be safely used to drive TTL Inputs, Switch
Strobes, Coin Mechanism Enables, etc.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 15

6.10 AUX Outputs, AUX0-7

8 auxiliary TTL level open drain outputs are provided by U30 (see Figure 9 - Schematic Sheet 9 – IO
Connectors). U30 is a TPIC6B259 which functions exactly the same as the TPIC6259 devices used to
drive OP0-63, but with a lower drive capability (see data sheet “tpic6b259.pdf”).

On the Standard Pluto 5, they are memory mapped as the least significant bit of a block of 8 bytes of
address space at an address determined by the FPGA fitted to the board.

However, on the Pluto 5 Casino Controller, they are selected by the same line as the 64 Open drain
outputs, OP0-63, via 1/2 74HCT139, U52.

They are open drain outputs fitted with 1K pull-up resistors to Vcc.

AUX0-5 are routed to connector P12 “AUX OUTPUTS”.

2
AUX6-7 are routed to Connector P13 “I C”.

6.11 Inputs, IP0-31

External inputs are catered for by 32 input lines, IP0-31, shown on Schematic Sheet 7. Like the Open
Drain outputs these are memory mapped as the least significant byte of a block of 4 words of address
space.

Each input is provided with a 3K3 pull-up resistor to Vcc (+5V) and feeds into a 74HC family device
(rather than 74HCT). This give the inputs a low level threshold of <1.5V and a high threshold of
>3.5V. The 47K resistor in series with the input protects the 74HC253 devices from noise spikes or
high voltages on the inputs.

The 1.5V low threshold allows the inputs to be safely driven as a multiplexed array with a diode in
series with each switch with the strobes generated using a number of the Open Drain Outputs, OP0-
63, described above.

The 32 inputs are mapped as shown in the following table. The top 4 bits of each word are read as
“1”s and bits 8 to 11 contain the DIL Switch Settings (as described in the next section). The base
address is defined by the FPGA.

Table 11. Mapping of Inputs IP0-31

D15-12 D11-8 D7 D6 D5 D4 D3 D2 D1 D0
Base+6 0xF IP31 IP30 IP29 IP28 IP27 IP26 IP25 IP24
DIL
SW
Base+4 0xF IP23 IP22 IP21 IP20 IP19 IP18 IP17 IP16
Base+2 0xF IP15 IP14 IP13 IP12 IP11 IP10 1P9 IP8
Base 0xF IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0

Document No. 80-15744 Issue 5 HEBER LTD

 Page 16

6.12 DIL Switches

The Pluto 5 board is equipped with two 8 way DIL Switches, SW1 and SW2. These are read at the
same addresses as the 32 Inputs (see preceding Section).

Table 12. Mapping of DIL Switch Inputs

D15-D12 D11 D10 D9 D8 D7-D0
Base+6 0xF SW2:8 SW2:7 SW1:8 SW1:7 IP31-24
Base+4 0xF SW2:6 SW2:5 SW1:6 SW1:5 IP23-16
Base+2 0xF SW2:4 SW2:3 SW1:4 SW1:3 IP15-8
Base 0xF SW2:2 SW2:1 SW1:2 SW1:1 IP7-0

6.13 Software Controlled Indicator LED

LD2 is a green LED that may be turned on or off under software control (see Schematic Sheet 9). The
LED may be used to provide an indication that software is running or perhaps for fault diagnosis.

The PORTA2 line from the MC68340 SIM40 Module drives the LED. After reset, the PORTA pins are
high impedance and pulled high by resistor network N11. This signal passes through the inverter U7F
which thus turns ON the LED. Therefore, initially and with no action on the part of the software, the
LED will be ON indicating that Vcc is present.

If the software sets PORTA2 pin as an output and drives it low, the LED will go OFF.

The PORTA pins are taken to the I/O Expansion Connector P14. Future I/O Expansion Cards may use
the PORTA2 pin for some other function, in which case this will have to be taken into consideration
when operating the indicator LED.

6.14 On-board Push Button

A Push Button Switch, SW3, is provided on the board (see Schematic Sheet 2). The function of this
switch is at the discretion of the user of the board.

It is connected so as to pull the PORTA3 line from the MC68340 SIM40 Module to GND when
operated.

The PORTA pins are taken to the I/O Expansion Connector P14. Future I/O Expansion Cards may use
the PORTA3 pin for some other function, in which case the possible interaction with SW3 will have to
be taken into account.

6.15 Multiplexer
The Pluto 5 Casino Controller provides hardware assistance (within the FPGA) to the Processor
allowing a single 32*16 Multiplex Array (MPX1) to be controlled.

The Pluto 5 Casino Controller has ½ of MPX1 configured as a 16*16 (256) Lamp Drive Array and
the other ½ configured as a 16*16 (32 seven-segment digits) LED Drive Array.

The Lamp Multiplex Drive Circuitry is designed to drive 12V, 100mA bulbs. However, it is permissible
for a small number (up to 16) of positions to drive either a higher power bulb (12V, 180ma) or a pair of
100mA bulbs. These "high load" positions should be arranged such that no more than one is on any
one Row or Column drive.

The Lamp Multiplexer will normally be driven from a 48V dc supply (Vmpx) and run with a 1 in 16 duty
cycle which allows the maximum complement of 256 lamps to be driven. However, if necessary, a 36V

Document No. 80-15744 Issue 5 HEBER LTD

 Page 17

supply may be used provided the duty cycle is reduced to 1 in 8, which has the side effect of reducing
the drive capability to 128 lamps and 128 LEDs (16 seven-segment digits).

The Multiplex Array has hardware assistance from the FPGA to enable dimming control. Dimming
level may be set independently for each of the 16 Column strobes, e.g. the 8 lamps on one Column
Strobe could be set to one brightness level while the 8 lamps on a different Column Strobe could be
set to another brightness. The overall basic timing of the multiplexing remains under software control
allowing “overdrive” of lamps for special effects.

Dimming is achieved changing the data presented to the Lamp Row / LED Segment drives at an
adjustable time within the 1mS strobe time. Thus each lamp/LED has two bits of data associated with
it in software – the first bit is the data applied during the first part of the 1mS Strobe period, the second
bit is applied during the second period. The duration of the period that the first bit is applied for may be
set in units of 1/16 mS.

The multiplex is software driven. Every 1mS, data for the next strobe is written to the FPGA which in
turn formats and serialises the data before clocking out the MPX1 data to the on-board 4094 shift
registers (U18,U19,U20,U21,U35,U36).

The exact format of the data to be written each millisecond is determined by the design of the FPGA
being used, but in general it is as follows.

• 32 bits of MPX1 Row/Segment data. First period data.

• 32 bits of MPX1 Row/Segment data. Second period data.
• 4 bits defining Column/Digit strobe number to activate.
• 4 bits defining First Period duration (units of 62.5µS).

Consult the User Manual of the actual FPGA in use for exact details of operation.

6.16 Multiplexed Lamp Current Sense

A facility is provided to allow the processor to check the 256/128 possible lamp positions of MPX1 to
determine:

a. Is a light bulb present?

b. Is there a short circuit in this position?

This facility is intended to be run at power up and, perhaps, as a production test. The facility cannot be
used during normal operation of the machine.

A resistance of approximately 24mΩ is implemented, as a copper track on the PCB, between common
source connection of all the Lamp Column/LED Digit sinks, Q35-50 and Gnd (see Schematic Sheet
11). The voltage across this resistor is compared against 2 thresholds formed by resistor chain R124,
R125 and R126 by comparators U16C and U16D (see Schematic Sheet 8). These thresholds
correspond to nominal currents of about 375mA and 4.8A.

The outputs of the 2 comparators, U16C and U16D are connected to processor lines PORTA6 and
PORTA7. The current sensing comparators may be disabled by SFX_CLK being enabled. When
SFX_CLK, a 640kHz clock, is enabled by setting a bit in the FPGA (see FPGA USER MANUAL), the
“+” inputs of the 2 comparators are pulled up to about +5V by D21/C9/C10 which forces the
comparator outputs (which are open collector) OFF. In this state the lines PORTA6 and PORTA7 are
free to be used as outputs driving the S1 & S2 pins of SFX Channel #2 or as required by any card
fitted to the I/O Expansion Connector, P14. When the SFX-CLK is turned OFF (and forced low), any
voltage on C9/10 is discharged by R127, and the current sensing circuit is enabled.

With no current through the Column/Digit Sinks, both outputs PORTA6/7 will be LOW because V+ < V-
on the comparators. When the current through the 24mΩ resistor exceeds a nominal 375mA, PORTA6
will go high. When the current exceeds a nominal 4.8A, PORTA7 will also go high.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 18

The sequence of operation to test a lamp is as follows:

• Turn off SFX_CLK in FPGA to enable circuit.

• Turn off all Row/Digit drives on MPX1.
• Ensure PORTA6 and PORTA7 both read 0
• Turn on lamp to be tested on multiplex by writing appropriate data to FPGA.
• Start a 1mS timer.
• Loop watching lines PORTA6 and PORTA7.
• If PORTA7 line goes high, there is a short circuit in this position, so immediately disable the
multiplex drives by turning off Multiplex OE line in the FPGA.
• If PORTA6 line goes high but not PORTA7, then there is a light bulb connected and apparently
working.
• If 1mS timer times out without either line going high, then either no bulb present or it is open
circuit.
• Record result and go on to next bulb.
• When complete, act as required on results. Re-enable SFX-CLK to allow Sound Channels to work.

6.17 Sound Generation

The sound generation circuits are shown on Schematic Sheet 5, Figure 5.

U8 and (optionally) U39 are the source of Sound Channel 1 & 2 respectively with the audio output
being pin 10, Aout. These OKI MSM6585 devices are 4 bit ADPCM D-A converters capable of running
at sample rates of 4KHz, 8KHz, 16KHz or 32KHz. This rate is selected by software by setting levels on
the S1 and S2 pins. On Channel 1 (U8) these pins are controlled by the OP4 and OP6 lines from the
MC68340 Serial Module. On Channel 2 (U39) these pins are controlled by the PORTA6 and PORTA7
lines from the MC68340 SIM40 Module.

The VCK- output from the MSM6585 is a square wave at the sampling frequency selected by S1 and
S2. The MSM6585 reads the 4 bit sample immediately after the rising edge of VCK-.

The VCK- from the MSM6585 is connected to the FPGA where it is divided by 2 to produce a DMA
Request signal to the processor. Sound data is transferred, a byte at a time (1 byte = 2 * 4 bit sound
samples), to the appropriate register within the FPGA by the DMA Module if a sound is being played.
The FPGA in turn presents alternately the high and low nibble to the MSM6585 OKI chip.

The sound channel requests a byte of data (via the FPGA) at half the sound sample rate. E.g., if the
MSM6585 has been set to run at 16KHz sample rate, the FPGA will issue DMA requests at 8KHz.

These requests are issued continuously to the DMA Module, but in times of silence, the DMA
channels are inactive and therefore no new data is transferred into the FPGA sound register. In this
case, the user must ensure that the last data written to the FPGA sound register before a period of
silence is 0x80. This will ensure that, during a silent period, the MSM6585 is being continuously fed a
repeated sequence of alternate 0x8 and 0x0 nibbles. This keeps the ADPCM converter in its quiescent
state. If the sound data is generated using the Heber Sound Solutions software, the last byte of the
data is always 0x80, so this condition will automatically be satisfied.

Sound Channel 1 (U8) is fitted as standard and uses DMA Channel 1. Sound Channel 2 (U39) is
optional and uses DMA Channel 2.

The RESET pin of each channel is under individual software control. Pin PORTA0 drives SFX
Channel #1 RESET. Pin PORTA1 drives SFX Channel #2 RESET. After Power –Up, these pins will
default to being inputs and therefore the Resistor network N11 will pull them High, holding both Sound
Channels in a RESET state. Before the Sound Channels can be used, these two pins must be set as
outputs by the SIM40.

6.18 Stereo Amplifier and Volume Controls

The Stereo Amplifier is shown on Schematic Sheet 5, Figure 5.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 19

U32 is a Philips TDA7057AQ Stereo Audio Amplifier with independent DC volume controls. Note that
the loudspeaker outputs, on Connector P10, are bridge driven so neither of the loudspeaker wires may
be connected to Gnd.

The DC volume controls of the TDA7057 work over the range 0.4V(min) to 1.2V (Max). The variable
duty cycle outputs on pins TOUT1/2 from the two timers in the MC68340 Timer Module are integrated
by the combination of two 3K3 resistors and a 1µF capacitor (R108, R109, C45 on Channel 1: R110,
R113, C46 on Channel 2) to provide the control voltage needed. The control voltage is given by the
formula 2.5*{duty cycle} where “duty cycle” is the proportion of the time that the TOUT Pin is HIGH.

Normally, Sound Channel 1 (U8, DMA Channel 1) feeds Amplifier Section 1 (volume control - Timer
Channel 1) driving LS1. Sound Channel 2 (U39, DMA Channel 2) feeds Amplifier Section 2 (volume
control – Timer Channel 2) driving LS2.

A pin on the Loudspeaker Connector, P10, pin 3, which allows the output signal from Amplifier
Channel 1 to be fed back into the input of Amplifier Channel 2. This allows various alternative modes
of operation, for example, if only Sound Channel 1 is fitted, then by linking the LS1+ output to the
feedback pin, the same signal can drive BOTH loudspeakers. See Section 7.9, “Making Sounds”
below for a more detailed explanation of the different operational modes that are possible.

6.19 Serial I/O

P1 provides connections to RS232 Channel A, Data Receive & Transmit plus RTS/CTS.

P2 provides connections to RS232 Channel B, Data Receive & Transmit plus RTS/CTS and is in the
format specified by the BACTA standard.

Operation of the above two ports is determined by the operation of the Serial Module in the MC68340
Processor. Refer to the Serial Module Section of Motorola MC68340 User Manual for a full
explanation.

6.20 Internal I2C Bus

2
An internal I C Bus is implemented using SIM40 Lines PORTA4 (SCL) and PORTA5 (SDA). This bus
allows the processor to read and write the optional Real Time Clock chip, U40, and the optional
2
E PROM, U37. If neither of these devices is fitted, then these 2 lines are also available on the I/O
Expansion Connector P14 and are free for other uses.

6.20.1 Real Time Clock

2
U40 is a position that accepts a Philips PCF8583 I C Real Time Clock. The standard Pluto 5 Casino
Controller has a socket fitted in this position along with the 32.768KHz Crystal, X2. However, the
PCF8583 IC is NOT fitted as standard but is available as an optional extra or may be fitted by the
user.
2
The I C Slave Address of the RTC is as follows:

2
Table 13. I C Slave Addresses for RTC, U40
READ: 0xA1
WRITE: 0xA0

6.20.2 E2PROM
2
U37 position is fitted with a socket that accepts an “Industry Standard” E PROM, 24C04 (512 bytes) or
24C08 (1024 bytes) with pin 7, which serves a different function on devices from different
manufacturers, connected to GND. The Pluto 5 Casino Controller Boards, as standard, do not have an
2
E PROM fitted but they are available as an optional extra or may be fitted by the user.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 20

We strongly recommend that, if a user supplies or fits his own devices, that only NM24C04 or
NM24C08 devices should be used (manufactured by Fairchild or National Semiconductor). Heber
cannot offer Technical Support for the use of devices from alternate manufacturers.
2 2
To avoid a clash of I C addressing between the PCF8583 RTC and the 24Cnn E PROM, A2 (Pin 3) of
2
the E PROM is strapped to Vcc and A0/A1 to GND and this socket is restricted to accepting devices
no larger than the 24C08. Note, however, that there is no such size restriction on the devices that may
2
be connected via P13, the External I C Bus Connector.
2 2
The I C Slave Address of each of the 256 byte “Page Blocks” in the E PROM, U37, is as follows:

2 2
Table 14. I C Slave Addresses for E PROM, U37
BLOCK 0 BLOCK 1 BLOCK 2 BLOCK 3
24C04 or 24C08 24C04 or 24C08 24C08 only 24C08 only
READ 0xA9 0xAB 0xAD 0xAF
WRITE 0xA8 0xAA 0xAC 0xAE

6.21 Serial Channels C-H

Three 44 lead PLCC sockets are provided, U53, U54 and U55, into which may be fitted 68681 or
68692 DUARTs.

These are mapped as 8 bit devices by the FPGA. Please consult the User Manual for the FPGA being
used for details of mapping.

• Channel C is buffered to RS232 levels and taken to 9 way D Type Plug, P17, to provide a PC-AT
compatible Serial Port with lines RX, TX, RTS, CTS, DST, DTR & CD. Control line RI is not
implemented.

• Channels D-G are buffered to RS232 levels and taken to connector P18. Only RX, TX, RTS &
CTS lines are provided on these channels.

• Channel H is buffered to TTL levels by non-inverting buffer U49 and taken to P19. 3 Input and 3
Output control lines are provided in addition to the RX and TX data lines.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 21

6.21.1 Mapping of DUART Lines

The I/O lines of the DUARTs are mapped as shown in the following tables:

U53 – Channels C & D

Pin Channel Name Comments
TXDA C TXDC RS232 Level to P17-3
RXDA C RXDC RS232 Level to P17-2
TXDB D TXDD RS232 Level to P18-7
RXDB D RXDD RS232 Level to P18-5
OP0 C RTSC RS232 Level to P17-7
OP1 D RTSD RS232 Level to P18-6
OP2 - No connection
OP3 - No connection
OP4 - No connection
OP5 - No connection
OP6 - No connection
OP7 - No connection
IP0 C CTSC RS232 Level to P17-8
IP1 D CTSD RS232 Level to P18-8
IP2 C DSRC RS232 Level to P17-6
IP3 C CDC RS232 Level to P17-1
IP4 - - Strapped to VCC
IP5 - - Strapped to VCC

Table 15 - Mapping of DUART U53 I/O Pins

U54 – Channels E & F
Pin Channel Name Comments
TXDA E TXDE RS232 Level to P18-13
RXDA E RXDE RS232 Level to P18-11
TXDB F TXDF RS232 Level to P18-19
RXDB F RXDF RS232 Level to P18-17
OP0 E RTSE RS232 Level to P18-12
OP1 F RTSF RS232 Level to P18-18
OP2 - - No connection
OP3 - - No connection
OP4 - - No connection
OP5 - - No connection
OP6 - - No connection
OP7 - - No connection
IP0 E CTSE RS232 Level to P18-14
IP1 F CTSF RS232 Level to P18-20
IP2 - - Strapped to VCC
IP3 - - Strapped to VCC
IP4 - - Strapped to VCC
IP5 - - Strapped to VCC

Document No. 80-15744 Issue 5 HEBER LTD

 Page 22

Table 16 - Mapping of DUART U54 I/O Pins

U55 – Channels G & H
Pin Channel Name Comments
TXDA G TXDG RS232 Level to P18-25
RXDA G RXDG RS232 Level to P18-23
TXDB H TXDH TTL Level to P19-3
RXDB H RXDH TTL Level to P19-5
OP0 G RTSG RS232 Level to P18-24
OP1 H RTSH TTL Level to P19-7
OP2 H OP2 TTL Level to P19-11
OP3 H OP3 TTL Level to P19-13
OP4 - - No connection
OP5 - - No connection
OP6 - - No connection
OP7 - - No connection
IP0 G CTSG RS232 Level to P18-26
IP1 H CTSH TTL Level to P19-9
IP2 H IP2 TTL Level to P19-15
IP3 H IP3 TTL Level to P19-17
IP4 - - Strapped to VCC
IP5 - - Strapped to VCC

Table 17 - Mapping of DUART U55 I/O Pins

6.21.2 DUART Interrupts

The interrupt outputs from the 3 DUARTs are connected in parallel (wire-ored) and taken to IRQ5-
/PB5 pin on the 68340 processor.

Note that IRQ5- must be run in Autovector mode and software must poll the 3 DUARTs to establish
the source of the interrupt.

Note also that if a Video Card is added on P14 & P15, that IRQ5- may also be used as a Video
Interrupt and the software must poll accordingly.

6.22 Secondary RAM

U50 is a 32Kx8 RAM, completely independent of the main RAMs, U3 and U4. It is battery backed,
either by the Primary Backup Battery (see Section 6.3 above) if JP5 is fitted or by the Secondary
Backup Battery BT2 (if fitted).

The RAM is mapped as a Byte Wide Port at an address determined by the FPGA.

6.23 Security PIC Microcontroller

U51 is a socket for an optional PIC16C54 microcontroller.

It is powered by a battery backed supply and therefore continues to run when the controller is powered
down. The oscillator crystal is 32.768KHz to reduce power consumption.

Details of operation will be found in the Heber User Manual of the device fitted.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 23

7 MACHINE OPERATION
This section discusses how various standard amusement machine functions can be implemented.

7.1 Driving Reels

Up to six 12V Stepper Motor Reel Mechanisms may be connected to the “REEL” connector, P7. +12V
outputs are available for the motor common connection and GND/Vcc are available for the Opto
supply. A 6*6 subset of the Lamp Multiplex is configured so up to 6 lamps per reel may be
accommodated, in either “sinking” or “sourcing” mode (depending on the wiring of the Reel
Mechanism. 6 inputs, IP0-5, are provided for the Opto Inputs

When driving stepper motor reels, because the maximum (static) current load of each winding is
400mA (assuming 30Ω,12V windings), it is important to connect the motors to distribute the load
evenly amongst the TPIC6259 driver chips.

The recommended method of connection is to wire the reel motors as follows:

Table 18. Recommended Reel Stepper Motor Drive Connections

REEL 1 OP0-3
REEL 2 OP4-7
REEL 3 OP8-11
REEL 4 OP12-15
REEL 5 OP16-19
REEL 6 OP20-23

This guarantees that a maximum of 3 motor windings are driven simultaneously by any one TPIC6259
device which is within the ratings of the device even under the worst case of a reel being stationary
and unchopped. Of course, when the motor is running or is being chopped the average current drops
significantly.

Extra reels could be connected via pins on the other connectors. Providing the software chops the
current to the reels when they are not spinning, an extra 2 reels can be wired to OP24-27 and OP28-
31 and should allow the TPIC6259s to remain within their ratings.

NB: The +12V outputs on P7 Pins 45-50 are fed directly from the +12V Input to the Pluto 5 Board on
P3, Pin 4. It does not go via Fuse F1 on the board.

7.2 Reading the DIL Switches

The state of the DIL Switches may be read at any time by reading the memory locations as described
in Section 6.12 above.

7.3 Reading the Switch Inputs

The 32 switch inputs may be read at any time by reading the memory locations as described in
Section 6.11 above.

In most applications, these inputs should be debounced in software. A typical debounce algorithm
might be to read the switches every 1mS, but only register a change of state on the input after it has
been stable for 3 consecutive readings.

It is possible to implement, say, a 64 multiplexed switch input array by using, 8 of the Open Drain
Outputs OP0-63 as strobes and 8 of the Inputs IP0-31. In this case, a diode would need to be
connected in series with each switch.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 24

7.4 Interfacing to Coin & Note Acceptors

Most Coin or Note Acceptors have open collector (“sink to ground”) outputs. These may be connected
directly to any of the Pluto 5 Inputs (IP0-31). Mechanism “Enable” or “Control” inputs may usually be
driven directly from any of the Pluto 5 Open Drain Output lines (OP0-63).

7.5 Interfacing to Coin Payout Mechanisms

Payout Hoppers that require relatively low drive currents, e.g. Coin Controls Universal Hopper, may be
driven directly from an Open Drain Output. Higher current devices, such as 50Vac or 24Vdc Payout
Solenoids, should be driven using Open Drain Outputs via a suitable Triac or Relay Interface Card.
Heber produces a number of suitable interfaces.

7.6 Driving Vacuum Fluorescent Displays (VFD)

The standard VFD/Linewriter display used in most Gaming/Amusement Machines is driven by 3 TTL
level signals, Clock, Data and Reset.

Connector P12 has 6 TTL level outputs which could drive up to 2 display modules.

The mapping of these outputs as the LSB of 6 bytes makes it convenient for the software to implement
the bitwise drive required.

7.7 Using the External I2C Bus

2
Connector P13 is intended for driving external boards containing I C Bus components. A common use
2
for this could be the provision of a removable E PROM Module for use in Spain or any other country
with a similar requirement.
2
Heber have available a small PCB containing a NM24C04 or NM24C08 E PROM that plugs directly on
to P13.

On this connector, the SDA line is driven by the Open Drain Output, AUX7 and may be read by the
68340 Timer Module as the (inverted) TGATE2- signal.

Similarly, the SCL line is driven by AUX6 and read by TGATE1.

Note, On the Pluto 5 Casino Controller, these 2 lines are also connected to the internal Security PIC
2
Microcontroller which acts as an I C slave device. Care must be taken to avoid possible conflicts
2
between the PIC and any external I C device connected on this bus.

7.8 Driving Meters

Electromechanical Meters or Counters should be 12V DC parts. The common +12V supply to them
should be the Vmeter+ supply from Connector P9 (“I/O 2”), pin B17 and each should be driven by an
Open Drain Output (OP0-63).

As the meter is pulsed ON, the software should check that the Vmeter Current Sense Input has
operated, i.e. that pin PORTB4 has gone high.

Because of possible delays in responding to a meter being turned on it is recommended that the
software checks the current sense pin immediately before the meter is turned OFF at the end of a
pulse. To detect tampering or a failure of the current sense circuitry, the software should also check
that the current sense pin goes LOW when no meter is operated.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 25

7.9 Making Sounds

Loudspeaker outputs on connector P10 are bridge driven, so do NOT connect either connection of a
loudspeaker to ground or to any other loudspeaker drive. Ideally 8Ω loudspeaker(s) should be used,
but higher impedance components could be used without any risk of damage to the amplifier. The use
of 3 or 4ohm loudspeakers should be avoided.

It is possible to run the sound in a number of different modes:

7.9.1 Single Channel/Single Speaker (Mono) Mode

This is the lowest cost option, using the standard Pluto 5 Board with a single loudspeaker.

The optional SFX Channel 2, U39, is not fitted and only SFX Channel 1, U8, is operational. A single
loudspeaker is connected to LS1 pins (1 & 2) only. Pins 3,4,5 should be left open.

7.9.2 Single Channel/Dual Speaker Mode

This mode still uses the standard Pluto 5 Board with only SFX Channel 1, U8, operational, but allows
the use of 2 loudspeakers to improve the quality or quantity of the sound.

One loudspeaker, LS1, is connected between Pins 1 & 2 of P10. The second loudspeaker, LS2, is
connected between Pins 4 & 5 of P10. A wire should also be fitted joining together Pins 1 & 3 of P10,
which allows the sound from SFX Channel 1 to be reproduced via Amplifier Channel 2.

The Channel 1 Volume Control will control the overall volume heard from both speakers, while
Channel 2 Volume Control may be used to control “Balance”, allowing an adjustment of the level of
sound heard from LS2 relative to LS1. If Channel 2 Volume is fixed at 7 or 8 (where 15 is maximum),
this will result in approximately equal sounds being heard from each speaker and the overall volume
may be controlled by the Channel 1 Volume Control.

7.9.3 Dual Channel/Dual Speaker (Stereo) Mode

In Stereo Mode, the optional second channel IC U39 is fitted and 2 loudspeakers are used, connected
to LS1 and LS2 pins. Pin 3 is left open. Channel 1 Volume Control will adjust the level of LS1, Channel
2 Volume Control will adjust the level of LS2.

In this mode true stereo sound effects may be reproduced, although the subjective effect heard by the
player will depend upon the placement of the loudspeakers in the cabinet.

7.9.4 Dual Channel/Single Speaker Mode

This mode may be used when the Pluto 5 Casino Controller is used in a cabinet containing only 1
loudspeaker, but has the optional Channel 2 IC, U39, fitted.

The single loudspeaker is connected to the LS2 pins, 4 & 5, of P10. A link is fitted between pins 1 and
3. This will allow sounds generated on Channel 1 to be heard through LS2 along with the sounds from
Channel 2. Note that the Channel 2 Volume Control will adjust the overall volume of the sound heard
from LS2 while the Channel 1 Volume Control will adjust the volume of Channel 1 relative to Channel
2.

If the Channel 1 Volume Control is fixed at 7 or 8, (where 15 is maximum), then sounds reproduced
through either Channel 1 or Channel 2 will come out at approximately the same level and the overall
volume may be controlled by the Channel 2 Volume Control.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 26

7.10 Using Multiplexed Lamps

On all Multiplex lamp outputs, the Column Drives, LC0-15, SINK current to ground and the Row
Drives, LR0-15, SOURCE current from the Lamp Supply (+36V or +48V). Thus, any lamps should be
connected between a Row and a Column drive with their series diodes orientated with the cathode
towards the Column Drive.

The choice of operation at 36V or 48V is determined by the Power Supply and the software. When
running at 48V, the software will sequentially drive all 16 Columns, LC0-15, on a 1/16 duty cycle, each
column being ON for 1mS and OFF for 15.

When running at 36V, the software will sequentially drive only the first 8 Columns (LC0-7) on a 1/8
duty cycle, each column being ON for 1mS and OFF for 7.

Please note that the multiplex circuitry is designed to drive 12V/100mA bulbs only.

7.11 Using Multiplexed LEDs

The multiplexed LED drive circuit is intended to be used with Common Cathode digits, either 7
segment plus decimal point or 14 segment. The common cathode connection of each digit should be
connected to a digit drive output, DIG0-15, on connector P5. Each digit drive output can drive two 7
Segment Digits, the segment anodes for one connecting to drive SEG0-7 and the other to SEG8-15.
By convention, segment “a” would connect to SEG0 or SEG8.

Alternatively, 14 segment starburst digits can be used, in which case each digit output would drive one
digit and the 14 segment anodes should each be connected to one of the segment drive lines, SEG0-
13.

The LED Digit drive circuitry shares the same Current Sink transistors as the Lamp Column drives.
Thus, if the system is being driven in a 1/8 duty cycle to allow a 36V Lamp Supply, only Digit drive
lines DIG0-7 are active. In this case only 16 Seven Segment LED digits may be driven from the
controller.

7.12 Using the Multiplex Expansion Connector

The outputs on P11 are all CMOS signals swinging between GND and +12V. These signals may be
connected to Pluto 5 Multiplex Expansion Boards to increase the Lamp and/or LED drive capability of
the system.

See the PLUTO 5 MULTIPLEX EXPANSION BOARD USER MANUAL for details of connection and
operation.

7.13 Adding Video Capabilities

A Calypso 16 Video Card is available from Heber Ltd. which plugs directly onto the Pluto 5 Casino
board via the 2 DIN41612 connectors P14 and P15.

See the CALYPSO 16 USER MANUAL for details.

The Calypso 16 Video Card supersedes the Pluto 5 CGA/VGA Video Card. For further information on
the Pluto 5 CGA/VGA Video Card refer to the PLUTO 5 CGA/VGA BOARD USER MANUAL.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 27

8 SOFTWARE DEVELOPMENT
A number of options exist for the development and debug of software for use on Pluto 5.

Software will normally be generated using a Cross-Assembler, Cross Compiler and Linker package. A
suitable package is included with the Pluto 5 Development Kit.

When software has been successfully compiled, assembled and linked, it may be tested and
debugged using the Background Debug Mode facility built in to the 68340 Processor.

For full details of debugging, refer to the PLUTO 5 DEVELOPMENT KIT QUICK START GUIDE and
other documentation supplied with the Development Kit.

Document No. 80-15744 Issue 5 HEBER LTD

 Page 28

9 CONNECTOR TYPES AND PIN OUTS

9.1 Schedule of Connector Types

There are two types of Pluto 5 Casino Board with either Ultrex or Box Header connectors, and 3 other
families of connectors:

• Pluto 5 Casino with Ultrex connectors is referred to as Pluto 5CU

• Pluto 5 Casino with Box Header connectors is referred to as Pluto 5CB

Pluto 5CU uses the following 4 different families of connectors for connection to the cableform in the
machine:

• AMPMTA-100. 2.54mm single in-line headers with friction lock and polarisation.
• AMP MTA-156. 3.96mm single in-line headers with friction lock and polarisation.
• AMP Ultrex. 2.54mm dual row headers.
• 25 way “D” Type

Pluto 5CB uses the following 4 different families of connectors for connection to the cableform in the
machine:

• AMPMTA-100. 2.54mm single in-line headers with friction lock and polarisation.
• AMP MTA-156. 3.96mm single in-line headers with friction lock and polarisation.
• Tyco Box Header 2.54mm dual row headers
• 25 way “D” Type

The actual part numbers of the board headers fitted to the Pluto 5 Casino PCB along with the part
numbers of suitable mating (cableform) parts are given in the following tables:

Table 19. AMP Ultrex Connector Part Numbers

Ident Description PCB Header AMP IDC Connector Part Number
AMP Part No.
28-24 AWG Wire
P5 32W Ultrex 3-172870-2 3-172866-2
P7 50W Ultrex 5-172870-0 5-172866-0
P8 40W Ultrex 4-172870-0 4-172866-0
P9 34W Ultrex 3-172870-4 3-172866-4

Table 20. Tyco Box Header Connector Part Numbers

Ident Description PCB Header Tyco IDC Connector Part Number
Tyco Part No.
28-24 AWG Wire
P5 34W Box Header 7-1437061-5 102387-8
P7 50W Box Header 9-1437061-5 102387-0
P8 40W Box Header 8-1437061-5 102387-9
P9 34W Box Header 7-1437061-5 102387-8

Document No. 80-15744 Issue 5 HEBER LTD

 Page 29

Table 21. AMP MTA-100 Connector Part Numbers

Ident Description PCB Header AMP IDC Connector Part Number
AMP Part No.
2 2
24 AWG (0.22mm ) 22 AWG Wire(0.35mm )
(Colour Natural) (Colour Red)
P1 6W MTA-100 640456-6 640621-6 640620-6
P4 18W MTA-100 1-640456-8 1-640621-8 1-640620-8
P6 16W MTA-100 1-640456-6 1-640621-6 1-640620-6
P10 5W MTA-100 640456-5 640621-5 640620-5
P11 7W MTA-100 640456-7 640621-7 640620-7
P12 8W MTA-100 640456-8 640621-8 640620-8
P13 4W MTA-100 640456-4 640621-4 640620-4

Table 22. AMP MTA-156 Connector Part Numbers

Ident Description PCB Header AMP IDC Connector Part Number
AMP Part No.
2 2
24 AWG (0.22mm ) 20 AWG Wire(0.5mm )
(Colour Natural) (Colour Yellow)
P3 6W MTA-156 640388-6 640429-6 640427-6

The above MTA-100 and MTA-156 IDC Connector Part Numbers are for illustration and are of the
“Feed-Through Receptacle without Polarising Tabs” type. A number of alternatives exist that could
also be used, for example “Closed-End” types. Please consult the relevant AMP information for an
exhaustive list. If you have Internet Access, the information is also available on the AMP Web Site at
http://www.amp.com/.

Strain relief covers are also available.

9.2 P1 – RS232 Channel A

Reference: P1
Type: Header 6W AMP MTA-100
Description: RS232 Channel A

1 GND
2 RXA Input to Pluto 5
3 TXA Output from Pluto 5
4 CTSA Input to Pluto 5
5 RTSA Output from Pluto 5
6 +12V

Document No. 80-15744 Issue 5 HEBER LTD

 Page 30

9.3 P2 – Dataport (RS232 Channel B)

Reference: P2
Type: 25W ‘D’ Socket
Description: BACTA Dataport / RS232 Channel B

nc 1
14 nc
RXB (Input to Pluto 5) 2
15 nc
TXB (Output from Pluto 5) 3
16 nc
CTSB (Input to Pluto5) 4
17 nc
RTSB (Output from Pluto 5) 5
18 GND
nc 6
19 nc
GND 7
20 nc
nc 8
21 nc
nc 9
22 nc
nc 10
23 nc
-12V 11
24 nc
nc 12
25 +12V
nc 13

Document No. 80-15744 Issue 5 HEBER LTD

 Page 31

9.4 P3 – Power Input

Reference: P3
Type: Header 6W AMP MTA-156
Description: Power

1 -12V Neg supply for RS232 buffers

2 GND Ground
3 GND Ground
4 +12V Main supply
5 GND Ground
6 Vmpx+ Lamp MPX supply, +36V or +48V

9.5 P4 – Multiplexed Lamp Sinks

Reference: P4
Type: Header 18W AMP MTA-100
Description: Lamp Columns/Sinks

1 LC0 Lamp Column/Sink 0

2 LC1 Lamp Column/Sink 1
3 LC2 Lamp Column/Sink 2
4 LC3 Lamp Column/Sink 3
5 LC4 Lamp Column/Sink 4
6 LC5 Lamp Column/Sink 5
7 LC6 Lamp Column/Sink 6
8 LC7 Lamp Column/Sink 7
9 LC8 Lamp Column/Sink 8
10 LC9 Lamp Column/Sink 9
11 LC10 Lamp Column/Sink 10
12 LC11 Lamp Column/Sink 11
13 LC12 Lamp Column/Sink 12
14 LC13 Lamp Column/Sink 13
15 LC14 Lamp Column/Sink 14
16 LC15 Lamp Column/Sink 15
17 nc No Connection
18 nc No Connection

Document No. 80-15744 Issue 5 HEBER LTD

 Page 32

9.6 P5 Ultrex – Multiplexed LEDs

Reference: P5
Type: Header 32W AMP Ultrex
Description: LED - Drive for 16 or 32 seven-segment LED Digits.

Cathodes, Digit 0 DIG0 A1 B1 DIG1 Cathodes, Digit 1

Cathodes, Digit 2 DIG2 A2 B2 DIG3 Cathodes, Digit 3
Cathodes, Digit 4 DIG4 A3 B3 DIG5 Cathodes, Digit 5
Cathodes, Digit 6 DIG6 A4 B4 DIG7 Cathodes, Digit 7
Cathodes, Digit 8 DIG8 A5 B5 DIG9 Cathodes, Digit 9
Cathodes, Digit 10 DIG10 A6 B6 DIG11 Cathodes, Digit 11
Cathodes, Digit 12 DIG12 A7 B7 DIG13 Cathodes, Digit 13
Cathodes, Digit 14 DIG14 A8 B8 DIG15 Cathodes, Digit 15
Anodes, Segment 0 SEG0 A9 B9 SEG1 Anodes, Segment 1
Anodes, Segment 2 SEG2 A10 B10 SEG3 Anodes, Segment 3
Anodes, Segment 4 SEG4 A11 B11 SEG5 Anodes, Segment 5
Anodes, Segment 6 SEG6 A12 B12 SEG7 Anodes, Segment 7
Anodes, Segment 8 SEG8 A13 B13 SEG9 Anodes, Segment 9
Anodes, Segment 10 SEG10 A14 B14 SEG11 Anodes, Segment 11
Anodes, Segment 12 SEG12 A15 B15 SEG13 Anodes, Segment 13
Anodes, Segment 14 SEG14 A16 B16 SEG15 Anodes, Segment 15

9.7 P5 Box Header – Multiplexed LEDs

Reference: P5
Type: Header 34W Tyco Box Header
Description: LED - Drive for 16 or 32 seven-segment LED Digits.

Not Used 1 2 Not Used

Cathodes, Digit 0 DIG0 3 4 DIG1 Cathodes, Digit 1
Cathodes, Digit 2 DIG2 5 6 DIG3 Cathodes, Digit 3
Cathodes, Digit 4 DIG4 7 8 DIG5 Cathodes, Digit 5
Cathodes, Digit 6 DIG6 9 10 DIG7 Cathodes, Digit 7
Cathodes, Digit 8 DIG8 11 12 DIG9 Cathodes, Digit 9
Cathodes, Digit 10 DIG10 13 14 DIG11 Cathodes, Digit 11
Cathodes, Digit 12 DIG12 15 16 DIG13 Cathodes, Digit 13
Cathodes, Digit 14 DIG14 17 18 DIG15 Cathodes, Digit 15
Anodes, Segment 0 SEG0 19 20 SEG1 Anodes, Segment 1
Anodes, Segment 2 SEG2 21 22 SEG3 Anodes, Segment 3
Anodes, Segment 4 SEG4 23 24 SEG5 Anodes, Segment 5
Anodes, Segment 6 SEG6 25 26 SEG7 Anodes, Segment 7
Anodes, Segment 8 SEG8 27 28 SEG9 Anodes, Segment 9
Anodes, Segment 10 SEG10 29 30 SEG11 Anodes, Segment 11
Anodes, Segment 12 SEG12 31 32 SEG13 Anodes, Segment 13
Anodes, Segment 14 SEG14 33 34 SEG15 Anodes, Segment 15

Document No. 80-15744 Issue 5 HEBER LTD

 Page 33

9.8 P6 – Multiplexed Lamps Sources

Reference: P6
Type: Header 16W AMP MTA-100
Description: Lamp Rows/Sources

1 LR0 Lamp Row/Source 0

2 LR1 Lamp Row/Source 1
3 LR2 Lamp Row/Source 2
4 LR3 Lamp Row/Source 3
5 LR4 Lamp Row/Source 4
6 LR5 Lamp Row/Source 5
7 LR6 Lamp Row/Source 6
8 LR7 Lamp Row/Source 7
9 LR8 Lamp Row/Source 8
10 LR9 Lamp Row/Source 9
11 LR10 Lamp Row/Source 10
12 LR11 Lamp Row/Source 11
13 LR12 Lamp Row/Source 12
14 LR13 Lamp Row/Source 13
15 LR14 Lamp Row/Source 14
16 LR15 Lamp Row/Source 15

Document No. 80-15744 Issue 5 HEBER LTD

 Page 34

9.9 P7 Ultrex – Reels

Reference: P7
Type: Header 50W AMP Ultrex
Description: Reels - Connector for 6 Stepper Motor Reel Mechanisms

Lamp Column 0 LC0 A1 B1 LC1 Lamp Column 1

Lamp Column 2 LC2 A2 B2 LC3 Lamp Column 3
Lamp Column 4 LC4 A3 B3 LC5 Lamp Column 5
Lamp Row 0 LR0 A4 B4 LR1 Lamp Row 1
Lamp Row 2 LR2 A5 B5 LR3 Lamp Row 3
Lamp Row 4 LR4 A6 B6 LR5 Lamp Row 5
GND A7 B7 VCC
Open Drain Output 0 OP0 A8 B8 OP1 Open Drain Output 1
Open Drain Output 2 OP2 A9 B9 OP3 Open Drain Output 3
Open Drain Output 4 OP4 A10 B10 OP5 Open Drain Output 5
Open Drain Output 6 OP6 A11 B11 OP7 Open Drain Output 7
Open Drain Output 8 OP8 A12 B12 OP9 Open Drain Output 9
Open Drain Output 10 OP10 A13 B13 OP11 Open Drain Output 11
Open Drain Output 12 OP12 A14 B14 OP13 Open Drain Output 13
Open Drain Output 14 OP14 A15 B15 OP15 Open Drain Output 15
Open Drain Output 16 OP16 A16 B16 OP17 Open Drain Output 17
Open Drain Output 18 OP18 A17 B17 OP19 Open Drain Output 19
Open Drain Output 20 OP20 A18 B18 OP21 Open Drain Output 21
Open Drain Output 22 OP22 A19 B19 OP23 Open Drain Output 23
Input 0 IP0 A20 B20 IP1 Input 1
Input 2 IP2 A21 B21 IP3 Input 3
Input 4 IP4 A22 B22 IP5 Input 5
+12V A23 B23 +12V
+12V A24 B24 +12V
+12V A25 B25 +12V

Document No. 80-15744 Issue 5 HEBER LTD

 Page 35

9.10 P7 Box Header – Reels

Reference: P7
Type: Header 50W Tyco Box Header
Description: Reels - Connector for 6 Stepper Motor Reel Mechanisms

Lamp Column 0 LC0 1 2 LC1 Lamp Column 1

Lamp Column 2 LC2 3 4 LC3 Lamp Column 3
Lamp Column 4 LC4 5 6 LC5 Lamp Column 5
Lamp Row 0 LR0 7 8 LR1 Lamp Row 1
Lamp Row 2 LR2 9 10 LR3 Lamp Row 3
Lamp Row 4 LR4 11 12 LR5 Lamp Row 5
GND 13 14 VCC
Open Drain Output 0 OP0 15 16 OP1 Open Drain Output 1
Open Drain Output 2 OP2 17 18 OP3 Open Drain Output 3
Open Drain Output 4 OP4 19 20 OP5 Open Drain Output 5
Open Drain Output 6 OP6 21 22 OP7 Open Drain Output 7
Open Drain Output 8 OP8 23 24 OP9 Open Drain Output 9
Open Drain Output 10 OP10 25 26 OP11 Open Drain Output 11
Open Drain Output 12 OP12 27 28 OP13 Open Drain Output 13
Open Drain Output 14 OP14 29 30 OP15 Open Drain Output 15
Open Drain Output 16 OP16 31 32 OP17 Open Drain Output 17
Open Drain Output 18 OP18 33 34 OP19 Open Drain Output 19
Open Drain Output 20 OP20 35 36 OP21 Open Drain Output 21
Open Drain Output 22 OP22 37 38 OP23 Open Drain Output 23
Input 0 IP0 39 40 IP1 Input 1
Input 2 IP2 41 42 IP3 Input 3
Input 4 IP4 43 44 IP5 Input 5
+12V 45 46 +12V
+12V 47 48 +12V
+12V 49 50 +12V

Document No. 80-15744 Issue 5 HEBER LTD

 Page 36

9.11 P8 Ultrex – General I/O #1

Reference: P8
Type: Header 40W AMP Ultrex
Description: General Purpose I/O #1

Open Drain Output 24 OP24 A1 B1 OP25 Open Drain Output 25

Open Drain Output 26 OP26 A2 B2 OP27 Open Drain Output 27
Open Drain Output 28 OP28 A3 B3 OP29 Open Drain Output 29
Open Drain Output 30 OP30 A4 B4 OP31 Open Drain Output 31
Open Drain Output 32 OP32 A5 B5 OP33 Open Drain Output 33
Open Drain Output 34 OP34 A6 B6 OP35 Open Drain Output 35
Open Drain Output 36 OP36 A7 B7 OP37 Open Drain Output 37
Open Drain Output 38 OP38 A8 B8 OP39 Open Drain Output 39
Open Drain Output 40 OP40 A9 B9 OP41 Open Drain Output 41
Open Drain Output 42 OP42 A10 B10 OP43 Open Drain Output 43
Open Drain Output 44 OP44 A11 B11 OP45 Open Drain Output 45
Open Drain Output 46 OP46 A12 B12 OP47 Open Drain Output 47
GND A13 B13 GND
Input 20 IP20 A14 B14 IP21 Input 21
Input 22 IP22 A15 B15 IP23 Input 23
Input 24 IP24 A16 B16 IP25 Input 25
Input 26 IP26 A17 B17 IP27 Input 27
Input 28 IP28 A18 B18 IP29 Input 29
Input 30 IP30 A19 B19 IP31 Input 31
+12V A20 B20 +12V

Document No. 80-15744 Issue 5 HEBER LTD

 Page 37

9.12 P8 Box Header – General I/O #1

Reference: P8
Type: Header 40W Tyco Box Header
Description: General Purpose I/O #1

Open Drain Output 24 OP24 1 2 OP25 Open Drain Output 25

Open Drain Output 26 OP26 3 4 OP27 Open Drain Output 27
Open Drain Output 28 OP28 5 6 OP29 Open Drain Output 29
Open Drain Output 30 OP30 7 8 OP31 Open Drain Output 31
Open Drain Output 32 OP32 9 10 OP33 Open Drain Output 33
Open Drain Output 34 OP34 11 12 OP35 Open Drain Output 35
Open Drain Output 36 OP36 13 14 OP37 Open Drain Output 37
Open Drain Output 38 OP38 15 16 OP39 Open Drain Output 39
Open Drain Output 40 OP40 17 18 OP41 Open Drain Output 41
Open Drain Output 42 OP42 19 20 OP43 Open Drain Output 43
Open Drain Output 44 OP44 21 22 OP45 Open Drain Output 45
Open Drain Output 46 OP46 23 24 OP47 Open Drain Output 47
GND 25 26 GND
Input 20 IP20 27 28 IP21 Input 21
Input 22 IP22 29 30 IP23 Input 23
Input 24 IP24 31 32 IP25 Input 25
Input 26 IP26 33 34 IP27 Input 27
Input 28 IP28 35 36 IP29 Input 29
Input 30 IP30 37 38 IP31 Input 31
+12V 39 40 +12V

Document No. 80-15744 Issue 5 HEBER LTD

 Page 38

9.13 P9 Ultrex – General I/O #2

Reference: P9
Type: Header 34W AMP Ultrex
Description: General Purpose I/O #2

Open drain Output 48 OP48 A1 B1 OP49 Open drain Output 49

Open drain Output 50 OP50 A2 B2 OP51 Open drain Output 51
Open drain Output 52 OP52 A3 B3 OP53 Open drain Output 53
Open drain Output 54 OP54 A4 B4 OP55 Open drain Output 55
Open drain Output 56 OP56 A5 B5 OP57 Open drain Output 57
Open drain Output 58 OP58 A6 B6 OP59 Open drain Output 59
Open drain Output 60 OP60 A7 B7 OP61 Open drain Output 61
Open drain Output 62 OP62 A8 B8 OP63 Open drain Output 63
GND A9 B9 GND
Input 6 IP6 A10 B10 IP7 Input 7
Input 8 IP8 A11 B11 IP9 Input 9
Input 10 IP10 A12 B12 IP11 Input 11
Input 12 IP12 A13 B13 IP13 Input 13
Input 14 IP14 A14 B14 IP15 Input 15
Input 16 IP16 A15 B15 IP17 Input 17
Input 18 IP18 A16 B16 IP19 Input 19
+12V A17 B17 Vmeter Current Sensing +12V

9.14 P9 Box Header – General I/O #2

Reference: P9
Type: Header 34W Box Header
Description: General Purpose I/O #2

Open drain Output 48 OP48 1 2 OP49 Open drain Output 49

Open drain Output 50 OP50 3 4 OP51 Open drain Output 51
Open drain Output 52 OP52 5 6 OP53 Open drain Output 53
Open drain Output 54 OP54 7 8 OP55 Open drain Output 55
Open drain Output 56 OP56 9 10 OP57 Open drain Output 57
Open drain Output 58 OP58 11 12 OP59 Open drain Output 59
Open drain Output 60 OP60 13 14 OP61 Open drain Output 61
Open drain Output 62 OP62 15 16 OP63 Open drain Output 63
GND 17 18 GND
Input 6 IP6 19 20 IP7 Input 7
Input 8 IP8 21 22 IP9 Input 9
Input 10 IP10 23 24 IP11 Input 11
Input 12 IP12 25 26 IP13 Input 13
Input 14 IP14 27 28 IP15 Input 15
Input 16 IP16 29 30 IP17 Input 17
Input 18 IP18 31 32 IP19 Input 19
+12V 33 34 Vmeter Current Sensing +12V

Document No. 80-15744 Issue 5 HEBER LTD

 Page 39

9.15 P10 – Loudspeakers

Reference: P10
Type: Header 5W AMP MTA-100
Description: Loudspeakers

1 LS1+ Loudspeaker, Channel 1

2 LS1- Loudspeaker, Channel 1
3 MIX Channel 2 mixer input
4 LS2+ Loudspeaker, Channel 2
5 LS2- Loudspeaker, Channel 2

WARNING: Loudspeaker outputs are bridge driven and must NOT be connected ground.

9.16 P11 – Multiplex Expansion

Reference: P11
Type: Header 7W AMP MTA-100
Description: Multiplex Expansion

1 MPX1_DATA_A 12V CMOS Output

2 Logic "1" Level 12V CMOS Output
3 MPX_STR_A 12V CMOS Output
4 GND
5 MPX_CLK 12V CMOS Output
6 MPX_STR 12V CMOS Output
7 MPX_OE 12V CMOS Output

9.17 P12 – Aux Outputs

Reference: P12
Type: Header 8W AMP MTA-100
Description: Aux. Outputs

1 GND
2 AUX0 Open drain output, 150mA, 1K pull-up to +5V
3 AUX1 Open drain output, 150mA, 1K pull-up to +5V
4 AUX2 Open drain output, 150mA, 1K pull-up to +5V
5 AUX3 Open drain output, 150mA, 1K pull-up to +5V
6 AUX4 Open drain output, 150mA, 1K pull-up to +5V
7 AUX5 Open drain output, 150mA, 1K pull-up to +5V
8 +12V

Document No. 80-15744 Issue 5 HEBER LTD

 Page 40

9.18 P13 – External I2C Bus

Reference: P13
Type: Header 4W AMP MTA-100
2
Description: External I C Bus

1 GND
2 AUX7/SDA I2C SDA line, TTL Open Collector I/O, 1K Pull-up
3 AUX6/SCL I2C SCL line, TTL Open Collector I/O, 1K Pull-up
4 +5V

9.19 P14 – IO Expansion Card Connector

Reference: P14
Type: DIN41612, C/2 Vertical Plug
Description: Connector for IO Expansion Boards

c b a
1 D8 PORTA0 HALT-
2 D9 PORTA1 CLKOUT
3 D10 PORTA2 CS3-
4 D11 PORTA3 RESET-
5 D12 PORTA4 BERR-
6 D13 PORTA5 A20
7 D14 A22 A23
8 D15 AS- A4
9 RXDA- (TTL) DS- A5
10 TXDA- (TTL) R/W- A6
11 CTSA- (TTL) DSACK0- A7
12 RTSA- (TTL) DSACK1- +12V
13 A0 SIZ0 VCC
14 A1 SIZ1 VCC
15 A2 PB5 GND
16 A3 PB6 GND

Document No. 80-15744 Issue 5 HEBER LTD

 Page 41

9.20 P15 – Memory Expansion Card Connector

Reference: P15
Type: DIN41612, C/2 Socket Vertical
Description: Connector for Memory Expansion Boards

a b c
1 A4 A5 A6
2 VCC A7 A8
3 VCC A9 A10
4 A3 A11 A12
5 A2 A13 A14
6 A1 A15 A16
7 GND A17 A18
8 GND A19 A20*
9 FPGA0 A21 D15
10 FPGA1 D14 D13
11 FPGA2 D12 D11
12 FPGA3 D10 D9
13 FPGA4 D8 D7
14 FPGA5 D6 D5
15 FPGA6 D1 D3
16 D0 D2 D4

* NB. - Pin c8, “A20” is in fact the connection to Pin 1 (ROM_P1) of the 2 on-board EPROMs, U1 &
U2, and is driven by the FPGA.
For all memory accesses, excluding those to the ROM/EPROM area mapped by CS0-, the FPGA
routes A20 to this pin.
For all memory accesses to the ROM/EPROM area mapped by CS0-, the FPGA routes either Vcc,
A19 or A20 to this pin, depending on the memory mode set in the FPGA.

See Section 6.6, “EPROM Sockets / EPROM Autoselect Feature”, for further information.

9.21 P16 – Background Debug Mode Connector

Reference: P16
Type: 10W Low Profile Header
Description: Background Debug Mode Connector
Only fitted to Software Development Boards

DS- 1 2 BERR-
GND 3 4 BKPT
GND 5 6 FREEZE
RESET- 7 8 IFETCH
VCC 9 10 IPIPE

Document No. 80-15744 Issue 5 HEBER LTD

 Page 42

9.22 P17 – RS232 Channel C

Reference: P17
Type: 9W ‘D’ Plug
Description: RS232 Channel C

GND 5
9 nc
DTRC(1) (Output from Pluto) 4
8 CTSC (Input to Pluto)
TXC (Output from Pluto) 3
7 RTSC (Output from Pluto)
RXC (Input to Pluto) 2
6 DSRC (Input to Pluto)
CDC (Input to Pluto) 1

Note (1) – This signal (DTRC) is commoned with RTSD

9.23 P18 - RS232 Channels D, E, F & G.

Reference: P5
Type: Header 26W, 2.54mm Low Profile
Description: Connections for RS232 Channels D-G

+12V 1 2 +12V
+12V 3 4 +12V
Input to Pluto RXD 5 6 RTSD Output from Pluto
Output from Pluto TXD 7 8 CTSD Input to Pluto
GND 9 10 GND
Input to Pluto RXE 11 12 RTSE Output from Pluto
Output from Pluto TXE 13 14 CTSE Input to Pluto
GND 15 16 GND
Input to Pluto RXF 17 18 RTSF Output from Pluto
Output from Pluto TXF 19 20 CTSF Input to Pluto
GND 21 22 GND
Input to Pluto RXG 23 24 RTSG Output from Pluto
Output from Pluto TXG 25 26 CTSG Input to Pluto

Document No. 80-15744 Issue 5 HEBER LTD

 Page 43

9.24 P19 – Channel H – TTL Serial Port

Reference: P19
Type: Header 20W, 2.54mm Low Profile
Description: TTL Level Serial Port, Channel H

Power Out (100mA Max) +12V 1 2 GND

Output from Pluto TXDH 3 4 GND
Input to Pluto RXDH 5 6 GND
Output from Pluto RTSH 7 8 GND
Input to Pluto CTSH 9 10 GND
Output from Pluto OP2 11 12 GND
Output from Pluto OP3 13 14 GND
Input to Pluto IP2 15 16 GND
Input to Pluto IP3 17 18 GND
GND 19 20 GND

9.25 P20 – Power-Off Security Monitor

Reference: P20
Type: Header 8W AMP MTA-100
Description: 7 Switch Inputs, monitored while Pluto powered off

1 PSW1
2 PSW2
3 PSW3
4 PSW4
5 PSW5
6 PSW6
7 PSW7
8 PSW_COMMON

Document No. 80-15744 Issue 5 HEBER LTD

 Page 44
Figure 1 – Schematic Sheet 1 - Root Sheet

D[0 ..15]
D[0..15] A [0..2 3] SHT 9 - CONNECTORS
A [0..2 3] SHT 6 - OPEN DRA IN OUTPUTS
CS_DUA RT- RESET- CS_TTL-
CS_DUA RT- 3.68MHZ CS_OP- RESET- CS_TTL-
3.68MHZ R/W- SHT 8 - +5V /CURRENT SENSE CS_OP- OP[0..63]
R/W- RESET- D[0..15] OP[0..63] OP[0..63]
RESET- PB5 D[0..15]
PB5 DSACK0 - A[0..23] SEL[0..2] IP[0..31]
DSA CK0- RA M_ LITH METER_SENSE A [0..23]
RA M_ LITH METER_SENSE V REF CS_TTL-
15741_6
SFX2_D[0..3] V REF NMI- SHT 7 - INPUTS/DIL SW A S- CS_TTL-
SFX2_D[0..3] PIC_IP0 NMI- MPX_REF2 DS- AS-
PIC_IP0 PIC_IP1 MPX_REF2 MPX_REF1 CS_IP- SEL[0..2] R/W- DS-
PIC_IP1 PIC_OP0 MPX_REF1 PORTA [0..7] CS_IP- SEL[0..2] DSA CK0 - R/W-
PIC_OP0 PIC_OP1 PORTA [0..7] SFX_CLK D[0..15] DSA CK1 - DSA CK0-
PIC_OP1 SFX_CLK D[0..15] IP[0..31] SIZ0 DSA CK1-
IP[0..3 1] SIZ1 SIZ0
15741_8
15741_14 FC3 SIZ1
SERIAL PORTS CS3- FC3
15741_7
CLKOUT CS3-
FC3 CLKOUT
SHT 2 - MC68340 CPU SHT 3 - FPGA SHT 4 - EPROM/RA M RXDA FC3
R/W- CS_OP- TXDA RXDA
R/W- SIZ0 R/W- CS_OP- CS_IP- CTSA - TXDA
SIZ0 DSACK0 - SIZ0 CS_IP- RA M_ CS- RTSA - CTSA -
DSA CK0- EXTA L DSACK0 - RAM_CS- A [0..23] RXDB RTSA -
EXTA L 3.68MHZ EXTA L RA M_WL- RAM_WL- A[0..23] TXDB RXDB
3.68MHZ CS0- 3.68MHZ RA M_WU- RAM_WU- D[0..15] CTSB- TXDB
CS0- CS1- CS0- RAM_OE- RAM_OE- D[0 ..15] RTSB- CTSB-
CS1- CS2- CS1- ROM_P12 ROM_P12 RESET- RTSB-
CS2- CS3- CS2- ROM_OE- ROM_OE- FPGA [0..6] RESET RESET-
CS3- CLKOUT CS3- ROM_P1 ROM_P1 3.68MHZ RESET
CLKOUT DREQ1- CLKOUT RA M_ LITH 3.68MHZ
15741_4
DREQ1- DREQ2- DREQ1- RAM_LITH FPGA [0..6] PIC_IP0
DREQ2- RESET DREQ2- FPGA[0..6] PIC_IP1 PIC_IP0
RESET SFX2_VCK MPX_CLK PIC_IP1
MPX_CLK MPX_STR PIC_OP0
D[0 ..15] MPX_STR MPX_OE PIC_OP1 PIC_OP0
D[0..15] D[0 ..15] MPX_OE MPX1_DA TA_ A PIC_OP1
DSACK1 - MPX1_DA TA_A
DSA CK1- SIZ1 DSACK1 - MPX_STR_DA TA_A SHT 13 - LED SEG DRIVES
SIZ1 MPX_STR_DA TA_A
CS_DUA RT- SFX2_D[0..3] MPX_CLK D[0 ..15]
CS_DUA RT- SFX1_D[0..3] MPX_STR A [0..2 3] D[0..15]
A [0..23] SFX1_VCK MPX_OE PORTA [0..7] A[0..23]
A [0..2 3] A [0..2 3] SFX_CLK MPX1_DA TA_A PORTA [0..7]
METER_SENSE MPX_STR_DA TA_A SFX_CLK
15741_3
METER_SENSE NMI- SHT 5 - SOUND MPX2_DA TA_A SFX_MIX SFX_CLK
NMI- SFX_CLK MPX1_D_12V TOUT2 SFX_MIX
PORTA [0..7] SFX_CLK CLK_12V LS1+ TOUT2
PORTA[0..7] SFX1_VCK SFX1_D[0..3] STR_12V MPX1_C_12V LS2+ LS1+
POP4 SFX1_D[0..3] SFX2_D[0..3] OE_12V TGA TE1- LS2+
POP4 POP6 POP4 SFX2_D[0..3] MPX1_A_12V MPX1_B_12V TGA TE2- TGA TE1-
POP6 TOUT1 POP6 SFX2_V CK SEG[0..15] TGA TE2-
TOUT1 TOUT2 TOUT1 SFX2_VCK RESET STR_A _12V SEG[0..1 5]
TOUT2 TOUT2 RESET
15741_13
HA LT- PB5
HA LT- BERR- SHT 11 - COL/DIG SINKS PB6 PB5
BERR- PB6
15741_5
SHT 1 0 - RESET/BATT/RS232/I2C CLK_12V SEG[0..1 5] BERR-
CTSA - V REF STR_12V HA LT- BERR-
CTSA - RTSA - CTSA - V REF OE_12V HA LT-
RTSA - CTSB- RTSA - RA M_CS- LC[0..15]
CTSB- RTSB- CTSB- RAM_CS- STR_A _12V LC[0..15] MPX_REF1 LC[0..15]
RTSB- RXDA RTSB- RESET MPX_REF1 MPX_REF2
RXDA TXDA RXDA RESET MPX_REF2
TXDA RXDB TXDA
15741_11
RXDB TXDB RXDB
TXDB RESET- TXDB SHT 12 - LAMP ROW SOURCES
RESET- PB0 RESET-
PB0 PB5 PB0 CLK_12V MPX1_B_12V MPX1_B_12V
PB5 PB6 PORTA [0..7] STR_12V MPX1_C_12V MPX1_C_12V
PB6 PORTA [0..7] OE_12V MPX1_D_12V MPX1_D_12V
LR[0..15]
PORTA[0..7] MPX1_A_12V LR[0..15] LR[0..15]
PORTA[0..7]
SEL[0..2] 15741_12 15741_9
SEL[0..2]
15741_1 0

A S-
A S- DS-
DS- FC3
FC3 TGATE1-
TGATE1- TGATE2-
TGATE2- HEBER L TD.

15741_2 Belvedere Mill

Chalfor d, Str oud
Glo ucester shire GL6 8NT
Tel: 0453 886000 Fax: 0453 885013

Title
PLUTO 5C - ROOT SHEET

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 1 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 45
Figure 2 - Schematic Sheet 2 - CPU

BACKGRO UND DEBUG

PP TCK CONNECT OR N7 N8
PP1 TMS 1 1
PP P16 V CC V CC
PP2 TDI IPIPE A S- 2 PB0 2
PP V CC
PP3 TDO IFETCH 10 9 RESET- R/W- 3 METER_SENSE 3
PP
PP4 FREEZE 8 7 BERR- 4 PB5 4
6 5 GND
IEEE 11 49.1 ACCESS
V CC BKPT GND BKPT 5 PB6 5
BERR- 4 3 DS- TCK 6 PB7 6
2 1 BR- 7 DONE1- 7
LOW PROFILE HDR 10W BGACK- 8 DONE2- 8

110
119
130
140
VCC V CC U5 FITTED FOR DEV . ONLY HA LT- 9 RESET- 9

19
31
41
50
59
68
74
86
92
94

78
77
76
75

83
82
85
84
7
3K3*8 SIL 3K3*8 SIL

TDO
TCK
TMS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

TDI

BKPT
FREEZE
IPIPE
IFETCH
R102 R103 69 144 D0
680R 680R 70 FC0 D0 143 D1
71 FC1 D1 142 D2
72 FC2 D2 141 D3 D[0..15]
TP9 D[0 ..15] 3,4,6,7,9,15,18
FC3 D3 138 D4
PAD
A S- 103 D4 137 D5
9 A S- DS- 104 AS D5 136 D6
9 DS- R/W- 107 DS D6 135 D7 A [0..23]
3,9,15,18 R/W- R/W D7 A [0..2 3] 3,4,6,9,15,18
SIZ0 105 134 D8
3,9 SIZ0 SIZ1 106 SIZ0 D8 133 D9
9 SIZ1 SIZ1 D9 132 D10
DSACK0 - 112 D10 131 D11
3,9,15 DSA CK0- DSACK1 - 111 DSA CK0 D11 128 D12
3,9 DSA CK1- DSA CK1 D12 126 D13
BERR- 99 D13 125 D14 LD1 R44
9 BERR- HA LT- 98 BERR D14 124 D15 RESET- RESET L ED
9 HA LT- HA LT D15 V CC
RESET- 97
10 RESET- RESET
RED 3K3
TP10 PP BR- 100
PP23 BG- 101 BR 113 A0
PAD PP
PP24 BGACK- 102 BG A0 37 A1
PP U7F
PP25 108 BGACK A1 38 A2 LD2 R45 SOFTWAR E
RMC A2 39 A3 PORTA 2 13 12 CONTROL LED
A3 V CC
PB0 87 42 A4 LED
10 PB0 CS1- 2 MODCK/PB0 A4 43 A5 GREEN 3K3
3 CS1- CS2- 3 CS1/IRQ1/PB1 A5 44 A6 74HC14
3 CS2- METER_SENSE 4 CS2/IRQ2/PB2 A6 45 A7
8 METER_SENSE CS3- 5 IRQ3/PB3 A7 46 A8
9 CS3- PB5 8 CS3/IRQ4/PB4 A8 47 A9
9,15 PB5 PB6 9 IRQ5/PB5 A9 48 A 10 SW3
9 PB6 PB7 10 IRQ6/PB6 A 10 51 A 11 PORTA 3 ON-BOAR D
8 NMI- IRQ7/PB7 A 11 GND
52 A 12 PUSHBUT TON
CS0- 1 A 12 53 A 13 SW PUSHBUTTON N15
3 CS0- CS0/A V EC A 13 55 A 14 1
A 14 V CC
RXDA 33 56 A 15 A0 2
9,10 RXDA TXDA 32 RXDA A 15 57 A 16 A1 3
9,10 TXDA CTSA - 28 TXDA A 16 60 A 17 PORTA [0..7] A2 4
9,10 CTSA - CTSA A 17 PORTA [0..7] 5,8,9,10
RTSA - 29 61 A 18 A3 5
9,10 RTSA - RTSA /OP0 A 18 62 A 19 A4 6
POP4 27 A 19 63 A 20 A5 7
N11
5 POP4 POP6 26 RXRDYA /OP4 A 20 64 A 21 1 A6 8
5 POP6 TXRDY A/OP6 A 21 V CC
65 A 22 PORTA 0 2 A7 9
RXDB 25 A 22 66 A 23 PORTA 1 3
10 RXDB TXDB 24 RXDB A 23 PORTA 2 4 3K3*8 SIL
10 TXDB CTSB- 22 TXDB PORTA 3 5
10 CTSB- RTSB- 23 CTSB PORTA 4 6 N10 N16
10 RTSB- RTSB/OP1 123 PORTA 0 PORTA 5 7 1 1
A 24/PA0 V CC V CC
79 122 PORTA 1 PORTA 6 8 D0 2 A8 2
9 TGA TE1- 81 TGA TE1 A 25/PA1/IACK1 121 PORTA 2 PORTA 7 9 D1 3 A9 3
V CC TIN1 A 26/PA2/IACK2
TOUT1 80 120 PORTA 3 D2 4 A 10 4
5 TOUT1 TOUT1 A 27/PA3/IACK3 117 PORTA 4 D3 5 A 11 5
3K3*8 SIL
36 A 28/PA4/IACK4 116 PORTA 5 D4 6 A 12 6
9 TGA TE2- 34 TGA TE2 A 29/PA5/IACK5 115 PORTA 6 D5 7 A 13 7
V CC TIN2 A 30/PA6/IACK6
TOUT2 35 114 PORTA 7 D6 8 A 14 8
5 TOUT2 TOUT2 A 31/PA7/IACK7 D7 9 A 15 9
DREQ1- 16 13 DREQ2-
3 DREQ1- DREQ1 DREQ2 DREQ2- 3
15 12 3K3*8 SIL 3K3*8 SIL
DONE1- 14 DA CK1 DA CK2 11 DONE2-
TP11
DONE1 DONE2
PA D N9 N17
CLKOUT 16.77MH z 95 1 V CC 1 V CC
3,9 CLKOUT CLKOUT D8 2 A 16 2
EXTA L 32.768K Hz 91 17 3.68MHZ D9 3 A 17 3
3 EXTA L EXTA L X1 3.68MHZ 3
D10 4 A 18 4
TP12 TP13 D11 5 A 19 5
PA D PA D D12 6 A 20 6
D13 7 A 21 7
89 20 D14 8 A 22 8
XTAL X2 D15 9 A 23 9
90 21 GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

VCCSYN SCLK
XFC

LC3 3K3*8 SIL 3K3*8 SIL

EMC FILTER
V CC 1 3 MC68340PV
109
118
127
129
139
93

18
30
40
49
54
58
67
73
88
96
6

C24 PP5
2

GND
100n PP
VCC V CC V CC VCC V CC V CC V CC V CC
C23
100n
C25 C26 C27 C28 C29 C30 C31 C32
100n 100n 100n 100n 100n 100n 100n 100n

GND GND GND GND GND GND GND GND GND

HEBER LTD.

Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013

Title
PLUTO 5C - MC68340 CPU

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-2 002
Date: Tuesday , August 12, 2003 Sheet 2 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 46
Figure 3 - Schematic Sheet 3 - FPGA

2 R/W-
2,9,15 DSA CK0-
2 SIZ0 CS_OP- 6
CS_IP- 7
10 RESET
RA M_WL- 4
2 CS0- RA M_WU- 4
2 CS1- RA M_OE- 4
2 CS2-
2,9 DSA CK1-
ROM_OE- 4
ROM_P1 4
D[0 ..15]
2,4,6,7,9,15,18 D[0 ..15]
D8
D9
D10
D11
D12

GND FPGA[0..6]
FPGA [0..6] 4
V CC
D13

U6 N14

11
10

84
83
82
81
80
79
78
77
76
75
9
8
7
6
5
4
3
2
1
1 VCC
FPGA 0 2

VCC

GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
FPGA 1 3
FPGA 2 4
A [0..2 3] 12 74 FPGA 3 5
2 A [0..2 3] D14 13 NC I/O 73 FPGA 4 6
D15 14 I/O I/O 72 FPGA 0 FPGA 5 7
A0 15 I/O I/O 71 FPGA 1 FPGA 6 8
A1 16 I/O I/O 70 FPGA 2 9
A2 17 I/O I/O 69 FPGA 3
18 I/O I/O 68
GND V CC 3K3*8 SIL
19 GND V CC 67
GND GND V CC V CC
A3 20 66 GND
A4 21 I/O MODE 65 FPGA 4
A5 22 I/O I/O 64
A6 23 I/O I/O(CLK) 63 FPGA 5
A7 24 I/O I/O 62 FPGA 6 SFX2_D[0..3]
I/O I/O SFX2_D[0..3] 5
V CC 25 61 GND
26 VCC GND 60
V CC VCC GND GND
A 19 27 59 SFX2_D0
A 20 28 I/O I/O 58 SFX2_D1
A 21 29 I/O I/O 57 SFX2_D2
A 22 30 I/O I/O 56 SFX2_D3
A 23 31 I/O I/O 55 SFX2_V CK
I/O I/O SFX2_V CK 5
32 54 RA M_LITH
I/O I/O RA M_LITH 18

GND
VCC

VCC
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
FPGA

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
SFX1_D[0..3] GND ROM_P12
SFX1_D[0..3] ROM_P12 4
V CC
SFX1_D0
SFX1_D1
SFX1_D2
SFX1_D3

5 SFX1_V CK

5,8 SFX_CLK

2 DREQ1- MPX_OE 13
2 DREQ2- MPX_CLK 13
MPX_STR 13
MPX1_DA TA_A 13
2,15 3.68MHZ CS_DUART- 15
2 EXTA L MPX_STR_DATA_A 13

2 CLKOUT

R104

10M

X1 R105

14.7456MHz 680R

C38 C37 HEBER L TD.

33p 33p V CC V CC V CC VCC
Belvedere Mill
GND GND Chalfor d, Str oud, GL6 8NT
C33 C34 C35 C36 Tel: +44 (0) 1453 886000
100n 100n 100n 100n Fax: +44 (0 ) 1 453 885 013

GND GND GND GND Title

PLUTO 5 C - FPGA

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 3 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 47
Figure 4 - Schematic Sheet 4 - Memory

D[0..15]
2,3,6,7,9,15,18 D[0..15]
A [0..23]
2 A [0..2 3]

VBATT V BATT
ROM_ P12
3 ROM_P12
U2 U1 U4 U3

28

28
12 13 D0 12 13 D8 A1 10 11 D0 A1 10 11 D8

VDD

VDD
A1 11 A0 D0 14 D1 A1 11 A0 D0 14 D9 A2 9 A0 O0 12 D1 A2 9 A0 O0 12 D9
A2 10 A1 D1 15 D2 A2 10 A1 D1 15 D10 A3 8 A1 O1 13 D2 A3 8 A1 O1 13 D10
A3 9 A2 D2 17 D3 A3 9 A2 D2 17 D11 A4 7 A2 O2 15 D3 A4 7 A2 O2 15 D11
A4 8 A3 D3 18 D4 A4 8 A3 D3 18 D12 A5 6 A3 O3 16 D4 A5 6 A3 O3 16 D12
A5 7 A4 D4 19 D5 A5 7 A4 D4 19 D13 A6 5 A4 O4 17 D5 A6 5 A4 O4 17 D13
A6 6 A5 D5 20 D6 A6 6 A5 D5 20 D14 A7 4 A5 O5 18 D6 A7 4 A5 O5 18 D14
A7 5 A6 D6 21 D7 A7 5 A6 D6 21 D15 A8 3 A6 O6 19 D7 A8 3 A6 O6 19 D15
A8 27 A7 D7 A8 27 A7 D7 A9 25 A7 O7 A9 25 A7 O7
A9 26 A8 V CC A9 26 A8 V CC A 10 24 A8 A 10 24 A8
A 10 23 A9 A 10 23 A9 A 11 21 A9 A 11 21 A9
A 11 25 A 10 A 11 25 A 10 A 12 23 A 10 A 12 23 A 10
A 12 4 A 11 C21 A 12 4 A 11 C22 A 13 2 A 11 V BATT A 13 2 A 11 V BATT
A 13 28 A 12 100n A 13 28 A 12 100n A 14 26 A 12 A 14 26 A 12
A 14 29 A 13 A 14 29 A 13 A 15 1 A 13 A 15 1 A 13
A 15 3 A 14 GND A 15 3 A 14 GND A 14 C20 A 14 C19
A 16 2 A 15 A 16 2 A 15 27 100n 27 100n
A 17 30 A 16 A 17 30 A 16 3 RA M_WL- 20 WR 3 RA M_WU- 20 WR

GND

GND
A 18 31 A 17 32 A 18 31 A 17 32 10 RA M_CS- 22 CE GND 10 RA M_ CS- 22 CE GND
A 18 VCC V CC A 18 V CC V CC
3 RA M_OE- OE 3 RA M_ OE- OE
ROM_ P1 1 ROM_P1 1 HM62256BLFP HM62256BLFP
3 ROM_P1 V PP 3 ROM_P1 V PP

14

14
ROM_ OE- 24 ROM_OE- 24
3 ROM_OE- 22 OE 16 3 ROM_ OE- 22 OE 16
GND CE GND GND GND CE GND GND
GND GND
EPROM EPROM
EPROMS - 2*27C040 OR 2*27C801 U3/U4 - 32K*8 STATIC RAMS, SOP

PINS 1, 12 SET BY FPG A

CS0- MODE ROM_P1 ROM_P12

0 READ 1* 27C040 VCC A0

0 READ 2* 27C040 VCC A19
0 READ 1* 27C801 A19 A0
0 READ 2* 27C801 A20 A19
1 NON-ROM CYCLE A20 A0/A19
x RESET 1 1

------- ------------- ------------ --- MEMORY EX PANSION CONNE CTOR ------- ------------- ------------- -------

A [0..2 3]
2 A [0..23]

P15a P15b P15c

A4 A1 A5 B1 A6 C1
A2 A1 A7 B2 B1 A8 C2 C1
V CC A2 B2 C2
A3 A9 B3 A 10 C3 LINES F PGA0-6 HAVE T HE FOLLOWING DEFAULT FUNC TIONS
A3 A4 A3 A 11 B4 B3 A 12 C4 C3
A2 A5 A4 A 13 B5 B4 A 14 C5 C4
A1 A6 A5 A 15 B6 B5 A 16 C6 C5 NAME I/O FUNCTIO N
A7 A6 A 17 B7 B6 A 18 C7 C6
GND A7 B7 C7
A8 A 19 B8 ROM_ P1 (A20) C8 FPGA0 IN MEM_CAR D_PRESENT-
FPGA 0 A9 A8 A 21 B9 B8 D15 C9 C8 FPGA1 OUT ROM_MAP _1
FPGA 1 A 10 A9 D14 B10 B9 D13 C10 C9 FPGA2 OUT ROM_MAP _2
FPGA 2 A 11 A 10 D12 B11 B10 D11 C11 C10 FPGA3 OUT WU- (WR ITE HIGH BYTE )
FPGA 3 A 12 A 11 D10 B12 B11 D9 C12 C11 FPGA4 OUT WL- (WR ITE LOW BYTE)
FPGA 4 A 13 A 12 D8 B13 B12 D7 C13 C12 FPGA5 OUT RAM_CS- (CS- FOR EXP ANSION RAM)
FPGA 5 A 14 A 13 D6 B14 B13 D5 C14 C13 FPGA6 OUT A22
FPGA 6 A 15 A 14 D1 B15 B14 D3 C15 C14
D0 A 16 A 15 D2 B16 B15 D4 C16 C15
A 16 B16 C16
DIN41612-48W DIN41612-48W DIN41612-48W
TY PE "C/2" V ERT SKT TY PE "C/2" V ERT SKT TY PE "C/2" V ERT SKT

D[0 ..15]
2,3,6,7,9,15,18 D[0 ..15]

FPGA [0..6]
3 FPGA[0..6]

HEBER L TD.

Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0 ) 1 453 885 013

Title
PLUTO 5 C - MAIN EPROM/RA M

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 4 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 48
Figure 5 - Schematic Sheet 5 - Sound

SAMPLED SOUND CHANNEL #1 SAMPLED SOUND CHANNEL #2

V CC V CC
C40 C39
GND GND
SFX1_D[0..3] 100n SFX2_D[0..3] 100n
SFX1_D[0..3] 3 SFX2_D[0..3]
U8 U39

18

18
VDD

VDD
SFX1_D0 4 12 GND SFX2_D0 4 12 GND
SFX1_D1 5 D0 T1 13 SFX2_D1 5 D0 T1 13
SFX1_D2 6 D1 T2 3 PORTA [0..7] SFX2_D2 6 D1 T2 3
SFX1_D3 7 D2 T3 8 2,8,9,10 PORTA[0..7] SFX2_D3 7 D2 T3 8
PORTA[0..7] D3 T4 D3 T4
POP4 SFX1_S1 1 PORTA 6 SFX2_S1 1
2 POP4 POP6 SFX1_S2 2 S1 11 PORTA 7 SFX2_S2 2 S1 11
2 POP6 S2 DAO S2 DAO
PORTA 0 15 PORTA 1 15
RESET RESET
SFX_CLK 16 10 SFX_CLK 16 10
3 SFX_CLK XT AOUT 3 SFX_CLK XT A OUT

17 14 17 14

GND

GND
XT V CK XT V CK

MSM6585 MSM6 585

9
R111 R130
47K 2% 47K 2%
GND GND
SFX1_V CK SFX2_V CK
3 SFX1_V CK 3 SFX2_V CK
C44 C51
10n 10n
R129 C49

R112 R131
22K 1/50 22K 22K

+12V

GND GND
C50
C43 GND
GND
220/16
100n
U32
4

+
LS CONN ECTOR 13
+ C47 PP6
P10 3
1 LS1+
2 LS1- 11 - 1/50 PP
3 CH2_MIX R108
4 LS2+ 1
TOUT1 2
5 LS2-
8 3K3
HDR 5W A MP MTA - 100 + C48 C45 R109 PP7
5 1/50 3K3

10 - 1/50 PP
R110
7
TOUT2 2
3K3
TDA 7057A Q C46 R113
12

1/50 3K3
9

GND

HEBER L TD.

Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0 ) 1 453 885 013

Title
PLUTO 5 C - SOUND

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 5 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 49
Figure 6 - Schematic Sheet 6 – Open Drain Outputs

OP[0..63]
OP[0..63] 9

U22 U26
VCC V CC V CC V CC D0 18 4 OP56 D4 18 4 OP60
D Q0 5 OP48 D Q0 5 OP52
SEL0 3 Q1 6 OP40 SEL0 3 Q1 6 OP44
C1 C3 C2 C4 SEL1 8 S0 Q2 7 OP32 SEL1 8 S0 Q2 7 OP36
100n 100n 100n 100n SEL2 12 S1 Q3 14 OP24 SEL2 12 S1 Q3 14 OP28
S2 Q4 15 OP16 S2 Q4 15 OP20
GND GND GND GND 13 Q5 16 OP8 13 Q5 16 OP12
19 G Q6 17 OP0 19 G Q6 17 OP4
CLR Q7 CLR Q7

VCC 2 1 GND V CC 2 1 GND

V CC PGND 10 V CC PGND 10
PGND GND PGND GND
11 GND 11 GND
9 PGND 20 9 PGND 20
GND GND PGND GND GND GND PGND GND
TPIC6259 TPIC6259

U23 U27
A [0..23] D1 18 4 OP57 D5 18 4 OP61
2 A [0..23] D Q0 5 OP49 D Q0 5 OP53
U7A
SEL0 3 Q1 6 OP41 SEL0 3 Q1 6 OP45
A1 1 2 SEL0 SEL1 8 S0 Q2 7 OP33 SEL1 8 S0 Q2 7 OP37
SEL2 12 S1 Q3 14 OP25 SEL2 12 S1 Q3 14 OP29
S2 Q4 15 OP17 S2 Q4 15 OP21
13 Q5 16 OP9 13 Q5 16 OP13
74HC14
19 G Q6 17 OP1 19 G Q6 17 OP5
U7B
CLR Q7 CLR Q7
A2 3 4 SEL1 VCC 2 1 GND V CC 2 1 GND
V CC PGND 10 V CC PGND 10
PGND GND PGND GND
11 GND 11 GND
9 PGND 20 9 PGND 20
74HC14 GND GND GND GND
GND PGND GND PGND
U7C
TPIC6259 TPIC6259
A3 5 6 SEL2

U24 U28
74HC14 D2 18 4 OP58 D6 18 4 OP62
D Q0 5 OP50 D Q0 5 OP54
SEL0 3 Q1 6 OP42 SEL0 3 Q1 6 OP46
SEL1 8 S0 Q2 7 OP34 SEL1 8 S0 Q2 7 OP38
SEL2 12 S1 Q3 14 OP26 SEL2 12 S1 Q3 14 OP30
S2 Q4 15 OP18 S2 Q4 15 OP22
13 Q5 16 OP10 13 Q5 16 OP14
19 G Q6 17 OP2 19 G Q6 17 OP6
CLR Q7 CLR Q7
VCC 2 1 GND V CC 2 1 GND
V CC PGND 10 V CC PGND 10
PGND GND PGND GND
11 GND 11 GND
9 PGND 20 9 PGND 20
GND GND PGND GND GND GND PGND GND
TPIC6259 TPIC6259

U25 U29
D3 18 4 OP59 D7 18 4 OP63
D Q0 5 OP51 D Q0 5 OP55
SEL0 3 Q1 6 OP43 SEL0 3 Q1 6 OP47
SEL1 8 S0 Q2 7 OP35 SEL1 8 S0 Q2 7 OP39
SEL2 12 S1 Q3 14 OP27 SEL2 12 S1 Q3 14 OP31
S2 Q4 15 OP19 S2 Q4 15 OP23
GP_OP- 13 Q5 16 OP11 13 Q5 16 OP15
19 G Q6 17 OP3 19 G Q6 17 OP7
10 RESET- CLR Q7 CLR Q7
VCC 2 1 GND V CC 2 1 GND
V CC PGND 10 V CC PGND 10
PGND GND PGND GND
11 GND 11 GND
9 PGND 20 9 PGND 20
GND GND PGND GND GND GND PGND GND
TPIC6259 TPIC6259

D[0..15]
2,3,4,7,9 ,15,18 D[0..15] SEL[0..2]
SEL[0..2] 7

A[0..23]

U52B
A4 14 12 GP_OP- HEBER L TD.
13 A Y0 11 CS_TTL-
GND B Y1 CS_TTL- 9
10 Belvedere Mill
CS_OP- 15 Y2 9 Chalfor d, Str oud, GL6 8NT
3 CS_OP- G Y3 Tel: +44 (0) 1453 886000
74HCT139 Fax: +44 (0 ) 1 453 885 013

Title
PLUTO 5 C - OUTPUTS

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 6 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 50
Figure 7 - Schematic Sheet 7 - Inputs

IP[0..31]
IP[0..31] 9

D[0 ..15]
2,3,4,6,9,15,18 D[0 ..15]
U9 R1
D0 7 6 R2 IP24 V CC
1Y 1C0 5 IP16
R3
1C1

1
4 47K 2% R4 IP8
1C2 3 IP0 N12
47K 2%
1C3 3K3*8 SIL
R5 47K 2%
D1 9 10 R6 47K 2% IP25
2Y 2C0 11 IP17
R7

2
3
4
5
6
7
8
9
2C1 12 IP9
47K 2% R8 U14 SW1
2C2 13 IP1 D8 7 6 1 16
47K 2%
2C3 1Y 1C0 5 2 15
47K 2%
14 SEL0 1C1 4 3 14
47K 2%
A 2 SEL1 1C2 3 4 13
B 1C3

9
8
7
6
5
4
3
2
1 5 12
1G 15 N1 D9 9 10 6 11
2G 3K3*8 SIL 2Y 2C0 11 7 10
2C1 12 8 9
74HC253
2C2 13
U10 R9

1
VCC 2C3
D2 7 6 R10 IP26 8W DIL SW
1Y 1C0 5 IP18 14 SEL0
R11
1C1 4 IP10 A 2 SEL1
47K 2% R12
1C2 3 IP2 B 1
47K 2%
1C3 1G 15 GND
R13 47K 2%
D3 9 10 IP27 2G
R14 47K 2%
2Y 2C0 11 IP19
R15 74HC253
2C1 12 IP11
47K 2% R16
V CC 2C2 13 IP3 V CC
47K 2%
2C3
47K 2%

1
14 SEL0 47K 2%
C5 A 2 SEL1 N13
B

9
8
7
6
5
4
3
2
100n 1 3K3*8 SIL
1G 15 N2
GND 2G 3K3*8 SIL

2
3
4
5
6
7
8
9
74HC253 U13 SW2
U11 R17 D10 7 6 1 16

1
VCC 1Y 1C0
D4 7 6 R18 IP28 5 2 15
1Y 1C0 5 IP20 1C1 4 3 14
R19
1C1 4 IP12 1C2 3 4 13
47K 2% R20
1C2 3 IP4 1C3 5 12
47K 2%
1C3 D11 9 10 6 11
R21 47K 2%
D5 9 10 IP29 2Y 2C0 11 7 10
R22 47K 2%
2Y 2C0 11 IP21 2C1 12 8 9
R23
2C1 12 IP13 2C2 13
47K 2% R32
2C2 13 IP5 2C3
47K 2% 8W DIL SW
2C3 14 SEL0
47K 2%
14 SEL0 A 2 SEL1
47K 2%
A 2 SEL1 B 1
B 1G

9
8
7
6
5
4
3
2
1 15 GND
1G 15 N3 2G
2G 3K3*8 SIL 74HC253
74HC253
U12 R24

1
VCC
D6 7 6 R25 IP30
1Y 1C0 5 IP22
R26
1C1 4 IP14
47K 2% R27
1C2 3 IP6
47K 2%
1C3
R28 47K 2%
D7 9 10 R29 47K 2% IP31
2Y 2C0 11 IP23
R30
2C1 12 IP15
47K 2% R31
V CC 2C2 13 IP7
47K 2%
2C3
47K 2%
14 SEL0 47K 2%
C6 A 2 SEL1
B
9
8
7
6
5
4
3
2

100n 1
1G 15 N4
GND 2G 3K3*8 SIL
74HC253
1

VCC
3 CS_IP-

SEL[0..2]
6 SEL[0..2]
NOTE: S EL0-2 ARE INV ERTED A1-3
HEBER L TD.

Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0 ) 1 453 885 013

Title
PLUTO 5 C - INPUTS

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 7 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 51
Figure 8 - Schematic Sheet 8 - Power Supply

+12V
+12V

D1
UF4002
R33
47R
METER DETECTION
V METER+ 1 3 POWER FAIL DETECTION R35
LC1 V CC 47K 2%
EMC FILTER
U16B PP13

2
GND
7
R37 R38 R39 R40 1 +
+12V 47K 2% 47K 2% 47K 2% 4K7
R40 revision: 2 NMI- 6
PP
3k3 -> 4k7 Jul 2003 - V REF 10
R34
LM339 22K
U16A

3
PP8
5
METER_SENSE 2 + GND
R36 PP9
2 METER_SENSE 4 PP
-
LM339 PP10 47K 2% PP

12
GND TP5
PP PA D
GND

V CC TP6
V CC PA D

+12V TP7
R124 D21 PA D
PORTA [0..7] 47K 2% SFX_CLK
2,5,9,10 PORTA [0..7] SFX_CLK 3
U16C PP11 1N4148 +12V _IN TP8
PA D
- 8
PORTA7 14 PP R127
+ 9 MPX_REF1
MPX_REF1 11
LM339 22K

Thresho ld 2 - Lamp s hort cct. R125

1K

U16D PP12
MPX CURRENT
- 10
PORTA6 13 PP
+ 11 SENSE
LM339
C9 C10
Thresho ld 1 - Lamp p resent 47p 47p
R126
120R
GND GND

MPX_REF2
MPX_REF2 11

V MOT+

+12V
LC2 U15
F1 EMC FILTER LM7805 P3
+12V _IN 1 3 V CC -12V 1
VI VO 2
GND
GND

3.15A F 20*5MM GND 3

-12V 4 POWER IN
2

+12V _IN
MPX_GND 5
V MPX+ 6

D20 C7 C8 D2 D3 HDR 6W A MP MTA - 156

SA 15 1/50 1/50 SA 5 SA 15

GND

GND GND

MPX_GND GND

GND V SS
REGULATED +5V HEBER LTD.

Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013

Title
PLUTO 5C - POWER SUPPLY

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , August 12, 2003 Sheet 8 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 52
Figure 9 - Schematic Sheet 9 – IO Connectors

I/O 1
P8
OP24 A1 B1 OP25
OP26 A2 A1 B1 B2 OP27
OP28 A3 A2 B2 B3 OP29
OP30 A4 A3 B3 B4 OP31
OP32 A5 A4 B4 B5 OP33 V CC
OP34 A6 A5 B5 B6 OP35
A6 B6

1
OP36 A7 B7 OP37
OP38 A8 A7 B7 B8 OP39 N20 TTL I/O
OP40 A9 A8 B8 B9 OP41 12 LR[0..15] 1K0*8 SIL
OP42 A 10 A9 B9 B10 OP43
OP44 A 11 A 10 B10 B11 OP45 LR[0..15] P12

2
3
4
5
6
7
8
9
OP46 A 12 A 11 B11 B12 OP47 1
U30 GND
A 13 A 12 B12 B13 D8 18 4 2
GND A 13 B13 GND D Q0
IP20 A 14 B14 IP21 5 3
IP22 A 15 A 14 B14 B15 IP23 A0 3 Q1 6 4
IP24 A 16 A 15 B15 B16 IP25 11 LC[0..15] A1 8 S0 Q2 7 5
IP26 A 17 A 16 B16 B17 IP27 A2 12 S1 Q3 14 6
IP28 A 18 A 17 B17 B18 IP29 LC[0..15] S2 Q4 15 7
IP30 A 19 A 18 B18 B19 IP31 CS_TTL- 13 Q5 16 8
A 19 B19 6 CS_TTL- G Q6 +12V
+12V A 20 B20 +12V RESET- 19 17
A 20 B20 REELS CLR Q7
HDR 8W A MP MTA - 100
V CC 2 1 GND
HDR 40W V CC PGND 10 PIC_IP0
P7 GND PIC_IP0 18
LC0 A1 B1 LC1 PGND 11
A1 B1 PGND GND
I/O 2 LC2 A2
A2 B2
B2 LC3 GND 9
GND PGND
20 GND PIC_IP1
PIC_IP1 18
LC4 A3 B3 LC5
LR0 A4 A3 B3 B4 LR1
P9 TPIC6B259
OP48 A1 B1 OP49 LR2 A5 A4 B4 B5 LR3 LC4 2
OP50 A2 A1 B1 B2 OP51 LR4 A6 A5 B5 B6 LR5 I C
EMC FILTER
OP52 A3 A2 B2 B3 OP53 A7 A6 B6 B7 3 1
A3 B3 GND A7 B7 V CC
OP54 A4 B4 OP55 OP0 A8 B8 OP1 P13
OP56 A5 A4 B4 B5 OP57 OP2 A9 A8 B8 B9 OP3 1
A5 B5 A9 B9 GND
OP58 A6 B6 OP59 OP4 A 10 B10 OP5 LC5 2

2
OP60 A7 A6 B6 B7 OP61 OP6 A 11 A10 B10 B11 OP7 GND 3
EMC FILTER
OP62 A8 A7 B7 B8 OP63 OP8 A 12 A11 B11 B12 OP9 1 3 4
A8 B8 A12 B12 VCC
GND A9 B9 GND OP10 A 13 B13 OP11
IP6 A 10 A9 B9 B10 IP7 OP12 A 14 A13 B13 B14 OP13 HDR 4W A MP MTA - 100
IP8 A 11 A 10 B10 B11 IP9 OP14 A 15 A14 B14 B15 OP15

2
IP10 A 12 A 11 B11 B12 IP11 OP16 A 16 A15 B15 B16 OP17
IP12 A 13 A 12 B12 B13 IP13 OP18 A 17 A16 B16 B17 OP19 GND
IP14 A 14 A 13 B13 B14 IP15 OP20 A 18 A17 B17 B18 OP21
IP16 A 15 A 14 B14 B15 IP17 OP22 A 19 A18 B18 B19 OP23
IP18 A 16 A 15 B15 B16 IP19 IP0 A 20 A19 B19 B20 IP1
A 17 A 16 B16 B17 IP2 A 21 A20 B20 B21 IP3
+12V A 17 B17 A21 B21
IP4 A 22 B22 IP5
A 23 A22 B22 B23
V MOT+ VMOT+ U7E
HDR 34W A 24 A23 B23 B24
V MOT+ VMOT+ R107
A 25 A24 B24 B25 10 11
VMETER+ V MOT+ A25 B25 VMOT+ 2 TGATE2-
PP15 22K
HDR 50W 74HC14 PIC_OP0
PIC_OP0 18
PP14
PP
IP[0..31]
7 IP[0..3 1]
PP
U7D
OP[0..63] R106
6 OP[0..63] 8 9
2 TGATE1-
PP17 22K
74HC14 PIC_OP1
PIC_OP1 18
PP16
PP

PP

PORTA [0..7]
2,5,8,10 PORTA [0..7]
D[0..15]
2,3,4,6,7,15,18 D[0..15]
P14c P14b P14a
D8 C1 PORTA0 B1 HALT- A1
D9 C2 C1 PORTA1 B2 B1 2 HA LT- CLKOUT A2 A1
D10 C3 C2 PORTA2 B3 B2 2 CLKOUT CS3- A3 A2
D11 C4 C3 PORTA3 B4 B3 2 CS3- RESET- A4 A3
D12 C5 C4 PORTA4 B5 B4 10 RESET- BERR- A5 A4
D13 C6 C5 PORTA5 B6 B5 2 BERR- A 20 A6 A5
D14 C7 C6 A 22 B7 B6 A 23 A7 A6
D15 C8 C7 A S- B8 B7 A4 A8 A7
RXDA C9 C8 2 A S- DS- B9 B8 A5 A9 A8
2,10 RXDA TXDA C10 C9 2 DS- R/W- B10 B9 A6 A 10 A9
2 TXDA CTSA - C11 C10 2 R/W- DSACK0 - B11 B10 A7 A 11 A 10
2 CTSA - RTSA - C12 C11 2,3,15 DSA CK0- DSACK1 - B12 B11 A 12 A 11
2 RTSA - C12 2,3 DSA CK1- B12 +12V A 12
A0 C13 SIZ0 B13 V CC A 13
A1 C14 C13 2 SIZ0 SIZ1 B14 B13 A 14 A 13
C14 2 SIZ1 B14 V CC A 14
A2 C15 PB5 B15 GND A 15
A3 C16 C15 2,15 PB5 PB6 B16 B15 A 16 A 15
C16 2 PB6 B16 GND A 16 HEBER L TD.
DIN41612-48W DIN41612-48W DIN41612-48W
TYPE "R/2" V ERT MALE TY PE "R/2" V ERT MALE TY PE "R/2" V ERT MALE Belvedere Mill
Chalfor d, Str oud, GL6 8NT
2 A [0..23]
A [0..23] I/O EXP. Tel: +44 (0) 1453 886000
Fax: +44 (0 ) 1 453 885 013

Title
PLUTO 5 C - CONNECTORS

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 9 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 53
Figure 10 - Schematic Sheet 10 - Reset/Battery/RS232 Channels A & B

BATTERY BACK-UP
SM
Q2
V CC FMMT717 VBATT

TP16 TP14 R42

PA D PA D 3K3

R43
3K3 PP18 RA M_CS- 4
R132
+12V -12V
TP15 PP
PA D 3K3 Q1
BT1 C11 2N7002
2.4V NiMH 1/50 U33

14

1
P1
GND GND 1

V+

V-
2
2 3 3 RS232
RESET- 2 TXDA A1 TXA 4 (PORT A )
4 5
2 RTSA - 5 B1 6 6
VCC B2 TXB +12V
9 HDR 6W A MP MTA - 100
2 TXDB 10 C1 8
VCC C2 TXC
12
2 RTSB- 13 D1 11
VCC D2 TXD

GND
1488

7
C52
22p
X2
32Khz
RTC GND

U40
1 8 V BATT PORTA[0..7] P2
OSCI V DD PORTA [0..7] 2,5,8,9
GND 2 7 R160 1
3 OSCO INT 6 SCL PORTA 4 14
4 A0 SCL 5 SDA 2
GND GND SDA 120R 15
PCF8583 R161 3
PORTA 5 16
4
120R 17
EEPROM 5
GND 18
U37 6
GND 1 8 V CC VCC 19 DATAPOR T
2 A0 V CC 7 7 (PORT B )
GND A1 TST GND GND
V CC 3 6 20
4 A2 SCL 5 8
U38

14
GND GND SDA 21
24C04/24C08 9

VCC
22
10
R114
INTERNA L I2C BUS 3 1 23
2,9 RXDA A RXA 11
R115 3K3 -12 V
6 4 24
2 CTSA - B RXB 12
3K3 8 10 25
2 RXDB C RXC +12V
13
11 13
2 CTSB- D RXD
25W D SOCKET

GND
1489

7
PP19

POWER-ON RESET GND

PP
VCC

8 V REF
U17
8

RESET- 5 7
VCC

2,6,9,15,18 RESET- RESET SENSE

RESET 6 2 RESIN-
3 RESET RESET RESIN PB0 2
GND

1 3
R41 C12 REF CT V CC
3K3 100n TL7705 C14
C13 220/16
4

100n
C53 HEBER L TD.
GND
100n
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
GND Tel: +44 (0) 1453 886000
Fax: +44 (0 ) 1 453 885 013

Title
PLUTO 5 C - RESET/BA TTERY/RS232

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 10 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 54
Figure 11- Schematic Sheet 11 - Lamp Column/LED Digit Drives

GND

1
N18 LC[0..15]
3K3*8 SIL LC[0..15] 9

LC0 LC0 DIG0

2
3
4
5
6
7
8
9
D4
U20 R94 Q35 UF4002
1 4 R95
13 STR_12V 2 STR Q1 5 LC1 LC1 DIG1
R96
13 STR_A _12V 3 D Q2 6 680R R97 D5
13 CLK_12V 15 CLK Q3 7 R98 680R Q36
BUK552 UF4002
13 OE_12V OE Q4 14 R99 680R
Q5 13 LC2 LC2 DIG2
R100 680R
16 Q6 12
+12v 680R R101 D6
VDD Q7 11 680R Q37
BUK552 UF4002
Q8
680R
9 680R LC3 LC3 DIG3
8 QS 10 GND
GND GND QS D7
Q38
BUK552 UF4002

1
4094
N19 * LC4 LC4 DIG4
3K3*8 SIL
D8
Q39
BUK552 UF4002

2
3
4
5
6
7
8
9
LC5 LC5 DIG5 P4
U21 * R116 *
D9 LC0 1
1 4 R117 * LC1 2
STR Q1 Q40
BUK552 UF4002
2 5 R118 * LC2 3
3 D Q2 6 LC6 LC6 DIG6 LC3 4
680R R119 *
15 CLK Q3 7 LC4 5
R120 * 680R D10
+12V +12V OE Q4 14 LC5 6
R121 * 680R Q41
BUK552 UF4002
Q5 13 LC6 7
R122 * 680R
16 Q6 12 LC7 LC7 DIG7 LC7 8
+12v 680R R123 *
C17 C18 VDD Q7 11 LC8 9
680R D11
100n 100n Q8 LC9 10
680R Q42
BUK552 UF4002
9 680R LC10 11
GND GND 8 QS 10 LC8 LC8 DIG8 LC11 12
GND GND QS * *
D12 LC12 13
4094 LC13 14
Q43
BUK552 UF4002
LC14 15
LC9 LC9 DIG9 LC15 16
* *
D13 17
18
Q44
BUK552 UF4002
LC10 LC10 DIG10
HDR 18W A MP MTA - 100
P5 * *
D14
DIG0 A1 B1 DIG1 LAMP CO LUMNS(SINKS)
A1 B1 Q45
BUK552 UF4002
DIG2 A2 B2 DIG3
DIG4 A3 A2 B2 B3 DIG5 LC11 LC11 DIG11
DIG6 A4 A3 B3 B4 DIG7 * *
A4 B4 D15
DIG8 A5 B5 DIG9
A5 B5 Q46
BUK552 UF4002
DIG10 A6 B6 DIG11
DIG12 A7 A6 B6 B7 DIG13 LC12 LC12 DIG12
DIG14 A8 A7 B7 B8 DIG15 * *
A8 B8 D16
SEG0 A9 B9 SEG1
A9 B9 Q47
BUK552 UF4002
SEG2 A 10 B10 SEG3
SEG4 A 11 A 10 B10 B11 SEG5 LC13 LC13 DIG13
SEG6 A 12 A 11 B11 B12 SEG7 * *
A 12 B12 D17
SEG8 A 13 B13 SEG9
A 13 B13 Q48
BUK552 UF4002
SEG10 A 14 B14 SEG11
SEG12 A 15 A 14 B14 B15 SEG13 LC14 LC14 DIG14
SEG14 A 16 A 15 B15 B16 SEG15 * *
A 16 B16 D18
Q49
BUK552 UF4002
HDR 32W A MP ULTREX D4-D19 Changed from 1N4005 to UF 4002
OR 34W BOX HEADER, LC15 LC15 DIG15 March, 2003
Pins 33/34 - no connection * *
D19
Q50
BUK552 UF4002

DIG[0..15]

7 SEG L ED DRIVE (32 DIGIT) BUK552

OR 14 S EG LED DRIVE (16 DIGIT) MPX_REF1
MPX_REF1 8

* - THESE C OMPONENTS OMI TTED Rsense

ON PLUT O 5 128/16. 24 milliohms
(DRIVE FOR LC8-15/D IG8-15) copper track

MPX_REF2
MPX_REF2 8
SEG[0..15]
13 SEG[0..15]

MPX_GND

HEBER L TD.

Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0 ) 1 453 885 013

Title
PLUTO 5 C - LA MP/LED SINKS

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 11 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 55
Figure 12 - Schematic Sheet 12 - Lamp Row Drives

V MPX+

1
N5
3K3*8 SIL
V MPX+ LR0

2
3
4
5
6
7
8
9
Q19
R54
TIP126
GND
V MPX+ LR1
U18 R85 22K Q20
1 4 R84 Q11 R55
13 STR_12V 2 STR Q1 5 TIP126
R83 GND
LAMP RO WS(SOURCE)
13 MPX1_A _12V 3 D Q2 6 LR2
3K3 R82 V MPX+
13 CLK_12V 15 CLK Q3 7 R81 3K3 BC846 22K Q21 P6
13 OE_12V OE Q4 14 LR0 1
R80 3K3 Q12 R56
Q5 13 TIP126 LR1 2
R79 3K3 GND
16 Q6 12 LR3 LR2 3
+12V 3K3 R78 V MPX+
V DD Q7 11 LR3 4
3K3 BC846 22K Q22
Q8 LR4 5
3K3 Q13 R57
9 3K3 TIP126 LR5 6
QS GND
GND 8 10 V MPX+ LR4 LR6 7
GND QS LR7 8
BC846 22K Q23
4094 Q14 R58 LR8 9
TIP126 LR9 10
GND
V MPX+ LR5 LR10 11
13 MPX1_B_12V LR11 12
BC846 22K Q24
Q15 R59 LR12 13
TIP126 LR13 14
GND
+12V V MPX+ LR6 LR14 15
BC846 22K LR15 16
Q25
Q16 R60
C15 TIP126 HDR 16W A MP MTA - 100
GND
100n LR7
V MPX+
BC846 22K Q26
GND Q17 R61
TIP126
GND

BC846 22K
Q18
V MPX+

1
BC846
PP20 PP21 PP22 N6
PP PP PP 3K3*8 SIL
V MPX+ LR8

2
3
4
5
6
7
8
9
Q27
R46
TIP126
GND
V MPX+ LR9
U19 R93 22K Q28
1 4 R92 Q3 R47
2 STR Q1 5 TIP126
R91 GND
13 MPX1_C_12V 3 D Q2 6 LR10
3K3 R90 V MPX+
15 CLK Q3 7 R89 3K3 BC846 22K Q29
OE Q4 14 R88 3K3 Q4 R48
Q5 13 TIP126
R87 3K3 GND
16 Q6 12 LR11
+12V 3K3 R86 V MPX+
V DD Q7 11 3K3 BC846 22K Q30
Q8
3K3 Q5 R49
9 3K3 TIP126
QS GND
GND 8 10 V MPX+ LR12
GND QS
BC846 22K Q31
4094 Q6 R50
TIP126
GND
V MPX+ LR13
13 MPX1_D_12V
BC846 22K Q32
Q7 R51
TIP126
GND
+12V V MPX+ LR14
BC846 22K Q33
Q8 R52
C16 TIP126
GND
100n LR15 LR[0..15]
V MPX+ LR[0..15] 9
BC846 22K Q34
GND Q9 R53
TIP126
GND

BC846 22K
Q10

BC846

HEBER L TD.

Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0 ) 1 453 885 013

Title
PLUTO 5 C - LA MP ROW DRIVES

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 12 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 56
Figure 13 - Schematic Sheet 13 - LED Segment Drives

U34
3 2 OE_12V
3 MPX_OE AI AO OE_12V 11,12
5 4 CLK_12V
3 MPX_CLK BI BO CLK_12V 11,12
7 6 STR_12V R62
3 MPX_STR CI CO STR_12V 11,12
9 10 MPX1_A_12V +12V SEG0
3 MPX1_DA TA_A DI DO MPX1_A _12V 12
11 12 Q51
14 EI EO 15 STR_A _12V
STR_A _12V 11 BC337 150R
3 MPX_STR_DATA_A FI FO
R63
V CC 13 16 +12V SEG1
MODE VDD
Q52
V CC 1 8 GND BC337 150R
V CC GND
R64
SEG2
4504 Q53
BC337 150R
U35 R65
1 4 SEG3
2 STR Q1 5
12 MPX1_B_12V D Q2 Q54
3 6 BC337 150R
15 CLK Q3 7 R66
OE Q4 14 SEG4
Q5 13
Q6 Q55
+12V 16 12 BC337 150R
V DD Q7 11 R67
Q8 SEG5
9 Q56
8 QS 10
GND BC337 150R
GND QS
R68
4094 SEG6
Q57
BC337 150R
12 MPX1_C_12V
R69
+12V SEG7
Q58
BC337 150R
C41
100n

GND

R70
+12V SEG8
Q59
BC337 150R
+12V R71
SEG9
Q60
C42 BC337 150R
100n R72
SEG10
GND Q61
BC337 150R
U36 R73
1 4 SEG11
2 STR Q1 5
12 MPX1_D_12V D Q2 Q62
3 6 BC337 150R
15 CLK Q3 7 R74
OE Q4 14 SEG12
Q5 13
Q6 Q63
+12V 16 12 BC337 150R
V DD Q7 11 R75
Q8 SEG13
9 Q64
8 QS 10
GND BC337 150R
GND QS
R76
4094 SEG14
Q65
BC337 150R
R77
SEG15
Q66
BC337 150R
SEG[0..15]
SEG[0..1 5] 11
U31A

MPX1_A _12V 1 2 1 3

U31B GND LC6

4069
2

GND 3 4 1 3

U31C GND LC7

4069
2

STR_A _12V 5 6 1 3 P11

1
U31D GND LC8 2
4069 3
2

CLK_12V 9 8 1 3 GND 4
5
U31E GND LC9 6 MULTIPLEX EXPANSION
4069 7
2

STR_12V 11 10 1 3
HDR 7W 0.1 KK
U31F GND LC10
4069
2

OE_12V 13 12 1 3 HEBER L TD.

LC11 Belvedere Mill

GND
4069 Chalfor d, Str oud, GL6 8NT
2

Tel: +44 (0) 1453 886000

Fax: +44 (0 ) 1 453 885 013

Title
+12V V DD
PLUTO 5 C - LED DRIVES

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 13 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 57
Figure 14 - Schematic Sheet 14 – Root Sheet 2

SHT 15 - DUA RTS SHT 1 6 - RS232 BUFFERS SHT 18 - PIC/RA M

D[0 ..15] TXDC D[0 ..15]

2,3,4,6,7,9 D[0..15] D[0..15] TXDC TXDD TXDC D[0..15]
A [0..2 3] TXDD TXDE TXDD
2 A[0..23] A [0..23] TXDE TXDF TXDE A [0..2 3]
CS_DUA RT- TXDF TXDG TXDF A [0..23]
3 CS_DUART- CS_DUART- TXDG TXDH TXDG
R/W- TXDH
2 R/W- R/W-
RESET- RXDC
10 RESET- RESET- RXDC RXDD RXDC R/W-
RXDD RXDE RXDD R/W-
PB5 RXDE RXDF RXDE
2,9 PB5 PB5 RXDF RXDG RXDF RA M_LITH
3.68MHZ RXDG RXDH RXDG 3 RA M_ LITH RA M_LITH
3 3.68MHZ 3.68MHZ RXDH
DSA CK0-
2,3,9 DSA CK0- DSA CK0- RTSC- RESET-
RTSC- RTSD- RTSC- RESET-
RTSD- RTSE- RTSD-
RTSE- RTSF- RTSE- PIC_IP0
RTSF- RTSG- RTSF- 9 PIC_IP0 PIC_IP1 PIC_IP0
RTSG- RTSH- RTSG- 9 PIC_IP1 PIC_IP1
RTSH- PIC_OP0
CTSC- 9 PIC_OP0 PIC_OP1 PIC_OP0
CTSC- CTSD- CTSC- 9 PIC_OP1 PIC_OP1
CTSD- CTSE- CTSD-
CTSE- CTSF- CTSE-
CTSF- CTSG- CTSF-
CTSG- CTSH- CTSG-
CTSH-
DSRC- 15741_18
DSRC- CDC- DSRC-
CDC- CDC-
EXP_OP2
EXP_OP2 EXP_OP3
EXP_OP3
EXP_IP2
EXP_IP2 EXP_IP3
EXP_IP3
15741_1 6

SHT 1 7 - RS485 EXPA NSION

TXDH
RXDH TXDH
RXDH
15741_15
RTSH-
CTSH- RTSH-
CTSH-
EXP_OP2
EXP_OP3 EXP_OP2
EXP_OP3
EXP_IP2
EXP_IP3 EXP_IP2
EXP_IP3

15741_1 7

HEBER L TD.

Belvedere Mill
Chalfor d, Str oud
Glo ucester shire GL6 8NT
Tel: 0453 886000 Fax: 0453 885013

Title
PLUTO 5C - ROOT 2

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 14 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 58
Figure 15 - Schematic Sheet 15 – DUARTS, Channels C-H

D[0..15]
2,3,4,6,7 ,9,18 D[0 ..15]

A [0..23]
2 A [0..2 3]

U54
3.68MHZ 36 33 TXDE
X1/CLK TXDA TXDE 16
35 RXDE
RXDA RXDE 16
37
GND X2 13 TXDF
TXDB TXDF 16
D8 28 11 RXDF
D0 RXDB RXDF 16
D9 18
D10 27 D1 32 RTSE-
D2 OP0 RTSE- 16
D11 19 14 RTSF-
D3 OP1 RTSF- 16
D12 26 31
D13 20 D4 OP2 15
D14 25 D5 OP3 30
D15 21 D6 OP4 16
U53
3.68MHZ 36 33 TXDC D7 OP5 29
3 3.68MHZ X1/CLK TXDA TXDC 16 OP6
35 RXDC A0 2 17
RXDA RXDC 16 A1 OP7
37 A1 4
GND X2 A2
13 TXDD A2 6 8 CTSE-
TXDB TXDD 16 A3 IP0 CTSE- 16
D8 28 11 RXDD A3 7 5 CTSF-
D0 RXDB RXDD 16 A4 IP1 CTSF- 16
D9 18 40 V CC
D10 27 D1 32 RTSC- CS_DUA RT1- 39 IP2 3
D2 OP0 RTSC- 16 CS IP3 V CC
D11 19 14 RTSD- R/W- 9 43 V CC
D3 OP1 RTSD- 16 R/W IP4
D12 26 31 V CC 41 42 V CC
D13 20 D4 OP2 15 RESET- 38 IACK IP5
D14 25 D5 OP3 30 RESET
D15 21 D6 OP4 16 DSA CK0- 10
D7 OP5 29 PB5 24 DTA CK
A0 2 OP6 17 IRQ
A1 4 A1 OP7
68692PLCC
A2 6 A2 8 CTSC-
A3 IP0 CTSC- 16
A3 7 5 CTSD-
A4 IP1 CTSD- 16
40 DSRC-
IP2 DSRC- 16
CS_DUA RT0- 39 3 CDC-
CS IP3 CDC- 16
R/W- 9 43 V CC
2 R/W- 41 R/W IP4 42
V CC IACK IP5 V CC
RESET- 38
10 RESET- RESET
DSA CK0- 10 U55
2,3,9 DSA CK0- PB5 24 DTA CK 3.68MHZ 36 33 TXDG
2,9 PB5 IRQ X1/CLK TXDA TXDG 16
35 RXDG
RXDA RXDG 16
68692PLCC 37
GND X2 13 TXDH
TXDB TXDH 17
D8 28 11 RXDH
D0 RXDB RXDH 17
D9 18
D10 27 D1 32 RTSG-
D2 OP0 RTSG- 16
D11 19 14 RTSH-
D3 OP1 RTSH- 17
D12 26 31 EXP_OP2
D4 OP2 EXP_OP2 17
D13 20 15 EXP_OP3
D5 OP3 EXP_OP3 17
D14 25 30
D15 21 D6 OP4 16
D7 OP5 29
A0 2 OP6 17
A1 4 A1 OP7
U52A
A4 2 4 CS_DUA RT0- A2 6 A2 8 CTSG-
A Y0 A3 IP0 CTSG- 16
A5 3 5 CS_DUA RT1- A3 7 5 CTSH-
B Y1 A4 IP1 CTSH- 17
6 CS_DUA RT2- 40 EXP_IP2
Y2 IP2 EXP_IP2 17
CS_DUART- 1 7 CS_DUA RT2- 39 3 EXP_IP3
3 CS_DUART- G Y3 CS IP3 EXP_IP3
R/W- 9 43 V CC
41 R/W IP4 42
74HCT139 V CC V CC
RESET- 38 IACK IP5
RESET
DSA CK0- 10
PB5 24 DTA CK
IRQ
68692PLCC

V CC V CC V CC V CC V CC

C67 C68 C69 C70 C71 HEBER L TD.

100n 100n 100n 100n 100n
Belvedere Mill
GND GND GND GND GND Chalfor d, Str oud
Glo ucester shire GL6 8NT
Tel: 01453 886000 Fax: 01453 885013

Title
PLUTO 5C - DUA RTS

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 15 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 59
Figure 16 - Schematic Sheet 16 – RS232 Buffers Channels C-H

+12V -12V

P17
U41 CDC 1

14

1
DSRC 6
RXC 2

V+

V-
RTSC 7
TXDC 2 3 TXC 3
15 TXDC A1 TXA CTSC 8
RTSC- 4 DTRC 4
15 RTSC- 5 B1 6 9
V CC B2 TXB
GND 5
TXDD 9
15 TXDD 10 C1 8
V CC 9W "D" PLUG
C2 TXC
RTSD- 12
15 RTSD- 13 D1 11
V CC D2 TXD

GND
V CC 1488 P18

7
+12V 1 2 +12V
+12V 3 4 +12V
U42 RXD RTSD

14
GND TXD 5 6 CTSD
7 8
GND GND

VCC
RXE 9 10 RTSE
TXE 11 12 CTSE
RXDC 3 1 13 14
15 RXDC A RXA GND 15 16 GND
RXF RTSF
CTSC- 6 4 TXF 17 18 CTSF
15 CTSC- B RXB 19 20
GND 21 22 GND
RXDD 8 10 RXD RXG RTSG
15 RXDD C RXC RTSD TXG 23 24 CTSG
CTSD- 11 13 TXD PORTD 25 26
15 CTSD- D RXD CTSD HDR 26W
GND

1489
7

GND

+12V -12V +12V -12V

U43 U46
14

14
1

1
RXE RXG
V+

V+
V-

V-
RTSE RTSG
TXDE 2 3 TXE PORTE TXDG 2 3 TXG PORTG
15 TXDE A1 TXA CTSE 15 TXDG A1 TXA CTSG
RTSE- 4 RTSG- 4
15 RTSE- 5 B1 6 15 RTSG- 5 B1 6
V CC B2 TXB V CC B2 TXB
TXDF 9 9
15 TXDF 10 C1 8 10 C1 8
V CC C2 TXC V CC C2 TXC
RTSF- 12 GND 12
15 RTSF- 13 D1 11 13 D1 11
V CC D2 TXD V CC D2 TXD
GND

GND
V CC 1488 V CC 1488
7

7
U44 RXF U47
14

14
GND RTSF GND
TXF PORTF
VCC

VCC
CTSF

RXDE 3 1 RXDG 3 1
15 RXDE A RXA 15 RXDG A RXA
CTSE- 6 4 CTSG- 6 4
15 CTSE- B RXB 15 CTSG- B RXB
RXDF 8 10 CDC- 8 10 CDC
15 RXDF C RXC 15 CDC- C RXC
CTSF- 11 13 DSRC- 11 13 DSRC
15 CTSF- D RXD 15 DSRC- D RXD
GND

GND
1489 1489
7

7
GND GND

HEBER L TD.

V CC V CC V CC +12V -12V Belvedere Mill

Chalfor d, Str oud
Glo ucester shire GL6 8NT
C54 C55 C56 C57 C58 Tel: 01453 886000 Fax: 01453 885013
100n 100n 100n 100n 100n
Title
GND GND GND GND GND PLUTO 5C - RS232 BUFFERS

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 16 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 60
Figure 17 - Schematic Sheet 17 – Port H, TTL Buffers

R153
V CC
3K3
R154

3K3
R155

3K3
R156

3K3

P19
+12V 1
U49 R139 2
TXDH 2 18 R140 TX0 3
15 TXDH RTSH- 4 1A 1 1Y 1 16 4
R141
15 RTSH- EXP_OP2 6 1A 2 1Y 2 14 RX0 5
47R R145
15 EXP_OP2 EXP_OP3 8 1A 3 1Y 3 12 6
R149 47R
15 EXP_OP3 RX0 11 1A 4 1Y 4 9 XRTS 7
R150 47R
XCTS 13 2A 1 2Y 1 7 8
R151 47R
XIP2 15 2A 2 2Y 2 5 XCTS 9
R152 47K 2%
XIP3 17 2A 3 2Y 3 3 10
47K 2%
2A 4 2Y 4 XOP2 11
47K 2%
47K 2% GND 1 12
19 1G XOP3 13
2G 14
74HCT244 XIP2 15
16
XIP3 17
EXP_IP3 18
EXP_IP3 EXP_IP2 19
15 EXP_IP2 CTSH- 20
15 CTSH- RXDH
15 RXDH
20W

GND
VCC

PORT H
TTL LEV EL
C73
100n

GND

HEBER L TD.

Belvedere Mill
Chalfor d, Str oud
Glo ucester shire GL6 8NT
Tel: 01453 886000 Fax: 01453 885013

Title
PLUTO 5C - PORT H, TTL LEV ELS

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 17 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 61
Figure 18 - Schematic Sheet 18 – Secondary NV RAM, Security PIC Microcontroller

GND GND

GND

C64 C65 D37 P20

1
15p 15p 1
V BAT2 N21 2
X3 10K *8 SIL 1N4148 3
D38 4
5

2
3
4
5
6
7
8
9
32.7KhZ U51 6

14
1N4148 7
16 D39 8

VCC
OSC1
15 6 HDR 8W A MP MTA 100
OSC2 RB0 7 1N4148
PIC_IP0 17 RB1 8 D40
9 PIC_IP0 PIC_IP1 18 RA 0 RB2 9
9 PIC_IP1 PIC_OP0 1 RA 1 RB3 10
9 PIC_OP0 PIC_OP1 2 RA 2 RB4 11 1N4148
9 PIC_OP1 RA 3 RB5 12 D41
3 RB6 13
RTCC RB7
V BAT2 4 1N4148

GND
MCLR
D42

PIC16LV 54P
1N4148

5
D43
V BAT2

GND 1N4148

C66 R148
100n

120R
GND

+12V

R142
D[0..15] 22K
2,3,4,6,7,9,15 D[0..15]
PP26
V CC
A [0..23]
2 A [0..23]
PP TP19
V BAT2 PP27
Q67
BC846 PA D
PP
U50

28
V BAT2
A0 10 11 D8

VCC
A1 9 A0 D0 12 D9
A2 8 A1 D1 13 D10
A3 7 A2 D2 15 D11 TP17
A4 6 A3 D3 16 D12
A5 5 A4 D4 17 D13
A6 4 A5 D5 18 D14 PA D
A7 3 A6 D6 19 D15 R144
V BAT2 A8 25 A7 D7 390R
A9 24 A8 C61 C62
A 10 21 A9 100n 47/16
TP18
A 11 23 A 10
R147 A 12 2 A 11
390R A 13 26 A 12
PA D
A 14 1 A 13
A 14
20 BT2
R/W- 27 CS 3.6V NiMH
GND

2 R/W- 22 WE
OE
GND
R146 Q69 62256
2N7002
14

RA M_ LITH GND
3 RA M_ LITH BATTERY BACK-UP
120R

Q70 GND
RESET- 2N7002 V BAT2
10 RESET-

GND C63
100n

HEBER L TD.
GND
Belvedere Mill
Chalfor d, Str oud
Glo ucester shire GL6 8NT
Tel: 01453 886000 Fax: 01453 885013

Title
PLUTO 5C - PIC/RAM

Size Document Number Rev

A3 56- 15741 7r2
© HEBER LTD, 1996-20 02
Date: Tuesday , Aug ust 12, 2003 Sheet 18 of 18

Document No. 80-15744 Issue 5 HEBER LTD

 Page 62
Figure 19 – Pluto 5 Casino with Ultrex connectors (Pluto 5CU) Photograph

Document No. 80-15744 Issue 5 HEBER LTD

 Page 63
Figure 20 - Pluto 5 Casino Component Ident

Document No. 80-15744 Issue 5 HEBER LTD