Task 5
NAME : AAKASH M
REGD No : 21BEC0798
1.Design and simulate 4 bit sequence detector using Mealy modeling. Consider the overlapping
sequence (1101)2
CODE :
module seqdet_mealy(x,clk,rst,z);
input x,clk,rst;
output reg z;
parameter S0 = 2'b00 , S1 = 2'b01 , S2 = 2'b10 , S3 = 2'b11 ;
reg [1:0] pst,nst;
always@(posedge clk)
begin
if(rst)
pst = S0;
else
pst = nst ;
case(pst)
S0 : begin if(x==0)
begin
z=0;
nst = S0;
end
else
begin
z = 0;
nst = S1;
end
end
S1 : begin if (x==0)
begin
z=0;
nst = S0;
end
else
begin
z=0;
nst = S2;
end
end
S2 : begin if (x==0)
begin
z=0;
nst = S3;
end
else
begin
z = 0;
nst = S2;
end
end
S3 : begin if (x==0)
begin
z = 0;
nst = S0;
end
else
begin
nst = S1;
z = 1;
end
end
endcase
end
endmodule
OUTPUT :
2. Design and simulate 4 bit sequence detector using Moore modeling. Consider the overlapping
sequence (1001)2
CODE :
module seq_detector(input x,clk,reset,output reg z);
parameter S0 = 0 , S1 = 1 , S2 = 2 , S3 = 3 ;
reg [1:0] PS,NS ;
always@(posedge clk or posedge reset)
begin
if(reset)
PS <= S0;
else
PS <= NS ;
end
always@(PS or x)
begin
case(PS)
S0 : begin
z=0;
NS = x ? S1 : S0 ;
$display(PS);
end
S1 : begin
z=0;
NS = x ? S1 : S2 ;
$display(PS);
end
S2 : begin
z=0;
NS = x ? S3 : S0 ;
$display(PS);
end
S3 : begin
z=x?1:0;
NS = x ? S1 : S2 ;
$display(PS);
end
endcase
end
endmodule
OUTPUT :
3.Write the Verilog HDL and simulate the problem number 1 & 2 using proper test bench.
PROBLEM CODE 1:
Problem Code 2 :
4.Write the Verilog HDL for the following Hardwired control unit using module instantiation.
REGISTER CODE :
module free_run_shift_reg
#(parameter N=8)
input wire clk,
reset, input wire
s_in, output wire
s_out
);
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
always @(posedge clk, negedge reset)
begin
if (~reset)
r_reg <= 0;
else
r_reg <= r_next;
end
assign r_next = {s_in, r_reg[N-1:1]};
assign s_out = r_reg[0];
endmodule
2 : 4 DECODER CODE :
module decoder24_behaviour(en,a,b,y);
input en,a,b; output reg [3:0]y;
always @(en,a,b)
begin
if(en==0) begin
if(a==1'b0 & b==1'b0) y=4'b1110;
else if(a==1'b0 & b==1'b1) y=4'b1101;
else if(a==1'b1 & b==1'b0) y=4'b1011;
else if(a==1 & b==1) y=4'b0111;
else y=4'bxxxx;
end
else
y=4'b1111;
end
endmodule
RING COUNTER CODE :
module ring_counter( Clock, Reset,Count_out );
input Clock;
input Reset;
output [3:0] Count_out;
reg [3:0] Count_temp;
always @(posedge(Clock),Reset)
begin if(Reset == 1'b1)
begin
Count_temp = 4'b0001;
end
else if(Clock == 1'b1) begin
Count_temp = {Count_temp[2:0],Count_temp[3]};
end
end
assign Count_out = Count_temp;
endmodule
module tb_ring;
reg Clock;
reg Reset;
wire [3:0] Count_out;
ring_counter uut (.Clock(Clock), .Reset(Reset), .Count_out(Count_out) );
initial Clock = 0;
always #10 Clock = ~Clock;
initial begin
Reset = 1;
#50;
Reset = 0;
EnD
endmodule
6 BIT _ ADDER CODE:
module fulladder(s,c,a,b,cin);
input a,b,cin; output s,c;
assign s = a^b^cin; assign c
=(a&b)|(a&cin)|(b&cin);
endmodule
module adder_6(s,c6,a,b,c0);
input[5:0] a,b;
input c0; output [5:0]s;
output c6; wire c1,c2,c3,c4,c5;
fulladder FA0(s[0],c1,a[0],b[0],c0);
fulladder FA1(s[1],c2,a[1],b[1],c1);
fulladder FA2(s[2],c3,a[2],b[2],c2);
fulladder FA3(s[3],c4,a[3],b[3],c3);
fulladder FA4(s[4],c5,a[4],b[4],c4);
fulladder FA5(s[5],c6,a[5],b[5],c5);
endmodule
6 BIT _ SUBTRACTOR CODE:
module fullsubtractor(s,B,a,b,bin);
input a,b,bin;
output s,B;
assign s = a^b^bin;
assign B =(~a&b)|(~a|b)&bin;
endmodule
module subtractor_6(s,c6,a,b,c0);
input[5:0] a,b;
input c0;
output [5:0]s;
output c6;
wire c1,c2,c3,c4,c5;
fullsubtractor FS0(s[0],c1,a[0],b[0],c0);
fullsubtractor FS1(s[1],c2,a[1],b[1],c1);
fullsubtractor FS2(s[2],c3,a[2],b[2],c2);
fullsubtractor FS3(s[3],c4,a[3],b[3],c3);
fullsubtractor FS4(s[4],c5,a[4],b[4],c4);
fullsubtractor FS5(s[5],c6,a[5],b[5],c5);
endmodule
MULTIPLIER 3X3 CODE:
module halfadder(sum,carry,a,b);
input a,b;
output sum,carry;
xor u0(sum,a,b);
and u1(carry,a,b);
endmodule
module fulladder(sum,carry,a,b,c);
input a,b,c;
output sum,carry;
xor u0(sum,a,b,c);
and u(carry,a,b,c);
endmodule
module mul_3bit(p,a,b);
input [2:0]a,b;
output [5:0]p;
wire [12:0]w;
and u0(p[0],a[0],b[0]);
and u1(w[0],a[1],b[0]);
and u2(w[1],a[0],b[1]);
and u3(w[3],a[2],b[0]);
and u4(w[4],a[1],b[1]);
and u5(w[7],a[0],b[1]);
and u6(w[9],a[2],b[1]);
and u7(w[10],a[1],b[2]);
and u8(w[12],a[2],b[2]);
halfadder u9(p[1],w[2],w[1],w[0]);
halfadder u10(p[4],p[5],w[11],w[12]);
fulladder u11(w[5],w[6],w[2],w[3],w[4]);
fulladder u12(p[2],w[8],w[5],w[6],w[7]);
fulladder u13(p[3],w[11],w[10],w[9],w[8]);
endmodule
module tb_mul_3bit;
reg [2:0]a,b; wire [5:0]p; mul_3bit u0(p,a,b);
initial
begin
#50 a=3'b111; b=3'b101;
#50 a=3'b000; b=3'b010; #50 a=3'b011; b=3'b001; end
endmodule
AAKASH M
21BEC0798
