SPC574Kx

32-bit Power Architecture® based MCU for automotive applications

Datasheet - production data

• Generic timer module (GTM122)

– Intelligent complex timer module
– 88 channels (24 input and 64 output)
– 3 programmable fine grain multi-threaded
eTQFP144 cores
(20 mm × 20 mm × 1.0 mm)
eTQFP176 (24 x 24 x 1.4 mm) – 26 KB of dedicated SRAM
– Hardware support for engine control, motor
control and safety related applications
Features
• Enhanced analog-to-digital converter system
• AEC-Q100 qualified with:
• Two main 32-bit Power Architecture® VLE – 1 supervisor 12-bit SAR analog converter
compliant CPU core (e200z4), dual issue, – 4 separate fast 12-bit SAR analog
running in lockstep converters
– Single-precision floating point operations – 2 separate 16-bit Sigma-Delta analog
– 16 KB local instruction SRAM and 64 KB converters
local data SRAM • 5 Deserial Serial Peripheral Interface (DSPI)
– 4 KB I-Cache and 2 KB D-Cache modules
• One 32-bit Power Architecture® VLE compliant • 5 LIN and UART communication interface
I/O processor core (e200z2) (LINFlexD) modules
– Single-precision floating point operations • 3 MCAN interfaces with advanced shared
– Lightweight Signal Processing Auxiliary memory scheme, two supporting ISO CAN-FD
Processing Unit (LSP APU) instruction and one supporting TTCAN
support for digital signal processing (DSP)
• One Ethernet controller 10/100 Mbps,
– 16 KB local instruction SRAM and 48 KB compliant IEEE 802.3-2008
local data SRAM
• Dual-channel FlexRay controller
• 2624 KB on-chip flash memory
• Nexus development interface (NDI) per IEEE-
– Supporting EEPROM emulation (64 KB)
ISTO 5001-2003 standard, with partial support
• 64 KB on-chip general-purpose SRAM for 2010 standard
(+112 KB data RAM included in the CPUs)
• Device and board test support per Joint Test
• Multi-channel direct memory access controller Action Group (JTAG) (IEEE 1149.1)
(eDMA) with 32 channels
• Single 5 V +/-10% Power supply supporting
• Dual interrupt controller (INTC) cold start conditions (down to 3.0 V)
• Dual phase-locked loops, including one • Designed for eTQFP144 and eLQFP176
Frequency-modulated
• System integration unit lite (SIUL)
• Boot Assist Flash (BAF) supports factory
programming using a serial bootload through
the asynchronous CAN or LIN/UART

July 2017 DocID023601 Rev 6 1/160

This is information on a product in full production. www.st.com
 SPC574Kx

Table 1. Device summary

Root Part Numbers
Memory Flash size
Package eTQFP144 Package eLQFP176
2624 KByte SPC574K72E5 SPC574K72E7
2112 KByte SPC574K70E5 SPC574K70E7

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SPC574Kx Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5 Feature overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 17

2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.1 Power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.3 LVDS pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.4 Generic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Electromagnetic compatibility (EMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.1 BISS port and power supply limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.6 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7 Temperature profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.8 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.9 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.9.1 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.9.2 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.10 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.11 Reset pad (PORST, ESR0) electrical characteristics . . . . . . . . . . . . . . . . 48
3.12 Oscillator and FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.12.1 FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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Contents SPC574Kx

3.12.2 External oscillator (XOSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.12.3 Internal oscillator (IRCOSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.13 ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.13.1 ADC input description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.13.2 SAR ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.13.3 S/D ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.14 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.15 LVDS Fast Asynchronous Serial Transmission (LFAST) pad electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.15.1 LFAST interface timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.15.2 LFAST and MSC/DSPI LVDS interface electrical characteristics . . . . . 74
3.15.3 LFAST PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.16 Aurora LVDS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.17 Power management: PMC, POR/LVD, sequencing . . . . . . . . . . . . . . . . . 79
3.17.1 Power management integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.17.2 Main voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . 80
3.17.3 Device voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.17.4 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.18 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.18.1 Flash read wait state and address pipeline control settings . . . . . . . . . 88
3.19 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.19.1 Debug and calibration interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.19.2 DSPI timing with CMOS and LVDS pads . . . . . . . . . . . . . . . . . . . . . . . . 96
3.19.3 FEC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
3.19.4 FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.19.5 PSI5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.19.6 UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
3.19.7 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
3.19.8 GPIO delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

4.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

4.2 eTQFP144 case drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.3 eLQFP176 case drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.4 FusionQuad® case drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

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4.5.1 General notes for specifications at maximum junction temperature . . 132

5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

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List of tables SPC574Kx

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. SPC574Kx device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. LVDSM pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. LVDSF pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Radiated emissions testing specification, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Conducted emissions testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. RF immunity—Direct Power Injection (DPI) test specifications . . . . . . . . . . . . . . . . . . . . . 27
Table 11. ESD ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Device operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. Emulation (buddy) device operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14. Temperature profile – Packaged parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 15. Unbiased temperature profile – Packaged parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. DC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 17. I/O pad specification descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 20. WEAK configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21. MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 42
Table 22. STRONG configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . 43
Table 23. VERY STRONG configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . 44
Table 24. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 26. PLL0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 27. PLL1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 28. External Oscillator electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 29. Selectable load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 30. Internal RC oscillator electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 31. ADC pin specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 32. ADC pin specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 33. SARn ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 34. SDn ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 35. Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 36. LVDS pad startup and receiver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 37. LFAST transmitter electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 38. MSC/DSPI LVDS transmitter electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 39. LFAST PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 40. Aurora LVDS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 41. Device Power Supply Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 42. Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 43. Device supply relation during power-up/power-down sequence. . . . . . . . . . . . . . . . . . . . . 84
Table 44. Functional terminals state during power-up and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 45. Flash memory program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 46. Flash memory Life Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 47. Flash memory RWSC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 48. JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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Table 49. Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 50. Aurora LVDS interface timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 51. Aurora debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 52. DSPI channel frequency support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 53. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 54. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 55. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0 or
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 56. DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,
CPOL = 0 or 1, continuous SCK clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 57. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,
CPOL = 0 or 1, continuous SCK clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 58. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1) . . . . . . . . . . . . . . . . 110
Table 59. RMII serial management channel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 60. RMII receive signal timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 61. RMII transmit signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 62. TxEN output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 63. TxD output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 64. RxD input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 65. PSI5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 66. UART frequency support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 67. I2C input timing specifications — SCL and SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 68. I2C output timing specifications — SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 69. GPIO delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 70. Package case numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 71. Thermal characteristics for eTQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 72. Thermal characteristics for eLQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 73. Conditional text tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 74. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

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List of figures SPC574Kx

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. Periphery allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. 144-pin QFP and 172-pin FQ configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. 176-pin QFP and 216-pin FQ configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. BISS port limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 6. BISS power supply limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 8. Weak pull-up electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 9. I/O output DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 10. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 11. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 12. PLL integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 13. Crystal/Resonator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 14. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 15. Input equivalent circuit (Fast SARn channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 16. Input equivalent circuit (SARB channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 17. S/D impedance generic model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 18. LFAST and MSC/DSPI LVDS timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 19. Power-down exit time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 20. Rise/fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 21. LVDS pad external load diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 22. Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 23. Voltage monitor threshold definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 24. JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 25. JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 26. JTAG JCOMP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 27. JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 28. Nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 29. Nexus TDI/TDIC, TMS/TMSC, TDO/TDOC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 30. Aurora timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 31. DSPI CMOS master mode – classic timing, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 32. DSPI CMOS master mode – classic timing, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 33. DSPI PCS strobe (PCSS) timing (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 34. DSPI CMOS master mode – modified timing, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 35. DSPI CMOS master mode – modified timing, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 36. DSPI PCS strobe (PCSS) timing (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 37. DSPI LVDS master mode – modified timing, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 38. DSPI LVDS master mode – modified timing, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 39. DSPI LVDS and CMOS master timing – output only – modified transfer format MTFE = 1,
CHPA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 40. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1)—CPHA = 0 . . . . . . . . 111
Figure 41. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1)—CPHA = 1 . . . . . . . . 112
Figure 42. RMII serial management channel timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 43. RMII receive signal timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 44. RMII transmit signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 45. TxEN signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 46. TxEN signal propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 47. TxD signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

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Figure 48. TxD Signal propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 49. I2C input/output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 50. eTQFP144 – STMicroelectronics package mechanical drawing (1 of 2) . . . . . . . . . . . . . 123
Figure 51. eTQFP144 – STMicroelectronics package mechanical drawing (2 of 2) . . . . . . . . . . . . . 124
Figure 52. eLQFP176 – STMicroelectronics package mechanical drawing (1 of 2) . . . . . . . . . . . . . 125
Figure 53. eLQFP176 – STMicroelectronics package mechanical drawing (2 of 2) . . . . . . . . . . . . . 126
Figure 54. FusionQuad® QFP172 package mechanical drawing (1 of 2) . . . . . . . . . . . . . . . . . . . . . 127
Figure 55. FusionQuad® QFP172 package mechanical drawing (2 of 2) . . . . . . . . . . . . . . . . . . . . . 128
Figure 56. FusionQuad® QFP216 package mechanical drawing (1 of 2) . . . . . . . . . . . . . . . . . . . . . 129
Figure 57. FusionQuad® QFP216 package mechanical drawing (2 of 2) . . . . . . . . . . . . . . . . . . . . . 130
Figure 58. Product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

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Introduction SPC574Kx

1 Introduction

1.1 Document overview

This document provides electrical specifications, pin assignments, and package diagrams
for the SPC574Kx series of microcontroller units (MCUs). For functional characteristics, see
the SPC574Kx microcontroller reference manual.

1.2 Description
This family of MCUs targets automotive powertrain controller applications for four-cylinder
gasoline and diesel engines, chassis control applications, transmission control applications,
steering and braking applications, as well as low-end hybrid applications.
Many of the applications are considered to be functionally safe and the family is designed to
achieve ISO26262 ASIL-D compliance.

1.3 Device feature summary

Table 2. SPC574Kx device feature summary
Feature Description

Process 55 nm
Main processor Core e200z4
Number of main cores 1
Number of checker cores 1
Local RAM (per main core) 16 KB Instruction
64 KB Data
Single precision floating point Yes
VLE Yes
Cache 4 KB Instruction
2 KB Data
I/O processor Core e200z2
Local RAM 16 KB Instruction
48 KB Data
Single precision floating point Yes
LSP Yes
VLE Yes
Cache No
Main processor frequency 160 MHz
I/O processor frequency 80 MHz
MPU Yes

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SPC574Kx Introduction

Table 2. SPC574Kx device feature summary(Continued)

Feature Description

Semaphores Yes
CRC channels 2
Software watchdog timer (task SWT/safety SWT) 3 (2/1)
Core Nexus class 3+
Sequence processing unit (SPU) Yes
Debug and calibration interface (DCI) / run control module Yes
System SRAM 64 KB
Flash memory 2560 KB
Flash memory fetch accelerator 2 × 2 × 256-bit
Data flash memory (EEPROM) 4 × 16 KB
Flash memory overlay RAM 16 KB
UTEST flash memory 16 KB
Boot assist flash (BAF) 16 KB
Calibration interface 64-bit IPS slave
DMA channels 32
DMA Nexus Class 3
LINFlexD (UART/MSC) 5 (3/2)
M_CAN (ISO CAN-FD/TTCAN) 3 (2/1)
DSPI (SPI/MSC/sync SCI) 5 (3/2/1)(1)
Microsecond bus downlink Yes
SENT bus 6
I2C 1
PSI5 bus 2
FlexRay 1 × dual channel
Ethernet (RMII) Yes
Zipwire (SIPI/LFAST) interprocessor bus High speed
System timers 6 PIT channels
2 AUTOSAR® (STM)
64-bit PIT
GTM timer 24 input channels,
64 output channels
GTM RAM 26 KB
Interrupt controller 360 sources
ADC (SAR) 5
ADC (SD) 2
Temperature sensor Yes

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Introduction SPC574Kx

Table 2. SPC574Kx device feature summary(Continued)

Feature Description

Self-test control unit (STCU2) Yes

PLL Dual PLL with FM
Internal linear voltage regulator 1.2 V
External power supplies 5 V(2)
3.3 V(3)
Low-power modes Stop mode
Slow mode
Packages eTQFP144
eLQFP176
172-pin FusionQuad®(4)
216-pin FusionQuad®(4)
1. One of the two MSC DSPIs is remapped to be used as sync SCI.
2. The device can be powered up at 5V only.
3. Optional: can be used for special I/O segments.
4. Also available in a 172-pin FusionQuad® package, which allows an eTQFP144 pin-compatible package for development,
and in a 216-pin FusionQuad® package, which allows an eLQFP176 pin-compatible package for development.

1.4 Block diagram

Figure 1 and Figure 2 show the top-level block diagrams.

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Introduction
Peripheral Domain – 40 MHz LFAST JTAGM JTAGC DCI SPU Nexus Aurora Router
SWT_3 Computational Shell– Fast Domain 160 MHz

SWT_2
Dual INTC SWT_0
DMAMUX
STM_2 STM_0
32ch. eDMA
with E2E ECC E200 z225 – 80 MHz E200 z420 – 160 MHz E200 z419 – 160 MHz
Peripheral Core_2 Nexus3p Nexus3p Delayed Lock-step
Main Core_0 Checker Core_0s
with Redundancy
Scaler Scaler Checkers ScalerSP-
VLE LSP VLE VLE
Concentrator SP-FPU SP-FPU FPU
With
E2E ECC I-Mem I-Mem I-Cache I-Mem I-Cache
Delay RCCU
80 MHz Control Control Control Control Control
Zipwire
(LFAST Nexus Data 16 KB Unified 16KB 4 KB Unified Unified
& SIPI) Trace I-MEM Backdoor I-MEM 2 way Backdoor Backdoor
Interface Interface Interface
D-MEM with D-MEM D-Cache with With D-MEM D-Cache
Control E2E ECC Control Control E2E ECC E2E ECC Control Control
DocID023601 Rev 6

Ethernet FlexRay
48 KB 64KB 2 KB
Delay RCCU
D-MEM D-MEM 2 way

Core Memory Protection Unit Core Memory Protection Unit Core Memory Protection Unit
Concentrator (CMPU) (CMPU) (CMPU)
With
E2E ECC
40 MHz BIU with E2E ECC BIU with E2E ECC BIU with E2E ECC

Nexus Data
Trace Instruction
32 ADD Load/ 32 ADD Instruction Safety Lake
Store 32DATA 32 ADD Load/ 32 ADD
32DATA 32 ADD
32 ADD 64 DATA Store 64 DATA
64 DATA
32 DATA

M2 M1 M0 M5 M0 M1
Slow Cross Bar Switch (XBAR_1, AMBA 2.0 v6 AHB) – 32 bit – 80 MHz M3 M4 Fast Cross Bar Switch (XBAR_0, AMBA 2.0 v6 AHB) – 64 bit– 160 MHz

System Memory Protection Unit(SMPU_1) S0 S7 System Memory Protection Unit(SMPU_0)

S3 S2 S1 S4 S0 S1 S2

32 ADD 32 ADD 32 ADD

64 DATA 64 DATA 64 DATA
Intelligent
Peripheral Bridge A Peripheral Bridge B Overlay 256 Page Line
Bridging FLASH Controller
E2E ECC E2E ECC Backdoor for
Bus Gasket SRAM Control
Decorate Storage Decorate Storage
SRAM with E2E ECC System RAM Dual Ported Incl. FLASH EEPROM
40 MHz 40 MHz Set-Associative 2.5 MB 4 x16KB
Peripherals 64 KB Decorated
Prefetch Buffers
32 ADD 32 ADD allocation to Access with E2E ECC Calibration
the bridges Interface NVM (Single Module)
32 DATA 32 DATA
is based on

SPC574Kx
Peripheral Cluster A Peripheral Cluster B safety and Overlay RAM
(See “Periphery (See“Periphery pinout 16 KB Buddy Device Interface
allocation” diagram ) allocation” diagram ) requirements
Introduction SPC574Kx

Figure 2. Periphery allocation

PBRIDGE_A BAR
XBAR_0 SSCM
XBAR_1 PASS
SMPU_0 PBRIDGE_B Flash control
SMPU_1 SARADC_2 LFAST_1
XBIC_0 SARADC_6 LFAST_0
XBIC_1 PSI5_1 SIPI_0
PRAM_0 SENT SRX_1 SIUL2

Peripheral Bus B
PCM DSPI_2 MC_ME
PFLASH_0 DSPI_5 MC_CGM
SEMA4 LINFlexD_2 CMU_PLL
INTC_0 LINFlexD_15 PLLDIG
SWT_0 SDADC_3 XOSC
SWT_2 FCCU IRCOSC
SWT_3 CRC_1 MC_RGM
STM_0 10 x CMU PMCDIG
STM_2 MC_PCU
DMA_0 WKPU
FEC_0
Peripheral Cluster B PIT_0
GTM PIT_1
SARADC_0
SARADC_4
SARADC_B
PSI5_0
FLEXRAY_0 Peripheral Bus A
SENT SRX_0

LINFlexD_14

M_TTCAN_0

DMAMUX_0
DMAMUX_1
DMAMUX_2
DMAMUX_3
CAN SRAM
LINFlexD_0
LINFlexD_1

M_CAN_1

SDADC_0
M_CAN_2
DSPI_0
DSPI_1
DSPI_4

JTAGM

CRC_0
MEMU
CCCU

STCU
IIC_0

TDM
DTS
JDC

IMA

Peripheral Cluster A

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1.5 Feature overview

On-chip modules within SPC574Kx include the following features:
• One main processor core and one checker core, single-issue, 32-bit CPU core
complexes (e200z4), running in lockstep
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length encoding (VLE), encoding a
mix of 16-bit and 32-bit instructions, for code size footprint reduction
– Single-precision floating point operations
– 16 KB local instruction SRAM and 64 KB local data SRAM
– 4 KB I-Cache and 2 KB D-Cache
• I/O processor, single issue, 32-bit CPU core complexes (e200z2), with
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length encoding (VLE), encoding a
mix of 16-bit and 32-bit instructions, for code size footprint reduction
– Single-precision floating point operations
– Lightweight Signal Processing Auxiliary Processing Unit (LSP APU) instruction
support for digital signal processing (DSP)
– 16 KB local instruction SRAM and 48 KB local data SRAM
• 2624 KB (2560 KB code + 64 KB EEPROM) on-chip flash memory: supports read
during program and erase operations, and multiple blocks allowing EEPROM
emulation
• 64 KB on-chip general-purpose SRAM (+ 112 KB data RAM included in the CPUs)
• Multi-channel direct memory access controller (eDMA) with 32 channels
• Dual interrupt controller (INTC)
• Dual phase-locked loops with stable clock domain for peripherals and FM modulation
domain for computational shell
• Dual crossbar switch architecture for concurrent access to peripherals, flash memory,
or SRAM from multiple bus masters with end-to-end ECC
• System integration unit lite (SIUL2)
• Boot assist Flash (BAF) supports factory programming using a serial bootload through
the asynchronous CAN or LIN/UART
• Generic timer module (GTM122)
– Intelligent complex timer module
– 88 channels (24 input and 64 output)
– 3 programmable fine grain multi-threaded cores
– 26 KB of dedicated SRAM
– 24-bit wide channels
– Hardware support for engine control, motor control and safety related applications
• Enhanced analog-to-digital converter system with:
– 1 supervisor 12-bit SAR analog converter
– 4 separate fast 12-bit SAR analog converters
– 2 separate 16-bit Sigma-Delta analog converters
• 5 Deserial Serial Peripheral Interface (DSPI) modules

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Introduction SPC574Kx

• 5 LIN and UART communication interface (LINFlexD) modules

– LINFlexD_0 is a Master/Slave
– LINFlexD_1, LINFlexD_2, LINFlexD_14, and LINFlexD_15 are Masters
• 3 MCAN interfaces with advanced shared memory scheme, two supporting ISO CAN-
FD and one supporting TTCAN
• One Ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008
• Dual-channel FlexRay controller
• Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with partial
support for 2010 standard
• Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1)
• Single 5 V +/-10% Power supply supporting cold start conditions (down to 3.0 V) and
the supply voltage down to 1.2 V for core logic

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SPC574Kx Package pinouts and signal descriptions

2 Package pinouts and signal descriptions

2.1 Package pinouts

The QFP and FusionQuad® package pinouts are shown in Figure 3 and Figure 4.

Figure 3. 144-pin QFP and 172-pin FQ configuration (top view)

VDD_HV_PMC/VDD_HV_IO_MAIN
VDD_HV_IO_MAIN

VDD_HV_IO_FLEX

VDD_HV_IO_MAIN
VDD_HV_FLA

PG[15]
PC[10]

PC[12]

PC[13]
PC[14]
PC[15]
PE[12]

PE[10]
PC[11]

PE[11]

PA[10]

PA[13]
PA[12]
PA[11]

PH[0]
PD[0]
PD[1]
PD[2]
PD[3]

PH[4]
PH[3]

PH[2]

PH[1]
PF[2]
PF[3]

PF[5]
PF[4]

PA[0]

PA[1]
PA[2]
NC
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PD[14] 1 108 PE[9]
PD[15] 2 107 PE[8]
PC[9]
PC[8]
3
4 eTQFP144 / FQ1723 106
105
PD[5]
PD[4]
PC[7] 5 104 PE[7]
VDD_HV_IO_MAIN

VDD_HV_IO_MAIN
PC[6] 6 103 PE[6]
PC[5] 7 102 PE[5]
LVDS Test In−*
LVDS Test In+*

PC[4] 8 101 PG[14]

VDD_LV_BD

PC[3] 9 100 PG[13]

VSS_HV

VSS_HV

NC/VDD_LV_BD5 10 99 VDD_LV
PK[14]

11
PM[5]
PM[6]

PC[2] 98 ESR0
12 97 PORST
NC
NC
NC

NC

PC[1]
PC[0] 13 96 PA[4]
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15

PE[0] 14 95 PF[15]
PE[1] 15 94 TESTMODE
PE[2] 16 93 PF[14]
PD[12] 17 92 PA[6]
PD[13] 18 91 PA[5]
PE[3] 19 90 PA[9]
PE[4]
PI[9]
20
21
VSS4 89
88
PA[7]
PA[8]
VDD_LV 22 87 PA[14]
VDD_HV_IO_MAIN 23 86 PD[6]
VDD_HV_ADR_D 24 85 PD[7]
VSS_HV_ADR_D 25 84 PF[13]
PG[1] 26 83 VDD_HV_IO_JTAG
A10

A12
A13
A14

27 82
A11

PG[2] XTAL
A1
A2
A3
A4
A5
A6
A7
A8
A9

PG[3] 28 81 EXTAL
29
VDD_HV_IO_BD
TX1N
TX1P

TX0N
TX0P

VDD_LV_BD
NC

CLKN

80
VSS_HV

VSS_HV

VSS_HV

VSS_HV

CLKP
VSS_HV

PG[4] VSSOSC
PB[15] 30 79 VDD_LV
PB[14] 31 78 VDD_HV_IO_MAIN
PB[13] 32 77 PF[12]
PB[12] 33 76 PF[11]
PB[5] 34 75 PF[10]
PG[5] 35 74 PF[9]
PG[6] 36 73 PF[8]
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PG[11]
PB[7]
PB[6]
PG[7]
PG[8]

PG[9]
PG[10]

PG[12]
PE[15]
PE[14]

PD[11]
PB[4]
PE[13]

PB[3]
PB[2]
PB[1]
PB[0]

PF[1]
PF[0]
PD[9]
PD[10]
PB[11]
PB[10]
PB[9]
PB[8]
PA[3]
PD[8]
PF[6]
PF[7]
PA[15]
VSS_HV_ADR_S
VDD_HV_ADR_S
VSS_HV_ADV
VDD_HV_ADV

VDD_LV
VDD_HV_IO_MAIN

Note:
1
Pins marked “NC” have no connection.
2
LVDS Test pins marked with an asterix (*) can be soldered to GND or left unconnected.
3
The eLQFP144 and FQ172 package pinouts are nearly identical, with the following exception:
A1–A28 are additional pins that appear only on the FQ172 package.
4 The shaded area in the middle of the pinout is an exposed pad that on both the eLQFP144 and FQ172 packages is the primary V
SS
connection.
5
Pin 10 is NC in the 144-pin package and VDD_LV_BD in the 172-pin package.

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Figure 4. 176-pin QFP and 216-pin FQ configuration (top view)

VDD_HV_PMC/VDD_HV_IO_MAIN
VDD_HV_IO_MAIN

VDD_HV_IO_MAIN
VDD_HV_IO_FLEX

NC/VDD_LV_BD5
VDD_HV_FLA

PG[15]
PH[12]
PH[13]

PH[14]

PH[15]
PC[10]

PC[12]

PC[13]
PC[14]
PC[15]

PH[10]
PE[12]

PE[10]
PC[11]

PE[11]

PA[10]

PA[13]
PA[12]
PA[11]
PD[0]
PD[1]
PD[2]
PD[3]

PH[7]
PH[8]
PH[9]

PH[4]
PH[3]

PH[2]

PH[1]
PH[0]
PF[2]
PF[3]

PF[5]
PF[4]

PA[0]

PA[1]
PA[2]
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PD[14] 1 132 PE[9]
PD[15] 2 131 PE[8]
PC[9] 3 130 PD[5]
eLQFP176 / FQ2163
PC[8] 4 129 PD[4]
PC[7] 5 128 PE[7]
PC[6] 6 127 PE[6]
PC[5] 7 126 PE[5]
PC[4] 8 125 PG[14]
PC[3] 9 124 PG[13]
NC/VDD_LV_BD5 10 123 VDD_LV
VDD_HV_IO_MAIN

VDD_HV_IO_MAIN
PC[2] 11 122 ESR0
PC[1] 12 LVDS Test In+* 121 PORST
LVDS Test In–*

PC[0] 13 120 PA[4]_ESR1

PE[0] 14 119 PF[15]
PE[1] 15 118 TESTMODE
VSS_HV

VSS_HV

PE[2] 16 117 PH[11]

PK[14]
PM[5]
PM[6]
PM[4]

PD[12] 17 116 PF[14]

PD[13] 18 115 PA[6]
NC
NC
NC
NC
NC
NC

NC
NC

NC
NC
PE[3] 19 114 PA[5]
PE[4] 20 113 PA[9]
21 112 PA[7]
A40
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21

PG[0]
PI[8] 22 111 PA[8]
PI[9] 23 110 PA[14]
VDD_LV 24 109 PD[6]
VDD_HV_IO_MAIN 25 108 PD[7]
VSS4
VDD_HV_ADR_D 26 107 PF[13]
VSS_HV_ADR_D 27 106 PI[15]
PG[1] 28 105 PI[14]
PG[2] 29 104 VDD_HV_IO_JTAG
PG[3] 30 103 XTAL
PG[4] 31 102 EXTAL
PB[15] 32 101 VSSOSC
A10

A12
A13
A14
A15
A16
A17
A18
A19
A20
A11

PB[14] 33 100 VDD_LV

A1
A2
A3
A4
A5
A6
A7
A8
A9

PB[13] 34 99 VDD_HV_IO_MAIN
PB[12] 35 98 PF[12]
TX1N

TX0N
NC
NC
NC

VDD_HV_IO_BD

NC

CLKN
VSS_HV

VDD_LV_BD
NC
NC
NC
TX1P

VSS_HV

TX0P
VSS_HV

VSS_HV

CLKP
VSS_HV

PB[5] 36 97 PF[11]
PI[0] 37 96 PF[10]
PI[1] 38 95 PF[9]
PI[2] 39 94 PH[6]
PI[3] 40 93 PH[5]
PI[4] 41 92 PJ[4]
PI[5] 42 91 PJ[3]
PG[5] 43 90 PF[8]
PG[6] 44 89 PJ[2]
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PB[7]
PB[6]
PI[6]
PI[7]
PG[7]
PG[8]

PG[9]
PG[10]
PG[11]
PG[12]
PE[15]
PE[14]
PB[4]
PE[13]
PD[11]
PB[3]
PB[2]
PB[1]
PB[0]

PI[13]
PI[12]
PI[11]
PI[10]
PF[1]
PF[0]
PD[9]

PF[6]
PF[7]
PJ[0]
PJ[1]
PD[10]
PB[11]
PB[10]
PB[9]
PB[8]
PA[3]
PD[8]

PA[15]
VDD_LV
VDD_HV_IO_MAIN
VSS_HV_ADR_S
VDD_HV_ADR_S
VSS_HV_ADV
VDD_HV_ADV

Note:
1
Pins marked “NC” have no connection.
2
FQ LVDS Test pins marked with an asterix (*) can be soldered to GND or left unconnected.
3
The eLQFP176 and FQ216 package pinouts are nearly identical, with the following exception:
A1–A40 are additional pins that appear only on the FQ216 package.
4 The shaded area in the middle of the pinout is an exposed pad that on both the eLQFP176 and FQ216 packages is the primary V
SS connection.
5 Pins 10 and 154 are NC in the 176-pin package and VDD_LV_BD in the 216-pin package.

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Note: The FusionQuad® package is for development purposes only and is not available as a
production device. The FusionQuad package is not intended to be qualified and is available
only in small quantities.

2.2 Pin descriptions

The following sections provide signal descriptions and related information about device
functionality and configuration.

2.2.1 Power supply and reference voltage pins

The Supply Pins Table contains information on power supply and reference pins. See the
Signal Table (Excel file) attached to this document. Locate the paperclip symbol on the left
side of the PDF window, and click it. Double-click on the excel file to open it and select the
Supply Pins Table tab.
Note: All ground supplies must be toed to ground. They must not float.

2.2.2 System pins

Table 3 contains information on system pin functions for the devices.

Table 3. System pins

QFP pin
Symbol Description Direction
144 FQ172 176 FQ216

PORST Power on reset with Schmitt trigger characteristics and Bidirectional 97 121
noise filter. PORST is active low
ESR0 External functional reset with Schmitt trigger Bidirectional 98 122
characteristics and noise filter. ESR0 is active low
TESTMODE Pin for testing purpose only. Input only 94 118
An internal pull-down is implemented on the
TESTMODE pin to prevent the device from entering
TESTMODE. It is recommended to connect the
TESTMODE pin to VSS_HV_IO on the board. The value
of the TESTMODE pin is latched at the negation of
reset and has no affect afterward. The device will not
exit reset with the TESTMODE pin asserted during
power-up.
XTAL Analog output of the oscillator amplifier circuit Output 82 103
needs to be grounded if oscillator is used in bypass
mode.
EXTAL Analog input of the oscillator amplifier circuit when Input 81 102
oscillator is not in bypass mode
Analog input for the clock generator when oscillator is
in bypass mode

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2.2.3 LVDS pins

Table 4 contains information on LVDS pin functions for the devices.

Table 4. LVDSM pin descriptions

Package pin number
Port
Functional block Signal Signal description Direction
pin eTQFP144, eLQFP176,
FQ172 FQ216

SIPI LFAST(1) PF[13] SIPI_RXN Interprocessor Bus LFAST, I 84 107

LVDS Receive Negative
Terminal
PD[7] SIPI_RXP Interprocessor Bus LFAST, I 85 108
LVDS Receive Positive Terminal
PD[6] SIPI_TXN Interprocessor Bus LFAST, O 86 109
LVDS Transmit Negative
Terminal
PA[14] SIPI_TXP Interprocessor Bus LFAST, O 87 110
LVDS Transmit Positive Terminal
Debug LFAST(1)(2) PA[8] DEBUG_TXN Debug LFAST, LVDS Transmit O 88 111
Positive Terminal
PA[7] DEBUG_TXP Debug LFAST, LVDS Transmit O 89 112
Negative Terminal
PA[9] DEBUG_RXP Debug LFAST, LVDS Receive I 90 113
Negative Terminal
PA[5] DEBUG_RXN Debug LFAST, LVDS Receive I 91 114
Positive Terminal
DSPI 4 PD[3] SCK_N DSPI 4 Microsecond Bus Serial O 128 156
Microsecond Bus Clock, LVDS Negative Terminal
PD[2] SCK_P DSPI 4 Microsecond Bus Serial O 129 157
Clock, LVDS Positive Terminal
PD[1] SOUT_N DSPI 4 Microsecond Bus Serial O 130 158
Data, LVDS Negative Terminal
PD[0] SOUT_P DSPI 4 Microsecond Bus Serial O 131 159
Data, LVDS Positive Terminal
DSPI 5 PF[9] SCK_N DSPI 5 Microsecond Bus Serial O 74 95
Microsecond Bus Clock, LVDS Negative Terminal
PF[10] SCK_P DSPI 5 Microsecond Bus Serial O 75 96
Clock, LVDS Positive Terminal
PF[11] SOUT_N DSPI 5 Microsecond Bus Serial O 76 97
Data, LVDS Negative Terminal
PF[12] SOUT_P DSPI 5 Microsecond Bus Serial O 77 98
Data, LVDS Positive Terminal

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Table 4. LVDSM pin descriptions(Continued)

Package pin number
Port
Functional block Signal Signal description Direction
pin eTQFP144, eLQFP176,
FQ172 FQ216

Differential DSPI 2 PD[3] SCK_N Differential DSPI 2 Clock, LVDS O 128 156
Negative Terminal
PD[2] SCK_P Differential DSPI 2 Clock, LVDS O 129 157
Positive Terminal
PD[1] SOUT_N Differential DSPI 2 Serial Output, O 130 158
LVDS Negative Terminal
PD[0] SOUT_P Differential DSPI 2 Serial Output, O 131 159
LVDS Positive Terminal
PF[13] SIN_N Differential DSPI 2 Serial Input, I 84 107
LVDS Negative Terminal
PD[7] SIN_P Differential DSPI 2 Serial Input, I 85 108
LVDS Positive Terminal
Differential DSPI 5 PF[9] SCK_N Differential DSPI 5 Clock, LVDS O 74 95
Negative Terminal
PF[10] SCK_P Differential DSPI 5 Clock, LVDS O 75 96
Positive Terminal
PF[11] SOUT_N Differential DSPI 5 Serial Output, O 76 97
LVDS Negative Terminal
PF[12] SOUT_P Differential DSPI 5 Serial Output, O 77 98
LVDS Positive Terminal
PF[13] SIN_N Differential DSPI 5 Serial Input, I 84 107
LVDS Negative Terminal
PD[7] SIN_P Differential DSPI 5 Serial Input, I 85 108
LVDS Positive Terminal
1. DRCLK and TCK/DRCLK usage for SIPI LFAST and Debug LFAST are described in the SPC574Kxx reference manual,
refer to SIPI LFAST and Debug LFAST chapters.
2. Pads use special enable signal from DCI block: DCI driven enable for Debug LFAST pads is transparent to user.

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Table 5. LVDSF pin descriptions

Package pin number
Functional
Pad Signal Signal description Direction
block
eTQFP144 FQ172 eLQFP176 FQ216

Nexus — TXAP Not available O — — — —

Aurora High
— TXAN Not available O — — — —
Speed
Trace — TXBP Nexus Aurora High O — A7 — A10
(TX0P) Speed Trace Lane 0,
LVDS Positive
Terminal
— TXBN Nexus Aurora High O — A6 — A9
(TX0N) Speed Trace Lane 0,
LVDS Negative
Terminal
— TXCP Nexus Aurora High O — A3 — A6
(TX1P) Speed Trace Lane 1,
LVDS Positive
Terminal
— TXCN Nexus Aurora High O — A2 — A5
(TX1N) Speed Trace Lane 1,
LVDS Negative
Terminal
— TXDP Not available O — — — —
— TXDN Not available O — — — —
— CLKP (BD- Nexus Aurora High O — A13 — A19
AGBTCLKP) Speed Trace Clock,
LVDS Positive
Terminal
— CLKN (BD- Nexus Aurora High O — A12 — A18
AGBTCLKN) Speed Trace Clock,
LVDS Negative
Terminal
— LPBK_P Aurora High Speed I — A18 — A27
Trace Loopback, LVDS
Positive Terminal
(LVDS Test In +)
— LPBK_N Aurora High Speed I — A19 — A28
Trace Loopback, LVDS
Negative Terminal
(LVDS Test In −)

2.2.4 Generic pins

The I/O Signal Description Table contains information on generic pins. See the I/O Signal
Description and Input Multiplexing Tables (Excel file) attached to this document. Locate the
paperclip symbol on the left side of the PDF window, and click it. Double-click on the excel
file to open it and select the I/O Signal Description Table tab.

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3 Electrical characteristics

3.1 Introduction
This section contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” (Controller Characteristics) is included in the “Symbol”
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” (System Requirement) is included in the
“Symbol” column.
Note: Parameters given to junction temperature TJ = 150 °C are for packaged parts .
Note: Within this document, VDD_HV_IO refers to supply pins VDD_HV_IO_MAIN, VDD_HV_IO_JTAG,
VDD_HV_IO_FLEX, VDD_HV_OSC and VDD_HV_FLA.

3.2 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 6 are used and
the parameters are tagged accordingly in the tables where appropriate.

Table 6. Parameter classifications

Classification tag Tag description

P Parameters are guaranteed by production testing on each individual device.

C Parameters are guaranteed by the design characterization by measuring a statistically relevant
sample size across process variations.
T Parameters are guaranteed by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D Parameters are derived mainly from simulations.

3.3 Absolute maximum ratings

Table 7 describes the maximum ratings of the device.

Table 7. Absolute maximum ratings(1)

Value
Symbol Parameter Conditions Unit
Min Max

Cycle T Lifetime power cycles — — 1000 k —

VSS_HV D Ground voltage — — — —
VDD_LV D 1.2 V core supply voltage(2),(3),(4) — –0.3 1.5 V

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Table 7. Absolute maximum ratings(1)(Continued)

Value
Symbol Parameter Conditions Unit
Min Max

VDD_LV_BD D 1.2 V Emulation module supply — –0.3 1.5 V

(3),(3),(4)

VDD_HV_IO(5) D I/O supply voltage(6) — –0.3 6.0 V

VDD_HV_IO_BD D I/O Emulation module supply — –0.3 6.0 V
VDD_HV_PMC D Power Management Controller — –0.3 6.0 V
supply voltage(6)
VSS_HV_ADV D SAR and S/D ADC ground voltage Reference to VSS_HV –0.3 0.3 V
VDD_HV_ADV (7) D SAR and S/D ADC supply voltage Reference to VSS_HV_ADV –0.3 6.0 V
VSS_HV_ADR_D D S/D ADC ground reference — –0.3 0.3 V
VDD_HV_ADR_D D S/D ADC voltage reference Reference to –0.3 6.0 V
VSS_HV_ADR_D
VSS_HV_ADR_S D SAR ADC ground reference — –0.3 0.3 V
VDD_HV_ADR_S D SAR ADC voltage reference Reference to –0.3 6.0 V
VSS_HV_ADR_S
VDD_LV_BD – VDD_LV — Emulation module supply — –0.3 1.5 V
differential to 1.2 V core supply
VSS – VSS_HV_ADR_D D VSS_HV_ADR_D differential voltage — –0.3 0.3 V
VSS – VSS_HV_ADR_S D VSS_HV_ADR_S differential voltage — –0.3 0.3 V
VSS_HV – D VSS_HV_ADV differential voltage — –0.3 0.3 V
VSS_HV_ADV
VIN D I/O input voltage range(8) — –0.3 6.0 V
Relative to –0.3 —
VSS_HV_IO(9),(10)
Relative to — 0.3
VDD_HV_IO(9),(10)
Relative to VDD_HV_ADV — 0.3
IINJD T Maximum DC injection current for Per pin, applies to all digital –5 5 mA
digital pad pins
IINJA T Maximum DC injection current for Per pin, applies to all –5 5 mA
analog pad analog pins
IMAXD SR Maximum output DC current when Medium −7 8 mA
driven
Strong –10 10
Very strong –11 11
IMAXSEG SR Maximum current per power — –90 90 mA
segment(11)
TSTG T Storage temperature range and — –55 175 °C
non-operating times

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Table 7. Absolute maximum ratings(1)(Continued)

Value
Symbol Parameter Conditions Unit
Min Max

STORAGE — Maximum storage time, assembled No supply; storage — 20 years

part programmed in ECU temperature in range –40
°C to 85 °C
TSDR T Maximum solder temperature(12) — — 260 °C
Pb-free package
MSL T Moisture sensitivity level(13) — — 3 —
tXRAY T X-ray screen time At 80÷130 KV; 20÷50 µA; — 200 ms
max 1 Gy dose
1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
2. Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum TJ = 125 °C, remaining time as defined in note 3 and
note 4
3. Allowed 1.375 – 1.45 V for 10 hours cumulative time at maximum TJ = 125 °C, remaining time as defined in note 4
4. 1.32 – 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.288 V at
maximum TJ = 125 °C
5. VDD_HV_IO refers to supply pins VDD_HV_IO_MAIN, VDD_HV_IO_JTAG, VDD_HV_IO_FLEX, VDD_HV_OSC, VDD_HV_FLA.
6. Allowed 5.5–6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ
= 125 °C, remaining time at or below 5.5 V.
7. Includes ADC supplies VDD_HV_ADV_S and VDD_HV_ADV_D. VDD_HV_ADV is also the supply for the device temperature
sensor and bandgap reference.
8. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current
condition on a pin, the voltage equals the supply plus the voltage drop across the internal ESD diode from I/O pin to supply.
The diode voltage varies significantly across process and temperature, but a value of 0.3V can be used for nominal
calculations.
9. VDD_HV_IO/VSS_HV_IO refers to supply pins and corresponding grounds: VDD_HV_IO_MAIN, VDD_HV_IO_FLEX, VDD_HV_IO_JTAG,
VDD_HV_OSC, VDD_HV_FLA.
10. Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameters IINJD and
IINJA).
11. Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDD_HV_IO power segment is
defined as one or more GPIO pins located between two VDD_HV_IO supply pins.
12. Solder profile per IPC/JEDEC J-STD-020D.
13. Moisture sensitivity per JEDEC test method A112.

3.4 Electromagnetic compatibility (EMC)

Table 8 and Table 9 describe the EMC characteristics of the device.

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Table 8. Radiated emissions testing specification(1), (2)

Functional BISS radiated
Coupling structure Test setup Function
configuration emissions limit

Entire IC (G) TEM Reference test C1-S3 36 dBµV

Reference test with SSCG C1-S3 36 dBµV
Memory copy C4-S2 36 dBµV
Memory copy with SSCG C4-S2 36 dBµV
1. Reference “BISS Generic IC EMC Test Specification”, version 1.2, section 9.3, “Emission test configuration for ICs with
CPU”.
2. The EMC parameters are classified as "T", validated on testbench.

Table 9 contains the conducted emissions testing specifications. The BISS port limits are
described in Section 3.4.1, BISS port and power supply limits.

Table 9. Conducted emissions testing specifications(1)

Emission test
Single/ Functional method BISS
Module Signal
Differential configuration limits(2)(3)
150 Ω

CAN TXCAN Single C1-S3, C5-S3 Yes As per Figure 5

RXCAN Yes As per Figure 5
DSPI SCLK - Diff Differential C1-S3, C5-S3 Yes As per Figure 5
MRST - Diff Yes As per Figure 5
MTSR - Diff Yes As per Figure 5
SCK Single C1-S3, C5-S3 Yes As per Figure 5
(4)
MRST Yes As per Figure 5
(4)
MTSR Yes As per Figure 5
Ethernet TXD(5) Single C1-S3 Yes As per Figure 5
RXD(5) Yes As per Figure 5
REF_CLK Yes As per Figure 5
TXCLK Yes As per Figure 5
RXCLK Yes As per Figure 5
FlexRay TXD Single C1-S3, C5-S3 Yes As per Figure 5
RXD Yes As per Figure 5
2C
I SCL Single C1-S3 Yes As per Figure 5
SDA Yes As per Figure 5
PSI5 PSI-TX Single C1-S3 Yes As per Figure 5
PSI-RX Yes As per Figure 5
SENT SENT Single C1-S3 Yes As per Figure 5

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Table 9. Conducted emissions testing specifications(1)(Continued)

Emission test
Single/ Functional method BISS
Module Signal
Differential configuration limits(2)(3)
150 Ω

SIPI RF_TX Differential C1-S3 Yes As per Figure 5

RF_RX Yes As per Figure 5
SysClk Tx Single Yes As per Figure 5
(10/20 MHz)
SysClk Rx Yes As per Figure 5
SCI TXD Single C1-S3 Yes As per Figure 5
RXD Yes As per Figure 5
LINFlex LINTX Single C1-S3, C5-S3 Yes As per Figure 5
LINRX Yes As per Figure 5
Oscillator XTAL Single C1-S3 Yes As per Figure 5
EXTAL Yes As per Figure 5
(6)
External clock SYSCLK Single C1-S3 Yes As per Figure 5
GPIO GPIO(7) Single C1-S3, C5-S3 Yes As per Figure 5
1.2 V core supply voltage VDD_LV N/A C1-S3 Yes As per Figure 6
I/O supply voltage VDD_HV_IO N/A C1-S3 Yes As per Figure 6
Power management controller VDD_HV_PMC N/A C1-S3 Yes As per Figure 6
(PMC) supply voltage
1. Reference “BISS Generic IC EMC Test Specification”, section 9.3, “Emission test configuration for ICs with CPU”.
2. All pins of the microcontroller are defined as ‘Local’ (according to BISS specification). Therefore, the supply pin on the
microcontroller are tested to ‘Local’ requirements.
3. Limits apply to signal under test in static mode only
4. BISS port limits measured with SCK frequency below 10 MHz
5. BISS port limits: The 25/50 MHz clocks for an Ethernet RMII interface could cause the limits specified in Figure 5 (BISS
port limits) to be exceeded unless care is taken in the application to ensure high EMC.
6. BISS port limits measured with clock less than 10 MHz and only one clock enabled at a time
7. BISS port limits: GPIO toggling less than 50 kHz and not more than 40 GPIO pins toggling simultaneously

Table 10. RF immunity—Direct Power Injection (DPI) test specifications(1)

BISS signal/power
Module Signal Monitor pin Function
supply limit class

Oscillator XTAL EXTCLK C11 0 dBm

Reset PORST GPIO C10 12 dBm
ESR0 GPIO C10 12 dBm
Test controller TESTMODE GPIO C10 12 dBm
VDD core VDD_LV Power C10 12 dBm
VDD I/O VDD_HV_IO Power C10 12 dBm
VDD FlexRay I/O VDD_HV_IO_FLX Power C10 12 dBm

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Table 10. RF immunity—Direct Power Injection (DPI) test specifications(1)(Continued)

BISS signal/power
Module Signal Monitor pin Function
supply limit class

VDD regulator VDD_HV_PMC Power C10 0 dBm

VDD Flash VDD_HV_FLA Power C10 12 dBm
VDD JTAG/OSC VDD_HV_IO_JTAG Power C10 0 dBm
1. Reference “BISS Generic IC EMC Test Specification”, section 9.4, “Immunity test configuration for ICs with CPU”.

3.4.1 BISS port and power supply limits

Figure 5 shows the BISS port limits behavior and Figure 6 shows BISS power supply limits
behavior. Class limits apply to signal under test in static mode only.
All pins of the microcontroller are defined as ‘Local’ (according to BISS specification).
Therefore, the supply pins on the microcontroller are tested to ‘Local’ requirements.

Figure 5. BISS port limits

dBμV BISS Limits

80
-Limits 4 layer
70

60

50

40

30

20

10

0
0.1 1 10 100
(Start = 0.10, Stop = 1000.00) MHz

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Figure 6. BISS power supply limits

dBμV BISS Limits

80

70

60 -Limits 4 Layer

50

40

30

20

10

0
0.1 1 10 100

(Start = 0.10, Stop = 1000.00) MHz

3.5 Electrostatic discharge (ESD)

The following table describes the ESD ratings of the device.

Table 11. ESD ratings(1)(2)

Parameter C Conditions Value Unit

ESD for Human Body Model (HBM)(3) T All pins 2000 V

(4)
ESD for field induced Charged Device Model (CDM) T All pins 500 V
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature.
Maximum DC parametrics variation within 10% of maximum specification”
3. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing
4. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level

3.6 Operating conditions

The following table describes the operating conditions for the device for which all
specifications in the datasheet are valid, except where explicitly noted.
The device operating conditions must not be exceeded or the functionality of the device is
not guaranteed.

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Table 12. Device operating conditions(1)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Frequency
fSYS SR C Device operating TJ = −40 °C to — — 160 MHz
frequency(2) 150 °C
fLBIST SR C Self-test operating TJ = −40 °C to — — 20 MHz
frequency 150 °C
Temperature
TJ SR P Junction –40.0 — 150.0 °C
Temperature
TA (TL to TH) SR P Ambient temperature –40.0 — 125.0 °C
Voltage
VDD_LV CC P Core supply voltage Refer to Section 3.17: Power management: PMC, V
measured at external POR/LVD, sequencing
pin(3),(4)
VDD_HV_IO_MAIN SR P I/O supply voltage LVD400/HVD600 4.5 — 5.5 V
enabled
C LVD400/HVD600 4.0 — 5.9
disabled (5),(6),(7)
C 3.0 — 5.9
VDD_HV_IO_JTAG SR P JTAG I/O supply 5 V range 4.5 — 5.5 V
voltage(8)
C 3.3 V range 3.0 — 3.6
C 5 V range 4.0 — 5.9
VDD_HV_IO_FLEX SR P FlexRay I/O supply 5 V range 4.5 — 5.5 V
voltage
C 3.3 V range 3.0 — 3.6
VDD_HV_PMC(9) SR P Power Management Full functionality 4.5 — 5.5 V
Controller (PMC)
C 3.0 — 5.5
supply voltage
VDD_HV_FLA(10), CC P Flash core voltage — 3.0 — 5.5 V
(11)

VDD_HV_ADV SR P SARADC and LVD295/ enabled 4.5 — 5.5 V

SDADC supply
C LVD295/ 4.0 — 5.9
voltage
disabled(5),(6)
C LVD295/ 3.7 — 5.9
disabled(5),(6)
VDD_HV_ADR_D SR P SD ADC supply — 4.5 VDD_HV_ADV 5.5 V
reference voltage
C 4.0 5.9
C 3.0 4.0
VDD_HV_ADR_D – SR D SD ADC reference — — — 25 mV
VDD_HV_ADV differential voltage

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Table 12. Device operating conditions(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

VSS_HV_ADR SR P SD ADC ground — VSS_HV_ADV V

reference voltage
VSS_HV_ADR_D – SR D VSS_HV_ADR_D — –25 — 25 mV
VSS_HV_ADV differential voltage
VDD_HV_ADR_S(12) SR P SARADC reference — 4.5 — 5.5 V
C 4.0 5.9
C 2.0 4.0
VDD_HV_ADR_S – SR D SARADC reference — — — 25 mV
VDD_HV_ADV differential voltage
VSS_HV_ADR_S – SR D VSS_HV_ADR_S — –25 — 25 mV
VSS_HV_ADV differential voltage
VSS_HV_ADV – VSS SR D VSS_HV_ADV — –25 — 25 mV
differential voltage
VRAMP_HV SR D Slew rate on HV — — — 100 V/ms
power supply pins
VIN SR C I/O input voltage — 0 — 5.5 V
range
Injection current
IIC SR T DC injection current Digital pins and –3.0 — 3.0 mA
(per pin)(13),(14),(15) analog pins
IMAXSEG SR D Maximum current per — –80 — 80 mA
power segment(16)
1. The ranges in this table are design targets and actual data may vary in the given range.
2. Maximum operating frequency is applicable to the computational cores and platform for the device. See the Clocking
chapter in the SPC574Kxx Microcontroller Reference Manual for more information on the clock limitations for the various IP
blocks on the device.
3. Core voltage as measured on device pin to guarantee published silicon performance.
4. During power ramp, voltage measured on silicon might be lower. Maximum performance is not guaranteed, but correct
silicon operation is guaranteed. Refer to the Power Management and Reset Generation Module chapters in the
SPC574Kxx Microcontroller Reference Manual for further information.
5. Maximum voltage is not permitted for entire product life. See Table 7: Absolute maximum ratings.
6. When internal LVD/HVDs are disabled, external monitoring is required to guarantee correct device operation.
7. Reduced output/input capabilities below 4.2 V. See performance derating values in I/O pad electrical characteristics
8. VDD_HV_IO_JTAG supply is shorted with VDD_HV_OSC supply within package.
9. VDD_HV_PMC is shorted with VDD_HV_IO_MAIN in the package.
10. Flash read operation is supported for a minimum VDD_HV_FLA value of 3.0 V. Flash read, program, and erase operations
are supported for a minimum VDD_HV_FLA value of 3.0 V.
11. This voltage can be measured on the pin but is not supplied by an external regulator. The Power Management Controller
generates PORs based on this voltage.
12. VDD_HV_ADR_S must be between 4.5 V and 5.5 V for accurate reading of the device Temperature Sensor.
13. Full device lifetime without performance degradation
14. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See Table 7:
Absolute maximum ratings for maximum input current for reliability requirements.

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15. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is
above the supply rail, current is injected through the clamp diode to the supply rail. For external RC network calculation,
assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.
16. Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDD_HV_IO power segment is
defined as one or more GPIO pins located between two VDD_HV_IO supply pins.

Table 13. Emulation (buddy) device operating conditions(1)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Frequency
— SR C Standard JTAG 1149.1/1149.7 — — — 50 MHz
frequency
— SR C High-speed debug frequency — — — 320 MHz
— SR T Data trace frequency — — — 1250 MHz
Temperature
TJ_BD SR P Device junction operating temperature — –40.0 — 150.0 °C
range
TA _BD SR P Ambient operating temperature range — –40.0 — 125.0 °C
Voltage
VDD_LV_BD SR P Buddy core supply voltage — 1.2 — 1.32 V
VDD_HV_IO_BD SR P Buddy I/O supply voltage — 3.0 — 5.5 V
VRAMP_LV_BD SR D Buddy slew rate on core power supply — — — 100 V/ms
pins
VRAMP_HV_BD SR D Buddy slew rate on HV power supply — — — 100 V/ms
pins
1. The ranges in this table are design targets and actual data may vary in the given range.

3.7 Temperature profile

Table 14. Temperature profile – Packaged parts
Vehicle category Operation Temperature Cumulated duration (hours)

Passenger cars Active operation TJ = 150 °C 3000

TJ = 135 °C —
TJ = 125 °C 9000
TJ = 110 °C 6000
TJ = 85 °C 1000
TJ = 40 °C 500
TJ = –40 °C 500
Total operation time 20000

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Table 14. Temperature profile – Packaged parts(Continued)

Vehicle category Operation Temperature Cumulated duration (hours)

Passenger cars – low end Active operation TA = 120 to 125 °C 100

TA = 115 to 120 °C 100
TA = 110 to 115 °C 100
TA = 105 to 110 °C 100
TA = 100 to 105 °C 100
TA = 95 to 100 °C 100
TA = 90 to 95 °C 100
TA = 85 to 90 °C 150
TA = 80 to 85 °C 300
TA = 50 to 80 °C 800
TA = 40 to 50 °C 1600
TA = 25 to 40 °C 2200
TA = –10 to 25 °C 1500
TA = –40 to –10 °C 500
Total operation time 7750
Commercial vehicles Active operation TJ = 150 °C 360
TJ = 140 °C 1200
TJ = 130 °C 2100
TJ = 120 °C 29000
TJ = 110 °C 3600
TJ = 85 °C 2740
TJ = 40 °C 500
TJ = –40 °C 500
Total operation time 40000

Table 15. Unbiased temperature profile – Packaged parts

Operation Temperature Cumulated duration (years)

Unbiased TJ > 60 °C 0(1)

TJ = –40 to 60 °C 20
1. Temperatures above 60 °C are accumulated against active operation biased condition.

3.8 DC electrical specifications

The following table describes the DC electrical specifications.

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Table 16. DC electrical specifications(1)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

IDD CC P Operating current all fMAX(2) — — 450 mA

supply rails
IDDPE CC C Operating current all fMAX(3) — — 470 mA
supplies including
program/erase
IDDAPP(4) CC C Operating current all fSYS = 160 MHz — — 340 mA
supplies with typical TJ < 142 °C
application
T fSYS = 140 MHz — — 360
TJ < 165 °C
IDD_MAIN_CORE_AC CC C Main fSYS = 160 MHz — — 56 mA
Core 0 dynamic
operating current
IDD_CHKR_CORE_AC CC C Checker fSYS = 160 MHz — — 40 mA
Core 0 dynamic
operating current
IDDAR CC T VDD_HV_IO After Run Tamb = 55oC — — 35 mA
operating current at Total device consumption
1.32 V(5) on VDD_HV_IO, including
consumption for VDD_LV
generation.
No I/O activity
P Tamb = 40oC — — 33
IDD_LV_BD CC P Debug/Emulation low TJ = 150 °C — — 250 mA
voltage supply VDD_LV_BD = 1.32 V
operating current(6),(7)
IDD_HV_IO_BD CC D Debug/Emulation high TJ = 150 °C — — 130 mA
voltage supply operating
current (Aurora +
JTAGM/LFAST)
ISPIKE CC T Maximum short term < 20 µs observation — — 90 mA
current spike(8) window
dI CC T Current difference ratio to 20 µs observation — — 20 %
average current window
(dI/avg(I))(9)
ISR CC D Current variation during —(10) — — 90(11) mA
boot/shut-down
IDDOFF CC T Power-off current on VDD_HV_IO = 2.5 V 100 — — μA
VDD_HV_IO supply rails(12)
VREF_BG_T CC P Bandgap trimmed TJ = –40 °C to 150 °C 1.200 — 1.237 V
reference voltage VDD_HV_ADV = 5 V + 10%
VREF_BG_TC CC C Bandgap temperature TJ = –40 °C to 150 °C — — 50 ppm/
coefficient(13) VDD_HV_ADV = 5 V + 10% °C

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Table 16. DC electrical specifications(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max
VREF_BG_LR CC C Bandgap line regulation TJ = –40 °C — — 8000 ppm/
VDD_HV_ADV = 5 V + 10% V
C TJ = 150 °C — — 4000
VDD_HV_ADV = 5 V + 10%
1. The ranges in this table are design targets and actual data may vary in the given range.
2. Application with maximum consumption, excludes lock step (safety) core, unloaded I/O with LVDS pins active and
terminated.
3. Application with maximum consumption, excludes lock step (safety) core, unloaded I/O with LVDS pins active and
terminated, with active flash program and erase.
4. Typical application consumption, unloaded I/O with LVDS pins active and terminated.
5. Device in STOP mode running from the internal RCOSC, with the external oscillator and ADCs disabled. Includes regulator
consumption for VDD_LV generation. Includes static I/O current with no pins toggling. VDD_HV refers to all 5 V supplies
(VDD_HV_ADV, VDD_HV_IO_MAIN, VDD_HV_IO_JTAG, VDD_HV_IO_FLEX, and VDD_HV_PMC). The IDDAR current can be further
reduced by disabling the I/O pad compensation cells via the PDO bits in the ME_<mode>_MC registers in the mode entry
module (MC_ME).
6. Leakage of VDD_LV_BD at junction temperature of 150 °C with production device powered estimated at 120 mA
7. Aurora and LFAST enabled, further consumption of 70 mA on VDD_HV_IO_BD supply for Aurora transmission line
8. ISPIKE value is only valid for the use cases defined for the IDDAPP and IDDAPP_LV specifications and its conditions given in
Table 16 (DC electrical specifications).
9. Moving window, valid for IDDAPP and its conditions given in Table 16 (DC electrical specifications), with a maximum of
90 mA for the worst case application.
10. Condition 1: For power on period from 0 V up to normal operation with reset asserted.
Condition 2: From reset asserted until IRCOSC frequency.
Condition 3: Increasing frequency from IRCOSC to PLL full frequency.
Condition 4: reverse order for power down to 0 V.
11. Current variation is considered during boot or during shut-down sequence. Progressive clock switching should be use to
guarantee low current variation.This does not include current requested for the loading of the capacitances on the VDD_LV
domain. Please refer to Section 3.17.1, Power management integration, Iclamp specification
12. IDDOFF is the minimum guaranteed consumption of the device during power-up. It can be used to correctly size power-off
ballast in case of current injection during power-off state.Power up/down current transients can be limited by controlling the
clock ramp rates with the Progressive Clock Frequency Switching block on the device.
13. The temperature coefficient and line regulation specifications are used to calculate the reference voltage drift at an
operating point within the specified voltage and temperature operating conditions.

3.9 I/O pad specification

The following table describes the different pad type configurations.

Table 17. I/O pad specification descriptions

Pad type Description

Weak configuration Provides a good compromise between transition time and low electromagnetic emission.
Pad impedance is centered around 800 Ω.
Medium configuration Provides transition fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
Pad impedance is centered around 200 Ω.
Strong configuration Provides fast transition speed; used for fast interface.
Pad impedance is centered around 50 Ω.

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Table 17. I/O pad specification descriptions(Continued)

Pad type Description

Very strong configuration Provides maximum speed and controlled symmetric behavior for rise and fall transition.
Used for fast interface including Ethernet and FlexRay interfaces requiring fine control of
rising/falling edge jitter.
Pad impedance is centered around 40 Ω.
Differential configuration A few pads provide differential capability providing very fast interface together with good
EMC performances.
Input only pads These low input leakage pads are associated with the ADC channels.

Note: Each I/O pin on the device supports specific drive configurations. See the signal description
table in the device reference manual for the available drive configurations for each I/O pin.

3.9.1 I/O input DC characteristics

Table 18 provides input DC electrical characteristics as described in Figure 7.

Figure 7. I/O input DC electrical characteristics definition

VIN
VDD

VIH

VHYS

VIL

VINTERNAL
(SIUL register)

Table 18. I/O input DC electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

TTL
VIHTTL SR P Input high level TTL 4.5 V < VDD_HV_IO < 5.5 V(6) 2 — VDD_HV_IO V
+ 0.3
VILTTL SR P Input low level TTL 4.5 V < VDD_HV_IO < 5.5 V(6) –0.3 — 0.8
(6)
VHYSTTL — C Input hysteresis TTL 4.5 V < VDD_HV_IO < 5.5 V 0.275 — —
VDRFTTTL — C Input VIL/VIH — — — 100 mV
temperature drift TTL

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Table 18. I/O input DC electrical characteristics(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

AUTOMOTIVE
VIHAUT(1) SR P Input high level 4.5 V < VDD_HV_IO < 5.5 V 3.8 — VDD_HV_IO V
AUTOMOTIVE + 0.3
VILAUT(2) SR P Input low level 4.5 V < VDD_HV_IO < 5.5 V –0.3 — 2.1(3) V
AUTOMOTIVE
VHYSAUT(4) — C Input hysteresis 4.5 V < VDD_HV_IO < 5.5 V 0.4(6) — — V
AUTOMOTIVE
VDRFTAUT — C Input VIL/VIH 4.5 V < VDD_HV_IO < 5.5 V — — 100(5) mV
temperature drift
CMOS
VIHCMOS_H SR C Input high level CMOS 3.0 V < VDD_HV_IO < 3.6 V 0.65 * — VDD_HV_IO V
(6) (with hysteresis) VDD_HV_IO + 0.3
P 4.5 V < VDD_HV_IO < 5.5 V
VIHCMOS(6) SR C Input high level CMOS 3.0 V < VDD_HV_IO < 3.6 V 0.6 * — VDD_HV_IO V
(without hysteresis) VDD_HV_IO + 0.3
P 4.5 V < VDD_HV_IO < 5.5 V
(6)
VILCMOS_H SR C Input low level CMOS 3.0 V < VDD_HV_IO < 3.6 V –0.3 — 0.35 * V
(with hysteresis) VDD_HV_IO
P 4.5 V < VDD_HV_IO < 5.5 V
VILCMOS(6) SR C Input low level CMOS 3.0 V < VDD_HV_IO < 3.6 V –0.3 — 0.4 * V
(without hysteresis) VDD_HV_IO
P 4.5 V < VDD_HV_IO < 5.5 V
VHYSCMOS — C Input hysteresis CMOS 3.0 V < VDD_HV_IO < 3.6 V 0.1 * — — V
VDD_HV_IO
4.5 V < VDD_HV_IO < 5.5 V(7)
VDRFTCMOS — C Input VIL/VIH 3.0 V < VDD_HV_IO < 3.6 V — — 100(5) mV
temperature drift
4.5 V < VDD_HV_IO < 5.5 V
CMOS
INPUT CHARACTERISTICS(8)
ILKG CC Digital input leakage 4.5 V < VDD_HV < 5.5 V — — 1 µA
P 0.1*VDD_HV < VIN < 0.9*VDD_HV
TJ < 150 °C
ILKG_MED CC C Digital input leakage for 4.5 V < VDD_HV < 5.5 V — — 500 nA
MEDIUM pad VSS_HV < VIN < VDD_HV
CIN CC D Digital input GPIO input pins — — 10 pF
capacitance
Ethernet input pins — — 8
1. A good approximation for the variation of the minimum value with supply is given by formula VIHAUT = 0.69 × VDD_HV_IO.
2. A good approximation for the variation of the maximum value with supply is given by formula VILAUT = 0.49 × VDD_HV_IO.
3. Sum of VILAUT and VHYSAUT is guaranteed to remain above 2.6 V in the 4.5 V < VDD_HV_IO < 5.5 V. Production test done
with 2.06 V limit at cold, Tj < 25 oC.
4. A good approximation of the variation of the minimum value with supply is given by formula VHYSAUT = 0.11 × VDD_HV_IO.
5. In a 1 ms period, assuming stable voltage and a temperature variation of ±30 °C, VIL/VIH shift is within ±50 mV. For SENT
requirement refer to Note: on page 46.

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6. Only for VDD_HV_IO_JTAG and VDD_HV_IO_FLEX power segment. The TTL threshold are controlled by the VSIO bit.
VSIO[VSIO_xx] = 0 in the range 3.0 V < VDD_HV_IO < 3.6 V, VSIO[VSIO_xx] = 1 in the range 4.5 V < VDD_HV_IO < 5.5 V.
7. Only for VDD_HV_IO_JTAG and VDD_HV_IO_FLEX power segment.
8. For LFAST, microsecond bus and LVDS input characteristics, refer to dedicated communication module chapters.

Table 19 provides weak pull figures. Both pull-up and pull-down current specifications are
provided.

Table 19. I/O pull-up/pull-down DC electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

|IWPU| CC T Weak pull-up VIN = 0 V 10.6 * VDD_HV – — — µA

current absolute VDD_POR(2) < VDD_HV_IO 10.6
value(1) < 3.0 V(3)(4)
CC T VIN > VIL = 1.1 V (TTL) — — 130
4.5 V < VDD_HV_IO < 5.5 V
CC P VIN = 0.69* VDD_HV_IO 23 — 65
4.5 V < VDD_HV_IO < 5.5 V
CC T VIN = 0.49* VDD_HV_IO — — 82
4.5 V < VDD_HV_IO < 5.5 V
RWPU CC D Weak pull-up 0.49* VDD_HV_IO < VIN < 0.69* 34 — 62 kΩ
resistance VDD_HV_IO
4.5 V < VDD_HV_IO < 5.5 V
|IWPD| CC T Weak pull-down VIN < VIL = 0.9 V (TTL) 16 — — µA
current absolute 4.5 V < VDD_HV_IO < 5.5 V
value
P VIN = 0.69* VDD_HV_IO 50 — 130
4.5 V < VDD_HV_IO < 5.5 V
T VIN = 0.49* VDD_HV_IO 40 — —
4.5 V < VDD_HV_IO < 5.5 V
RWPD CC D Weak pull-down 0.49* VDD_HV_IO < VIN < 0.69* 30 — 55 kΩ
resistance VDD_HV_IO
4.5 V < VDD_HV_IO < 5.5 V
1. Weak pull-up/down is enabled within tWK_PU = 1 µs after internal/external reset has been asserted. Output voltage will
depend on the amount of capacitance connected to the pin.
2. VDD_POR is the minimum VDD_HV_IO supply voltage for the activation of the device pull-up/down, and is given in the
Table 25: Reset electrical characteristics of Section 3.11: Reset pad (PORST, ESR0) electrical characteristics.
3. VDD_POR is defined in the Table 25: Reset electrical characteristics of Section 3.11: Reset pad (PORST, ESR0) electrical
characteristics.
4. Weak pull-up behavior during power-up. Operational with VDD_HV_IO > VDD_POR.

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Figure 8. Weak pull-up electrical characteristics definition

tWK_PU tWK_PU
VDD_HV_IO

VDD_POR

RESET(INTERNAL)

pull-up
enabled
YES

NO

PAD (1)
(1)
(1)

POWER-UP Application defined RESET Application defined POWER-DOWN

1. Actual PAD slopes will depend on external capacitances and VDD_HV_IO supply.

3.9.2 I/O output DC characteristics

The figure below provides description of output DC electrical characteristics.

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Figure 9. I/O output DC electrical characteristics definition

VINTERNAL
(SIUL register)

50% 50%
VHYS

tPLH (rising edge) tPHL (falling edge)

Vout tSKEW20-80

90%
80%

50%

20%
10%

tR20-80
tF20-80
tR10-90
tF10-90

tTR (max) = MAX (tR10-90;tF10-90) tTR20-80(max) = MAX (tR20-80;tF20-80)

tTR (min) = MIN (tR10-90;tF10-90) tTR20-80(min) = MIN (tR20-80;tF20-80)

tSKEW = |tR20-80-tF20-80|

The following tables provide DC characteristics for bidirectional pads:

• Table 20 provides output driver characteristics for I/O pads when in WEAK
configuration.
• Table 21 provides output driver characteristics for I/O pads when in MEDIUM
configuration.
• Table 22 provides output driver characteristics for I/O pads when in STRONG
configuration.
• Table 23 provides output driver characteristics for I/O pads when in VERY STRONG
configuration.
Note: Driver configuration is controlled by SIUL2_MSCRn registers. It is available within two
PBRIDGEA_CLK clock cycles after the associated SIUL2_MSCRn bits have been written.
Table 20 shows the WEAK configuration output buffer electrical characteristics.

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Table 20. WEAK configuration output buffer electrical characteristics

Value(2)
(1)
Symbol C Parameter Conditions Unit
Min Typ Max

ROH_W CC P PMOS output impedance 4.5 V < VDD_HV_IO < 5.5 V — — 1040 Ω
weak configuration Push pull, IOH < 0.5 mA
ROL_W CC P NMOS output impedance 4.5 V < VDD_HV_IO < 5.5 V — — 1040 Ω
weak configuration Push pull, IOL < 0.5 mA
fMAX_W CC T Output frequency CL = 25 pF(3) — — 2 MHz
weak configuration (3)
CL = 50 pF — — 1
D CL = 200 pF(3) — — 0.25
tTR_W CC T Transition time output pin CL = 25 pF, 40 — 120 ns
weak configuration(4) 4.5 V < VDD_HV_IO < 5.5 V
CL = 50 pF, 80 — 240
4.5 V < VDD_HV_IO < 5.5 V
D CL = 200 pF, 320 — 820
4.5 V < VDD_HV_IO < 5.5 V
CL = 25 pF, 50 — 150
3.0 V < VDD_HV_IO < 3.6 V(5)
CL = 50 pF, 100 — 300
3.0 V < VDD_HV_IO < 3.6 V(5)
CL = 200 pF, 350 — 1050
3.0 V < VDD_HV_IO < 3.6 V(5)
|tSKEW_W| CC T Difference between rise — — — 25 %
and fall time
IDCMAX_W CC D Maximum DC current — — — 4 mA
TPHL/PLH CC D Propagation delay CL = 25 pF, — — 120 ns
4.5 V < VDD_HV_IO < 5.9 V
CL = 25 pF, — — 150
3.0 V < VDD_HV_IO < 3.6 V
CL = 50 pF, — — 240
4.5 V < VDD_HV_IO < 5.9 V
CL = 50 pF, — — 300
3.0 V < VDD_HV_IO < 3.6 V(5)
1. All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0
2. All values need to be confirmed during device validation.
3. CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 18) are to be added to
calculate total signal capacitance (CTOT = CL + CIN).
4. Transition time maximum value is approximated by the following formula:
0 pF < CL < 50 pFtTR_W(ns) = 22 ns + CL(pF) × 4.4 ns/pF
50 pF < CL < 200 pFtTR_W(ns) = 50 ns + CL(pF) × 3.85 ns/pF
5. Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_FLEX segment when VSIO[VSIO_IF] = 0.

Table 21 shows the MEDIUM configuration output buffer electrical characteristics.

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Table 21. MEDIUM configuration output buffer electrical characteristics

Value(2)
(1)
Symbol C Parameter Conditions Unit
Min Typ Max

ROH_M CC P PMOS output impedance 4.5 V < VDD_HV_IO < 5.5 V — — 270 Ω
MEDIUM configuration Push pull, IOH < 2 mA
ROL_M CC P NMOS output impedance 4.5 V < VDD_HV_IO < 5.5 V — — 270 Ω
MEDIUM configuration Push pull, IOL < 2 mA
fMAX_M CC T Output frequency CL = 25 pF(3) — — 12 MHz
MEDIUM configuration (4)
CL = 50 pF — — 6
D CL = 200 pF(4) — — 1.5
tTR_M CC T Transition time output pin CL = 25 pF 10 — 30 ns
MEDIUM configuration(4) 4.5 V < VDD_HV_IO < 5.5 V
CL = 50 pF 20 — 60
4.5 V < VDD_HV_IO < 5.5 V
D CL = 200 pF 60 — 200
4.5 V < VDD_HV_IO < 5.5 V
CL = 25 pF, 12 — 42
3.0 V < VDD_HV_IO <
3.6 V(5)
CL = 50 pF, 24 — 86
3.0 V < VDD_HV_IO <
3.6 V(5)
CL = 200 pF, 70 — 300
3.0 V < VDD_HV_IO <
3.6 V(5)
|tSKEW_M| CC T Difference between rise and — — — 25 %
fall time
IDCMAX_M CC D Maximum DC current — — — 4 mA
TPHL/PLH CC D Propagation delay CL = 25 pF, — — 35 ns
4.5 V < VDD_HV_IO < 5.9 V
CL = 25 pF, — — 42
3.0 V < VDD_HV_IO < 3.6 V
CL = 50 pF, — — 70
4.5 V < VDD_HV_IO < 5.9 V
CL = 50 pF, — — 85
3.0 V < VDD_HV_IO <
3.6 V(5)
1. All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0
2. All values need to be confirmed during device validation.
3. CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 18) are to be added to
calculate total signal capacitance (CTOT = CL + CIN).
4. Transition time maximum value is approximated by the following formula:
0 pF < CL < 50 pFtTR_M(ns) = 5.6 ns + CL(pF) × 1.11 ns/pF
50 pF < CL < 200 pFtTR_M(ns) = 13 ns + CL(pF) × 0.96 ns/pF

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5. Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_FLEX segment when VSIO[VSIO_IF] = 0

Table 22 shows the STRONG configuration output buffer electrical characteristics.

Table 22. STRONG configuration output buffer electrical characteristics

Value(2)
(1)
Symbol C Parameter Conditions Unit
Min Typ Max

ROH_S CC P PMOS output impedance 4.5 V < VDD_HV_IO < 5.5 V — — 70 Ω

STRONG configuration Push pull, IOH < 8 mA
ROL_S CC P NMOS output impedance 4.5 V < VDD_HV_IO < 5.5 V — — 70 Ω
STRONG configuration Push pull, IOL < 8 mA
fMAX_S CC T Output frequency CL = 25 pF(3) — — 40 MHz
STRONG configuration
CL = 50 pF(4) — — 20
CL = 200 pF(4) — — 5
tTR_S CC T Transition time output pin CL = 25 pF 2.5 — 10 ns
STRONG configuration(4) 4.5 V < VDD_HV_IO < 5.5 V
CL = 50 pF 3.5 — 16
4.5 V < VDD_HV_IO < 5.5 V
CL = 200 pF 13 — 50
4.5 V < VDD_HV_IO < 5.5 V
CL = 25 pF, 4 — 15
3.0 V < VDD_HV_IO <
3.6 V(5)
CL = 50 pF, 6 — 27
3.0 V < VDD_HV_IO <
3.6 V(5)
CL = 200 pF, 20 — 83
3.0 V < VDD_HV_IO <
3.6 V(5)
IDCMAX_S CC D Maximum DC current — — — 10 mA
|tSKEW_S| CC T Difference between rise and — — — 25 %
fall time
TPHL/PLH CC D Propagation delay CL = 25 pF, — — 12 ns
4.5 V < VDD_HV_IO < 5.9 V
CL = 25 pF, — — 18
3.0 V < VDD_HV_IO < 3.6 V
CL = 50 pF, — — 20
4.5 V < VDD_HV_IO < 5.9 V
CL = 50 pF, — — 36
3.0 V < VDD_HV_IO <
3.6 V(5)
1. All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0
2. All values need to be confirmed during device validation.

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3. CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 18) are to be added to
calculate total signal capacitance (CTOT = CL + CIN).
4. Transition time maximum value is approximated by the following formula: tTR_S(ns) = 4.5 ns + CL(pF) x 0.23 ns/pF.
5. Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_FLEX segment when VSIO[VSIO_IF] = 0

Table 23 shows the VERY STRONG configuration output buffer electrical characteristics.

Table 23. VERY STRONG configuration output buffer electrical characteristics(1)

Value(3)
Symbol C Parameter Conditions(2) Unit
Min Typ Max

ROH_V CC P PMOS output impedance VDD_HV_IO = 5.0 V ± 10%, — — 60 Ω

VERY STRONG VSIO[VSIO_xx] = 1,
configuration IOH = 8 mA
C VDD_HV_IO = 3.3 V ± 10%, — — 85
VSIO[VSIO_xx] = 0,
IOH = 7 mA(4)
ROL_V CC P NMOS output impedance VDD_HV_IO = 5.0 V ± 10%, — — 60 Ω
VERY STRONG VSIO[VSIO_xx] = 1,
configuration IOL = 8 mA
C VDD_HV_IO = 3.3 V ± 10%, — — 85
VSIO[VSIO_xx] = 0,
IOL = 7 mA(4)
fMAX_V CC T Output frequency VDD_HV_IO = 5.0 V ± 10%, — — 50 MHz
VERY STRONG VSIO[VSIO_xx] = 1,
configuration CL = 25 pF(5)
VDD_HV_IO = 3.3 V ± 10%, — — 50
VSIO[VSIO_xx] = 1,
CL = 15 pF(4),(5)
tTR_V CC T 10–90% threshold VDD_HV_IO = 5.0 V ± 10%, 1 — 5.3 ns
transition time output pin VSIO[VSIO_xx] = 1,
VERY STRONG CL = 25 pF(5)
configuration
VDD_HV_IO = 5.0 V ± 10%, 2.5 — 12
VSIO[VSIO_xx] = 1,
CL = 50 pF(5)
VDD_HV_IO = 5.0 V ± 10%, 11 — 45
VSIO[VSIO_xx] = 1,
CL = 200 pF(5)
tTR20-80 CC D 20–80% threshold VDD_HV_IO = 5.0 V ± 10%, 0.8 — 4 ns
transition time(6) output pin VSIO[VSIO_xx] = 1,
VERY STRONG CL = 25 pF(5)
configuration
VDD_HV_IO = 3.3 V ± 10%, 1 — 5
CL = 15 pF(5)
tTRTTL CC D TTL threshold transition VDD_HV_IO = 3.3 V ± 10%, 1 — 5 ns
time(7) for output pin in CL = 25 pF(5)
VERY STRONG
configuration

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Table 23. VERY STRONG configuration output buffer electrical characteristics(1)(Continued)

Value(3)
Symbol C Parameter Conditions(2) Unit
Min Typ Max

ΣtTR20-80 CC D Sum of transition time 20– VDD_HV_IO = 5.0 V ± 10%, — — 9 ns

80% output pin VERY VSIO[VSIO_xx] = 1,
STRONG configuration(8) CL = 25 pF
VDD_HV_IO = 3.3 V ± 10%, — — 9
CL = 15 pF(5)
|tSKEW_V| CC T Difference between rise VDD_HV_IO = 5.0 V ± 10%, 0 — 1 ns
and fall time at 20–80% VSIO[VSIO_xx] = 1,
CL = 25 pF(5)
TPHL/PLH CC D Propagation delay CL = 25 pF, — — 9 ns
4.5 V < VDD_HV_IO < 5.9 V
CL = 25 pF, — — 10.5
3.0 V < VDD_HV_IO < 3.6 V
CL = 50 pF, — — 15
4.5 V < VDD_HV_IO < 5.9 V
CL = 50 pF, — — 12
3.0 V < VDD_HV_IO < 3.6 V
IDCMAX_VS CC D Maximum DC current — — — 10 mA
1. Refer to FlexRay section for parameter dedicated to this interface.
2. All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0.
3. All values need to be confirmed during device validation.
4. Only available on the VDD_HV_IO_JTAG and VDD_HV_IO_FLEX segments.
5. CL is the sum of external capacitance. Add device and package capacitances (CIN, defined in Table 18: I/O input DC
electrical characteristics) to calculate total signal capacitance (CTOT = CL + CIN).
6. 20–80% transition time as per FlexRay standard.
7. TTL transition time as for Ethernet standard.
8. For specification per Electrical Physical Layer Specification 3.0.1, see the dCCTxDRISE25+dCCTxDFALL25 (Sum of Rise and
Fall time of TxD signal at the output pin) specification in Table 63: TxD output characteristics in Section 3.19.4.2: TxD.

3.10 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair.
Table 24 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment
should remain below the IAVGSEG maximum value.
In order to ensure device functionality, the sum of the dynamic and static currents of the I/O
on a single segment should remain below the IDYNSEG maximum value.
Pad mapping on each segment can be optimized using the pad usage information provided
in the I/O Signal Description table. The sum of all pad usage ratios within a segment should
remain below 100%.

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Note: In order to maintain the required input thresholds for the SENT interface, the sum of all I/O
pad output percent IR drop as defined in the I/O Signal Description table, must be below
50 %. See the I/O Signal Description attachment.
Note: The SPC574Kxx I/O Signal Description and Input Multiplexing Tables are contained in a
Microsoft Excel® workbook file attached to this document. Locate the paperclip symbol on
the left side of the PDF window, and click it. Double-click on the Excel file to open it and
select the I/O Signal Description Table tab.

Table 24. I/O consumption(1)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

IRMS_SEG SR D Sum of all the DC I/O current VDD = 5.0 V ± 10% — — 80 mA

within a supply segment
VDD = 3.3 V ± 10% — — 80
IRMS_W CC D RMS I/O current for WEAK CL = 25 pF, 2 MHz — — 1.1 mA
configuration VDD = 5.0 V ± 10%
CL = 50 pF, 1 MHz — — 1.1
VDD = 5.0 V ± 10%
CL = 25 pF, 2 MHz — — 0.6
VDD = 3.3 V ± 10%
CL = 50 pF, 1 MHz — — 0.6
VDD = 3.3 V ± 10%
IRMS_M CC D RMS I/O current for MEDIUM CL = 25 pF, 12 MHz — — 4.7 mA
configuration VDD = 5.0 V ± 10%
CL = 50 pF, 6 MHz — — 4.8
VDD = 5.0 V ± 10%
CL = 25 pF, 12 MHz — — 2.6
VDD = 3.3 V ± 10%
CL = 50 pF, 6 MHz — — 2.7
VDD = 3.3 V ± 10%
IRMS_S CC D RMS I/O current for STRONG CL = 25 pF, 50 MHz — — 19 mA
configuration VDD = 5.0 V ± 10%
CL = 50 pF, 25 MHz — — 19
VDD = 5.0 V ± 10%
CL = 25 pF, 50 MHz — — 10
VDD = 3.3 V ± 10%
CL = 50 pF, 25 MHz — — 10
VDD = 3.3 V ± 10%

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Table 24. I/O consumption(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

IRMS_V CC D RMS I/O current for VERY CL = 25 pF, 50 MHz, — — 22 mA

STRONG configuration VDD = 5.0V +/- 10%
CL = 50 pF, 25 MHz, — — 22
VDD = 5.0V ± 10%
CL = 25 pF, 50 MHz, — — 11
VDD = 3.3V ± 10%
CL = 25 pF, 25 MHz, — — 11
VDD = 3.3V ± 10%
IDYN_SEG SR D Sum of all the dynamic and DC I/O VDD = 5.0 V ± 10% — — 195 mA
current within a supply segment
VDD = 3.3 V ± 10% — — 150
IDYN_W(2) CC D Dynamic I/O current for WEAK CL = 25 pF, — — 5.0 mA
configuration VDD = 5.0 V ± 10%
CL = 50 pF, — — 5.1
VDD = 5.0 V ± 10%
CL = 25 pF, — — 2.2
VDD = 3.3 V ± 10%
CL = 50 pF, — — 2.3
VDD = 3.3 V ± 10%
IDYN_M CC D Dynamic I/O current for MEDIUM CL = 25 pF, — — 15 mA
configuration VDD = 5.0 V ± 10%
CL = 50 pF, — — 15.5
VDD = 5.0 V ± 10%
CL = 25 pF, — — 7.0
VDD = 3.3 V ± 10%
CL = 50 pF, — — 7.1
VDD = 3.3 V ± 10%
IDYN_S CC D Dynamic I/O current for STRONG CL = 25 pF, — — 50 mA
configuration VDD = 5.0 V ± 10%
CL = 50 pF, — — 55
VDD = 5.0 V ± 10%
CL = 25 pF, — — 22
VDD = 3.3 V ± 10%
CL = 50 pF, — — 25
VDD = 3.3 V ± 10%

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Table 24. I/O consumption(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

IDYN_V CC D Dynamic I/O current for VERY CL = 25 pF, — — 60 mA

STRONG configuration VDD = 5.0 V ± 10%
CL = 50 pF, — — 64
VDD = 5.0 V ± 10%
CL = 25 pF, — — 26
VDD = 3.3 V ± 10%
CL = 50 pF, — — 29
VDD = 3.3 V ± 10%
1. I/O current consumption specifications for the 4.5 V <= VDD_HV_IO <= 5.5 V range are valid for VSIO_[VSIO_xx] = 1, and
VSIO[VSIO_xx] = 0 for 3.0 V <= VDD_HV_IO <= 3.6 V.
2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. When possible (timed
output) it is recommended to delay transition between pads by few cycles to reduce noise and consumption.

3.11 Reset pad (PORST, ESR0) electrical characteristics

The device implements a dedicated bidirectional reset pin (PORST).
Note: PORST pin does not require active control. It is possible to implement an external pull-up to
ensure correct reset exit sequence. Recommended value is 4.7 kΩ.

Figure 10. Start-up reset requirements

VDD

VDDMIN

VDD_POR

PORST

VIH

VIL

PORST undriven. device start-up phase

Device reset by
internal power-on PORST driven low by Device reset forced by
reset. internal power-on reset. external circuitry.

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Figure 11 describes device behavior depending on supply signal on PORST:

1. PORST low pulse amplitude is too low—it is filtered by input buffer hysteresis. Device
remains in current state.
2. PORST low pulse duration is too short—it is filtered by a low pass filter. Device remains
in current state.
3. PORST low pulse generates a reset:
a) PORST low but initially filtered during at least WFRST. Device remains initially in
current state.
b) PORST potentially filtered until WNFRST. Device state is unknown: it may either be
reset or remains in current state depending on other factors (temperature, voltage,
device).
c) PORST asserted for longer than WNFRST. Device is under reset.

Figure 11. Noise filtering on reset signal

VPORST, VESR0

VDD

VIH
VHYS

VIL

internal
reset

filtered by
filtered by filtered by unknown reset
hysteresis lowpass filter lowpass filter state device under hardware reset

WFRST WFRST
WNFRST

1 2 3a 3b 3c

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Table 25. Reset electrical characteristics

Value(1)
Symbol Parameter Conditions Unit
Min Typ Max

VIH SR P Input high level TTL 2.0 — VDD_HV_IO V

—
(Schmitt trigger) +0.4
VIL SR P Input low level TTL — –0.4 — 0.8 V
(Schmitt trigger)
VHYS CC C Input hysteresis TTL — 275 — — mV
(Schmitt trigger)
VDD_POR CC D Minimum supply for strong — — — 1.2 V
pull-down activation
IOL_R CC P Strong pull-down current(2) Device under power-on 0.2 — — mA
reset
VDD_HV_IO = VDD_POR,
VOL = 0.35 * VDD_HV_IO
Device under power-on 8 — —
reset
3.0 V < VDD_HV_IO < 5.5 V,
VOL > 1.0 V
|IWPU| CC P Weak pull-up current absolute ESR0 pin 23 — 65 µA
value VIN = 0.69 * VDD_HV_IO
C ESR0 pin — — 82
VIN = 0.49 * VDD_HV_IO
|IWPD| CC P Weak pull-down current PORST pin 50 — 130 µA
absolute value VIN = 0.69 * VDD_HV_IO
C PORST pin 40 — —
VIN = 0.49 * VDD_HV_IO
WFRST SR P PORST and ESR0 input — — — 500 ns
filtered pulse
WNFRST SR P PORST and ESR0 input not — 2000 — — ns
filtered pulse
WFNMI SR P ESR1 input filtered pulse — — — 15 ns
WNFNMI SR P ESR1 input not filtered pulse — 400 — — ns
1. An external 4.7 KOhm pull-up resistor is recommended to be used with the PORST and ESR0 pins for fast negation of the
signals.
2. IOL_R applies to both PORST and ESR0: Strong pull-down is active on PHASE0 for PORST. Strong pull-down is active on
PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for ESR0.

PORST must be connected to an external power-on supply circuitry. Minimum requested

circuitry is external pull-up to ensure device can exit reset.

Note: No restrictions exist on reset signal slew rate apart from absolute maximum rating
compliance.

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3.12 Oscillator and FMPLL

3.12.1 FMPLL
Two frequency-modulated phase-locked loop (FMPLL) modules, the Reference PLL (PLL0)
and the System PLL (PLL1) generate the system and auxiliary clocks from the main oscillator
driver.

Figure 12. PLL integration

IRCOSC PLL0_PHI
PLL0 PLL0_PHI1

XOSC

PLL1_PHI
PLL1

Table 26. PLL0 electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

fPLL0IN SR — PLL0 input clock(1),(2) — 8 — 44 MHz

ΔPLL0IN SR — PLL0 input clock duty — 40 — 60 %
cycle(1)
fPLL0VCO CC P PLL0 VCO frequency — 600 — 1250 MHz
fPLL0PHI CC D PLL0 clock output — — — 400 MHz
frequency on PHI
fPLL0PHI1 CC D PLL0 clock output — — — 78 MHz
frequency on PHI1
tPLL0LOCK CC P PLL0 lock time — — — 110 µs
|ΔPLL0PHI0SPJIT| CC T PLL0_PHI0 single period fPLL0PHI0 = 400 MHz, 6- — — 200 ps
jitter sigma pk-pk
fPLL0IN = 20 MHz
(resonator)
|ΔPLL0PHI1SPJIT| CC T PLL0_PHI1 single period fPLL0PHI1 = 40MHz, 6- — — 300(3) ps
jitter sigma pk-pk
fPLL0IN = 20 MHz
(resonator)

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Table 26. PLL0 electrical characteristics(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

|ΔPLL0LTJIT| CC T PLL0 long-term jitter(3) 10 periods accumulated — — ± 250 ps

fPLL0IN = 20 MHz jitter (80 MHz equivalent
(resonator), VCO frequency), 6-sigma pk-pk
frequency = 800 MHz
16 periods accumulated — — ± 300 ps
jitter (50 MHz equivalent
frequency), 6-sigma pk-pk
long term jitter (< 1 MHz — — ± 500 ps
equivalent frequency), 6-
sigma pk-pk
IPLL0 CC C PLL0 consumption FINE LOCK state — — 5 mA
fPLL0FREE CC D VCO free running — 35 — 400 MHz
frequency
1. PLL0IN clock retrieved directly from either internal RC oscillator (IRCOSC) or external oscillator (XOSC) clock. Input
characteristics are granted when using XOSC.
2. fPLL0IN frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure PFD input signal is in the range
8 MHz-20 MHz.
3. VDD_LV noise due to application in the range VDD_LV = 1.25 V ± 5%, with frequency below PLL bandwidth (40 KHz) is
filtered.

Table 27. PLL1 electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

fPLL1IN SR — PLL1 input clock(1) — 38 — 78 MHz

ΔPLL1IN SR — PLL1 input clock duty cycle(1) — 35 — 65 %
fPLL1VCO CC P PLL1 VCO frequency — 600 — 1250 MHz
fPLL1PHI CC D PLL1 output clock frequency on PHI — 4.762 — 160 MHz
tPLL1LOCK CC P PLL1 lock time — — — 100 µs
fPLL1MOD CC T PLL1 modulation frequency — — — 250 KHz
|δPLL1MOD| CC T PLL1 modulation depth (when enabled) Center spread 0.25 — 2 %
Down spread 0.5 — 4 %
IPLL1 CC C PLL1 consumption FINE LOCK state — — 6 mA
fPLL1FREE CC D VCO free running frequency — 35 — 400 MHz
1. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when
using internal PLL0 or XOSC is used in functional mode.

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3.12.2 External oscillator (XOSC)

Table 28. External Oscillator electrical specifications

Value
Symbol C Parameter Conditions Unit
Min Max

fXTAL CC D Crystal Frequency — 4 8 MHz

Range(1)
— >8 20
— >20 40
(2),(3)
tcst CC T Crystal start-up time TJ = 150 °C — 5 ms
(4)
trec CC — Crystal recovery time — — 0.5 ms
VIHEXT CC D EXTAL input high voltage VREF = 0.28 * VDD_HV_IO_JTAG VREF + — V
(External Reference) 0.6
VILEXT CC D EXTAL input low voltage(5) VREF = 0.28 * VDD_HV_IO_JTAG — VREF - 0.6 V
CS_EXTAL CC T Total on-chip stray QFP 6.0 8.0 pF
capacitance on EXTAL
pin(6)
CS_XTAL CC T Total on-chip stray QFP 6.0 8.0 pF
capacitance on XTAL pin(8)
gm CC P Oscillator TJ = -40 °C to fXTAL ≤ 8 MHz 2.6 11.0 mA/V
Transconductance 150 °C
C fXTAL ≤ 20 MHz 7.9 26.0
4.5 V < VDD_HV
C _IO < 5.5 V fXTAL ≤ 40 MHz 10.4 34.0
VEXTAL CC D Oscillation Amplitude on TJ = –40 °C to 150 °C 0.5 1.8 V
the EXTAL pin after
startup(7)
VHYS CC D Comparator Hysteresis TJ = 150 °C 0.1 1.0 V
IXTAL CC D XTAL current(8) TJ = 150 °C — 14 mA
1. The range is selectable by UTEST miscellaneous DCF clients XOSC_LF_EN and XOSC_EN_40 MHz.
2. This value is determined by the crystal manufacturer and board design.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load
capacitor value.
5. Applies to an external clock input and not to crystal mode.
6. See crystal manufacturer’s specification for recommended load capacitor (CL) values.The external oscillator requires
external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (CS_EXTAL/CS_XTAL)
and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load
capacitor value is selected via S/W to match the crystal manufacturer’s specification, while accounting for on-chip and PCB
capacitance.
7. Amplitude on the EXTAL pin after startup is determined by the ALC block, i.e., the Automatic Level Control Circuit. The
function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to
reduce power, distortion, and RFI, and to avoid over-driving the crystal. The operating point of the ALC is dependent on the
crystal value and loading conditions.
8. IXTAL is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum
current during startup of the oscillator. The current after oscillation is typically in the 2-3 mA range and is dependent on the
load and series resistance of the crystal. Test circuit is shown in Figure 14. The ALC block is the Automatic Level Control
Circuit. The function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation
in order to reduce power, distortion, and RFI, and to avoid overdriving the crystal.

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Figure 13. Crystal/Resonator Connections

8-40MHz EXTERNAL
OSCILLATOR (XOSC) DRIVER

On chip Cx Cy
vsssyn
Off chip

EXTAL XTAL

Crystal or Resonator

Table 29. Selectable load capacitance

Capacitance offered on EXTAL/XTAL
load_cap_sel[4:0] from DCF record
(Cx and Cy)(1),(2) (pF)

00000 1.0
00001 2.0
00010 2.9
00011 3.8
00100 4.8
00101 5.7
00110 6.6
00111 7.5
01000 8.5
01001 9.4
01010 10.3
01011 11.2
01100 12.2
01101 13.1
01110 14.0
01111 15.0
(3)
10000–11111 Reserved
1. Values are determined from simulation across process corners and voltage and temperature variation. Capacitance values
vary ±12% across process, 0.25% across voltage, and no variation across temperature.

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2. Values in this table do not include the die and package capacitances given by Cs_xtal/Cs_extal in Table 28 (External
Oscillator electrical specifications).
3. Configurations 10000–11111 should not be used. Configurations 10000–11100 result in same capacitances of
configurations 00011–01111. Configurations 11101, 11110, and 11111 select maximum capacitances.

Figure 14. Test circuit

VDDOSC

Bias current
ALC

IXTAL XTAL
-
EXTAL
+ Comparator
A OFF
VSSOSC

V
VSS
Conditions
Z = R + jωL
VEXTAL = 0 V
VXTAL = 0 V
Tester ALC INACTIVE
PCB GND

3.12.3 Internal oscillator (IRCOSC)

Table 30. Internal RC oscillator electrical specifications

Value
Symbol C Parameter Conditions Unit
Min Typ Max

fTarget CC D IRCOSC target frequency — — 16 — MHz

δfvar_noT CC P IRC frequency variation without TJ < 150 °C –8 — +8 %
temperature compensation
δfvar_T CC T IRC frequency variation with temperature TJ < 150 °C –1.5 — +1.5 %
compensation
δfvar_SW — T IRC frequency accuracy after software Trimming temperature –0.5 — +0.5 %
trimming accuracy(1)
tstart_noT CC T Startup time to reach within fvar_noT Factory trimming already — — 5 µs
applied
tstart_T CC T Startup time to reach within fvar_T Factory trimming already — — 120 µs
applied
δfTC CC T RCOSC temperature coefficient without 4.5 V < VDD_HV_ADV < 5.5 V –6.0 — +6.0 KHz/
temperature compensation Stable supply, temperature °C
TJ = –40 °C to 150 °C compensation disabled

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1. The typical user trim step size δfTRIM = 0.35 %.

3.13 ADC specifications

3.13.1 ADC input description

Figure 15 shows the input equivalent circuit for fast SARn channels.

Figure 15. Input equivalent circuit (Fast SARn channels)

INTERNAL CIRCUIT SCHEME

VDD
Channel
Sampling
Selection

RSW1 RAD

CP1 CP2 CS

Common mode
switch
RSW1 Channel Selection Switch Impedance
RADSampling Switch Impedance
Common mode
CP Pin Capacitance (two contributions, CP1 and CP2) resistive ladder
CS Sampling Capacitance
RCMSWCommon mode switch
RCMLCommon mode resistive ladder
This figure can be used as approximation circuitry for external filtering definition.

Figure 16 shows the input equivalent circuit for SARB channels.

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Figure 16. Input equivalent circuit (SARB channels)

INTERNAL CIRCUIT SCHEME

VDD
Channel Extended
Sampling
Selection Switch

RSW1 RSW2 RAD

CP1 CP3 CP2 CS

Common mode
switch

Common mode
RSW: Channel Selection Switch Impedance (two contributions RSW1 and RSW2)
resistive ladder
RAD: Sampling Switch Impedance
CP: Pin Capacitance (three contributions, CP1, CP2 and CP3)
CS: Sampling Capacitance
RCMSW: Common mode switch
RCML: Common mode resistive ladder

The above figure can be used as approximation circuitry for external filtering definition.

Table 31. ADC pin specification(1)

Value
Symbol C Parameter Conditions Unit
Min Max

ILK_INUD CC C Input leakage current, two ADC TJ < 40 °C, no current — 70 nA

channels input with weak pull-up and injection on adjacent pin
weak pull-down
C TJ < 150 °C, no current — 220
injection on adjacent pin
ILK_INUSD CC C Input leakage current, two ADC TJ < 40 °C, no current — 80 nA
channels input with weak pull-up and injection on adjacent pin
strong pull-down
C TJ < 150 °C, no current — 250
injection on adjacent pin
ILK_INREF CC C Input leakage current, two ADC TJ < 40 °C, no current — 160 nA
channels input with weak pull-up and injection on adjacent pin
weak pull-down and alternate reference
C TJ < 150 °C, no current — 400
injection on adjacent pin
ILK_INOUT CC C Input leakage current, two ADC TJ < 40 °C, no current — 140 nA
channels input, GPIO output buffer with injection on adjacent pin
weak pull-up and weak pull-down
C TJ < 150 °C, no current — 380
injection on adjacent pin
IINJ CC T Injection current on analog input Applies to any analog –3 3 mA
preserving functionality pins
CHV_ADC SR D VDD_HV_ADV external capacitance(2) — 1 2.2 µF

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Table 31. ADC pin specification(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Max

CP1 CC D Pad capacitance — 0 10 pF

CP2 CC D Internal routing capacitance SARn channels 0 0.5 pF
D SARB channels 0 1
CP3 CC D Internal routing capacitance Only for SARB channels 0 1 pF
CS CC D SAR ADC sampling capacitance — 6 8.5 pF
RSWn CC D Analog switches resistance SARn channels 0 1.1 kΩ
D SARB channels 0 1.7
RAD CC D ADC input analog switches resistance — 0 0.6 kΩ
RCMSW CC D Common mode switch resistance — 0 2.6 kΩ
RCMRL CC D Common mode resistive ladder — 0 3.5 kΩ
RSAFEPD(3) CC D Discharge resistance for AN7/AN35 — 0 300 Ω
channels (strong pull-down for safety)
ΣIADV CC P ADC pin supply All SAR and S/D ADC — 31 mA
consumption associated to the pin are
enabled

T Static consumption — 1
(Power-down mode)

1. All specifications in this table valid for the full input voltage range for the analog inputs.
2. For noise filtering, add a high frequency bypass capacitance of 0.1 µF between VDD_HV_ADV and VSS_HV_ADV.
3. Safety pull-down is available for port pin PB[5] and PE[14]. It enables discharge of up to 100 nF from 5 V every
300 ms.

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3.13.2 SAR ADC electrical specification

Table 32. ADC pin specification(1)
Value
Symbol C Parameter Conditions Unit
Min Max

ILK_INUD CC C Input leakage current, two ADC channels Tj < 40 °C, no current — 70 nA
input with weak pull-up and weak pull- injection on adjacent pin
down
C Tj < 150 °C, no current — 220
injection on adjacent pin
ILK_INUSD CC C Input leakage current, two ADC channels Tj < 40 °C, no current — 80 nA
input with weak pull-up and strong pull- injection on adjacent pin
down
C Tj < 150 °C, no current — 250
injection on adjacent pin
ILK_INREF CC C Input leakage current, two ADC channels Tj < 40 °C, no current — 160 nA
input with weak pull-up and weak pull- injection on adjacent pin
down and alternate reference
C Tj < 150 °C, no current — 400
injection on adjacent pin
ILK_INOUT CC C Input leakage current, two ADC channels Tj < 40 °C, no current — 140 nA
input, GPIO output buffer with weak pull- injection on adjacent pin
up and weak pull-down
C Tj < 150 °C, no current — 380
injection on adjacent pin
IINJ CC T Injection current on analog input Applies to any analog –3 3 mA
preserving functionality pins
CHV_ADC SR D VDD_HV_ADV external capacitance(2) 1 2.2 µF
CP1 CC D Pad capacitance — 0 10 pF
CP2 CC D Internal routing capacitance SARn channels 0 0.5 pF
D SARB channels 0 1
CP3 CC D Internal routing capacitance Only for SARB channels 0 1 pF
CS CC D SAR ADC sampling capacitance — 6 8.5 pF

RSWn CC D Analog switches resistance SARn channels 0 1.1 kΩ

D SARB channels 0 1.7
RAD CC D ADC input analog switches resistance — 0 0.6 kΩ
RCMSW CC D Common mode switch resistance — 0 2.6 kΩ
RCMRL CC D Common mode resistive ladder — 0 3.5 kΩ
(3)
RSAFEPD CC D Discharge resistance for AN7/AN35 — 0 300 W
channels (strong pull-down for safety)
ΣIADV CC P ADC pin supply All SAR and S/D ADC — 31 mA
consumption associated to the pin are
enabled

T Static consumption — 1
(Power-down mode)

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1. All specifications in this table valid for the full input voltage range for the analog inputs.
2. For noise filtering, add a high frequency bypass capacitance of 0.1 µF between VDD_HV_ADV and VSS_HV_ADV.
3. Safety pull-down is available for port pin PB[5] and PE[14]. It enables discharge of up to 100 nF from 5 V every 300 ms.

The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters
with full capacitive DAC. The SARn architecture allows input channel multiplexing.

Table 33. SARn ADC electrical specification(1)

Value
Symbol C Parameter Conditions Unit
Min Max

VALTREF SR C ADC alternate VALTREF < VDD_HV_IO_MAIN 4.5 5.5 V

reference voltage VALTREF < VDD_HV_ADV
C 4.0 5.9
P Extended range with reduce 2.0 5.9
TUE
VALTREF < VDD_HV_IO_MAIN
VALTREF < VDD_HV_ADV
VIN SR D ADC input signal 0 < VIN < VDD_HV_IO_MAIN VSS_HV_ADR VDD_HV_ADR V
fADCK SR P Clock frequency TJ < 150 °C 7.5 14.6 MHz
tADCPRECH SR T ADC precharge time Fast SAR—fast precharge 135 — ns
Fast SAR—full precharge 270 —
Slow SAR (SARADC_B)— 270 —
fast precharge
Slow SAR (SARADC_B)— 540 —
full precharge
ΔVPRECH SR D ADC Precharge voltage Full precharge –0.25 0.25 V
VPRECH = VDD_HV_ADR/2
TJ < 150 °C
D Fast precharge –0.5 0.5 V
VPRECH = VDD_HV_ADR/2
TJ < 150 °C
ΔVINTREF CC P Internal reference Applies to all internal −0.20 0.20 V
voltage precision reference points
(VSS_HV_ADR,
1/3 * VDD_HV_ADR,
2/3 * VDD_HV_ADR,
VDD_HV_ADR)
tADCSAMPLE SR P ADC sample time(2) Fast SAR – 12-bit 0.750 — µs
configuration
D Fast SAR – 10-bit 0.555 —
configuration
P Slow SAR (SARADC_B) – 1.500 —
12-bit configuration
D Slow SAR (SARADC_B) – 0.833 —
10-bit configuration

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Table 33. SARn ADC electrical specification(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Max

tADCEVAL SR P ADC evaluation time 12-bit configuration (25 clock 1.712 — µs

cycles)
D 10-bit configuration (21 clock 1.458 —
cycles)
IADCSAR_RE CC T ADC high reference Dynamic consumption — 3.5(6) µA
(3),(4)
FH current (tconv = 5 µs(5))
Dynamic consumption — 7
(tconv = 2.5 µs6)
Static consumption (Power — 4
Down mode)
Bias Current(7) — +2
IADCSAR_RE CC D ADC low reference Run mode tconv ≥ 5 µs — 15 µA
(4)
FL current VDD_HV_ADR <= 5.5 V
Run mode tconv = 2.5 µs — 30
VDD_HV_ADR <= 5.5 V
Power Down mode — 1
VDD_HV_ADR <= 5.5 V
IADV_S CC T VDD_HV_ADV power Dynamic consumption — 4.0 mA
supply current (each (tconv = 5 µs)
ADC)
Dynamic consumption — 4.0
(tconv = 2.5 µs)
TUE12 CC T(8) Total unadjusted error TJ < 150 °C, –4 4 LSB
in 12-bit configuration(9) VDD_HV_ADV > 4 V, (12b)
VDD_HV_ADR > 4 V
P TJ < 150 °C, –6 6
VDD_HV_ADV > 4 V,
VDD_HV_ADR > 4 V
T TJ < 150 °C, –6 6
VDD_HV_ADV > 4 V,
4 V > VDD_HV_ADR > 2 V
T TJ < 150 °C, –12 12
4 V > VDD_HV_ADV > 3.5 V
TUE10 CC C Total unadjusted error TJ < 150 °C, –1.5 1.5 LSB
in 10-bit configuration VDD_HV_ADV > 4 V (10b)
VDD_HV_ADR > 4 V
C TJ < 150 °C, –2.0 2.0
VDD_HV_ADV > 4 V,
4 V > VDD_HV_ADR > 2 V

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Table 33. SARn ADC electrical specification(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Max

ΔTUE12 CC D TUE degradation due to VIN < VDD_HV_ADV 0 0 LSB

VDD_HV_ADR offset with VDD_HV_ADR − VDD_HV_ADV (12b)
respect to VDD_HV_ADV ∈ [0:25 mV]
D VIN < VDD_HV_ADV –2 2
VDD_HV_ADR − VDD_HV_ADV
∈ [25:50 mV]
D VIN < VDD_HV_ADV –4 4
VDD_HV_ADR − VDD_HV_ADV
∈ [50:75 mV]
D VIN < VDD_HV_ADV –6 6
VDD_HV_ADR − VDD_HV_ADV
∈ [75:100 mV]
D VDD_HV_ADV < VIN < –2.5 2.5
VDD_HV_ADR
VDD_HV_ADR − VDD_HV_ADV
∈ [0:25 mV]
D VDD_HV_ADV< VIN < –4 4
VDD_HV_ADR
VDD_HV_ADR − VDD_HV_ADV
∈ [25:50 mV]
D VDD_HV_ADV < VIN < –7 7
VDD_HV_ADR
VDD_HV_ADR − VDD_HV_ADV
∈ [50:75 mV]
D VDD_HV_ADV < VIN < –12 12
VDD_HV_ADR
VDD_HV_ADR − VDD_HV_ADV
∈ [75:100 mV]

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Table 33. SARn ADC electrical specification(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Max

ΔTUE10 CC D TUE degradation due to VIN < VDD_HV_ADV 0 0 LSB

VDD_HV_ADR offset with VDD_HV_ADR − VDD_HV_ADV (10b)
respect to VDD_HV_ADV ∈ [0:25 mV]
D VIN < VDD_HV_ADV –0.5 0.5
VDD_HV_ADR − VDD_HV_ADV
∈ [25:50 mV]
D VIN < VDD_HV_ADV –1 1
VDD_HV_ADR − VDD_HV_ADV
∈ [50:75 mV]
D VIN < VDD_HV_ADV –1.5 1.5
VDD_HV_ADR − VDD_HV_ADV
∈ [75:100 mV]
D VDD_HV_ADV < VIN < –1 1
VDD_HV_ADR
VDD_HV_ADR − VDD_HV_ADV
∈ [0:25 mV]
D VDD_HV_ADV< VIN < –1 1
VDD_HV_ADR
VDD_HV_ADR − VDD_HV_ADV
∈ [25:50 mV]
D VDD_HV_ADV < VIN < –2 2
VDD_HV_ADR
VDD_HV_ADR − VDD_HV_ADV
∈ [50:75 mV]
D VDD_HV_ADV < VIN < –3 3
VDD_HV_ADR
VDD_HV_ADR − VDD_HV_ADV
∈ [75:100 mV]
DNL CC P Differential non-linearity VDD_HV_ADV > 4 V –1 2 LSB
VDD_HV_ADR > 4 V (12b)

ΣIADR_S CC P ADC pin reference All SAR ADC associated to — 30 µA

consumption (single the pin enabled (tconv = 5 µs)
pin)(10)
1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
2. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal
sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within
the sampling window. Please refer to Figure 15 and Figure 16 for models of the internal ADC circuit, and the values to use
in external RC sizing and calculating the sampling window duration.
3. IADCSAR_REFH and IADCSAR_REFL are independent from ADC clock frequency. It depends on conversion rate: consumption
is driven by the transfer of charge between internal capacitances during the conversion.
4. Current parameter values are for a single ADC.
5. Total consumption is given by the sum for all ADCs (associated to the reference pin) of their dynamic consumption and their
static consumption.
6. IADCSAR_REFH typical consumption 60 % of maximum value.

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7. Extra bias current is present only when BIAS is selected.

8. Extended bench validation performed on 3 samples for each process corner.
9. This parameter is guaranteed by bench validation with a small sample of typical devices, and tested in production to ± 6
LSB.
10. Consumption is given after power-up, when steady state is reached. Extra consumption up to 2 mA may be required during
internal circuitry set-up.

3.13.3 S/D ADC electrical specification

The SDn ADCs are Sigma Delta 16-bit analog-to-digital converters with 333 Ksps maximum
output rate.

Table 34. SDn ADC electrical specification(1)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

VIN SR P ADC input signal — 0 — VDD_HV_A V

DV

VIN_PK2PK(2) SR D Input range peak to Single ended VDD_HV_ADR/GAIN V

peak VINM = VSS_HV_ADR
VIN_PK2PK = VINP(3)
D Single ended ±0.5*VDD_HV_ADR
– VINM
VINM = 0.5*VDD_HV_ADR
GAIN = 1
D Single ended ±VDD_HV_ADR/GAIN
VINM = 0.5*VDD_HV_ADR
GAIN = 2,4,8,16
D Differential, ±VDD_HV_ADR/GAIN
0 < VIN < VDD_HV_IO_MAIN
fADCD_M SR P S/D modulator Input — 4 14.4 16 MHz
Clock
BWIN SR D Input bandwith SNR = 80 dB 0.01 — 50(4) KHz
fADCD_S = 150 kHz
D SNR = 74 dB 0.01 — 111(4)
fADCD_S = 333 kHz
fADCD_S SR D Output conversion — — 333 ksps
rate TJ < 150 °C
— CC D Oversampling ratio Internal modulator 24 — 256 —
External modulator — — 256 —
RESOLUTION CC D S/D register 2’s complement notation 16 bit
resolution(5)
GAIN SR D ADC gain Defined via ADC_SD[PGA] 1 — 16 —
register. Only integer powers of
2 are valid gain values.

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Table 34. SDn ADC electrical specification(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

|δGAIN| CC C Absolute value of Before calibration (applies to — — 1.5 %

the ADC gain gain setting = 1)
error(6),(7)
D After calibration, ΔVDD_HV_ADR — — 5 mV
< 5%
ΔVDD_HV_ADV < 10%
ΔTJ < 50 °C
After calibration, ΔVDD_HV_ADR — — 7.5
< 5%
ΔVDD_HV_ADV < 10%
ΔTJ < 100 °C
After calibration, ΔVDD_HV_ADR — — 10
< 5%
ΔVDD_HV_ADV < 10%
ΔTJ < 150 °C
VOFFSET CC P Input Referred Before calibration (applies to all — 10* 20 mV
Offset Error(6),(7),(8) gain settings – 1, 2, 4, 8, 16) (1+1/gain)
D After calibration, — — 5
ΔVDD_HV_ADR < 10%
ΔTJ < 50 °C
After calibration, ΔVDD_HV_ADV 7.5
< 10%
ΔTJ < 100 °C
After calibration, ΔVDD_HV_ADV 0.5 10
< 10%
ΔTJ < 150 °C

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Table 34. SDn ADC electrical specification(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

SNRDIFF150(9) CC T Signal to noise ratio 4.5 < VDD_HV_ADV < 5.5(10),(11) 80 — — dBFS
in differential mode VDD_HV_ADR = VDD_HV_ADV
150 ksps output GAIN = 1
rate TJ < 150 °C
T 4.5 < VDD_HV_ADV < 5.5(10),(11) 77 — —
,

VDD_HV_ADR = VDD_HV_ADV
GAIN = 2
TJ < 150 °C
T 4.5 < VDD_HV_ADV < 5.5(10),(11) 74 — —
,

VDD_HV_ADR = VDD_HV_ADV
GAIN = 4
TJ < 150 °C
T 4.5 < VDD_HV_ADV < 5.5(10),(11) 71 — —
VDD_HV_ADR = VDD_HV_ADV
GAIN = 8
TJ < 150 °C
D 4.5 < VDD_HV_ADV < 5.5(10),(11) 68 — —
VDD_HV_ADR = VDD_HV_ADV
GAIN = 16
TJ < 150 °C
SNRDIFF333 CC P Signal to noise ratio 4.5 < VDD_HV_ADV < 5.5(10),(11) 74 — — dBFS
(12) in differential mode VDD_HV_ADR = VDD_HV_ADV
333 ksps output GAIN = 1
rate TJ < 150 °C
T 4.5 < VDD_HV_ADV < 5.5(10),(11) 71 — —
VDD_HV_ADR = VDD_HV_ADV
GAIN = 2
TJ < 150 °C
T 4.5 < VDD_HV_ADV < 5.5(10),(11) 68 — —
VDD_HV_ADR = VDD_HV_ADV
GAIN = 4
TJ < 150 °C
T 4.5 < VDD_HV_ADV < 5.5(10),(11) 65 — —
VDD_HV_ADR = VDD_HV_ADV
GAIN = 8
TJ < 150 °C
D 4.5 < VDD_HV_ADV < 5.5(10),(11) 62 — —
VDD_HV_ADR = VDD_HV_ADV
GAIN = 16
TJ < 150 °C

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Table 34. SDn ADC electrical specification(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

SNRSE150(16) CC T Signal to noise ratio 4.5 < VDD_HV_ADV < 5.5(10),(11) 74 — — dBFS
in single ended VDD_HV_ADR = VDD_HV_ADV
mode 150 ksps GAIN = 1
output rate TJ < 150 °C
T 4.5 < VDD_HV_ADV < 5.5(10),(11) 71 — —
VDD_HV_ADR = VDD_HV_ADV
GAIN = 2
TJ < 150 °C
4.5 < VDD_HV_ADV < 5.5(10),(11) 68 — —
VDD_HV_ADR = VDD_HV_ADV
GAIN = 4
TJ < 150 °C
4.5 < VDD_HV_ADV < 5.5(10),(11) 65 — —
VDD_HV_ADR = VDD_HV_ADV
GAIN = 8
TJ < 150 °C
D 4.5 < VDD_HV_ADV < 5.5(10),(11), 62 — —
VDD_HV_ADR=VDD_HV_ADV
GAIN = 16
TJ < 150 °C

SFDR CC P Spurious free GAIN = 1 60 — — dBc

dynamic range
C GAIN = 2 60 — —
C GAIN = 4 60 — —
C GAIN = 8 60 — —
D GAIN = 16 60 — —
ZIN CC D Input impedance(13) GAIN = 1, 1.2 1.6 1.9 MΩ
fADCD_M = 16 MHz
GAIN = 16, 0.1 — —
fADCD_M = 16 MHz
CC D Differential Input GAIN = 1 1000 1250 1500 kΩ
impedance
GAIN = 2 600 800 1000
ZDIFF(14) GAIN = 4 300 400 500
GAIN = 8 200 250 300
GAIN = 16 200 250 300
CC D Common Mode GAIN = 1 1400 1800 2200 kΩ
Input impedance
GAIN = 2 1000 1300 1600
ZCM (15) GAIN = 4 700 950 1150
GAIN = 8 500 650 800
GAIN = 16 500 650 800

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Table 34. SDn ADC electrical specification(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

RBIAS CC D bias resistance — 110 144 180 kΩ

ΔVINTCM CC D Common mode — –12 12 %
input reference
voltage
VBIAS CC D Bias voltage — — VDD_HV_ — V
ADR/2

δVBIAS CC D Bias voltage — –2.5 — +2.5 %

accuracy
CMRR SR D Common mode — 54 — — dB
rejection ratio
RCaaf SR D Anti-aliasing filter External series resistance — — 20 kΩ
CC D Filter capacitances 180 — — pF
(16)
fPASSBAND CC D Pass band — 0.01 — 0.333 * KHz
fADCD_S
δRIPPLE CC D Pass band ripple(17) 0.333 * fADCD_S –1 — 1 %
Frolloff CC D Stop band [0.5 * fADCD_S, 1.0 * fADCD_S] 40 — — dB
attenuation
[1.0 * fADCD_S, 1.5 * fADCD_S] 45 — —
[1.5 * fADCD_S, 2.0 * fADCD_S] 50 — —
[2.0 * fADCD_S, 2.5 * fADCD_S] 55 — —
[2.5 * fADCD_S, fADCD_M/2] 60 — —

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Table 34. SDn ADC electrical specification(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

δGROUP CC D Group delay Within pass band – Tclk is — — — —

fADCD_M / 2
OSR = 24 — — 238.5 Tclk
OSR = 28 — — 278
OSR = 32 — — 317.5
OSR = 36 — — 357
OSR = 40 — — 396.5
OSR = 44 — — 436
OSR = 48 — — 475.5
OSR = 56 — — 554.5
OSR = 64 — — 633.5
OSR = 72 — — 712.5
OSR = 75 — — 699
OSR = 80 — — 791.5
OSR = 88 — — 870.5
OSR = 96 — — 949.5
OSR = 112 — — 1107.5
OSR = 128 — — 1265.5
OSR = 144 — — 1423.5
OSR = 160 — — 1581.5
OSR = 176 — — 1739.5
OSR = 192 — — 1897.5
OSR = 224 — — 2213.5
OSR = 256 — — 2529.5
Distortion within pass band –0.5/ — +0.5/ —
fADC fADCD_S
D_S

fHIGH CC D High pass filter 3dB Enabled — 10e-5* — —

frequency fADCD_S
tSTARTUP CC D Start-up time from — — — 100 µs
power down state
tLATENCY CC D Latency between HPF = ON — — δGROUP + —
input data and fADCD_S
converted data
HPF = OFF — — δGROUP —
when input mux
(18)
does not change

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Table 34. SDn ADC electrical specification(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

tSETTLING CC D Settling time after Analog inputs are muxed — — 2*δGROUP —

mux change(19) HPF = ON +
3*fADCD_S
HPF = OFF — — 2*δGROUP —
+
2*fADCD_S
tODRECOVERY CC D Overdrive recovery After input comes within range — — 2*δGROUP —
time from saturation + fADCD_S
HPF = ON
HPF = OFF — — 2*δGROUP —
CS_D CC D S/D ADC sampling GAIN = 1, 2, 4, 8 — — 75*GAIN fF
capacitance after
D GAIN = 16 — — 600 fF
sampling switch(19)
IBIAS CC D Bias consumption At least 1 ADCD enabled — — 3.5 mA
IADV_D CC T VDD_HV_ADV power ADCD enabled — — 3.5 mA
supply current
P Sum of all ADCs + BIAS — — 10.5
(each ADC)
ΣIADR_D CC P Sum of all ADC ADCD enabled — — 30 µA
reference
consumption(20)
IADCS/D_REFH CC T S/D ADC Dynamic consumption — — 3.5 µA
Reference (Conversion)
High Current
T Static consumption — — +10
(Power-down mode and bias)
1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
2. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the
signal will only be ‘clipped’.
3. VINP is the input voltage applied to the positive terminal of the SDADC.
4. Maximum input of 166.67 kHz supported with reduced accuracy. See SNR specifications.
5. When using a GAIN setting of 16, the conversion result will always have a value of zero in the least significant bit. The gives
an effective resolution of 15 bits.
6. Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the device.
7. Calibration of gain is possible when gain = 1.
Offset Calibration should be done with respect to 0.5*VDD_HV_ADR for differential mode and single ended mode with
negative input=0.5*VDD_HV_ADR.
Offset Calibration should be done with respect to 0 for “single ended mode with negative input=0”.
Both offset and Gain Calibration is guaranteed for ±5% variation of VDD_HV_ADR, ±10% variation of VDD_HV_ADV, and ± 50
°C temperature variation.
8. Conversion offset error must be divided by the applied gain factor (1, 2, 4, 8, or 16) to obtain the actual input referred offset
error.
9. This parameter is guaranteed by bench validation with a small sample of devices across process variations, and tested in
production to a value of 3 dB less.
10. S/D ADC is functional in the range 3.6 V – 4.5 V, SNR parameter degrades by 3 dB. Degraded SNR value based on
simulation.

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11. S/D ADC is functional in the range 3.0 – 4.5 V, SNR parameter degrades by 9 dB. Degraded SNR value based on
simulation.
12. This parameter is guaranteed by bench validation with a small sample of devices across process variations.
13. Input impedance is valid over the full input frequency range.Input impedance is calculated in megaohms by the formula
25.6/(Gain * fADCD_M).
14. Impedance given at FADCD_M = 16MHz. Impedance is inversely proportional to frequency: ZDIFF(FADCD_M) =
16MHz/FADCD_M*ZDIFF
15. Impedance given at FADCD_M = 16MHz. Impedance is inversely proportional to frequency: ZCM(FADCD_M) =
16MHz/FADCD_M*ZCM
16. SNR values guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the
frequency range of fADCD_M – fADCD_S to fADCD_M + fADCD_S, where fADCD_M is the input sampling frequency, and fADCD_S
is the output sample frequency. A proper external input filter should be used to remove any interfering signals in this
frequency range.
17. The ±1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.087 dB.
18. Propagation of the information from the pin to the register CDR[CDATA] and flags SFR[DFEF], SFR[DFFF] is given by the
different modules that need to be crossed: delta/sigma filters, high pass filter, fifo module, clock domain synchronizers. The
time elapsed between data availability at pin and internal S/D module registers is given by the below formula:

REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)fPBRIDGEx_CLK

where fADCD_S is the frequency of the sampling clock, fADCD_M is the frequency of the modulator, and fPBRIDGEx_CLK
is the frequency of the peripheral bridge clock feeds to the ADC S/D module. The (~+1) symbol refers to the number of
clock cycles uncertainty (from 0 to 1 clock cycle) to be added due to resynchronization of the signal during clock domain
crossing.
Some further latency may be added by the target module (core, DMA, interrupt) controller to process the data received
from the ADC S/D module.
19. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before
sampling switch.
20. Consumption is given after power-up, when steady state is reached. Extra consumption up to 2 mA may be required during
internal circuitry set-up.

Figure 17. S/D impedance generic model

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Equation 1 IINP = (VINP – VINM)/2.ZDIFF + (VICM – VINT)/ZCM

= (VINP – VICM)/ZDIFF + (VICM – VINT)/ZCM

Equation 2 IINP = (VINM – VINP)/2.ZDIFF + (VICM – VINT)/ZCM

= (VINM – VICM)/ZDIFF + (VICM – VINT)/ZCM

3.14 Temperature sensor

The following table describes the temperature sensor electrical characteristics.

Table 35. Temperature sensor electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max

— CC Temperature monitoring range — –40 — 150 °C

TSENS CC T Sensitivity — — 5.18 — mV/°C
TACC CC C Accuracy TJ < 150 °C –3 — 3 °C
ITEMP_SENS CC C VDD_HV_ADV power supply — — — 700 µA
current

3.15 LVDS Fast Asynchronous Serial Transmission (LFAST) pad

electrical characteristics
The LFAST pad electrical characteristics apply to both the SIPI and high-speed debug serial
interfaces on the device. The same LVDS pad is used for the Microsecond Channel (MSC)
and DSPI LVDS interfaces, with different characteristics given in the following tables.

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3.15.1 LFAST interface timing diagrams

Figure 18. LFAST and MSC/DSPI LVDS timing definition

Signal excursions above this level NOT allowed

1743 mV

Max. common mode input at RX

1600 mV

|ΔVOD|
Max Differential Voltage = 285
mV p-p (LFAST)
400 mV p-p (MSC/DSPI)

Minimum Data Bit Time

Opening =
0.55 * T (LFAST)
0.50 * T (MSC/DSPI)

“No-Go” Area VOS = 1.2 V +/- 10%

TX common mode
|ΔVOD|
Min Differential Voltage =
100 mV p-p (LFAST)
150 mV p-p (MSC/DSPI)
VICOM

|ΔPEREYE |ΔPEREYE

Data Bit Period

T = 1 /FDATA

Min. common mode input at RX

150 mV

0V
Signal excursions below this level NOT allowed

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Figure 19. Power-down exit time

lfast_pwr_down

tPD2NM_TX

Differential TX
Data Lines pad_p/pad_n Data Valid

Figure 20. Rise/fall time

VIH
Differential TX 90%
Data Lines

10%
pad_p/pad_n VIL

tTR
tTR

3.15.2 LFAST and MSC/DSPI LVDS interface electrical characteristics

The following table contains the electrical characteristics for the LFAST interface.

Table 36. LVDS pad startup and receiver electrical characteristics(1)(2)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

STARTUP(3),(4)
tSTRT_BIAS CC T Bias current reference startup — — 0.5 4 µs
time(5)
tPD2NM_TX CC T Transmitter startup time (power — — 0.4 2.75 µs
down to normal mode)(6)

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Table 36. LVDS pad startup and receiver electrical characteristics(1)(2)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

tSM2NM_TX CC T Transmitter startup time (sleep Not applicable to the — 0.2 0.5 µs
mode to normal mode)(7) MSC/DSPI LVDS
pad
tPD2NM_RX CC T Receiver startup time (power down — — 20 40 ns
to normal mode)(8)
tPD2SM_RX CC T Receiver startup time (power down Not applicable to the — 20 50 ns
to sleep mode)(9) MSC/DSPI LVDS
pad
ILVDS_BIAS CC C LVDS bias current consumption Tx or Rx enabled — — 0.95 mA
TRANSMISSION LINE CHARACTERISTICS (PCB Track)
Z0 SR D Transmission line characteristic — 47.5 50 52.5 Ω
impedance
ZDIFF SR D Transmission line differential — 95 100 105 Ω
impedance
RECEIVER
VICOM SR T Common mode voltage — 0.15 — 1.6(11) V
(10)

|ΔVI| SR T Differential input voltage(12) — 100 — — mV

RIN CC D Terminating resistance VDD_HV_IO = 80 125 150 Ω
5.0 V ± 10%
D VDD_HV_IO = 80 115 150 Ω
3.3 V ± 10%
CIN CC D Differential input capacitance(13) — — 3.5 6.0 pF
ILVDS_RX CC C Receiver DC current consumption Enabled — — 0.5 mA
1. The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST & High-speed Debug
(HSD) LVDS pad, and the MSC/DSPI LVDS pad except where noted in the conditions.
2. All LVDS pad electrical characteristics are valid from –40 °C to 150 °C.
3. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS
control registers (LCR) of the LFAST and High-Speed Debug modules. The value of the LCR bits for the LFAST/HSD
modules don’t take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode. Startup times for
MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS in the corresponding
SIUL2 MSCR ODC field.
4. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter
electrical characteristic tables.
5. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being
enabled.
6. Total transmitter startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_TX + 2 peripheral bridge clock
periods.
7. Total transmitter startup time from sleep mode to normal mode is tSM2NM_TX + 2 peripheral bridge clock periods. Bias block
remains enabled in sleep mode.
8. Total receiver startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_RX + 2 peripheral bridge clock periods.
9. Total receiver startup time from power down to sleep mode is tPD2SM_RX + 2 peripheral bridge clock periods. Bias block
remains enabled in sleep mode.
10. Absolute min = 0.15 V – (285 mV/2) = 0 V

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11. Absolute max = 1.6 V + (285 mV/2) = 1.743 V

12. The LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to ensure proper LFAST receive timing.
13. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions.

Table 37. LFAST transmitter electrical characteristics(1)(2)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

fDATA SR D Data rate — — — 320 Mbps

VOS CC P Common mode voltage — 1.08 — 1.32 V
|VOD| CC P Differential output voltage swing — 110 171 285 mV
(terminated)(3)(4)
tTR CC T Rise/Fall time (absolute value of the — 0.26 — 1.5 ns
differential output voltage
swing)(3),(4)
CL SR D External lumped differential load VDD_HV_IO = 4.5 V — — 12.0 pF
capacitance(3)
VDD_HV_IO = 3.0 V — — 8.5
ILVDS_TX CC T Transmitter DC current consumption Enabled — — 3.2 mA
1. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance
values shown in Figure 21.
2. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from –40 °C to 150 °C.
3. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in
Figure 21.
4. Valid for maximum external load CL.

Table 38. MSC/DSPI LVDS transmitter electrical characteristics (1)(2)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Data Rate
fDATA SR D Data rate — — — 80 Mbps
VOS CC P Common mode voltage — 1.08 — 1.32 V
|VOD| CC P Differential output voltage swing — 150 214 400 mV
(terminated)(3)(4)
tTR CC T Rise/Fall time (absolute value of the — 0.8 — 4.0 ns
differential output voltage
swing)(3),(4)
CL SR D External lumped differential load VDD_HV_IO = 4.5 V — — 50 pF
capacitance(3)
VDD_HV_IO = 3.0 V — — 39
ILVDS_TX CC T Transmitter DC current consumption Enabled — — 4.0 mA
1. The MSC and DSPI LVDS pad electrical characteristics are based on the application circuit and typical worst case internal
capacitance values given in Figure 21.
2. All MSC and DSPI LVDS pad electrical characteristics are valid from –40 °C to 150 °C.

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3. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in
Figure 21.
4. Valid for maximum external load CL.

Figure 21. LVDS pad external load diagram

bond pad

GPIO Driver
CL
1pF

2.5pF

100Ω
terminator
LVDS Driver

bond pad

GPIO Driver
CL
1pF

2.5pF

Die Package PCB

3.15.3 LFAST PLL electrical characteristics

The following table contains the electrical characteristics for the LFAST PLL.

Table 39. LFAST PLL electrical characteristics(1)

Value
Symbol C Parameter Conditions Unit
Min Nominal Max

fRF_REF SR D PLL reference clock frequency — 10 — 26 MHz

ERRREF CC D PLL input reference clock frequency — –1 — 1 %
error
DCREF CC D PLL input reference clock duty cycle — 45 — 55 %

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Table 39. LFAST PLL electrical characteristics(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Nominal Max

PN CC D Integrated phase noise (single side fRF_REF = 20 MHz — — –58 dBc

band)
D fRF_REF = 10 MHz — — –64
(2)
fVCO CC D PLL VCO frequency — — 640 — MHz
(3)
tLOCK CC D PLL phase lock — — — 40 µs
ΔPERREF SR T Input reference clock jitter (peak to Single period, — — 300 ps
peak) fRF_REF = 10 MHz
T Long term, –500 — 500 ps
fRF_REF = 10 MHz
ΔPEREYE CC T Output Eye Jitter (peak to peak)(4) — — — 400 ps
1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.
2. The 640 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 26 MHz reference, the VCO
frequency is 624 MHz. PLL lock with 640 MHz VCO frequency guaranteed by production testing.
3. The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral
bridge clock that is connected to the PLL on the device.
4. Measured at the transmitter output across a 100 Ohm termination resistor on a device evaluation board. See Figure 21.

3.16 Aurora LVDS electrical characteristics

The following table describes the Aurora LVDS electrical characteristics.
Note: The Aurora interface is AC coupled, so there is no common-mode voltage specification.

Table 40. Aurora LVDS electrical characteristics(1)(2)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Transmitter
FTX CC D Transmit Data Rate — — — 1.25 Gbps
|ΔVOD_LVDS| CC P Differential output voltage swing — 400 600 800 mV
(terminated)(3)
tTR_LVDS CC T Rise/Fall time (10%–90% of swing) — 60 — — ps
RV_L_Tx SR D Differential Terminating resistance — 81 100 120 W
TLoss CC D Transmission Line Loss due to loading — — — 6(4) dB
effects
Transmission line characteristics (PCB track)
LLINE SR D Transmission line length — — — 20 cm
ZLINE SR D Transmission line characteristic — 45 50 55 W
impedance
Cac_clk SR D Clock Receive Pin External AC Values are nominal, valid 100 — 270 pF
Coupling Capacitance for +/– 50% tolerance

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Table 40. Aurora LVDS electrical characteristics(1)(2)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Cac_tx SR D Transmit Lane External AC Coupling Values are nominal, valid 250 — 2000 pF
Capacitance for +/– 50% tolerance
Receiver
FRX CC D Receive Clock Rate TJ = 150 °C — — 1.25 Gbps
|ΔVI_L| SR P Differential input voltage (peak to — 200 — 1000 mV
peak)
RV_L_Rx CC D Differential Terminating resistance — 81 100 120 W
1. All Aurora electrical characteristics are valid from –40 °C to 150 °C, except where noted.
2. All specifications valid for maximum transmit data rate FTX.
3. The minimum value of 400 mV is only valid for differential terminating resistance (RV_L) = 99 Ohm to 101 ohm. The
differential output voltage swing tracks with the value of RV_L.
4. Transmission line loss maximum value is specified for the maximum drive level of the Aurora transmit pad.

3.17 Power management: PMC, POR/LVD, sequencing

The power management module monitors the different power supplies as well as generating
the required internal supplies. The power management module is supplied by the
VDD_HV_PMC supply, with redundant voltage references and monitors guaranteeing safe
operation.

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3.17.1 Power management integration

Use the integration scheme provided below to ensure proper device function.

Figure 22. Voltage regulator capacitance connection

CDECHV CDECBV
(regulator supply decoupling) (regulator supply decoupling)

VDD_HV_PMC

VDD_BV_PMC VDD_HV_IO_MAIN VSS VDD_HV_PMC VSS

(supplied via

CDECREG4 (LV_COR)
VDD_IO_MAIN)
VREF VDD_LV

VDD_LVn
CDECREG1 (LV_COR/LV_FLA)

Voltage
Regulator VDD_LV VSS
I DEVICE

CDECREG3 (LV_COR\LV_PLL)
VSS

VSS
DEVICE

VSS
VDD_LV
VSS VDD_LV

CDECREG2
(LV_COR)

CREG
(LV_COR)

Note: The pins positions correspond to the pins positions in the pins package.

The internal voltage regulator requires external capacitance (CREGn) to be connected to the
device to provide a stable low voltage digital supply to the device. Placed capacitances on
the board as near as possible to the associated pins and limit the serial inductance of the
board to less than 5 nH.
Place a decoupling capacitor between each VDD_LV supply pin and VSS ground plane to
ensure stable voltage. Place the capacitor as near as possible to the VDD_LV supply pin.

3.17.2 Main voltage regulator electrical characteristics

The device implements an internal voltage regulator to generate the low voltage core supply
VDD_LV from the high voltage ballast supply VDD_BV_PMC, internally connected to
VDD_HV_IO_MAIN supply. The regulator itself is supplied by VDD_HV_PMC. Both high voltage
supplies are common with VDD_HV_IO.
Note: Refer to SPC574Kx_IO_Signal_Table.xls table for details regarding power connectivity.

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The following supplies are involved:

• HV—High voltage external power supply for voltage regulator module. This must be
provided externally through VDD_HV_PMC/VDD_HV_IO_MAIN power pin.
• BV—High voltage external power supply for internal ballast module. This must be
provided externally through VDD_HV_PMC/VDD_HV_IO_MAIN power pins.
• LV—Low voltage internal power supply for core, PLL and Flash digital logic. This is
generated by the internal voltage regulator but provided externally to allow connection
to a stability capacitor. It is further split into three main domains to ensure noise
isolation between critical LV modules:
– LV_COR—Low voltage supply for the core. It is also used to provide supply
LV_PLL through double bonding.
– LV_FLA—Low voltage supply for code flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
– LV_PLL—Low voltage supply for PLL0. It is shorted to LV_COR through double
bonding.

Table 41. Device Power Supply Integration

Value(2)
Symbol C Parameter Conditions(1) Unit
Min Typ Max

CREG SR D Internal voltage regulator stability — 1.3 2(3) — µF

external capacitance
RREG SR D Stability capacitor equivalent serial Total resistance including — — 50 mΩ
resistance board track
CDECREGn SR D Internal voltage regulator VDD_LV/VSS pair 30 100 — nF
decoupling external capacitance
RDECREGn SR D Stability capacitor equivalent serial — — — 50 mΩ
resistance
CDECBV SR D Relay capacitance for ballast — 3 4(3) — µF
power-up
CDECHV SR D Decoupling capacitance regulator VDD_HV_IO_MAIN/VSS pair 30 100 — nF
supply
VMREG CC P Main regulator output voltage Before trimming 1.14 1.28 1.4(4) V
P After trimming 1.14 1.28 1.32
IDDMREG SR P Main regulator current provided to — — — 350 mA
VDD_LV domain
IDDCLAMP CC D Main regulator rush current sinked Power-up condition 200 — 1500 mA
from VDD_HV_IO_MAIN domain
during VDD_LV external
capacitance loading
ΔIDDMREG SR T Main regulator current variation 20 µs observation –60 — 60 mA
window
IMREGINT CC D Main regulator current IMREG = 300 mA — — 3.5 mA
consumption
D IMREG = 0 mA — — 2.2

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Table 41. Device Power Supply Integration(Continued)

Value(2)
Symbol C Parameter Conditions(1) Unit
Min Typ Max

CDECFLA D Decoupling capacitance for flash VDD_HV_FLA/VSS pair 100 220 — nF

SR
supply
CHV_ADC SR D VDD_HV_ADV external 1 2.2 — µF
capacitance(5)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 / 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Recommended X7R or X5R ceramic –35 % / +20 % variation across process, temperature, voltage and after aging.
4. At power-up condition before trimming.
5. For noise filtering, add a high frequency bypass capacitance of 0.1 µF between VDD_HV_ADV and VSS_HV_ADV.

3.17.3 Device voltage monitoring

The LVD/HVDs and their associated levels for the device are given in the following table.
The figure below illustrates the workings of voltage monitoring threshold.

Figure 23. Voltage monitor threshold definition

VDD_xxx

VHVD(rise)
VHVD(fall)

VLVD(rise)
VLVD(fall)

tVDASSERT tVDRELEASE

HVD TRIGGER
(INTERNAL)

tVDRELEASE tVDASSERT

LVD TRIGGER
(INTERNAL)

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Table 42. Voltage monitor electrical characteristics(1)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

VPORUP_LV(2) CC D LV supply power on reset Rising voltage (power up) 1040 — 1180 mV
threshold[
P Falling voltage (power 960 — 1100
down)(3)
Hysteresis on power-up 50 — —
VLVD096 CC P LV internal(4) supply low voltage See note (5) 960 — 1100 mV
monitoring
VLVD108 CC P Core LV internal(4) supply low See note(6) 1080 — 1170 mV
voltage monitoring
VLVD112 CC P LV external(7) supply low voltage See note (5) 1110 — 1180 mV
monitoring
VHVD140 CC P LV external(7) supply high voltage See note (8) 1320 — 1420 mV
monitoring
VHVD145 CC P LV external(7) supply high voltage See note (8) 1390 — 1480 mV
monitoring
VPORUP_HV(2) CC P HV supply power on reset Rising voltage (power up) 2850 — 3210 mV
threshold(9) on PMC/IO Main supply
Rising voltage (power up) 2680 — 2980
on IO JTAG and Osc
supply
Rising voltage (power up) 2870 — 3182
on ADC supply
Falling voltage (power 2710 — 3000
down)(10)
Hysteresis on power 150 — —
up(11)
VPOR240 CC P HV supply power-on reset voltage Rising voltage 2420 — 2780 mV
monitoring
Falling voltage 2400 — 2760
VLVD270 CC P HV supply low voltage monitoring Rising voltage 2750 — 3000 mV
Falling voltage 2700 — 2950
VLVD295 CC P ADC supply low voltage Rising voltage — — 3120 mV
monitoring
Falling voltage 2920 — 3100
VLVD400 CC P HV supply low voltage monitoring Rising voltage 4110 — 4410 mV
Falling voltage 3970 — 4270
VHVD600 CC P HV supply high voltage Rising voltage 5560 — 5960 mV
monitoring
Falling voltage 5500 — 5900

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Table 42. Voltage monitor electrical characteristics(1)(Continued)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

tVDASSERT CC D Voltage detector threshold — 0.1 — 2 µs

crossing assertion
tVDRELEASE CC D Voltage detector threshold — 5 — 20 µs
crossing de-assertion
1. For VDD_LV levels, a maximum of 30 mV IR drop is incurred from the pin to all sinks on the die. For other LVD, the IR drop
is estimated by multiplying the supply current by 0.5 Ω.
2. VPORUP_LV and VPORUP_HV threshold are untrimmed values before completion of the power-up sequence. All other
LVD/HVD thresholds are provided after trimming.
3. Assume all of LVDs on LV supplies disabled.
4. LV internal supply levels are measured on device internal supply grid after internal voltage drop.
5. LVD is released after tVDRELEASE temporization when upper threshold is crossed, LVD is asserted tVDASSERT after detection
when lower threshold is crossed.
6. This is combination of LVD108_C, P, and F. Min is from min value of LVD108_F, and P which is the lowest one. Max is the
max value of LVD108_C which is the highest one of three.
7. LV external supply levels are measured on the die side of the package bond wire after package voltage drop.
8. HVD is released after tVDRELEASE temporization when lower threshold is crossed, HVD is asserted tVDASSERT after
detection when upper threshold is crossed. HVD140 does not cause reset.
9. This supply also needs to be below 5472 mV (untrimmed HVD600 min).
10. Untrimmed LVD300_A will be asserted first on power down.
11. Hysteresis is implemented only between the VDD_HV_IO_MAIN High voltage Supplies and the ADC high voltage supply.
When these two supplies are shorted together, the hysteresis is as is shown in Table 42. If the supplies are not shorted
(VDD_IO_MAIN and ADC high voltage supply), then there will be no hysteresis on the high voltage supplies.

3.17.4 Power up/down sequencing

The following table shows the constraints and relationships for the different power supplies.

Table 43. Device supply relation during power-up/power-down sequence

Supply 2(1)

VDD_HV_IO_JTAG/
VDD_LV VDD_HV_IO VDD_HV_ADV VDD_HV_ADR ALTREFn(2)
VDD_HV_IO_FLEX

VDD_LV

VDD_HV_IO_JTAG/
VDD_HV_IO_FLEX
Supply 1(1)

VDD_HV_IO

VDD_HV_ADV

VDD_HV_ADR 5 mA

ALTREFn 10 mA(3) 10 mA(3)

1. Red cells: Supply 1 (row) can exceed Supply 2 (column), granted that external circuitry ensures current flowing from
supply1 is less than absolute maximum rating current value provided.
2. ALTREFn are the alternate references for the ADC that can be used in place of the default reference (VDD_HV_ADR_*). They
are SARB.ALTREF and SAR2.ALTREF.

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3. ADC performance is not guaranteed when ALTREFn, and VDD_HV_ADR supplies are above VDD_HV_IO/VDD_HV_ADV.

During power-up, all functional terminals are maintained in a known state as described in the
following table.

Table 44. Functional terminals state during power-up and reset

TERMINAL POWER-UP(2) RESET DEFAULT Comments
type(1) pad state pad state pad state
(3)

PORST Strong pull- Weak pull-down Weak pull-down Power-on reset pad
down(4)
ESR0(5) Strong pull-down Strong pull-down Weak pull-up Functional reset pad
ESR1 Weak pull-up Weak pull-up Weak pull-up —
(6) (6)
TEST_MODE Weak pull-down Weak pull-down Weak pull-down —
(4)
GPIO Weak pull-up Weak pull-up Weak pull-up —

ANALOG High impedance High impedance High impedance —

ERROR[0] High impedance High impedance High impedance During functional reset, pad state
can be overridden by FCCU
TRST High impedance Weak pull-down Weak pull-down —

TCK High impedance Weak pull-down Weak pull-down —

TMS Weak pull-up Weak pull-up Weak pull-up —
TDI Weak pull-up Weak pull-up Weak pull-up —
TDO High impedance High impedance High impedance —
1. Refer to pinout information for terminal type.
2. POWER-UP state is guaranteed from VDD_HV_IO > VDD_POR and maintained until supply crosses the power-on reset
thresholds VPORUP_LV for LV supply and VPORUP_HV for high voltage supply.
3. Before software configuration.
4. Pull-down and pull-up strengths are provided in Table 19 (I/O pull-up/pull-down DC electrical characteristics)
5. Unlike ESR0, ESR1 is provided as a normal GPIO and implements weak pull-up during power-up.
6. An internal pull-down is implemented on the TESTMODE pin to prevent the device from entering test mode if the package
TESTMODE pin is not connected. It is recommended to connect the TESTMODE pin to VSS_HV_IO on the board for
maximum robustness, but not required. The value of TESTMODE is latched at the negation of reset and has no affect
afterward. The device will not exit functional reset with the TESTMODE pin asserted during power-up. The TESTMODE pin
can be connected externally directly to ground without any other components.

3.18 Flash memory electrical characteristics

Table 45 shows the estimated Program/Erase characteristics.

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Table 45. Flash memory program and erase specifications (1)

Value

Lifetime
Initial max
max(5)
Symbol Characteristics(2) Typical Unit
Typ(3) C end of C
All
life(4) < 1 k < 250 K
25 °C(6) temp C
(7) cycles cycles

tdwprogram Double Word (64 bits) program 34 C 100 — — 55 500 C µs

time [Packaged part]
tpprogram Page (256 bits) program time 60 C 200 — — 108 1000 C µs
tpprogrameep Page (256 bits) program time 69 C 220 — — 124 1000 C µs
EEPROM (partition 2) [Packaged
part]
tqprogram Quad Page (1024 bits) program 204 C 1040 1200 P 850 2000 C µs
time
tqprogrameep Quad Page (1024 bits) program 234 C 1140 1320 P 978 2000 C µs
time EEPROM (partition 2)
[Packaged part]
t16kpperase 16 KB block pre-program and 150 C 1000 1000 P 330 5000 — C ms
erase time
t32kpperase 32 KB block pre-program and 200 C 1000 1000 P 440 5000 — C ms
erase time
t64kpperase 64 KB block pre-program and 300 C 1000 1000 P 660 5000 — C ms
erase time
t256kpperase 256 KB block pre-program and 900 C 2000 3000 P 1100 15000 — C ms
erase time
t16kprogram 16 KB block program time 27 C 45 50 P 40 1000 — C ms
t32kprogram 32 KB block program time 54 C 90 100 P 80 2000 — C ms
t64kprogram 64 KB block program time 108 C 175 200 P 169 4000 — C ms
t256kprogram 256 KB block program time 432 C 700 850 P 634 17000 — C ms
t16kprogrameep Program 16 KB EEPROM 31 C 52 58 P 64 1000 C ms
(partition 2) [Packaged part]
t16keraseeep Erase 16 KB EEPROM (partition 160 C 1000 1000 P 500 5000 C ms
2) [Packaged part]
ttr Program rate(8) 1.73 C 2.24 3.40 C 1.9 — C s/MB
tpr Erase rate(8) 4.0 C 8.0 12.0 C 4.4 — C s/MB
tffprogram Full flash programming time(9) 5 C 20 30 P 5.8 32 — C s
tfferase Full flash erasing time(9) 13 C 26 30 P 14.2 40 — C s
tESRT Erase suspend request rate(10) 5.5 T — — — — — — ms
tPSRT Program suspend request rate(10) 20 T — — — — — — µs
(11)
tPSUS Program suspend latency — — — — — — 10 T µs

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Table 45. Flash memory program and erase specifications (1)(Continued)

Value

Lifetime
Initial max
(2) max(5)
Symbol Characteristics Typical Unit
Typ(3) C end of C
All
life(4) < 1 k < 250 K
25 °C(6) temp C
(7) cycles cycles

tESUS Erase suspend latency(11) — — — — — — 20 T µs

tAIC0S Array Integrity Check (2.5 MB, 25 T — — — — — — — ms
sequential)(12)
Array Integrity Check (256 KB, 2.5 T — — — — — — — ms
tAIC256KS
sequential)(12)
tAIC0P Array Integrity Check (2.5 MB, 2.5 T — — — — — — — s
proprietary)(12)
tMR0S Margin Read (2.5 MB, 125 T — — — — — — — ms
sequential)(12)
Margin Read (256 KB, 12.5 T — — — — — — — ms
tMR256KS
sequential)(12)
1. Characteristics are valid both for Data Flash and Code Flash, unless specified in the characteristics column.
2. Actual hardware programming times; this does not include software overhead.
3. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
4. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but
not tested.
5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified
number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.
6. Initial factory condition: < 100 program/erase cycles, 20 °C < TJ < 30 °C junction temperature, and nominal (± 2%) supply
voltages. These values are verified at production testing.
7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for
less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature, and nominal (± 2%) supply
voltages. These values are verified at production testing.
8. Rate computed based on 256 K sectors.
9. Only code sectors, not including EEPROM.
10. Time between suspend resume and next suspend. Value stated actually represents minimum value specification.
11. Timings guaranteed by design.
12. AIC is done using system clock, thus all timing is dependant on system frequency and number of wait states. Timing in the
table is calculated at max frequency.

Table 46. Flash memory Life Specification

Value
Symbol Characteristics(1) Unit
Min C Typ C

NCER16K 16 KB CODE Flash endurance 10 — 100 — kcycles

NCER32K 32 KB CODE Flash endurance 10 — 100 — kcycles
NCER64K 64 KB CODE Flash endurance 10 — 100 — kcycles

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Table 46. Flash memory Life Specification(Continued)

Value
Symbol Characteristics(1) Unit
Min C Typ C

NCER256K 256 KB CODE Flash endurance 1 — 100 — kcycles

NDER16K 16 KB EEPROM Flash endurance 250 — — — kcycles
Minimum data retention Blocks with 0 - 1,000 P/E 20 — — — Years
tDR1k
cycles
tDR10k Minimum data retention Blocks with 1,001 - 10,000 P/E 20 — — — Years
cycles
tDR250k Minimum data retention Blocks with 10,001 - 250,000 P/E 10 — — — Years
cycles
1. Program and erase cycles supported across specified temperature specs.

3.18.1 Flash read wait state and address pipeline control settings
Table 47 describes the recommended RWSC settings at various operating frequencies
based on specified intrinsic flash access times of the Flash array at 150 °C.

Table 47. Flash memory RWSC configuration

Minimum RWSC
Platform Frequency
settings

0 – 25 MHz 0
25 – 50 MHz 1
50 – 80 MHz 2
80 – 110 MHz 3
110 – 140 MHz 4
140 – 160 MHz 5

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3.19 AC specifications

3.19.1 Debug and calibration interface timing

3.19.1.1 JTAG interface timing

Table 48. JTAG pin AC electrical characteristics(1)(2)

Value
# Symbol C Characteristic Unit
Min Max

1 tJCYC CC D TCK cycle time 100 — ns

2 tJDC CC T TCK clock pulse width 40 60 %
3 tTCKRISE CC D TCK rise and fall times (40%–70%) — 3 ns
4 tTMSS, tTDIS CC D TMS, TDI data setup time 5 — ns
5 tTMSH, tTDIH CC D TMS, TDI data hold time 5 — ns
6 tTDOV CC D TCK low to TDO data valid — 15(3) ns
7 tTDOI CC D TCK low to TDO data invalid 0 — ns
8 tTDOHZ CC D TCK low to TDO high impedance — 15 ns
9 tJCMPPW CC D JCOMP assertion time 100 — ns
10 tJCMPS CC D JCOMP setup time to TCK low 40 — ns
11 tBSDV CC D TCK falling edge to output valid — 600(4) ns
12 tBSDVZ CC D TCK falling edge to output valid out of high — 600 ns
impedance
13 tBSDHZ CC D TCK falling edge to output high impedance — 600 ns
14 tBSDST CC D Boundary scan input valid to TCK rising edge 15 — ns
15 tBSDHT CC D TCK rising edge to boundary scan input invalid 15 — ns
1. These specifications apply to JTAG boundary scan only. See Table 49 for functional specifications.
2. JTAG timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O
section of the data sheet.
3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

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Figure 24. JTAG test clock input timing

TCK

2
3 2

1 3

Figure 25. JTAG test access port timing

TCK

TMS, TDI

7 8

TDO

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Figure 26. JTAG JCOMP timing

TCK

10
JCOMP

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Figure 27. JTAG boundary scan timing

TCK

11 13

Output
Signals

12

Output
Signals

14
15

Input
Signals

3.19.1.2 Nexus interface timing

Table 49. Nexus debug port timing(1)

Value
# Symbol C Characteristic Unit
Min Max

7 tEVTIPW CC P EVTI pulse width 4 — tCYC(2)

8 tEVTOPW CC P EVTO pulse width 40 — ns
9 tTCYC CC D TCK cycle time 2(3), — tCYC(2)
(4)

9 tTCYC CC D Absolute minimum TCK cycle time(5) (TDO sampled on posedge 40(6) — ns
of TCK)
11(7) tNTDIS CC D TDI/TDIC data setup time 5 — ns
12 tNTDIH CC D TDI/TDIC data hold time 5 — ns

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Table 49. Nexus debug port timing(1)(Continued)

Value
# Symbol C Characteristic Unit
Min Max

13(8) tNTMSS CC D TMS/TMSC data setup time 5 — ns

14 tNTMSH CC D TMS/TMSC data hold time 5 — ns
(9) (10)
15 — CC D TDO/TDOC propagation delay from falling edge of TCK — 16 ns
16 — CC D TDO/TDOC hold time with respect to TCK falling edge (minimum 2.25 — ns
TDO/TDOC propagation delay)
1. Nexus timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O
section of the data sheet.
2. tCYC is system clock period.
3. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less
than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency
being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number
greater than or equal to that specified here.
4. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute
minimum TCK period specification.
5. This timing applies to TDI/TDIC, TDO/TDOC, TMS/TMSC pins; however, actual frequency is limited by pad type for
EXTEST instructions. Refer to pad specification for allowed transition frequency.
6. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the
design (system frequency / 4) depending on the actual system frequency being used.
7. TDIC represents the TDI bit frame of the scan packet in compact JTAG 2-wire mode.
8. TMSC represents the TMS bit frame of the scan packet in compact JTAG 2-wire mode.
9. TDOC represents the TDO bit frame of the scan packet in compact JTAG 2-wire mode.
10. Timing includes TCK pad delay, clock tree delay, logic delay and TDO/TDOC output pad delay.

Figure 28. Nexus event trigger and test clock timings

TCK
EVTI
EVTO 9

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Figure 29. Nexus TDI/TDIC, TMS/TMSC, TDO/TDOC timing

TCK

11

13
12

14

TMS/TMSC,
TDI/TDIC

15

16

TDO/TDOC

3.19.1.3 Aurora LVDS interface timing

Table 50. Aurora LVDS interface timing specifications

Value
Symbol C Parameter Unit
Min Typ Max

Data Rate
— SR T Data rate — — 1250 Mbps
STARTUP
tSTRT_BIAS CC T Bias startup time(1) — — 5 µs
tSTRT_TX CC T Transmitter startup time(2) — — 5 µs
tSTRT_RX CC T Receiver startup time(3) — — 4 µs
1. Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down (power
down) has been deasserted. LVDS functionality is guaranteed only after the startup time.
2. Startup time is defined as the time taken by LVDS transmitter for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is
guaranteed only after the startup time.

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3. Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is
guaranteed only after the startup time.

3.19.1.4 Aurora debug port timing

Table 51. Aurora debug port timing

Value
# Symbol C Characteristic Unit
Min Max

1 tREFCLK CC T Reference clock frequency 625 1250 MHz

1a tMCYC CC T Reference clock rise/fall time — 400 ps
2 tRCDC CC D Reference clock duty cycle 45 55 %
3 JRC CC D Reference clock jitter — 40 ps
4 tSTABILITY CC D Reference clock stability 50 — PPM
5 BER CC D Bit error rate — 10–12 —
6 JD SR D Transmit lane deterministic jitter — 0.17 OUI
7 JT SR D Transmit lane total jitter — 0.35 OUI
8 SO CC T Differential output skew — 20 ps
9 SMO CC T Lane to lane output skew — 1000 ps
(1)
10 OUI CC D Aurora lane unit interval 625 Mbps 1600 1600 ps
D 1.25 Gbps 800 800
1. ± 100 PPM

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Figure 30. Aurora timings

2
2
CLOCKREF -

Zero Crossover

CLOCKREF +
1a 1a 1a 1a

8 8 8
Tx Data -

Ideal Zero Crossover

Tx Data +

Tx Data [n]
Zero Crossover

Tx Data [n+1]
Zero Crossover

Tx Data [m]
Zero Crossover

9 9

3.19.2 DSPI timing with CMOS and LVDS(a) pads

DSPI channel frequency support is shown in Table 52. Timing specifications are shown in
Table 53, Table 54, Table 55, Table 56 and Table 57.

Table 52. DSPI channel frequency support

Max usable
DSPI use mode
frequency (MHz)(1),(2)

CMOS (Master mode) Full duplex – Classic timing (Table 53) 17

Full duplex – Modified timing (Table 54) 30
Output only mode (SCK/SOUT/PCS) (Table 53 and Table 54) 30
Output only mode TSB mode (SCK/SOUT/PCS) (Table 57) 30

a. DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel bus protocol.

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Table 52. DSPI channel frequency support(Continued)

Max usable
DSPI use mode
frequency (MHz)(1),(2)

LVDS (Master mode) Full duplex – Modified timing (Table 55) 33

Output only mode TSB mode (SCK/SOUT/PCS) (Table 56) 40
CMOS Slave mode Full duplex (Table 58) 16
1. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.
2. Maximum usable frequency does not take into account external device propagation delay.

3.19.2.1 DSPI master mode full duplex timing with CMOS and LVDS pads

3.19.2.1.1 DSPI CMOS Master Mode – Classic Timing

Table 53. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or
1(1)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

1 tSCK CC D SCK cycle time SCK drive strength

Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 —
Medium 50 pF 200.0 —
2 tCSC CC D PCS to SCK delay SCK and PCS drive strength
Very strong 25 pF (N(4) × tSYS(5)) – — ns
16
Strong 50 pF (N(4) × tSYS(5)) – —
16
Medium 50 pF (N(4) × tSYS(5)) – —
16
PCS medium PCS = 50 pF (N(4) × tSYS(5)) – —
and SCK strong SCK = 50 pF 29
3 tASC CC D After SCK delay SCK and PCS drive strength
Very strong PCS = 0 pF (M(6) × tSYS(5)) – — ns
SCK = 50 pF 35
Strong PCS = 0 pF (M(6) × tSYS(5)) – —
SCK = 50 pF 35
Medium PCS = 0 pF (M(6) × tSYS(5)) – —
SCK = 50 pF 35
PCS medium PCS = 0 pF (M(6) × tSYS(5)) – —
and SCK strong SCK = 50 pF 35

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Table 53. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or
1(1)(Continued)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

4 tSDC CC D SCK duty cycle(7) SCK drive strength

1 1
Very strong 0 pF /2tSCK – 2 /2tSCK + 2 ns
1 1
Strong 0 pF /2tSCK – 2 /2tSCK + 2
1 1
Medium 0 pF /2tSCK – 5 /2tSCK + 5
PCS strobe timing
5 tPCSC CC D PCSx to PCSS PCS and PCSS drive strength
time(8)
Strong 25 pF 16.0 — ns
6 tPASC CC D PCSS to PCSx PCS and PCSS drive strength
time(8)
Strong 25 pF 16.0 — ns
SIN setup time
7 tSUI CC D SIN setup time to SCK drive strength
SCK(9)
Very strong 25 pF 25.0 — ns
Strong 50 pF 31.0 —
Medium 50 pF 52.0 —
SIN hold time
8 tHI CC D SIN hold time from SCK drive strength
SCK(9)
Very strong 0 pF –1.0 — ns
Strong 0 pF –1.0 —
Medium 0 pF –1.0 —
SOUT data valid time (after SCK edge)
9 tSUO CC D SOUT data valid SOUT and SCK drive strength
time from SCK(10)
Very strong 25 pF — 7.0 ns
Strong 50 pF — 8.0
Medium 50 pF — 16.0
SOUT data hold time (after SCK edge)
10 tHO CC D SOUT data hold SOUT and SCK drive strength
time after SCK(10)
Very strong 25 pF –7.7 — ns
Strong 50 pF –11.0 —
Medium 50 pF –15.0 —
1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
2. All timing values for output signals in this table are measured to 50% of the output voltage.
3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.

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4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
5. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).
7. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
8. PCSx and PCSS using same pad configuration.
9. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.
10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

Figure 31. DSPI CMOS master mode – classic timing, CPHA = 0

tCSC tASC

PCSx

tSDC tSCK

SCK Output
(CPOL = 0)
tSDC

SCK Output
(CPOL = 1)
tSUI
tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

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Figure 32. DSPI CMOS master mode – classic timing, CPHA = 1

PCSx

SCK Output
(CPOL = 0)

SCK Output
(CPOL = 1)

tSUI tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

Figure 33. DSPI PCS strobe (PCSS) timing (master mode)

tPCSC tPASC

PCSS

PCSx

3.19.2.1.2 DSPI CMOS Master Mode – Modified Timing

Table 54. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0
or 1(1)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

1 tSCK CC D SCK cycle time SCK drive strength

Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 —
Medium 50 pF 200.0 —

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Table 54. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0
or 1(1)(Continued)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

2 tCSC CC D PCS to SCK delay SCK and PCS drive strength

Very strong 25 pF (N(4) × tSYS(5)) – — ns
16
Strong 50 pF (N(4) × tSYS(5)) – —
16
Medium 50 pF (N(4) × tSYS(5)) – —
16
PCS medium PCS = 50 pF (N(4) × tSYS(5)) – —
and SCK SCK = 50 pF 29
strong
3 tASC CC D After SCK delay SCK and PCS drive strength
Very strong PCS = 0 pF (M(6) × tSYS(5)) – — ns
SCK = 50 pF 35
Strong PCS = 0 pF (M(6) × tSYS(5)) – —
SCK = 50 pF 35
Medium PCS = 0 pF (M(6) × tSYS(5)) – —
SCK = 50 pF 35
PCS medium PCS = 0 pF (M(6) × tSYS(5)) – —
and SCK SCK = 50 pF 35
strong
4 tSDC CC D SCK duty cycle(7) SCK drive strength
1/ t 1/ t
Very strong 0 pF 2 SCK –2 2 SCK +2 ns
1/ t 1/ t
Strong 0 pF 2 SCK –2 2 SCK +2
Medium 0 pF 1/ t –5 1/ t +5
2 SCK 2 SCK

PCS strobe timing

5 tPCSC CC D PCSx to PCSS PCS and PCSS drive strength
time(8)
Strong 25 pF 16.0 — ns
6 tPASC CC D PCSS to PCSx PCS and PCSS drive strength
time(8)
Strong 25 pF 16.0 — ns
SIN setup time

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Table 54. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0
or 1(1)(Continued)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

7 tSUI CC D SIN setup time to SCK drive strength

SCK
Very strong 25 pF 25 – — ns
CPHA = 0(9)
(P(10) × tSYS(5))
Strong 50 pF 31 – —
(P(10) × tSYS(5))
Medium 50 pF 52 – —
(P(10) × tSYS(5))
SIN setup time to SCK drive strength
SCK
Very strong 25 pF 25.0 — ns
CPHA = 1(9)
Strong 50 pF 31.0 —
Medium 50 pF 52.0 —
SIN hold time
8 tHI CC D SIN hold time from SCK drive strength
SCK
Very strong 0 pF – — ns
CPHA = 0(9)
1 + (P(9) × tSYS(4)
)
Strong 0 pF – —
1 + (P(9) × tSYS(4)
)
Medium 0 pF – —
1 + (P(9) × tSYS(4)
)
SIN hold time from SCK drive strength
SCK
Very strong 0 pF –1.0 — ns
CPHA = 1(9)
Strong 0 pF –1.0 —
Medium 0 pF –1.0 —
SOUT data valid time (after SCK edge)
9 tSUO CC D SOUT data valid SOUT and SCK drive strength
time from SCK
Very strong 25 pF — 7.0 + tSYS(5) ns
CPHA = 0(10)
Strong 50 pF — 8.0 + tSYS(5)
Medium 50 pF — 16.0 + tSYS(
5)

SOUT data valid SOUT and SCK drive strength

time from SCK
Very strong 25 pF — 7.0 ns
CPHA = 1(10)
Strong 50 pF — 8.0
Medium 50 pF — 16.0

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Table 54. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0
or 1(1)(Continued)
Condition Value(2)
# Symbol C Characteristic Unit
Pad drive(3) Load (CL) Min Max

SOUT data hold time (after SCK edge)

10 tHO CC D SOUT data hold SOUT and SCK drive strength
time after SCK
Very strong 25 pF –7.7 + tSYS(5) — ns
CPHA = 0(11)
Strong 50 pF –11.0 + tSYS(5) —
Medium 50 pF –15.0 + tSYS(5) —
SOUT data hold SOUT and SCK drive strength
time after SCK
Very strong 25 pF –7.7 — ns
CPHA = 1(11)
Strong 50 pF –11.0 —
Medium 50 pF –15.0 —
1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
2. All timing values for output signals in this table are measured to 50% of the output voltage.
3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
5. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).
7. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
8. PCSx and PCSS using same pad configuration.
9. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.
10. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using
DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to
1.
11. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

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Figure 34. DSPI CMOS master mode – modified timing, CPHA = 0

tCSC tASC

PCSx

tSDC tSCK

SCK Output
(CPOL = 0)
tSDC

SCK Output
(CPOL = 1)
tSUI
tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

Figure 35. DSPI CMOS master mode – modified timing, CPHA = 1

PCSx

SCK Output
(CPOL = 0)

SCK Output
(CPOL = 1)

tSUI tHI tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

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Figure 36. DSPI PCS strobe (PCSS) timing (master mode)

tPCSC tPASC

PCSS

PCSx

3.19.2.1.3 DSPI LVDS Master Mode – Modified Timing

Table 55. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0
or 1
Condition Value(1)
# Symbol C Characteristic Unit
Pad drive Load Min Max

1 tSCK CC D SCK cycle time LVDS 15 pF 30.0 — ns

to 25 pF
differential
2 tCSC CC D PCS to SCK PCS drive strength
delay
Very strong 25 pF (N(2) × tSYS(3)) – — ns
(LVDS SCK)
10
Strong 50 pF (N(2) × tSYS(3)) – — ns
10
Medium 50 pF (N(2) × tSYS(3)) – — ns
32
3 tASC CC D After SCK delay Very strong PCS = 0 pF (M(4) × tSYS(3)) – — ns
(LVDS SCK) SCK = 25 pF 8
Strong PCS = 0 pF (M(4) × tSYS(3)) – — ns
SCK = 25 pF 8
Medium PCS = 0 pF (M(4) × tSYS(3)) – — ns
SCK = 25 pF 8
4 tSDC CC D SCK duty cycle(5) LVDS 15 pF 1/ t
2 SCK –2 1/
2tSCK +2 ns
to 25 pF
differential
7 tSUI CC D SIN setup time
SIN setup time to SCK drive strength
SCK
LVDS 15 pF 23 – — ns
CPHA = 0(6)
to 25 pF (P(7) × tSYS(3))
differential
SIN setup time to SCK drive strength
SCK
LVDS 15 pF 23 — ns
CPHA = 1(6)
to 25 pF
differential

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Table 55. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0
or 1(Continued)
Condition Value(1)
# Symbol C Characteristic Unit
Pad drive Load Min Max

8 tHI CC D SIN Hold Time

SIN hold time SCK drive strength
from SCK
LVDS 0 pF differential – — ns
CPHA = 0(6)
1 + (P(7) × tSYS(3))
SIN hold time SCK drive strength
from SCK
LVDS 0 pF differential –1 — ns
CPHA = 1(6)
9 tSUO CC D SOUT data valid time (after SCK edge)
SOUT data valid SOUT and SCK drive strength
time from SCK
LVDS 15 pF — 7.0 + tSYS(3) ns
CPHA = 0(8)
to 25 pF
differential
SOUT data valid SOUT and SCK drive strength
time from SCK
LVDS 15 pF — 7.0 ns
CPHA = 1(8)
to 25 pF
differential
10 tHO CC D SOUT data hold time (after SCK edge)
SOUT data hold SOUT and SCK drive strength
time after SCK
LVDS 15 pF –7.5 + tSYS(3) — ns
CPHA = 0(8)
to 25 pF
differential
SOUT data hold SOUT and SCK drive strength
time after SCK
LVDS 15 pF –7.5 — ns
CPHA = 1(8)
to 25 pF
differential
1. All timing values for output signals in this table are measured to 50% of the output voltage.
2. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
3. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
4. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).
5. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
6. Input timing assumes an input slew rate of 1 ns (10% – 90%) and LVDS differential voltage = ±100 mV.
7. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using
DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to
1.
8. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

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Figure 37. DSPI LVDS master mode – modified timing, CPHA = 0

tCSC tASC

PCSx

tSDC tSCK

SCK Output
(CPOL = 0)
tSDC

SCK Output
(CPOL = 1)
tSUI
tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

Figure 38. DSPI LVDS master mode – modified timing, CPHA = 1

PCSx

SCK Output
(CPOL = 0)

SCK Output
(CPOL = 1)

tSUI tHI tHI

SIN First Data Data Last Data

tSUO tHO

SOUT First Data Data Last Data

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3.19.2.1.4 DSPI Master Mode – Output Only

Table 56. DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,
CPOL = 0 or 1, continuous SCK clock(1)(2)
Condition Value
# Symbol C Characteristic Unit
Pad drive Load Min Max

1 tSCK CC D SCK cycle time LVDS 15 pF 25.0 — ns

to 50 pF
differential
2 tCSV CC D PCS valid after Very strong 25 pF — 6.0 ns
SCK(3)
Strong 50 pF — 10.5 ns
(SCK with 50 pF
differential load cap.)
3 tCSH CC D PCS hold after Very strong 0 pF –4.0 — ns
SCK(3)
Strong 0 pF –4.0 — ns
(SCK with 50 pF
differential load cap.)
1/
4 tSDC CC D SCK duty cycle LVDS 15 pF 2tSCK – 2 1/2tSCK + 2 ns
(SCK with 50 pF to 50 pF
differential load cap.) differential
SOUT data valid time (after SCK edge)
5 tSUO CC D SOUT data valid SOUT and SCK drive strength
time from SCK(4)
LVDS 15 pF — 3.5 ns
to 50 pF
differential
SOUT data hold time (after SCK edge)
6 tHO CC D SOUT data hold time SOUT and SCK drive strength
after SCK(4)
LVDS 15 pF –3.5 — ns
to 50 pF
differential
1. All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS with pad
driver strength as defined. Timing may degrade for weaker output drivers.
2. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.
3. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This
timing value is due to pad delays and signal propagation delays.
4. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

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Table 57. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,
CPOL = 0 or 1, continuous SCK clock(1)(2)
Condition Value(3)
# Symbol C Characteristic Unit
Pad drive(4) Load (CL) Min Max

1 tSCK CC D SCK cycle time SCK drive strength

Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 — ns
Medium 50 pF 200.0 — ns
(5)
2 tCSV CC D PCS valid after SCK SCK and PCS drive strength
Very strong 25 pF 7 — ns
Strong 50 pF 8 — ns
Medium 50 pF 16 — ns
PCS medium PCS = 50 pF 29 — ns
and SCK SCK = 50 pF
strong
3 tCSH CC D PCS hold after SCK(5) SCK and PCS drive strength
Very strong PCS = 0 pF –14 — ns
SCK = 50 pF
Strong PCS = 0 pF –14 — ns
SCK = 50 pF
Medium PCS = 0 pF –33 — ns
SCK = 50 pF
PCS medium PCS = 0 pF –35 — ns
and SCK SCK = 50 pF
strong
4 tSDC CC D SCK duty cycle(6) SCK drive strength
1/ t
Very strong 0 pF 2 SCK – 2 1/2tSCK + 2 ns
1
Strong 0 pF /2tSCK – 2 1/2tSCK + 2 ns
1/ t
Medium 0 pF 2 SCK – 5 1/2tSCK + 5 ns
SOUT data valid time (after SCK edge)
9 tSUO CC D SOUT data valid time SOUT and SCK drive strength
from SCK
Very strong 25 pF — 7.0 ns
CPHA = 1(7)
Strong 50 pF — 8.0 ns
Medium 50 pF — 16.0 ns
SOUT data hold time (after SCK edge)
1 tHO CC D SOUT data hold time SOUT and SCK drive strength
0 after SCK
Very strong 25 pF –7.7 — ns
CPHA = 1(7)
Strong 50 pF –11.0 — ns
Medium 50 pF –15.0 — ns
1. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

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2. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
3. All timing values for output signals in this table are measured to 50% of the output voltage.
4. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
5. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This
timing value is due to pad delays and signal propagation delays.
6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
7. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

Figure 39. DSPI LVDS and CMOS master timing – output only – modified transfer
format MTFE = 1, CHPA = 1

PCSx
tCSV
tSDC tSCK tCSH

SCK Output
(CPOL = 0)

tSUO tHO

SOUT First Data Data Last Data

3.19.2.2 Slave Mode timing

Table 58. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)(1)
Condition
# Symbol C Characteristic Min Max Unit
Pad Drive Load

1 tSCK CC D SCK Cycle Time(2) — — 62 — ns

2 tCSC SR D SS to SCK Delay(2) — — 16 — ns
3 tASC SR D SCK to SS Delay(2) — — 16 — ns
4 tSDC D SCK Duty Cycle(2) — — 30 — ns
5 tA CC D Slave Access Time(2),(3),(4) Very 25 pF — 50 ns
(SS active to SOUT driven) Strong
Strong 50 pF — 50 ns
Medium 50 pF — 60 ns
6 tDIS CC D Slave SOUT Disable Very 25 pF — 5 ns
Time(2),(3),(4) Strong
(SS inactive to SOUT High-Z
Strong 50 pF — 5 ns
or invalid)
Medium 50 pF — 10 ns

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Table 58. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)(1)(Continued)
Condition
# Symbol C Characteristic Min Max Unit
Pad Drive Load

9 tSUI CC D Data Setup Time for Inputs(2) — — 10 — ns

10 tHI (2)
CC D Data Hold Time for Inputs — — 10 — ns
(2),(3),(4)
11 tSUO CC D SOUT Valid Time Very 25 pF — 30 ns
(after SCK edge) Strong
Strong 50 pF — 30 ns
Medium 50 pF — 50 ns
12 tHO CC D SOUT Hold Time(2),(3),(4) Very 25 pF 2.5 — ns
(after SCK edge) Strong
Strong 50 pF 2.5 — ns
Medium 50 pF 2.5 — ns
1. DSPI slave operation is only supported for a single master and single slave on the device. Timing is valid for that case only.
2. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.
3. All timing values for output signals in this table, are measured to 50% of the output voltage.
4. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

Figure 40. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1)—CPHA = 0
tASC
tCSC
SS

tSCK

SCK Input tSDC

(CPOL=0)
tSDC

SCK Input
(CPOL=1)

tSUO tHO
tA tDIS

SOUT First Data Data Last Data

tSUI tHI

SIN First Data Data Last Data

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Figure 41. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1)—CPHA = 1

SS

SCK Input
(CPOL=0)

SCK Input
(CPOL=1)
tSUO
tA tDIS
tHO

SOUT First Data Data Last Data

tHI
tSUI

SIN First Data Data Last Data

3.19.3 FEC timing

The FEC provides RMII in the eLQFP176 and FusionQuad® packages. RMII signals can
be configured for either CMOS or TTL signal levels compatible with devices operating at
either 5.0 V or 3.3 V.

3.19.3.1 RMII serial management channel timing (MDIO and MDC)

The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.

Table 59. RMII serial management channel timing(1)(2)

Value(3)
Symbol C Characteristic Unit
Min Max

M10 CC D MDC falling edge to MDIO output invalid -10 — ns

(minimum propagation delay)
M11 CC D MDC falling edge to MDIO output valid (max — 25 ns
prop delay)
M12 CC D MDIO (input) to MDC rising edge setup 10 — ns
M13 CC D MDIO (input) to MDC rising edge hold 10 — ns
M14 CC D MDC pulse width high 40% 60% MDC period
M15 CC D MDC pulse width low 40% 60% MDC period
1. All timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V
(TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.
2. RMII timing is valid only up to a maximum of 150 oC junction temperature.

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3. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance
is accounted for, and need not be subtracted from the 25 pF value. Care should be taken to align external load on MDIO
and MDC.

Figure 42. RMII serial management channel timing diagram

M14 M15

MDC (output)

M10

MDIO (output)

M11

MDIO (input)

M12
M13

3.19.3.2 RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.
There is no minimum frequency requirement. The system clock frequency must be at least
equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK
frequency.

Table 60. RMII receive signal timing(1)(2)

Value
Symbol C Characteristic Unit
Min Max

R1 CC D RXD[1:0], CRS_DV to REF_CLK setup 4 — ns

R2 CC D REF_CLK to RXD[1:0], CRS_DV hold 2 — ns
R3 CC D REF_CLK pulse width high 35% 65% REF_CLK period
R4 CC D REF_CLK pulse width low 35% 65% REF_CLK period
1. All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.
2. RMII timing is valid only up to a maximum of 150 oC junction temperature.

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Figure 43. RMII receive signal timing diagram

R3

REF_CLK (input)

R4
RXD[1:0] (inputs)
CRS_DV

R1 R2

3.19.3.3 RMII transmit signal timing (TXD[1:0], TX_EN)

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%.
There is no minimum frequency requirement. The system clock frequency must be at least
equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK
frequency.
The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the
rising or falling edge of REF_CLK, and the timing is the same in either case. This options
allows the use of non-compliant RMII PHYs.

Table 61. RMII transmit signal timing(1)(2)

Value(3)
Symbol C Characteristic Unit
Min Max

R5 CC D REF_CLK to TXD[1:0], TX_EN invalid 2 — ns

R6 CC D REF_CLK to TXD[1:0], TX_EN valid — 16 ns
R7 CC D REF_CLK pulse width high 35% 65% REF_CLK period
R8 CC D REF_CLK pulse width low 35% 65% REF_CLK period
o
1. RMII timing is valid only up to a maximum of 150 C junction temperature.
2. CL = 25pF, VDD_HV_IO_FLEX = 3.3V +/- 5% and CMOS levels are required for the REF_CLK input. For CL = 15pF,
VDD_HV_IO_FLEX = 3.3V +/- 10%, CMOS or TTL levels for the REF_CLK input.
3. CL is the external load to the device. The internal package capacitance is accounted for, and does not need to be
subtracted from the 25 pF value.

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Figure 44. RMII transmit signal timing diagram

R7

REF_CLK (input)
R5
R8
TXD[1:0] (outputs)
TX_EN

R6

3.19.4 FlexRay timing

This section provides the FlexRay Interface timing characteristics for the input and output
signals.
These are recommended numbers as per the FlexRay EPL v3.0 specification, and subject
to change per the final timing analysis of the device.

3.19.4.1 TxEN

Figure 45. TxEN signal

TxEN

80 %

20 %

dCCTxENFALL dCCTxENRISE

Table 62. TxEN output characteristics(1)

Value
Symbol C Characteristic Unit
Min Max

dCCTxENRISE25 CC D Rise time of TxEN signal at CC — 9 ns

dCCTxENFALL25 CC D Fall time of TxEN signal at CC — 9 ns

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Table 62. TxEN output characteristics(1)(Continued)

Value
Symbol C Characteristic Unit
Min Max

dCCTxEN01 CC D Sum of delay between Clk to Q of the last FF and the final — 25 ns
output buffer, rising edge
dCCTxEN10 CC D Sum of delay between Clk to Q of the last FF and the final — 25 ns
output buffer, falling edge
1. TxEN pin load maximum 25 pF

Figure 46. TxEN signal propagation delays

PE_Clk

TxEN

dCCTxEN10 dCCTxEN01

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3.19.4.2 TxD

Figure 47. TxD signal

TxD
dCCTxD50%
80 %

50 %

20

dCCTxDFALL dCCTxDRISE

Table 63. TxD output characteristics(1)(2)

Value
Symbol C Characteristic Unit
Min Max

dCCTxAsym CC D Asymmetry of sending CC at 25 pF load –2.45 2.45 ns

(= dCCTxD50% − 100 ns)
dCCTxDRISE25+dCCTxDFALL25 CC D Sum of Rise and Fall time of TxD signal at the — 9(5) ns
output pin(3),(4)
D — 9(6)
dCCTxD01 CC D Sum of delay between Clk to Q of the last FF and — 25 ns
the final output buffer, rising edge
dCCTxD10 CC D Sum of delay between Clk to Q of the last FF and — 25 ns
the final output buffer, falling edge
1. TxD pin load maximum 25 pF.
2. Specifications valid according to FlexRay EPL 3.0.1 standard with 20%–80% levels and a 10pF load at the end of a
50 Ohm, 1 ns stripline. Please refer to the Very Strong I/O pad specifications.
3. Pad configured as VERY STRONG.
4. Sum of transition time simulation is performed according to Electrical Physical Layer Specification 3.0.1 and the entire
temperature range of the device has been taken into account.
5. VDD_HV_IO = 5.0 V ± 10%, Transmission line Z = 50 ohms, tdelay = 1 ns, CL = 10 pF
6. VDD_HV_IO = 3.3 V ± 10%, Transmission line Z = 50 ohms, tdelay = 0.6 ns, CL = 10 pF

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Figure 48. TxD Signal propagation delays

PE_Clk*

TxD

dCCTxD10 dCCTxD01

* FlexRay Protocol Engine Clock

3.19.4.3 RxD

Table 64. RxD input characteristics(1)

Value
Symbol C Characteristic Unit
Min Max

C_CCRxD CC D Input capacitance on RxD pin — 7 pF

uCCLogic_1 CC D Threshold for detecting logic high 35 70 %
uCCLogic_0 CC D Threshold for detecting logic low 30 65 %
dCCRxD01 CC D Sum of delay from actual input to the D input of the
— 10 ns
first FF, rising edge
dCCRxD10 CC D Sum of delay from actual input to the D input of the
— 10 ns
first FF, falling edge
dCCRxAsymAccept15 CC D Acceptance of asymmetry at receiving CC with
–31.5 44 ns
15 pF load
dCCRxAsymAccept25 CC D Acceptance of asymmetry at receiving CC with
–30.5 43 ns
25 pF load
1. FlexRay RxD timing is valid for CMOS input levels, hysteresis disabled, and 4.5 V ≤ VDD_HV_IO ≤ 5.5 V.

3.19.5 PSI5 timing

The following table describes the PSI5 timing.

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Table 65. PSI5 timing

Value
Symbol C Parameter Unit
Min Max

tMSG_DLY CC D Delay from last bit of frame (CRC0) to assertion — 3 µs

of new message received interrupt
tSYNC_DLY CC D Delay from internal sync pulse to sync pulse — 2 µs
trigger at the SDOUT_PSI5_n pin
tMSG_JIT CC D Delay jitter from last bit of frame (CRC0) to — 1 cycles(1)
assertion of new message received interrupt
tSYNC_JIT CC D Delay jitter from internal sync pulse to sync — ±(1 PSI5_1µs_CLK + cycles
pulse trigger at the SDOUT_PSI5_n pin 1 PBRIDGEn_CLK)
1. Measured in PSI5 clock cycles (PBRIDGEn_CLK on the device). Minimum PSI5 clock period is 20 ns.

3.19.6 UART timing

UART channel frequency support is shown in the following table.

Table 66. UART frequency support

LINFlexD clock frequency Max usable frequency
Oversampling rate Voting scheme
LIN_CLK (MHz) (Mbaud)

80 16 3:1 majority voting 5

8 10
6 Limited voting on one 13.33
sample with configurable
5 16
sampling point
4 20
100 16 3:1 majority voting 6.25
8 12.5
6 Limited voting on one 16.67
sample with configurable
5 20
sampling point
4 25

3.19.7 I2C timing

The I2C AC timing specifications are provided in the following tables.

Table 67. I2C input timing specifications — SCL and SDA(1)

Value
No. Symbol C Parameter Unit
Min Max

1 — CC D Start condition hold time 2 — PER_CLK

Cycle(2)
2 — CC D Clock low time 8 — PER_CLK Cycle

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Table 67. I2C input timing specifications — SCL and SDA(1)(Continued)

Value
No. Symbol C Parameter Unit
Min Max

3 — CC D Bus free time between Start and Stop condition 4.7 — µs

4 — CC D Data hold time 0.0 — ns
5 — CC D Clock high time 4 — PER_CLK Cycle
6 — CC D Data setup time 0.0 — ns
7 — CC D Start condition setup time (for repeated start condition only) 2 — PER_CLK Cycle
8 — CC D Stop condition setup time 2 — PER_CLK Cycle
2
1. I C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower than
1 ns (10% – 90%).
2. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the
device reference manual for more detail.

Table 68. I2C output timing specifications — SCL and SDA(1)(2)(3)(4)

Value
No. Symbol C Parameter Unit
Min Max

1 — CC D Start condition hold time 6 — PER_CLK

Cycle(5)
2 — CC D Clock low time 10 — PER_CLK Cycle
3 — CC D Bus free time between Start and Stop condition 4.7 — µs
4 — CC D Data hold time 7 — PER_CLK Cycle
5 — CC D Clock high time 10 — PER_CLK Cycle
6 — CC D Data setup time 2 — PER_CLK Cycle
7 — CC D Start condition setup time (for repeated start condition 20 — PER_CLK Cycle
only)
8 — CC D Stop condition setup time 10 — PER_CLK Cycle
1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
2. Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speedsand may
cause incorrect operation.
4. Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum output
timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD register.
5. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the
device reference manual for more detail.

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Figure 49. I2C input/output timing

2 5

SCL
6 8
4
1 3
7
SDA

3.19.8 GPIO delay timing

The GPIO delay timing specification is provided in the following table.

Table 69. GPIO delay timing

Value
Symbol C Parameter Unit
Min Max

IO_delay CC D Delay from MSCR bit update to pad function enable 5 25 ns

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4 Package characteristics

The following table lists the case numbers for each available package for the device.

Table 70. Package case numbers

Package Type Device Type Package reference

eTQFP144 Production 7386636

FQ172 Emulation 8153717
eLQFP176 Production 8391697
FQ216 Emulation 8338897

4.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

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4.2 eTQFP144 case drawing

Figure 50. eTQFP144 – STMicroelectronics package mechanical drawing (1 of 2)

MECHANICAL PACKAGE DRAWINGS

TQFP 144L BODY 20x20x1.0

FOOT PRINT 1.0 EXPOSED PAD DOWN
PACKAGE CODE : X6
JEDEC/EIAJ REFERENCE NUMBER : JEDEC MS-026-AFB-HD
REFERENCE : 7386636

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Package characteristics SPC574Kx

Figure 51. eTQFP144 – STMicroelectronics package mechanical drawing (2 of 2)

Dimensions

Symbol Millimeters Inches(1)

Min Typ Max Min Typ Max

A — — 1.20 — — 0.047
A1 0.05 — 0.15 0.002 — 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041
b 0.17 0.22 0.27 0.007 0.009 0.011
c 0.09 — 0.20 0.004 — 0.008
D 21.80 22.00 22.20 0.858 0.866 0.874
D1 19.80 20.00 20.20 0.780 0.787 0.795
(2)
D2 — 7.35 — — 0.289 —
D3 — 17.50 — — 0.689 —
E 21.80 22.00 22.20 0.858 0.866 0.874
E1 19.80 20.00 20.20 0.780 0.787 0.795
E2 — 7.35 — — 0.289 —
(2)
E3 — 17.50 — — 0.689 —
e — 0.50 — — 0.020 —
L(3) 0.45 0.60 0.75 0.018 0.024 0.030
L1 — 1.00 — — 0.039 —
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc(4) 0.08 0.003
1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
2. The size of exposed pad is variable depending of leadframe design pad size.
3. L dimension is measured at gauge plane at 0.25 above the seating plane.
4. Tolerance

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SPC574Kx Package characteristics

4.3 eLQFP176 case drawing

Figure 52. eLQFP176 – STMicroelectronics package mechanical drawing (1 of 2)

MECHANICAL PACKAGE DRAWINGS

LQFP 176L BODY 24x24x1.4

FOOT PRINT 2.0 (2x1.0 mm) EXPOSED PAD DOWN
PACKAGE CODE :A0A4
JEDEC/EIAJ REFERENCE NUMBER : JEDEC MS-026-BGA-HD
REFERENCE : 8153717

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Figure 53. eLQFP176 – STMicroelectronics package mechanical drawing (2 of 2)

Dimensions

Symbol Millimeters Inches(1)

Min Typ Max Min Typ Max

A — — 1.60 — — 0.063
A1 0.05 — 0.15 0.002 — 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.17 0.22 0.27 0.007 0.009 0.011
c 0.09 — 0.20 0.004 — 0.008
D 25.80 26.00 26.20 1.016 1.024 1.032
D1 23.90 24.00 24.10 0.941 0.945 0.949
(2)
D2 — 7.35 — — 0.289 —
D3 — 21.500 — — 0.847 —
E 25.80 26.00 26.20 1.016 1.024 1.032
E1 23.90 24.00 24.10 0.941 0.945 0.949
E2(2) — 7.35 — — 0.289 —
E3 — 21.50 — — 0.847 —
e — 0.50 — — 0.020 —
(3)
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 — 1.00 — — 0.039 —
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc(4) 0.080 0.003
1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
2. The size of exposed pad is variable depending of leadframe design pad size.
3. L dimension is measured at gauge plane at 0.25 above the seating plane.
4. Tolerance

4.4 FusionQuad® case drawing

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127/160

Package characteristics
MECHANICAL PACKAGE DRAWINGS
DocID023601 Rev 6

SPC574Kx
FusionQuad® 144+28L 20x20x1.0 0.5 mm Pitch
PACKAGE CODE :A0SX
REFERENCE : 8391697
Package characteristics SPC574Kx

Figure 55. FusionQuad® QFP172 package mechanical drawing (2 of 2)

MECHANICAL OUTLINE ASSEMBLY

NOTES:
1. ALL DIMENSIONING AND TOLERANCING CONFORM ALL DIMENSIONS IN MILLIMETERS
TO ANSI Y14.5-1982.
2 DATUM PLANE H LOCATED AT MOLD PARTING LINE
AND COINCIDENT WITH LEAD, WHERE LEAD EXITS VARIATIONS
PLASTIC BODY AT BOTTOM OF PARTING LINE.
FUSION
3 DATUMS A–B AND D TO BE DETERMINED AT SYMBOL NOTE
MIN NOM MAX
CENTERLINE BETWEEN LEADS WHERE LEADS EXIT
PLASTIC BODY AT DATUM PLANE H. A — — 1.20
4 TO BE DETERMINED AT SEATING PLANE C. A1 0.05 0.10 0.15
A2 0.95 1.00 1.05
5 DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD A3 –0.05 0.00 0.05
PROTRUSION. ALLOWABLE MOLD PROTRUSION IS
0.254 MM ON D1 AND E1 DIMENSIONS. A4 0.152 REF
6. ‘N’ IS THE NUMBER OF TERMINALS FOR PERIPHERAL D 22.00 BSC 4
LEADS, AND ‘M’ IS THE NUMBER OF TERMINALS FOR D1 20.00 BSC 5
BOTTOM LANDS ON BOTTOM SURFACE OF PACKAGE D2 17.50 BSC
BODY. THE BOTTOM LANDS ARE IDENTIFIED BY
ALPHANUMERICS | A1~A#. D3 8.32 8.42 8.52
7 THESE DIMENSIONS TO BE DETERMINED AT DATUM E 22.00 BSC 4
PLANE H. E1 20.00 BSC 5
8. THE TOP OF PACKAGE MAY BE SMALLER THAN THE E2 17.50 BSC
BOTTOM OF PACKAGE BY 0.15 MM. E3 8.20 8.30 9.40
9 DIMENSION b DOES NOT INCLUDE DAMBAR E4 10.00 REF
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION L 0.45 0.60 0.75
SHALL BE 0.08 MM TOTAL IN EXCESS OF THE b
DIMENSION AT MAXIMUM MATERIAL CONDITION. N 144 6
DAMBAR CANNOT BE LOCATED ON THE LOWER e 0.50 BSC
RADIUS OR THE FOOT.
b 0.17 0.22 0.27
10. CONTROLLING DIMENSION | MILLIMETERS. c.c.c 0.08
11. MAXIMUM ALLOWABLE DIE THICKNESS TO BE d.d.d 0.08
ASSEMBLED IN THIS PACKAGE FAMILY IS 0.38 MM.
12 A1 IS DEFINED AS THE DISTANCE FROM THE
SEATING PLANE TO THE LOWEST POINT OF THE
PACKAGE BODY.
13. DIMENSIONS D2 AND E2 REPRESENT THE SIZE OF
THE EXPOSED PAD. THE ACTUAL DIMENSIONS ARE PITCH VARIATIONS
DETERMINED BY EACH INDIVIDUAL LEADFRAME FUSION
DRAWING. THE EXPOSED PAD SIZE TOLERANCE IS SYMBOL NOTE
0.10 MAX. MIN NOM MAX
eT 0.50 BSC
14. EXPOSED PAD SHALL BE COPLANAR WITH BOTTOM
OF PACKAGE WITHIN 0.05 MM. eC 0.39 BSC 18
M 28 6
15. UNILATERAL COPLANARITY ZONE APPLIES TO THE
EXPOSED PAD AS WELL AS THE TERMINALS. La 0.30 0.40 0.50
16. MECHANICAL CONNECT TABS ARE COUNTED FOR f 0.17 0.22 0.27
GROUND (VSS) SIGNAL PINS. THOSE ARE INCLUDED 999 — 0.08 —
INTO PACKAGE TOTAL PIN COUNTS.
17 THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 MM AND 0.25 MM FROM
THE LEAD TIP. THE FusionQuad PACKAGE IS A REGISTERED
18 THESE DIMENSIONS APPLY TO ALL 4 SYMMETRIC TRADEMARK OF AMKOR TECHNOLOGIES.
LOCATIONS.
THE FusionQuad PACKAGE IS ASSEMBLED
19 GATE PROTRUSION HEIGHT OR CHIP OUT DEPTH | BY AMKOR TECHNOLOGIES.
0.049 MM MAX

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 Figure 56. FusionQuad® QFP216 package mechanical drawing (1 of 2)
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Package characteristics
DocID023601 Rev 6

FusionQuad® 176+40L 24x24x1.0 0.5 mm Pitch

SPC574Kx
PACKAGE CODE: A0HX
REFERENCE : 8338897
Package characteristics SPC574Kx

Figure 57. FusionQuad® QFP216 package mechanical drawing (2 of 2)

MECHANICAL OUTLINE ASSEMBLY

NOTES:
1. ALL DIMENSIONING AND TOLERANCING CONFORM ALL DIMENSIONS IN MILLIMETERS
TO ANSI Y14.5-1982.
2 DATUM PLANE H LOCATED AT MOLD PARTING LINE
AND COINCIDENT WITH LEAD, WHERE LEAD EXITS VARIATIONS
PLASTIC BODY AT BOTTOM OF PARTING LINE.
FUSION
3 DATUMS A–B AND D TO BE DETERMINED AT SYMBOL NOTE
MIN NOM MAX
CENTERLINE BETWEEN LEADS WHERE LEADS EXIT
PLASTIC BODY AT DATUM PLANE H. A — — 1.20
4 TO BE DETERMINED AT SEATING PLANE C. A1 0.00 0.051 0.10
A2 0.95 1.00 1.05
5 DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
D 26.00 BSC 4
PROTRUSION. ALLOWABLE MOLD PROTRUSION IS
0.254 MM ON D1 AND E1 DIMENSIONS. D1 24.00 BSC 5
6. ‘N’ IS THE NUMBER OF TERMINALS FOR PERIPHERAL D2 17.50 BSC
LEADS, AND ‘M’ IS THE NUMBER OF TERMINALS FOR D3 9.58 9.68 9.78
BOTTOM LANDS ON BOTTOM SURFACE OF PACKAGE E 26.00 BSC 4
BODY. THE BOTTOM LANDS ARE IDENTIFIED BY
ALPHANUMERICS | A1~A#. E1 24.00 BSC 5
7 THESE DIMENSIONS TO BE DETERMINED AT DATUM E2 21.00 BSC
PLANE H. E3 9.40 9.50 9.60
8. THE TOP OF PACKAGE MAY BE SMALLER THAN THE E4 11.20 REF
BOTTOM OF PACKAGE BY 0.15 MM. L 0.45 0.60 0.75
9 DIMENSION b DOES NOT INCLUDE DAMBAR N 176 6
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION e 0.50 BSC
SHALL BE 0.08 MM TOTAL IN EXCESS OF THE b
DIMENSION AT MAXIMUM MATERIAL CONDITION. b 0.17 0.22 0.27
DAMBAR CANNOT BE LOCATED ON THE LOWER c.c.c 0.08
RADIUS OR THE FOOT.
d.d.d 0.08
10. CONTROLLING DIMENSION | MILLIMETERS.
11. MAXIMUM ALLOWABLE DIE THICKNESS TO BE
ASSEMBLED IN THIS PACKAGE FAMILY IS 0.38 MM.
12 A1 IS DEFINED AS THE DISTANCE FROM THE
SEATING PLANE TO THE LOWEST POINT OF THE
PACKAGE BODY.
13. DIMENSIONS D2 AND E2 REPRESENT THE SIZE OF
THE EXPOSED PAD. THE ACTUAL DIMENSIONS ARE PITCH VARIATIONS
DETERMINED BY EACH INDIVIDUAL LEADFRAME FUSION
DRAWING. THE EXPOSED PAD SIZE TOLERANCE IS SYMBOL NOTE
0.10 MAX. MIN NOM MAX
eT 0.50 BSC
14. EXPOSED PAD SHALL BE COPLANAR WITH BOTTOM
OF PACKAGE WITHIN 0.05 MM. eC 0.39 BSC 18
M 40 6
15. UNILATERAL COPLANARITY ZONE APPLIES TO THE
EXPOSED PAD AS WELL AS THE TERMINALS. La 0.30 0.40 0.50
16. MECHANICAL CONNECT TABS ARE COUNTED FOR f 0.17 0.22 0.27
GROUND (VSS) SIGNAL PINS. THOSE ARE INCLUDED 999 — 0.08 —
INTO PACKAGE TOTAL PIN COUNTS.
17 THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 MM AND 0.25 MM FROM
THE LEAD TIP. THE FusionQuad PACKAGE IS A REGISTERED
18 THESE DIMENSIONS APPLY TO ALL 4 SYMMETRIC TRADEMARK OF AMKOR TECHNOLOGIES.
LOCATIONS.
THE FusionQuad PACKAGE IS ASSEMBLED
BY AMKOR TECHNOLOGIES.

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4.5 Thermal characteristics

The following tables describe the thermal characteristics of the device.

Table 71. Thermal characteristics for eTQFP144(1)

Value
Symbol C Parameter Conditions Unit
Min Max

RθJA CC D Junction-to-ambient, natural convection(2) Four layer board—2s2p 26 29 °C/W

RθJMA CC D Junction-to-moving-air, ambient(2) At 200 ft./min., four layer 19 23 °C/W
board—2s2p
RθJB CC D Junction-to-board(3) — 12 16 °C/W
RθJCtop CC D Junction-to-case top(4) — 10 13 °C/W
RθJCbottom CC D Junction-to-case bottom(5) — 1.5 4 °C/W
ΨJT CC D Junction-to-package top(6) Natural convection 3 5 °C/W
Pd CC D Device power dissipation Maximum power and — 2 W
voltage condition
1. The lower number in the ranges specified in the ‘Value’ column are based on simulation; actual data may vary in the given
range. The specified characteristics are subject to change per final device design and characterization. Junction
temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any
interface resistance.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.

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Table 72. Thermal characteristics for eLQFP176(1)

Value
Symbol C Parameter Conditions Unit
Min Max

RθJA CC D Junction-to-ambient, natural convection(2) Four layer board—2s2p 25 28 °C/W

(2)
RθJMA CC D Junction-to-moving-air, ambient At 200 ft./min., four layer 18 22 °C/W
board—2s2p
RθJB CC D Junction-to-board(3) — 12 16 °C/W
RθJCtop CC D Junction-to-case top(4) — 12 15 °C/W
(5)
RθJCbottom CC D Junction-to-case bottom — 1.5 3.5 °C/W
ΨJT (6)
CC D Junction-to-package top Natural convection 3 4.5 °C/W
Pd CC D Device power dissipation Maximum power and — 2 W
voltage condition
1. The lower number in the ranges specified in the ‘Value’ column are based on simulation; actual data may vary in the given
range. The specified characteristics are subject to change per final device design and characterization. Junction
temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any
interface resistance.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.

4.5.1 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from the equation:

Equation 3 TJ = TA + (RθJA * PD)

where:
TA = ambient temperature for the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards
to provide consistent values for estimations and comparisons. The difference between the
values determined for the single-layer (1s) board compared to a four-layer board that has
two signal layers, a power and a ground plane (2s2p), demonstrate that the effective
thermal resistance is not a constant. The thermal resistance depends on the:
• Construction of the application board (number of planes)
• Effective size of the board which cools the component
• Quality of the thermal and electrical connections to the planes
• Power dissipated by adjacent components

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Connect all the ground and power balls to the respective planes with one via per ball. Using
fewer vias to connect the package to the planes reduces the thermal performance. Thinner
planes also reduce the thermal performance. When the clearance between the vias leave
the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for
the tightly packed printed circuit board. The value obtained on a board with the internal
planes is usually within the normal range if the application board has:
• One oz. (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the
surrounding components. In addition, the ambient temperature varies widely within the
application. For many natural convection and especially closed box applications, the board
temperature at the perimeter (edge) of the package is approximately the same as the local
air temperature near the device. Specifying the local ambient conditions explicitly as the
board temperature provides a more precise description of the local ambient conditions that
determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following
equation:

Equation 4 TJ = TB + (RθJB * PD)

where:
TB = board temperature for the package perimeter (°C)
RθJB = junction-to-board thermal resistance (°C/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, the
junction temperature is predictable if the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance
plus a case-to-ambient thermal resistance:

Equation 5 RθJA = RθJC + RθCA

where:
RθJA = junction-to-ambient thermal resistance (°C/W)
RθJC = junction-to-case thermal resistance (°C/W)
RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and is not affected by other factors. The thermal environment can be
controlled to change the case-to-ambient thermal resistance, RθCA. For example, change
the air flow around the device, add a heat sink, change the mounting arrangement on the
printed circuit board, or change the thermal dissipation on the printed circuit board
surrounding the device. This description is most useful for packages with heat sinks where
90% of the heat flow is through the case to heat sink to ambient. For most packages, a
better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board
thermal resistance and the junction-to-case thermal resistance. The junction-to-case

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thermal resistance describes when using a heat sink or where a substantial amount of heat
is dissipated from the top of the package. The junction-to-board thermal resistance
describes the thermal performance when most of the heat is conducted to the printed circuit
board. This model can be used to generate simple estimations and for computational fluid
dynamics (CFD) thermal models. More accurate compact Flotherm models can be
generated upon request.
To determine the junction temperature of the device in the application on a prototype board,
use the thermal characterization parameter (ΨJT) to determine the junction temperature by
measuring the temperature at the top center of the package case using the following
equation:

Equation 6 TJ = TT + (ΨJT x PD)

where:
TT = thermocouple temperature on top of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured in compliance with the JESD51-2
specification using a 40-gauge type T thermocouple epoxied to the top center of the
package case. Position the thermocouple so that the thermocouple junction rests on the
package. Place a small amount of epoxy on the thermocouple junction and approximately 1
mm of wire extending from the junction. Place the thermocouple wire flat against the
package case to avoid measurement errors caused by the cooling effects of the
thermocouple wire.
When board temperature is perfectly defined below the device, it is possible to use the
thermal characterization parameter (ΨJPB) to determine the junction temperature by
measuring the temperature at the bottom center of the package case (exposed pad) using
the following equation:

Equation 7 TJ = TB + (ΨJPB x PD)

where:
TB= thermocouple temperature on bottom of the package (°C)
ΨPB= thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)

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SPC574Kx Ordering information

5 Ordering information

Figure 58. Product code structure

Example code:
SPC57 4 K 72 E5 C 6 F A R
Product identifier Core Product Memory Package Temperature Frequency Custom Reserved Packing
vers.

Y = Tray
R = Tape and Reel

0 = No Options
1 = Up to ASIL-D SEooC
8 = add. computing e200z2 core with DSP
F = All Options

6 = 160 MHz

C = 125 ºC Ta

E5 = eTQFP144
E7 = eLQFP176
70 = 2 MB
72 = 2.5 MB
K = SPC574Kx family

4 = Single computing e200z4 core

SPC57 = Power Architecture in 55 nm

1. Order on 2M-Byte part numbers can be entered upon ST’s acceptance conditioned by volumes. Please
contact your ST sales office to ask for the availability of a particular commercial product.
2. Features (e.g. flash, RAM or peripherals) not included in the commercial product cannot be used. ST cannot
be called to take any liability for features used outside the commercial product.

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Revision history SPC574Kx

6 Revision history

Table 74. Revision history

Revision Date Description of changes

1 28 Oct 2011 Initial release

2 30 Aug 2012 Editorial and formatting changes throughout
SPC574Kxx Microcontroller Data Sheet title page: added chip part numbers
Harmonized package naming
Section 1.3, Device feature summary: modified title (was “Device comparison”)
Replaced “Family comparison” table with Table 2 (MPC5744K/SPC574Kx device feature
summary)
Updated Figure 1 (Block diagram)
Updated Figure 2 (Periphery allocation)
Section 1.5, Feature overview:
– Updated code flash memory size from 2048 KB code to 2560 KB
– Updated BAF feature description
– Updated BAM feature description
– Replaced instance of “K2” with “MPC5744K/SPC574K72”
Figure ():
– Modified names of pins 10, 23, A15, A22, and 125
– Replaced “A1–A28 are the additional FQ172 FQ pins” with “VSS” in the middle box
– Added notes 3 and 4
Figure 4 (176-pin QFP and 216-pin FQ configuration (top view)):
– Changed name of pin A23, A40, 153, and 154
– Replaced “A1–A40” are the additional FQ172 FQ pins” with “VSS” in the middle box
– Added notes 3 and 4
Removed Table “Power supply and reference pins” and added reference to the
JPC5744M IO Signal Table.xlsx
Table 3 (System pins): updated TESTMODE pin description
Table 4 (LVDSM pin descriptions): updated pin number column header
Table 5 (LVDSF pin descriptions): updated pin number column header
Updated Section 2.2.4, Generic pins
Section 3, Electrical characteristics: removed section “Thermal characteristics” (section
transferred to Section 4, Package characteristics)
Updated Section 3.1, Introduction
– Following note removed: “All parameter values in this document are tested with nominal
supply voltage values (VDD_LV = 1.25 V, VDD_HV = 5.0 V ± 10%, VDD_HV_IO = 5.0 V ±
10% or 3.3 V ± 10%) and TA = –40 to 125 °C unless otherwise specified.”. Operating
conditions will appear elsewhere in the data sheet.
– Following footnote on VDD_LV in above note removed: “Refer to the LVD specification.”
– VDD_HV_OSC deleted from note (list of supply pins)
Updated Table 6 (Absolute maximum ratings)
Updated Table 8 (Radiated emissions testing specification,)
Table 9 (Conducted emissions testing specifications): reworded footnote referencing
effect of 25/50 MHz clocks on BISS port limits
Added Table 10 (RF immunity—Direct Power Injection (DPI) test specifications)
Table 11 (ESD ratings): Added classification column
Table 14 (Temperature profile – Packaged parts): corrected temperature range in
“Passenger cars - low end” (was TA = 80 to 95 °C, is TA = 80 to 85 °C); updated “Total
operation time” value in “Passenger cars - low end”

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SPC574Kx Revision history

Table 74. Revision history(Continued)

Revision Date Description of changes

2 30 Aug 2012 Table 15 (Unbiased temperature profile – Packaged parts): replaced instance of “–40 to –
(cont’d) 60 °C” with “–40 to 60 °C”
Updated Table 12 (Device operating conditions)
Updated Table 16 (DC electrical specifications):
– Updated the max values
– Added condition values in IDDAPP row
– Added second condition in TJ < 165 oC to IDDAPP row
– Removed IINACT_D and TA (TL to TH) rows
Revised Section 3.9, I/O pad specification
Updated Section 3.9.1, I/O input DC characteristics
Table 18 (I/O input DC electrical characteristics):
– Added cross reference for SENT requirement to note 5
– Footnote moved to header of “INPUT CHARACTERISTICS” section: “For LFAST,
microsecond bus and LVDS input characteristics, refer to dedicated communication
module chapters.“
Updated Section 3.9.2, I/O output DC characteristics
Added Section 3.10, I/O pad current specification
Table 19 (I/O pull-up/pull-down DC electrical characteristics):
– |IWPU| parameter description changed: “Weak pull-up/down current absolute value”
(was “Weak pull-up current absolute value”)
– |IWPU| specification condition changed: VDD_POR < VDD_HV_IO < 3.0 V (was
VDD_POR < VDD < 3.0 V)
Table 21 (MEDIUM configuration output buffer electrical characteristics)
– New specification: IDCMAX_M (Maximum DC current)
Table 20 (WEAK configuration output buffer electrical characteristics)
– New specification: IDCMAX_W (Maximum DC current)
Updated Table 22 (STRONG configuration output buffer electrical characteristics)
Updated Table 23 (VERY STRONG configuration output buffer electrical characteristics)
Updated Section 3.11, Reset pad (PORST, ESR0) electrical characteristics:
– replaced instance of “bidirectional RESET pin” with “bidirectional reset pin (PORST)”
– inserted note “PORST pin does not require active control. It is possible to implement an
external pull-up to ensure correct reset exit sequence. Recommended value is
4.7 kohm”
– replaced instances of “PORST” with “PORST” (overlined)
– replaced instances of “VDDPOR” with “VDD_POR”
Table 25 (Reset electrical characteristics):
– New specification: WFNMI (ESR1 input filtered pulse)
– WNFNMI (ESR1 input not filtered pulse)
– |IWPU| and |IWPD| parameter rows moved to rows following IOL_R
Table 26 (PLL0 electrical characteristics):
– Note added to |ΔPLL0PHI1SPJIT| row
– Updated “conditions” in rows |ΔPLL0PHI0SPJIT|, |ΔPLL0PHI1SPJIT|, and |ΔPLL0LTJIT|
Figure 3.12 (Oscillator and FMPLL):
– Clarification: VESR0 is also described by VPORST behavior shown in illustration.
Table 27 (PLL1 electrical characteristics): modified title (was “FMPLL1 electrical
characteristics”)
– ΔTUE12 (TUE degradation due to VDD_HV_ADR offset with respect to VDD_HV_ADV)
(VIN < VDD_HV_ADV; VDD_HV_ADR − VDD_HV_ADV ∈ [0:25 mV]): Max value changed to
±0.0 (was ±1.0)
– TUE12 (Total unadjusted error in 12-bit configuration): Footnote added to “P” parameter
(TJ < 150 °C; VDD_HV_ADV > 4 V; VDD_HV_ADR_S > 4 V): values are subject to change
after characterization
– Replaced the characteristics value from “P” to “T” for tPLL1JIT row

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Table 74. Revision history(Continued)

Revision Date Description of changes

2 30 Aug 2012 Updated Table 28 (External Oscillator electrical specifications)

(cont’d) Updated Table 29 (Selectable load capacitance)
Updated Table 26 (SARn ADC electrical specification)
Updated Table 34 (SDn ADC electrical specification)
Revised Section 3.13, ADC specifications
Figure 19 (Power-down exit time): replaced symbol “Tsu” with “tPD2NM_TX”
Table 35 (Temperature sensor electrical characteristics):
– Following symbols added: TSENS, TACC, ITEMP_SENS
– Following sentence removed from footnote: “All values above are comprehended in the
IP test plan for 100% testing, except Power.”
– Footnote deleted: “Temperature sensor continues to function between 150 °C and
165 °C but accuracy is degraded”
Table 37 (LFAST interface electrical characteristics): removed redundant footnote
Replaced section “DigRF electrical characteristics” with Section 3.15, LVDS Fast
Asynchronous Serial Transmission (LFAST) pad electrical characteristics
Updated Table 39 (LFAST PLL electrical characteristics)
Updated Table 40 (Aurora LVDS electrical characteristics)
– Specification change: RV_L (Terminating resistance): min value is 81 ohm (was 90); max
value is 120 ohm (was 110).
– Footnote added to |ΔVOD_LVDS| (Differential output voltage swing (terminated)): “The
minimum value of 400 mV is only valid for differential terminating resistance (RV_L) =
99 ohm to 101 ohm. The differential output voltage swing tracks with the value of RV_L.“
– Updated and renamed specification fRX Receive Clock Rate (was Receive Data Rate)
– Specification description changed from “|ΔVI_L| (Differential input voltage)” to
“Differential input voltage (peak to peak)”.
– Clarification: The maximum value of TLoss (Transmission Line Loss due to loading
effects) is specified for the maximum drive level of the Aurora transmit pad.
– Note added: “The Aurora interface is AC coupled, so there is no common-mode voltage
specification.”
– Footnote (applies to entire table) updated: “All Aurora electrical characteristics are valid
from –40 °C to 165 °C, except where noted”
Reorganized subsections of Section 3.17, Power management: PMC, POR/LVD,
sequencing
Table 41 (Device Power Supply Integration):
– Replaced “TBD” with “—” in Typ column
– Removed VSREG, ISREG, ILPREGINT
Updated Table 42 (Voltage monitor electrical characteristics)
Table 43 (Device supply relation during power-up/power-down sequence):
– Replaced “VDD_HV_PMC” with VDD_HV_IO_JTAG/VDD_HV_IO_FLEX
– Replaced “VDD_HV_PMU” with VDD_HV_IO_JTAG/VDD_HV_IO_FLEX
– Replaced VDD_HV_ADR row value from 2 mA to 5 mA
Changed instance of “Supply 1” to “Supply 2” in column header row
Table 44 (Functional terminals state during power-up and reset):
– Changed “Power-up pad state” column value from “High impedance” to “weak pull-up”
in TDI row
– Updated pad states in TMS row
Section 3.17.3, Device voltage monitoring: added introductory text
Updated Table 44 (Flash memory program and erase specifications (pending silicon
characterization))
Revised Section 3.19.2, DSPI Timing with CMOS and LVDS Pads
Table 48 (JTAG pin AC electrical characteristics):
– Changed all parameters from “C” to “D”
– Specification change: tTCYC (TCK cycle time) is 100 ns (was 40 ns). Boundary scan
frequency is limited to 10 MHz or less.

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Table 74. Revision history(Continued)

Revision Date Description of changes

2 30 Aug 2012 Updated Table 49 (Nexus debug port timing)

(cont’d) Table 50 (Aurora LVDS interface timing specifications):
– Specification change: Data rate Typ is undefined (was 1200)
– Specification change: Data rate max is 1250 Mbps (was Typ + 0.1%)
Table 51 (Aurora debug port timing):
– Specification change: tREFCLK (Reference clock frequency) max value is 1250 MHz
(was 1200)
– Specification change: OUI (Aurora lane unit interval) is now specified by data rate
– Characteristic vs. Requirement change: JD (Transmit lane deterministic jitter) is “SR”
(was “CC”)
– Characteristic vs. Requirement change: JT (Transmit lane total jitter) is “SR” (was “CC”)
Table 57 (DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or
ITSB = 1, CPOL = 0 or 1, continuous SCK clock): added “SOUT and SCK drive
strength” to condition for tSUO
Table 59 (RMII serial management channel timing):
– Column added: SR/CC (system requirement or controller characteristic)
– Column added: Classification (parameters are guaranteed by design)
Table 62 (TxEN output characteristics):
– Column added: SR/CC (system requirement or controller characteristic)
– Column added: Classification (parameters are guaranteed by design)
Updated Table 63 (TxD output characteristics)
Updated Table 64 (RxD input characteristics)
Table 66 (MII receive signal timing):
– Column added: SR/CC (system requirement or controller characteristic)
– Column added: Classification (parameters are guaranteed by design)
Table 67 (MII transmit signal timing):
– Column added: SR/CC (system requirement or controller characteristic)
– Column added: Classification (parameters are guaranteed by design)
– Output parameter footnote changed to, “Output parameters are valid for CL = 25 pF,
where CL is the external load to the device. The internal package capacitance is
accounted for, and does not need to be subtracted from the 25 pF value” (Previously,
footnote stated CL included typical max internal capacitance of 2 pF)
Table 68 (MII async inputs signal timing):
– Column added: SR/CC (system requirement or controller characteristic)
– Column added: Classification (parameters are guaranteed by design)
Table 69 (MII serial management channel timing):
– Column added: SR/CC (system requirement or controller characteristic)
– Column added: Classification (parameters are guaranteed by design)
Added Section 3.20.4, UART timing
Section 4, Package characteristics: inserted Section 4.5, Thermal characteristics (was
previously in Section 3, Electrical characteristics)
Updated “conditions” in rows |ΔPLL0PHI0SPJIT|, |ΔPLL0PHI1SPJIT|, and |ΔPLL0LTJIT|
Updated Section 4.2, 144 LQFP-EPeTQFP144 case drawing
Updated Section 4.3, 176 LQFP-EPeLQFP176 case drawing
Updated Section 4.4, FusionQuad® case drawing
Added Section 6, Revision history

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Table 74. Revision history(Continued)

Revision Date Description of changes

3 31 Jan 2014 Table 2 (MPC5744K/SPC574Kx device feature summary):

– MCAN is updated to M_CAN
– TTCAN is updated to M_TTCAN
– SIPI / LFAST interprocessor bus is updated to Zipwire (SIPI/LFAST) interprocessor bus.
– Instances of ADC (SD) changed from 3 to 2
– removed row PSI5-S
– removed footnote The main computational shell...
– Replaced “4 × 256 bit” with “2 × 4 × 256-bit” for Flash memory fetch accelerator

Figure 1 (Block diagram):

– AIPS Bridge is updated to Peripheral Bridge
– LFAST & SIPI is updated to Zipwire LFAST & SIPI.
– DMACHMUX updated to read DMAMUX
– changed LFAST & SIPI module name to Zipwire LFAST & SIPI
– improved figure quality; changed “PBRIDGE_0” and “PBRIDGE_1” to “PBRIDGE_A”
and “PBRIDGE_B” respectively

Figure 2 (Periphery allocation):

– PLL_DIG is updated to PLLDIG
– OSC is updated to XOSC
– RCOSC is updated to IRCOSC
– Replaced single block DMAMUX with blocks DMACHMUX_0 to DMACHMUX_3
– SENT SRX_0 is updated to SRX_0
– SENT SRX_1 is updated to SRX_1
– Removed PSI5_S block from peripheral cluster B
– Removed the instance of SD ADC_2
– Updated DMACHMUX_0, DMACHMUX_1, DMACHMUX_2, and DMACHMUX_3 to
DMAMUX_0, DMAMUX_1, DMAMUX_2, and DMAMUX_3 respectively.
– changed “PBRIDGE_0” to “PBRIDGE_A”
– changed “PBRIDGE_1” to “PBRIDGE_B”
– changed Successive Approximation Register Analog-to-Digital Converter instances
from “SAR ADCx” to “SARADCx”.

Figure 3 (144-pin QFP and 172-pin FQ configuration (top view)):

– Pin A18 is now LVDS Test In+.
– Pin A19 is now LVDS Test In–.
– Pin 133 is now PC[15].
– Reworded note 2.
– Replaced “eLQFP144” with “eLQFP144” (ST_Specific)

Figure 4 (176-pin QFP and 216-pin FQ configuration (top view)):

– Pin A27 is now LVDS Test In+.
– Pin A28 is now LVDS Test In–.
– Reworded note 2.
Section 1.5, Feature overview:
– Updated text “3 separate 16-bit Sigma-Delta analog converters” to read “2 separate 16-
bit Sigma-Delta analog converters”
– Replaced “2 main CPUs” to “One main processor core and one checker core”

Table 5 (LVDSF pin descriptions):

– Replaced all instances of “N.C” with “—”
– Removed table footnote

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Table 74. Revision history(Continued)

Revision Date Description of changes

3 31 Jan 2014 Table 6 (Absolute maximum ratings):

(cont’d) – Parameter classification for Cycle is now “T”
– In footnote: 1.32 – 1.375 V range allowed periodically... changed 1.275 V to 1.288 V
– Added “VDD_HV_IO_BD”
– Removed “VDD_HV_IO_JTAG”
– Removed TJ
– Removed table footnote “Three Screen done, 1 minute each. No change in device
parameters during characterization of at least 10 devices at 30 minutes exposure of 150
KeV at maximum 5 mm” from tXRAY
– Added VDD_HV_ADV to VIN
– Added footnotes “VDD_HV_IO/VSS_HV_IO refers to supply pins and corresponding
grounds: VDD_HV_IO_MAIN, VDD_HV_IO_FLEX, VDD_HV_IO_JTAG, VDD_HV_OSC,
VDD_HV_FLA” and “Relative value can be exceeded if design measures are taken to
ensure injection current limitation (parameters IINJD and IINJA)” to “Relative to
VSS_HV_IO” and “Relative to VDD_HV_IO” in VIN

Table 8 (Radiated emissions testing specification,): Splited “BISS radiated emissions

limit” column into four rows to have clear figures for each function

Table 10 (RF immunity—Direct Power Injection (DPI) test specifications): Changed the
location of the table and placed it above Section 3.6, Operating conditions

Table 11 (ESD ratings):

– Classification parameter for ESD for Human Body Model is now T

Table 12 (Device operating conditions):

– In row VDD_HV_ADV Low Voltage Detector symbol changed to LVD295
– VDDSTBY added new footnote: The VDDSTBY pin should be connected to ground or an
HV I/O supply in the application when the standby RAM feature is not used. When
connected to an HV I/O supply, there will be leakage on the VDDSTBY pin, which is
given in the DC electrical specifications.
– Changed VRAMP to VRAMP_LV, changed parameter to 'slew rate on core power supply
pins.
– Add VRAMP_HV specification, parameter “Slew rate on HV power supply pins”, max
value 100 V/ms.
– Add a second VRAMP specification VRAMP_HV, parameter “Slew rate on HV power
supply pins”, max value 500 V/ms.
– Moved VREF_BG_T, VREF_BG_TC and VREF_BG_LR specifications from ADC pin
specification table to Device operating conditions table.
– VDD_HV_IO_FLEXE added specification.
– VREF_BG_T, VREF_BG_TC, and VREF_BG_LR moved to the DC electrical specifications
table.
– VSTBY_BO and VDD_LV_STBY_SW moved to the DC electrical specifications table.
– In rows fSYS and TJ removed 165 °C content
– In row fSYS changed the first value in the Conditions column to -40 °C
– Added fLBIST
– Added note “VDD_HV_IO_JTAG supply is shorted with VDD_HV_OSC supply within
package” to VDD_HV_IO_JTAG
– Added VIN

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Table 74. Revision history(Continued)

Revision Date Description of changes

3 31 Jan 2014 Table 16 (DC electrical specifications):

(cont’d) – In row IDDAPP Condition fSYS changed to 160 MHz, Condition TJ changed to 144 °C,
Max Value changed to 260.
– Footnote fMAX as specified...application specific pattern changed to application with
maximum consumption...
– Footnote fMAX as specified...with active flash... changed to Application with maximum
consumption...with active flash...
– Parameter classification of “IDDPE” changed to “C”.
– Parameter classification of “ISPIKE” changed to “T”.
– Parameter classification of “dl” changed to “T”.
– Parameter classification of “ISR” changed to “D”.
– 3 new parameters “IDD_MAIN_CORE_AC”, “IDD_CHKR_CORE_AC” and “IDD_HV_IO_BD”
added.
– Parameter “IDD_BD” updated to “IDD_LV_BD”. Also modified Parameter description,
added new condition “TJ = 150/165 C” and value.
– Added note “Moving window, measured on application specific pattern” to “ISPIKE”.
– Description of parameter “ISR” modified from “Current variation during power up/down”
to “Current variation during boot/shut-down”.
– Added note “Current variation is considered during boot or during shut-down sequence.
– Progressive clock switching should be use to guarantee low current variation. This does
not include current requested for the loading of the capacitances on the VDD_LV
domain. Please refer to Power management section, Iclamp specification” to the max
value of ISR.
– Moved IDD_HV_IO_BD before IDD_LV_BD
– Updated the parameter, conditions column of IDDAR and replaced the max value “10”
with “30”
– Added IDDOFF, VREF_BG_T, VREF_BG_TC, and VREF_BG_LR
– Updated Table footnote 4 and 8

Section 3.17.2, Main voltage regulator electrical characteristics: Updated the section

Table 18 (I/O input DC electrical characteristics):

– VIHTTL condition is 4.5 V < VDD_HV_IO < 5.5 V
– VILTTL condition is 4.5 V < VDD_HV_IO < 5.5 V
– VHYSTTL condition is 4.5 V < VDD_HV_IO < 5.5 V
– VIHCMOS_H condition is 2.7 V < VDD_HV_IO < 3.0 V and 4.0 V < VDD_HV_IO < 4.5 V
– VIHCMOS condition is 2.7 V < VDD_HV_IO < 3.0 V and 4.0 V < VDD_HV_IO < 4.5 V
– VILCMOS_H condition is 2.7 V < VDD_HV_IO < 3.0 V and 4.0 V < VDD_HV_IO < 4.5 V
– VILCMOS condition is 2.7 V < VDD_HV_IO < 3.0 V and 4.0 V < VDD_HV_IO < 4.5 V
– VHYSCMOS condition is 2.7 V < VDD_HV_IO < 3.0 V and 4.0 V < VDD_HV_IO < 4.5 V
– Updated the conditions and values for parameter ILKG
– The conditions “3.0 V < VDD_HV_IO < 3.6 V and 4.5 V < VDD_HV_IO < 5.5 V” split into 2
rows for the parameters VIHCMOS_H, VIHCMOS, VILCMOS_H, VILCMOS and VHYSCMOS.
– Added reference of Note 6 to VIHTTL, VILTTL, and VHYSTTL.
– VDDE replaced by VDD_HV_IO.
– VDRFTAUT specification, conditions column, added “4.5 V < VDD_HV_IO < 5.5 V”.
– VDRFTCMOS specification, added 3.0 V < VDD_HV_IO < 3.6 V and 4.5 V < VDD_HV_IO < 5.5 V
conditions.
– ILKG_EBI specification: changed “2.5 uA” Max value to “1 uA” and added condition
“0.1*VDD_HV<Vin<0.9*VDD_HV,Tj < 150 °C, 4.5V<VDD_HV<5.5V'. Added second
ILKG_EBI spec with conditions: "Tj < 150 °C, 4.5V < VDD_HV < 5.5V' and Parameter
“Digital input leakage for EBI pad, Vin = 10%/90%.” Value is max 1.5 uA
– Replaced “C” with “P” for ILKG

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Table 74. Revision history(Continued)

Revision Date Description of changes

3 31 Jan 2014 Table 19 (I/O pull-up/pull-down DC electrical characteristics):

(cont’d) – |IWPU| Parameter is Weak pull-up current absolute value
– |IWPU| (P) condition is VIN < VIH = 0.69*VDD_HV_IO, 4.5 V < VDD_HV_IO < 5.5 V
– |IWPU| (P) min is 23 µA, max is —
– Removed: |IWPU| (T) at VIN = 0 V, 3.0 V < VDD_HV_IO < 4.0 V
– Added: |IWPU| (T) at VIN > VIL = 0.49*VDDE, 4.5 V < VDD < 5.5 V
– Added: |IWPU| (T) at VIN > VIL = 1.1 V (TTL), 4.5 V < VDD < 5.5 V
– Added: RWPU (Weak pull-up resistance)
– |IWPD| (P) condition is VIN > VIH = 0.69*VDDE, 4.5 V < VDD < 5.5 V
– |IWPD| (P) min. is —, max is 130 µA
– Removed: |IWPD| (T) at VIN = VDD_HV_IO, 3.0 V < VDD_HV_IO < 4.0 V
– Added: |IWPD| (T) at VIN < VIL = 0.49*VDDE, 4.5 V < VDD < 5.5 V
– Added: |IWPD| (T) at VIN < VIL = 0.9 V (TTL), 4.5 V < VDD < 5.5 V
– Added: RWPD (Weak pull-down resistance)
– Replaced “VIN > VIH” with “VIN < VIH” and “VIN < VIH” with “VIN > VIH” in the first two rows of
|IWPD|
– Replaced VDD with VDD_HV_IO in the conditions column of IWPU and IWPD

Section 3.9.2, I/O output DC characteristics:

– Removed references to EBI in document.

Table 20 (WEAK configuration output buffer electrical characteristics):

– Added footnote All VDD_HV_IO conditions for 4.5V to 5.9V...
– Added footnote Only for VDD_HV_IO_JTAG segment...
– Added new parameter “Propagation delay”.

Table 21 (MEDIUM configuration output buffer electrical characteristics):

– ROH_M condition is 4.5 V < VDD_HV_IO < 5.9 V, Push pull, IOH < 2 mA
– ROL_M condition is 4.5 V < VDD_HV_IO < 5.9 V, Push pull, IOH < 2 mA
– tTR_M condition is CL = 25 pF, 4.5 V < VDD_HV_IO < 5.9 V
– tTR_M condition is CL = 50 pF, 4.5 V < VDD_HV_IO < 5.9 V
– tTR_M condition is CL = 200 pF, 4.5 V < VDD_HV_IO < 5.9 V
– Added footnotes: All VDD_HV_IO... and Only for VDD_HV_IO_JTAG...
– Added new parameter “Propagation delay”.

Table 22 (STRONG configuration output buffer electrical characteristics):

– ROH_S condition is 4.5 V < VDD_HV_IO < 5.9 V, Push pull, IOH < 8 mA;
– ROL_S condition is 4.5 V < VDD_HV_IO < 5.9 V, Push pull
– IOH < 8 mA; tTR_S condition changed to CL = 50 pF, 4.5 V < VDD_HV_IO < 5.9 V
– tTR_S condition changed to CL = 200 pF, 4.5 V < VDD_HV_IO < 5.9 V
– tTR_S condition CL = 25 pF, 4.0 V < VDD_HV_IO < 5.9 V changed to CL = 50 pF,
4.5 V < VDD_HV_IO < 5.9 V
– Added footnotes: All VDD_HV_IO conditions for 4.5V to 5.9V... and Only for
VDD_HV_IO_JTAG segment...
– Added new parameter “Propagation delay”

Table 23 (VERY STRONG configuration output buffer electrical characteristics):

– In rows ROH_V and ROL_V: Conditions for C Parameter changed to VSIO[VSIO_xx] = 1,
Push pull, IOH < 7 mA, Value Min is 30, TYP is 50, Max is 75.
– In row fSYS: Conditions for C Parameter changed to VSIO[VSIO_xx] = 1, CL = 15 pF
– Added footnote: All VDD_HV_IO conditions for 4.5V to 5.9V...

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Table 74. Revision history(Continued)

Revision Date Description of changes

3 31 Jan 2014 – Removed the parameter IDCMAX_V from the table.

(cont’d) – Added new parameter “Propagation delay”.
– Updated the rows pertaining to ROH_V, ROL_V, fMAX_V, tTR_V, tTR20-80, ΣtTR20-80, and
|tSKEW_V|

Section 3.10, I/O pad current specification:

– In Note: In order to ensure...remain below 10%. changed to ...below 50%
– Changed the first note: from “In order to ensure correct functionality for SENT, the sum
of all pad usage ratio within the SENT segment should remain below 50%.” to “In order
to maintain the required input thresholds for the SENT interface, the sum of all I/O pad
output percent IR drop as defined in the I/O Signal Description table, must be below
100%. See the I/O Signal Description attachment.”
– In second note, changed must be below “100%” to must be below “50 %.

Table 24 (I/O consumption):

– Removed footnote: Data based on simulation results...
– Removed all VSIO conditions (VSIO[VSIO_xx] = 1 and VSIO[VSIO_xx] = 0) from
conditions column and added footnote to I/O consumption table title: “I/O current
consumption specifications for the 4.5 V <= VDD_HV_IO <= 5.5 V range are valid for
VSIO_[VSIO_xx] = 1, and VSIO[VSIO_xx] = 0 for 3.0 V <= VDD_HV_IO <= 3.6 V.

Table 25 (Reset electrical characteristics):

– Parameter classification of “VDD_POR “ changed from “C” to “D”
– |IWPU| parameter, changed Min value from “25” to “23” and Max value from “100” to “82”
uA.
– |IWPD| parameter, changed Min value from “25” to “40” and Max value from “100” to
“130” uA.
– New “conditions” added for parameters “|IWPU|” and “|IWPD|”.
Removed “Device under power-on reset 3.0 V < VDD_HV_IO < 5.5 V,
VOL > 0.9 V” under IOL_R

Table 26 (PLL0 electrical characteristics):

– Added rows fPLL0PHI and fPLL0PHI0
– In footnote: PLL0IN clock retrieved... the second sentence now reads Input
characteristics are granted when using XOSC.
– Parameter “tPLL0LOCK” max value changed from “100-110” to “110”.

Table 27 (PLL1 electrical characteristics):

– Changed fPLL1PHI Max Value to 160

Table 28 (External Oscillator electrical specifications):

– Removed “(External Reference)” from parameter column of VILEXT and added notes “This
parameter is guaranteed by design rather than 100% tested” and “Applies to an external clock input and not to
crystal mode”
– Removed notes “CS_EXTAL/CS_XTAL have typical values of 7.5 pF in the QFP packages
of the device” and “CS_EXTAL/CS_XTAL have typical values of 6.0 pF for bare die devices”
– Updated the mIn and max values of QFP and Bare Die and removed notes from them
under CS_EXTAL and CS_XTAL
– Updated the min and max values of VHYS and max values of IXTAL
– Replaced “TJ = 150 °C” with “TJ = -40 °C to 150 °C” and replaced “TJ = 165 °C” with
“TJ = -40 °C to 165 °C” for gm
– Added row VEXTAL

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Table 74. Revision history(Continued)

Revision Date Description of changes

3 31 Jan 2014 Table 29 (Selectable load capacitance):

(cont’d) – Updated the table
– Changed column 2 heading to Capacitance offered on EXTAL/XTAL (Cx and Cy)
– Added Figure 13 (Crystal/Resonator Connections)

Table 30 (Internal RC oscillator electrical specifications):

– Added note “ IRC software trimmed accuracy is performed with the CMU_0 clock
monitor, using the XOSC as a reference. Software trim must be repeated as the device
operating temperature varies in order to maintain the specified accuracy” to δfvar_T
– The minimum and maximum value of parameter “δfvar_SW” changed from “-1” and “+1”
to “-0.5” and “+0.5” respectively.

Table 32 (ADC pin specification):

– Added row CHV_ADC
– Added footnote: For noise filtering, add...
– For parameter VREF_BG_TC, the condition VDD_HV_ADV updated from “5 V ± 10%” to “5
V”.
– For parameter VREF_BG_TC, the condition “TJ =150 °C to 165 °C” updated to “TJ = −40
°C to 165 °C”.
– For parameter VREF_BG_TC, the condition VDD_HV_ADV updated from “5 V ± 10%” to “5
V”.
– For parameter VREF_BG_TC, the condition “TJ =150 °C to 165 °C” updated to “TJ = −40
°C to 165 °C”.
– Changed all “Tj < 40 °C” to “Ta < 25 °C”
– Changed all “Tj < 150 °C” to “Ta < 125 °C”
– Moved VREF_BG_T, VREF_BG_TC and VREF_BG_LR specifications from ADC pin
specification table to Device operating table.
– Removed IBG specification as it is already provided in the dc electrical table.

Table 26 (SARn ADC electrical specification):

– In row VIN, set Parameter Classification as D.
– In row IADCREFH, added Bias Current condition.
– All negative values moved to the Min Value column for parameter “ΔTUE12”.
– Added new condition for “ΔVPRECH” - “VPRECH = VDD_HV_ADR/2 TJ < 150 °C
CTRn[PRECHG] > 2”
– IADCREFL specification: added VDD_HV_ADR_S <= 5.5 V to all modes in condition column.
– All negative values moved to the Min Value column for parameter “ΔTUE12”
– Replaced the conditions column of VALTREF “VALTREF < VDD_HV_IO_MAIN” with
“VALTREF < VDD_HV_IO_MAIN
VALTREF < VDD_HV_ADV”

Table 34 (SDn ADC electrical specification):

– In row VOFFSET, added 3 after calibration conditions.
– In row SNRSE150 for Gain=2, 4 and 8 conditions, set Parameter Classification to T
– In row ZIN conditions are now: GAIN = 1, fADCD_M = 16MHz; GAIN = 16, fADCD_M =
16MHz
– In row tLATENCY Max Value is now 2*δGROUP + 6/fADCD_S
– Added row IBIAS.
– Added footnote: extended bench validation...
– Split footnote S/D ADC... degrades by 9 dB into 2 footnotes:
• S/D ADC... degrades by 3 dB
• S/D ADC... degrades by 9 dB

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Table 74. Revision history(Continued)

Revision Date Description of changes

3 31 Jan 2014 – Updated footnote The 640 MHz frequency is achieved...

(cont’d) – fADCD_M specification, removed footnote “VINM is the input voltage applied to the
negative terminal of the SDADC.”
– fADCD_M specification, changed parameter from “S/D clock” to “S/D modulator input
clock”
– Changed fADCD_M Min from “—” to “4”.
– RESOLUTION specification, added footnote “When using a GAIN setting of 16, the
conversion result will always have a value of zero in the least significant bit. The gives
an effective resolution of 15 bits.”
– |δGAIN| specification, changed Max value from “0.1” % to “5” mV, “0.25” % to “7.5” mV,
and “0.5” % to “10” mV.
– Common mode rejection ratio parameter change symbol from “—” to “Vcmrr”
– Anti-aliasing filter parameter, changed symbol “—” to “RCaaf”
– Stop band attenuation parameter, changed “symbol “—” to “Frolloff”.
– For tLATENCY, tSETTLING, and tODRECOVERY specifications, changed max from 2
* &GROUP to “2 * &GROUP + 7 * fADCD_S”.
– Changed footnote 9 in “full input range (specified by Vin)” to “full input frequency range.”
– Changed footnote 11 “0.873” dB to “0.087” dB.
– Changed footnote from “The ±1% passband ripple specification is equivalent to 20 *
log10 (0.99) = 0.87 dB.” to “The ±1% passband ripple specification is equivalent to 20
* log10 (0.99) = 0.087 dB.
– tSTARTUP renamed as tPOWERUP
– tLATENCY renamed as tSTARTUP
– A new parameter tLATENCY added
– Max value of δGROUP modified for all values of OSR
– new condition and max value added for tSTARTUP, tLATENCY, tSETTLING and tODRECOVERY.
– tPOWERUP renamed as tSTARTUP.
– tSTARTUP row removed.
– Description of tLATENCY changed from “Latency between input data and converted data”
to “Latency between input data and converted data when input mux does not change”.
– Max value of tLATENCY changed from “2*δGROUP + fADCD_S” to “δGROUP + fADCD_S”.
– Maximum value of parameter “GAIN” changed from 16 to 15.
– Replaced the “—” in the conditions column of fADCD_S with “TJ < 150 °C”
– Replaced “2*δGROUP” with “δGROUP” in the max column of tLATENCY
– For max value of |δGAIN| row, replaced “1” with “1.5”

– Added one new table: Table 34 (Electrical specifications)

Table 35 (Temperature sensor electrical characteristics):

– In row ITEMP_SENS max value changed to 700 µA
– In row TSENS changed Parameter classification to P
– In row TACC added condition TJ < 165 °C
– The minimum value of “TACC” changed from 7 to “-7”.

Table 36 (LVDS pad startup and receiver electrical characteristics):

– |ΔVI| specification, Differential input voltage parameter, added footnote 12 “The
LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to
ensure proper LFAST receive timing.”
– max value of tSTRT_BIAS changed from 0.8 µs to 4 µs
– max value of tPD2NM_TX changed from 0.55 µs to 2.75 µs

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Table 74. Revision history(Continued)

Revision Date Description of changes

3 31 Jan 2014 Table 37 (LFAST transmitter electrical characteristics):

(cont’d) – CL (External lumped differential load capacitance) is 10.0 pF
– In row |VOD| removed the delta symbol removed “+/-” from each value
– Updated tTR Parameter description
– CL specification, changed max CL for VDD_HV_IO = 4.5 V from “10” to '”12” pF.
|VOD| changed Min value “100” to “110”

Table 38 (MSC/DSPI LVDS transmitter electrical characteristics):

– CL (External lumped differential load capacitance) is 50 pF
– In row |VOD| removed the delta symbol removed “+/-” from each value
– Updated tTR Parameter description

Table 39 (LFAST PLL electrical characteristics):

– fVCO (PLL VCO frequency) nominal value is 640 MHz

Table 40 (Aurora LVDS electrical characteristics):

– In row Transmitter Differential Terminating resistance changed symbol to RV_L_Tx.
– In row CAC
• Parameter changed to Clock Receive Pin External AC Coupling Capacitance;
• Min Value changed to 100 pF
• Max Value changed to 270 pF
– In row Receiver Differential Terminating resistance
• changed symbol to RV_L_Rx
• removed condition VDD_HV_IO_BD = 5 V±10%
– Unit of measurement of FRX changed from “GHz” to “Gbps”.
– Removed VDD_HV_IO_BD and VDD_LV specifications as they are supplied in the device
operating conditions table.
– Changed “CAC“specification name to “Cac_clk“.
– Added specification “Cac_tx”.

Figure 22 (Voltage regulator capacitance connection): The following note “The pins
positions correspond to the pins positions in the pins package” is added.

Table 41 (Device Power Supply Integration):

– Changed table name to Device Power Supply Integration
– Added Parameter Classification C column
– Added new parameter “IDDCLAMP”.
– Minimum capacitance of parameters “CDECREGn”, “CDECHV” and “CDECFLA” changed
from 10 nF to 30 nF
– Replaced “—” with “VDD_LV/VSS pair” in the conditions column of CDECREGn
– Replaced “Decoupling capacitance ballast” with “Relay capacitance for ballast power-
up” in the parameter column of CDECBV and replaced “VDD_HV_PMC/VSS pair” with “—” in
the conditions column
– Replaced “domain loading” with “external capacitance loading” in the parameter column
of IDDCLAMP and updated the min and max values.
– In IMREGINT removed note “By simulation” and changed C from “T” to “D”
– Changed the min and typ values of CDECFLA

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Table 74. Revision history(Continued)

Revision Date Description of changes

3 31 Jan 2014 Table 42 (Voltage monitor electrical characteristics):

(cont’d) – VLVD108 specification, changed Min value from “1080” to “1120”
– VLVD108 specification, changed Max value from “1140” to “1170”
– VLVD108Changed Parameter name “LV internal supply low voltage monitoring” to “Core
LV internal supply low voltage monitoring” and added note to conditions “This is
combination of LVD108_C, P, and F. Min is from min value of LVD108_F, and P which
is the lowest one. Max is the max value of LVD108_C which is the highest one of three.”
– VPORUP_LV Falling voltage (power down) condition, added footnote “assume all of LVDs
on LV supplies disabled”.
– Added “HVD140 does not cause reset” at end of footnote “HVD is released after
tVDRELEASE temporization when lower threshold is crossed, HVD is asserted
tVDASSERT after detection when upper threshold is crossed.”
– VLVD295 Rising voltage condition changed Max value “3100” to “3120”.
– VLVD295 Falling voltage condition changed Min value “2950” to “2920” and Max value
“3080” to “3100”.
– VHVD360 Rising voltage condition changed Min value “3420” to “3435” and Max value
“3610” to “3650”.
– VHVD360 Falling voltage condition changed Min value “3400” to “3415”.

Table 44 (Functional terminals state during power-up and reset):

– Replaced “Weak pull-down” with “Weak pull-up” for ESR1 in Power-up, reset, and
default states
– Replaced “ERROR” with “ERROR[0]”
– Updated note 6
– ESR1 POWER-UP Pad State changed to Weak pull-down.

Table 45 (Flash memory program and erase specifications): Updated the values.

Table 46 (Flash memory Life Specification): Replaced “K” with “k” in the unit column

Section 3.18.1, Flash read wait state and address pipeline control settings: Added this
section

Moved I2C AC timing specification after section “UART timing”

Moved “UART timing” section after “PSI5 timing”

Table 48 (K2 Flash memory program and erase specifications(pending silicon

characterization))
– Complete rework of table and contents.
– In row tdwprogram:
• removed Initial max parameter classification
• Lifetime max changed to 650
– In row tpprogra:
• Initial max parameter classification removed
– Added row tpprogrameep [KGD]
– In row tqprogram:
• Typical end of life changed to 396
– Added row tqprogrameep [KGD]

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Table 74. Revision history(Continued)

Revision Date Description of changes

3 31 Jan 2014 – Differentiated rows t16kprogrameep with [KGD] and [Packaged part]
(cont’d) – In row t16kprogrameep [Packaged part]:
• Typ value changed to 31
• Initial max 25 °C changed to 40
• Initial max All temp changed to 58
• Typical end of life changed to 64
– In row t16kprogrameep [KGD]:
• Typ value changed to 40.5
• Initial max 25 °C changed to 52.5
– In row tpr:
• Characteristics footnote changed to Rate computed based on 256K sectors.
– In row tfferase:
– Characteristics footnote changed to Only code sectors, not including EEPROM
– In row tPSRT:
• Characteristics footnote changed to Time between suspend resume and...
– In row tPSUS:
• Initial max 25 °C value removed
– In row tESUS:
• characteristics footnote changed to Timings guaranteed by design.
• Initial max 25 °C value removed
– Added row tAICOP
– Footnote: For memory sizes > 1 MB and... changed to Actual hardware programming
times...

Added new Section 3.19.2, DSPI timing with CMOS and LVDS pads

Table 48 (JTAG pin AC electrical characteristics): Added footnote “JTAG timing specified
at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and maximum loading per pad type as specified in
the I/O section of the data sheet.”

Table 49 (Nexus debug port timing):

– tTCYC (TCK cycle time) min value changed to 2
– Header “1K cycles” modified to “1k cycles”.
– Footnote 1 changed to “Nexus timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and
maximum loading per pad type as specified in the I/O section of the data sheet.”
– Added (TDO sampled on posedge of TCK) to tTCYC in the characteristics column and changed
the min value from “36” to “40”

Section 3.19.4, FlexRay timing:

Added new section that includes “DSPI CMOS Slave timing - Modified Transfer Format
(MTFE = 1)” table and timing diagrams “DSPI Slave Mode - Modified transfer format
timing (MFTE = 1) — CPHA = 0” and “DSPI Slave Mode - Modified transfer format
timing (MFTE = 1) — CPHA = 1”.

Table 58 (DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)):
– Changed table title “(MTFE = 1)” to “(MTFE = 0/1)”
– Added footnote 1 to table title "DSPI slave operation is only supported for a single
master and single slave on the device. Timing is valid for that case only."

Figure 40 (DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1)—CPHA = 0):
Changed figure title “(DSPI Slave Mode - Modified transfer format timing (MFTE = 1) —
CPHA = 0) to “(DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA
= 0)”.

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Table 74. Revision history(Continued)

Revision Date Description of changes

3 31 Jan 2014 Figure 41 (DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1)—CPHA = 1):
(cont’d) Changed figure title “(DSPI Slave Mode - Modified transfer format timing (MFTE = 1) —
CPHA = 1)” to “(DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA
= 1)

Figure 59 (144 LQFP-EP package mechanical drawing (1 of 3)), Figure 60 (144 LQFP-
EP package mechanical drawing (2 of 3)), Figure 61 (144 LQFP-EP package mechanical
drawing (3 of 3)): Updated the figures.

Figure 69 (172-pin FusionQuad® TQFP (1 of 4)), Figure 70 (172-pin FusionQuad® TQFP

(2 of 4)): Updated the figures.
Added 2 new figures: Figure 71 (172-pin FusionQuad® TQFP (3 of 4)), Figure 72 (172-
pin FusionQuad® TQFP (4 of 4)).

In <Cross Refs>Equation 7 description,

TT updated to TB and ΨJT updated to ΨPB as mentioned in the equation.

Table 59 (RMII serial management channel timing):

– Added note “RMII timing is valid only up to a maximum of 150 oC junction temperature”
and applied K2 tag
– Added note “Output parameters are valid for CL = 25 pF, where CL is the external load
to the device. The internal package capacitance is accounted for, and does not need
to be subtracted from the 25 pF value” to the value column and applied K2 tag

Table 60 (RMII receive signal timing): Added note “RMII timing is valid only up to a
maximum of 150 oC junction temperature”

Table 61 (RMII transmit signal timing):

– R6 (REF_CLK to TXD[1:0], TX_EN valid) Max Value changed to 16 ns.
– Added footnote: Output parameters are valid for...
– Added note “RMII timing is valid only up to a maximum of 150 oC junction temperature”
– Updated table footnotes

Table 64 (RxD input characteristics): Added footnote 1 “FlexRay RxD timing is valid for all
input levels and hysteresis disabled.”

Table 71 (Thermal characteristics for eTQFP144):

– All table Min and Max values revised.

Table 84 (Thermal characteristics for FQ172(144/28) FusionQuad® package,):

– All table Min and Max values revised.

Table 72 (Thermal characteristics for eLQFP176):

– All table Min and Max values revised.

Table 86 (Thermal characteristics for FQ216(176/40) FusionQuad® package,):

– All table Min and Max values revised.

Section 4, Package characteristics: Added Table 70 (Package case numbers)

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Table 74. Revision history(Continued)

Revision Date Description of changes

4 19 Dec 2014 Section 1.1, Document overview:

– Added note.

Table 2 (MPC5744K/SPC574Kx device feature summary):

– Replaced “SIMD” with “LSP” in I/O processor.
– Added cache row to I/O processor.
– Added 140 MHz to Main processor frequency.
– Added 70 MHz to I/O processor frequency.
– Replaced “2 x 4 x 256-bit” with “2 x 2 x 256-bit” in Flash memory fetch accelerator.
– Replaced M_CAN/M_TTCAN with CAN (M_CAN/M_TTCAN) || 3 (2/1)x.
– Replaced 2/1 with 3 (2/1).
– Added RMII to Ethernet.
– Replaced “365 sources” with “360 sources” in Interrupt controller
– Removed 1.2 V from External power supplies.
– Moved notes from 144 LQFP-EP/eTQFP1445 and 176 LQFP-EP/eLQFP176 to
172-pin FusionQuad® and 216-pin FusionQuad® in Packages.

Figure 1 (Block diagram):

– Changed “Calibration Bus” to “Calibration Interface”.

Figure 2 (Periphery allocation):

– Replaced SRX_0 with SENT_SRX_0 and SRX_1 with SENT_SRX_1.

Section 1.5, Feature overview: Replaced SIUL with SIUL2.

– Removed “UART” from “UART Serial Boot Mode Protocol”.
– Replaced “Boot Assist Module (BAM)” with “Boot Assist Flash (BAF)”.
– Removed LIN from UART / LIN.
– Removed FlexRay.

Figure 3 (144-pin QFP and 172-pin FQ configuration (top view)):

– Replaced VDD_LV_BD with NC/VDD_LV_BD and added a note on pin 10.
– Removed FQ from the second note.

Figure 4 (176-pin QFP and 216-pin FQ configuration (top view)):

– Added note on pins 10 and 154.
– Replaced VDD_LV_BD with NC/VDD_LV_BD and added a note on pin 10.

Section 2.2.1, Power supply and reference voltage pins:

– Added a note.

Table 4 (LVDSM pin descriptions):

– Changed the signals of the port pins PA[8], PA[7], PA[9], and PA[5] in “Debug LFAST”
functional block.

Section 3.2, Parameter classification:

– Removed note.

Table 6 (Absolute maximum ratings):

– In Notes, Changed TJ= 165 °C to 125 °C.
– Changed the classification of TSTG from “C” to “T”.
– Changed the classification of STORAGE from “C” to “—”.
– Added note to VDD_HV_ADV.

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Table 74. Revision history(Continued)

Revision Date Description of changes

4 19 Dec 2014 Table 9 (Conducted emissions testing specifications):

(cont’d) – Replaced EXTCLK with SYSCLK in External clock.

Table 12 (Device operating conditions):

– In footnote (“The PMC supply voltage...”), replaced cross-reference to PMC operating
conditions and external regulators supply voltage table, which has been removed, with
a text reference to the VDD_HV_PMC specification.
– Removed VDD_HV_IO_FLEXE.
– For VDD_HV_FLA replaced “SR” with “CC”.
– Replaced “P” with “C” in TJ for 165 °C.
– For VDD_HV_IO_JTAG replaced “P” with “C” and added another row for “P”.
– For VDD_HV_ADV, replaced “D” with “P” and replaced “P” with “C”.
– For VDD_HV_ADR replaced “P” with “C” and added another row for “P” (SD ADC supply
reference voltage).
– For VDD_HV_ADR replaced “P” with “C” and added another row for “P” (SARADC
reference).
– Removed VRAMP_LV.

Table 13 (Emulation (buddy) device operating conditions):

– Replaced “P” with “C” in TJ_BD for 165 °C.
– Removed VRAMP_BD.
– Added VRAMP_LV_BD and VRAMP_HV_BD.

Table 16 (DC electrical specifications):

– For IDDAPP replaced “TJ < 144 °C” with “TJ < 142 °C”.
– For IDDAPP replaced “TJ < 165 °C” with “fSYS = 140 MHz, TJ < 165 °C”.
– For IDD_MAIN_CORE_AC replaced “200 MHz” with “fSYS = 160 MHz”.
– For IDD_CHKR_CORE_AC replaced “160 MHz” with “fSYS = 160 MHz”.
– For IDDAR replaced “At 55 °C” with “TJ = 165 °C”.
– For IDDOFF replaced “P” with “T”.
– For VREF_BG_LR replaced all “P” with all “T”.
– Removed note from maximum value of TJ = 150 °C condition.
– Replaced IDDAPP with IDDMAX in the note below the table.

Section 3.17.2, Main voltage regulator electrical characteristics:

– Added text “internally connected to VDD_HV_IO_MAIN supply” to the first line.

Section 3.18.1, Flash read wait state and address pipeline control settings:
– Replaced C55FMC with Flash.

Table 18 (I/O input DC electrical characteristics):

– For ILKG_MED added 4.5 V < VDD_HV < 5.5 V
VSS_HV < VIN < VDD_HV in the “conditions” column.
– For VILAUT replaced maximum value “2.2” with “2.1” and added a note to it.
– For VHYSAUT replaced minimum value “0.5” with “0.4” and added a note to it

Table 19 (I/O pull-up/pull-down DC electrical characteristics):

– IWPU, IWPD: revised these specifications.

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Table 74. Revision history(Continued)

Revision Date Description of changes

4 19 Dec 2014 Figure 9 (I/O output DC electrical characteristics definition):

(cont’d) – Updated the figure. tPD10-90 (rising edge) replaced by tPLH (rising edge) and tPD10-
90 (falling edge) replaced by tPHL (falling edge). Added 50% dotted line.

Table 20 (WEAK configuration output buffer electrical characteristics):

– Replaced the minimum value of ROH_W with “520” from “560”.

Table 22 (STRONG configuration output buffer electrical characteristics):

– Added |tSKEW_S| parameter.

Table 23 (VERY STRONG configuration output buffer electrical characteristics):

– Added IDCMAX_VS specification.

Table 25 (Reset electrical characteristics):

– For VHYS, replaced minimum value “300” with “275”.
– For WFNMI, replaced maximum value “20” with “15”.

Table 26 (PLL0 electrical characteristics):

– In fPLL0IN added a second note to parameter column.

Table 27 (PLL1 electrical characteristics):

– Removed tPLL1JIT.
– Updated all the minimum and maximum values of gm.
– Removed note 6 from below the table.

Table 28 (External Oscillator electrical specifications):

– In gm, changed the minimum and maximum frequencies.

Table 30 (Internal RC oscillator electrical specifications):

– Moved the footnote from δfvar_T to δfvar_SW.
– Updated the description of δfvar_SW.
– Removed IAVDD5.
– Removed IDVDD12.

Table 26 (SARn ADC electrical specification):

– Added ΔTUE10.
– For VALTREF replaced “P” with “C” and added another row for “P”.
– For IADV_S, reorganised the notes and added a note to “Power Down mode”.
– Changed the minimum and maximum value of DNL.
– Removed INL.
– Revised condition entries for tADCPRECH and ΔVPRECH.

Table 34 (SDn ADC electrical specification):

– Updated SNRSE150.
– In Vcmrr specification: changed min value to 54 dB (was 20 dB).
– Replaced “Vcmrr” with “CMRR”.
– δGROUP specification: changed OSR = 75 max value to 699 Tclk (was 646), changed
OSR = 96 max value to 949.5 Tclk (was 946.4).
– VOFFSET: Changed parameter name to “Input Referred Offset Error” (was “Conversion
Offset”) and added footnote (“Conversion offset error must be...”).

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Table 74. Revision history(Continued)

Revision Date Description of changes

4 19 Dec 2014 – The maximum value changed from “15” to “16” for the maximum value for GAIN.
(cont’d) – Added note to tLATENCY and tSETTLING.
– SNRSE150 specification: changed footnote to “This parameter is guaranteed by bench
validation with a small sample of typical devices, and tested in production to a value of
6 dB less” (was 2 dB less).

Removed the Table : Electrical specifications.

Table 42 (Voltage monitor electrical characteristics):

– Changed the minimum and maximum value of VLVD108.
– Updated the minimum and maximum value of VPORUP_HV.

Table 47 (Flash memory RWSC configuration):

– Replaced “40 – 160 MHz” with “140 – 160 MHz” in the Platform Frequency column.

Table 52 (DSPI channel frequency support):

– Added CMOS Slave mode.

Table 64 (RxD input characteristics):

– Revised footnote (“FlexRay RxD timing is valid. . .”).

Section 3.19.8, GPIO delay timing:

– Added this section.

Table 65 (Order codes):

– Replaced EMU574K72K5-AA, EMU574K72K7-AA with EMU574K72K5-BB and
EMU574K72K7-BB respectively.
– Removed figure “Emulation device code structure EMU574M72K5-AA”.

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Table 74. Revision history(Continued)

Revision Date Description of changes

5 30 March 2015 Following are the changes:

Table 6 (Absolute maximum ratings):

In the classification column, replaced all “C” with “D”.

Table 12 (Device operating conditions):

For VDD_LV, replaced “D” with “P” and “P” with “D” in the respective rows of the
classification column.
Replaced VDD_HV_ADR with VDD_HV_ADR_D, and VSS_HV_ADR with VSS_HV_ADR_D.

Table 13 (Emulation (buddy) device operating conditions):

Replaced “C” with “T” in the classification column of “Data trace frequency”.

Table 16 (DC electrical specifications):

Replaced “C” with “T” in the classification column of 165 oC parameters.
Replaced maximum value of “350” with “450” for IDD parameter.
Replaced maximum value of “370” with “470” for IDDPE parameter.Replaced maximum
values of “260” with “340” and “280” with “360” for IDDAPP parameter.Updated IDDAR.
Added note to ISPIKE.

Table 18 (I/O input DC electrical characteristics):

Updated note in maximum value of VIHAUT.Replaced 4.0 with 3.6 in note below the table:
“3.0 V < VDD_HV_IO < 4.0 V”

Table 19 (I/O pull-up/pull-down DC electrical characteristics):

Added maximum value of “65” to |IWPU|.
Added maximum value of “50” to |IWPD|.
Added condition for RWPU and RWPD.

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Table 74. Revision history(Continued)

Revision Date Description of changes

5 30 March 2015 Table 25 (Reset electrical characteristics):

(cont’d) Replaced “P” with “C” in the classification column of IOL_R parameter.
Replaced “12” with “8” in the minimum value of IOL_R parameter.
Updated |IWPU| and |IWPD| parameters.
Added “C” classification to the second row of IOL_R.

Table 26 (PLL0 electrical characteristics):

Added fPLL0FREE parameter.

Table 27 (PLL1 electrical characteristics):

Added fPLL1FREE parameter.

Table 28 (External Oscillator electrical specifications):

Updated the classification and condition values of gm.
Removed the first note.

Table 32 (ADC pin specification):

Added ΣIADV parameter.

Table 26 (SARn ADC electrical specification):

Replaced “C” with “T” in the first row of the classification column of IADCREFH parameter
and added a footnote to the maximum value.
Updated IADV_S parameter.
Added parameter ΣIADR_S.

Table 34 (SDn ADC electrical specification):

Replaced “P” with “T” in the classification column of IADV_D parameter and .
Replaced maximum value of “15” with “30” for ΣIADR_D parameter, and added a footnote
to the parameter column.

Added IADCS/D_REFH parameter.

Table 35 (Temperature sensor electrical characteristics):

Replaced “P” with “C” in the first row of classification column of TACC parameter.
Replaced “P” with “T” in the first row of classification column of TSENS parameter.

Table 37 (LFAST transmitter electrical characteristics):

Replaced “C” with “T” in the classification column of ILVDS_TX parameter.

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Table 74. Revision history(Continued)

Revision Date Description of changes

5 30 March 2015 Table 39 (LFAST PLL electrical characteristics):

(cont’d) Replaced “P” with “T” in the classification column of fVCO parameter and updated note 2.

Table 38 (MSC/DSPI LVDS transmitter electrical characteristics):

Replaced “C” with “T” in the classification column of ILVDS_TX parameter.

Table 40 (Aurora LVDS electrical characteristics):

For |ΔVOD_LVDS| parameter, removed the “+” from the values.

Table 41 (Device Power Supply Integration):

Replaced maximum value of “300” with “350” for IDDMREG parameter.

Table 59 (RMII serial management channel timing):

For M10 parameter, replaced the minimum value of “0” with “-10”.
For M13 parameter, replaced the minimum value of “-10” with “10”.
Updated the third footnote.

Table 64 (RxD input characteristics):

Removed “Automotive and” from table footnote.

Table 71 (Thermal characteristics for eTQFP144):

Added Pd parameter.

Table 72 (Thermal characteristics for eLQFP176):

Added Pd parameter.

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Table 74. Revision history(Continued)

Revision Date Description of changes

5 01 July 2015 Following are the changes:

Removed all KGD related information and “TJ = 165 oC”.

Table 2 (MPC5744K/SPC574Kx device feature summary):

Removed 140 MHz from Main processor frequency.
Removed 70 MHz from I/O processor frequency.

Table 12 (Device operating conditions):

Updated VDD_LV.
Changed the description of TJ to “Junction Temperature” and description of TA to
“Ambient temperature”.

Table 22 (STRONG configuration output buffer electrical characteristics):

Updated the minimum values of tTR_S.

Table 23 (VERY STRONG configuration output buffer electrical characteristics):

Updated the minimum values of tTR_V.

Table 25 (Reset electrical characteristics):

Replaced the minimum value of “11” with “8” for IOL_R parameter.

Table 28 (External Oscillator electrical specifications):

For VEXTAL, replaced the maximum values of “1.6” with “1.8”. Removed the second row.

Table 26 (SARn ADC electrical specification):

Updated the minimum and maximum values of VALTREF parameter.
Added IADCSAR_REFH and IADCSAR_REFL.
Removed table footnote “Values are subject to change (possibly improved to ±2 LSB)
after characterization.”

Table 34 (SDn ADC electrical specification):

Updated the minimum, typical, and maximum values of ZIN for GAIN = 1.

Table 35 (Temperature sensor electrical characteristics):

Removed the second row of TACC parameter.

Table 36 (LVDS pad startup and receiver electrical characteristics):

Removed VHYS parameter.
Replaced “P” with “T” in the classification column of |ΔVI| parameter.

Table 41 (Device Power Supply Integration):

Replaced minimum value of “1.20” with “1.14” for VMREG parameter (After trimming).

Table 45 (Flash memory program and erase specifications), Table 46 (Flash memory Life
Specification), and Table 47 (Flash memory RWSC configuration):
– Removed texts “pending silicon characterization” and “pending silicon Qualification”
from table headings.

Table 42 (Voltage monitor electrical characteristics):

Replaced minimum value of “1400” with “1390” for VHVD145 parameter.

Table 43 (Device supply relation during power-up/power-down sequence):

In the third note below the table, added VDD_HV_ADR supply.

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SPC574Kx Revision history

Table 74. Revision history(Continued)

Revision Date Description of changes

6 28 July 2017 RPNs “SPC574K70E5, SPC574K72E5” on the cover page updated to “SPC574Kx”
RPN “SPC574Kxx” updated to “SPC574Kx” throughout the document
Updated attached I/O excel sheet “SPC574Kx_IO_Signal_Table.xlsx”
Table 2: MPC5744K/SPC574Kx device feature summary:
– “CAN (M_CAN/M_TTCAN)” updated to “M_CAN (ISO CAN-FD/TTCAN)”
– Footnote added for 5V External power supply.
Section 1.5: Feature overview:
– Reworded the Boot Assist Flash feature.
– “6 separate 12 bit SAR analog converters” updated to “1 supervisor 12-bit SAR analog
converter and 4 separate fast 12-bit SAR analog converters”
– Added feature “One Ethernet controller....IEEE 802.3-2008”
– Reworded feature MCAN
– Reworded feature Power supply voltage
Table 34: SDn ADC electrical specification:
– Added new parameters “ZDIFF”, “ZCM”, “RBIAS” and “ΔVINTCM”
– Values of parameter “RBIAS” updated
Added Figure 17: S/D impedance generic model
Figure 81: Product code structure:
– From custom version, “2 = FlexRay” removed
– From Frequency, “4 = 120MHz” removed
– Added footnote “Order on 2M-Byte part numbers...”
– Added footnote “Features (eg., flash, RAM....”

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