1. (4%) Which of the following statement(s) is/are true?

(a) High-level language source code typically generates more RISC machine instructions than CISC
machine instructions.
(b) Compliers are generally good at generating fast code from simple instructions, rather than
complete ones.
(c) Merging segments and resolve location-dependent external references are the responsibilities of
assemblers.
(d) The rule stating that the performance enhancement possible with a given improvement is limited
by the amount that the improved feature is used is called Moore’s law.

Sol. (a)(b)

2. (4%) For each design principle below, please give one MIPS instruction as an example and explain
why it follows the principles.
(a) Smaller is faster.
(b) Make the common case fast.

Sol.

(a) add, 3 operands are all registers because registers are faster than memory.

(b) addi, adding small constant is common in software.

3. (3%) Which of the following data have identical binary representation in memory no matter little
endian or big endian is used?
(a) 0xABCAACBA (b) 0xABCDCDAB (c) 0xABCDABCD

Sol. (b)

4. (17%) Consider two different implementations, M1 and M2, of the same instruction set. There are
three classes of instructions classes (A, B, and C) in the instruction set. M1 has a clock rate of 80MHz
and M2 has a clock rate of 100MHz. The average number of cycles for each instruction class and their
radio (for a typical workload) are shown in the table below). Please answer the questions below.
(a) (4%) What’s the average CPI of M1 and M2, respectively?
(b) (4%) What’s the MIPS of M1 and M2, respectively? (MIPS: Millions of Instructions Per Second)
(c) (3%) Which one is faster? (M1 or M2)
(d) (3%) For M2, what’s the speedup if we reduce the CPI of class-A instructions by 75%?
(e) (3%) For M2, suppose we can only improve class-B instruction. By how much CPI we should
reduce so that we can have a speedup of 2?

Instr. class M1 80MHz M2 100MHz Ratio of

CPI of instr. class CPI of instr. class instr. class
A 1 2 60%
B 2 3 30%
C 4 4 10%
Sol.

(a) CPI of M1: 1.6, CPI of M2: 2.5

(b) MIPS of M1: 50, MIPS of M2: 40
(c) M1 is faster.
(d) 1.5
(e) Impossible.

5. (6%) Suppose you have a machine which executes a program spending 50% of execution time in
floating-point multiply, 20% in floating-point divide, and 30% in integer instructions.
(a) What’s the speedup relative to the original machine if we make the integer instructions run 3 times
faster?
(b) Assume we not only can make integer instr. run 3 times faster, but also can improve floating-point
multiply. How much faster we should make the multiply instructions in order to make the overall
speedup become 2?

Sol.

(a) 100 / (50+20+30/3) = 100/80 = 1.25

(b) 50/x + 20 + 30/3 = 100/2  x = 2.5

6. (3%) Please write the code using the shortest sequence of MIPS instructions to put the 32-bit number
0x12345678 into register $t0.

Sol. lui $t0, 0x1234

ori $t0, $t0, 0x5678 (可以不用$t0，但兩個指令要用相同的)

7. (4%) Given the initial values of $t0 and $t1 on the right side, what’s
the value of $t2 after the execution of code sequence below? (please $t0 = 0xAAAAAAAA
write the answer in Hex) $t1 = 0x22222222
srl $t2, $t0, 3
or $t2, $t2, $t1

Sol. 0x37777777 (no sign extension)

8. (6%) Assume the PC is at 0x0000 0060, can we use a single branch instr. to get to addresses below,
respectively? (a) 0x0040 0000 (b) 0xFFFF F000 (c) 0x0000 8062

Sol. (a) No (b) Yes (c) No ((c) is no because 0x00008062 is not a multiple of 4)

9. (6%) Assume the PC is at 0x0000 0060, can we use a single jump instr. to get to addresses below,
respectively? (a) 0x0800 0000 (b) 0xFFFF F000 (c) 0x0004 0062

Sol. (a) Yes (b) No (c) No ((c) is no because 0x00040062 is not a multiple of 4)
10. (10%) Compiling a while loop in C language.
Assume i and k correspond to $s3 and $s5, and the base of the array save is in $s6. Write the rest of
other MIPS instructions (A~E) corresponding to the C code: (Hint: use a nor instruction to perform
not.)

Loop: sll $t1, $s3, 2

add $t1, $t1, $s6
while (save[i] ≥ k) { lw $t0, +++(A)+++
save[i] = ~save[i]; slt $t2, +++(B)+++
(C)++++++++++++++++
(D)++++++++++++++++
i++; sw +++(E)+++
} addi $s3, $s3, 1
j Loop
Exit:
Sol.

Loop: sll $t1, $s3, 2

add $t1, $t1, $s6
lw $t0, 0($t1)
slt $t2, $t0, $s5
bne $t2, $zero, Exit
nor $t0, $t0, $zero (or $t0)
sw $t0, 0($t1)
addi $s3, $s3, 1
j Loop
Exit:
11. (10%) The code sequence implements a factorial fact:
function. addi $sp, $sp, 8
(a) (4%) The implementation contains mistakes. Please sw $ra, 4($sp)
point out all the logic errors or the mistakes that sw $a0, 0($sp)
violate the MIPS call convention in the code slti $t0, $a0 1
sequence. (Hint: two types of errors.) beq $t0, $zero, L1
(b) (3%) Assume all the errors have been fixed and the addi $v0, $zero, 1
code was called by “jal fact” in main program with addi $sp, $sp, -8
$a0 set to 10 before the instruction “jal” is called. jr $ra
How many instructions will be executed before the L1: addi $a0, $a0, -1
execution went back to the main program? jal fact
(c) (3%) For above (b), what’s the content of $v0 when lw $ra, 0($sp)
the instruction “mul” indicated by “A” has lw $a0, 4($sp)
completed its execution of the 5th time? addi $sp, $sp, -8
A mul $v0, $a0, $v0
jr $ra

Sol.

(a) 1. The order of storing and restoring $ra and $a0 is incorrect
(stack 是 last in first out，所以 push 的順序是 $ra, $t0，pop 的順序則要是 $a0, $ra)
2. stack grows in wrong direction. ($sp 在 push 時要減，pop 時要加)
(b) 128
(c) 120

12. (15%) Given the sequence of MIPS machine codes below.

(a) (8%) Please convert the MIPS machine codes at label B, D, G, I into MIPS assembly instructions.
(b) (3%) Please convert the MIPS instruction at label J into MIPS machine code (in Hex format).
(c) (4%) Assume $s2 and $s3 contain 8 and 3, respectively, before the code runs. What’s the content
of register “v0” after the execution of the code below?

address

8000 4400h A: add $t0, $zero, $zero

B: 0001 0010 0100 0000 0000 0000 0000 01112
C: addi $s1, $zero, 10
D: 0001 0010 0010 0000 0000 0000 0000 00112
E: add $t0, $t0, $s3
F: addi $s1, $s1, -1
G: 0000 1000 0000 0000 0001 0001 0000 00012
H: addi $s2, $s2, -1
I: 0000 1000 0000 0000 0001 0001 0000 00112
J: add $v0, $t0, $zero

add sll slt add lw sw beq bne j $t0 $s $v

 i 0 0
op 0 0 0 8 35 45 4 5 2 Reg 8 16 6
#
funct. 32 0 24

Sol.

(a) B: beq $s2, $zero, J

D: beq add $t0, $zero, $zero $s1, $zero, H
G: j B L2: beq $s2, $zero, J
I: j D addi $s1, $zero, 10
(b) 0x01003020 L1: beq $s1, $zero, H
(c) v0 = 8*10*3 = add $t0, $t0, $s3 240 (題目兩個 j 位址寫反
addi $s1, $s1, -1
了 (變無窮迴圈)， 送分)
j L1
8000 4400h
E1: addi $ s2, $s2, -1
j L2
E2: add $v0, $t0, $zero
13. (12%) Given a 32-bit ALU and the details of its
corresponding 1-bit ALU below. (a) (4%) Please show how
to implement slt function and (b) (8%) Please show the
values of control signals for each function list in the table
below.

Ainvert Binvert op (2bits)

SUB
NOR
1-bit ALU (bit 0 ~ bit 30)
NAND
SLT

ALU 31

32-bit ALU
Sol.

(a) 1. Connect the adder output of ALU31 to the “less” input of ALU0.
2. The “less” input of ALU1~ALU31 are all zero.
(b) SUB: 0 1 10
NOR: 1 1 00
NAND: 1 1 01
SLT: 0 1 11