Synopsys EDA Tool Flow for

Front-End Digital IC Design

Professor: Sci.D., Professor

Vazgen Melikyan

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Course Overview

 Digital Design Flow

 2 lectures
 Logic Simulation
 2 lectures
 Logic Synthesis
 4 lectures
 Formal Verification
 4 lectures
 Static Timing Analysis
 4 lectures

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Formal Verification

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Digital Design Toolchain
Specification

Cell description coding

VCS Logic
simulation
Design Compiler Logic Synthesis
Front-End
Formality Formal
Verification

Prime Time Static Timing

Analysis (STA)

Physical Synthesis

Physical
Verification

Static Timing
Analysis (STA)

Finished design

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Synopsys Formality

 An equivalence-checking (EC) solution that uses static

techniques to determine whether two versions of a
design are functionally equivalent.
 Supports all of the out-of the-box DC Ultra optimizations
and so provides the highest quality of results that are
fully verifiable.
 Supports verification of power-up and power-down
states, multi-voltage, multi-supply and clock gated
designs for low-power designs.

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Formality: Galaxy Design Platform

 Formality is an integral part of the

Galaxy
complete Galaxy™ Design
Design Platform that delivers a complete
Compiler equivalence-checking solution.
The real strength of formal
Signoff


IC
verification is its ability to reveal
Compiler
unexpected differences without
relying on vector sets, which
Formality enables to prove large designs
faster than simulation while
providing 100 percent coverage.

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Capabilities of Formality

 Exhaustive verification, without test vectors, in a fraction of the time

consumed by traditional dynamic techniques

 Verification of all Design Compiler Ultra default optimizations

 No need to turn off optimizations to pass equivalence checking

 Proves functional correctness of register retiming, complex

datapath, phase inversion, ECO, and low power implementations

 Extends leading performance advantage with built-in distributed

verification.

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Capabilities of Formality (2)

 Reduces user setup with verified automated guidance

 Expands verification productivity to every engineer with flow-based

graphical interface

 Lockstep language support (SystemVerilog, VHDL, Verilog)

 ESP technology verifies full-custom and memory designs

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Synopsys Full-chip Equivalence
Checking
 Traditional EC solutions are limited by increasing design size and complexity

 Formality’s arithmetic proof engine provides the fastest arithmetic verification,

performance and completion

 Synthesis tool’s optimizations, such as resource sharing, containing retiming, register

merging, or register inversions can be easily verified

I/O Formality
Cell-based
Logic Full
Logic verification
R
I/O

A Custom I/O Formality ESP

Full-custom macro
M Data and library
Logic path
verification
ROM
I/O

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Key Concepts
 Reference Design
 This design is the golden design against which Formality tests for
equivalence
 This design passed functional verification

 Implementation Design
 This design is the modified design whose correctness is needed to
check. For example gate-level implementation of the RTL source

 Containers
 A container is a self-contained space into which Formality reads designs.
 Different containers for reference and implementation designs

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ASIC Verification Flow Using Formality

RTL
RTL Functional Simulation
To be sure the reference
Reference Design
design is functionally correct
Formality DC Ultra

Implementation Design Process

Design A Design B
Design Netlist

Formality

Reference ICC Formality

Design
Implementation Netlist
Design Equivalent?

 After Formality proves the equivalence of the implementation design to a known reference
design, the implementation design can be established as the new reference design. Using
this technique during regression testing keeps overall verification times to a minimum.

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Formal Verification Components

 Compare Points
 Primary output
 Internal registers DFF
 Inputs of a black box
BB
 Nets driven by multiple drivers

 Logic Cone
 Consists of combinational logic
 that drives a compare point

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Logic Cones and Compare Points

 During the read process, reference and implementation designs are automatically
segmented into manageable sections called “logic cones.”
 Logic cones are groups of logic bordered by registers, ports, or black boxes (BB).
 The output border of a logic cone is referred to as a “compare point.”

DFF

Compare Point
Logic
BB
Cone

BB

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The Matching Cycle

 After breaking designs into “logic cones” the tool

attempts to match, or “map,” logic cones from the
reference design to the corresponding logic cones within
the implementation design. This is called “matching”.

 Both non-function (name-based) and function-based

matching methods are deployed to map compare points.

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The Verification Cycle

 After the logic cones have been matched, the

next step is to verify that the functionality of
each matching cone is equivalent.
 Many solver (algorithm) technologies are
available to prove the equivalence of logic
cones:
 Formality EC uses SAT, BDD, isomorphism, ATPG,
and arithmetic, etc.

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The Debug Cycle

 Once the verification step is completed, the tool produces a list of any compare points
(logic cones) that are not equivalent.
 Formality EC also provides various debug and isolation capabilities to help isolate the
implementation error.

Reference
Design
1
0 0
DFF0 DFF DFF DFF
Abc_reg Abc_reg
Implementation
Design

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Formality Flow Overview
Environment Setup

Create Container

Load Libraries and Designs

Specify Reference and

Implementation

Debug
Run Verify

View Results

Debug +
Success -

End

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Formality Interfaces

 Library Interface
 Reads LIB synthesis library containing functionality, timing and design
rule constraints

 Inputs
 Synopsys DC, DDC
 SystemVerilog 3.1a
 Verilog-95, Verilog-2001
 VHDL-87, VHDL-93
 Spice (Formality-ESP)

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Formality Interfaces (2)

 Guided Setup Formats

 Synopsys V-SDC
 Formality Guide Files (SVF)
 Outputs
 Failing patterns
 Formality reports
 Saved session
 Saved containers
 Supported Platforms
 AMD64, Sparc64, Linux32 3.0, Suse 32 , Suse 64

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Formality GUI – Main Window
Tool bar Formal Verification
Status

Formal Verification Stage

Selected
Successfully
Files Loaded Files

Information About Executed

Commands

TCL Command Prompt

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Guided Setup

 Formality can account for synthesis optimizations through the use of

a guided setup file automatically generated by DC Ultra.

 Guided setup includes information about name changes, register

merging, multiplier architectures and many other transformations
that may occur during synthesis.
 By utilizing the most efficient algorithms during matching and
verification guided setup improves performance and first-pass
completion.

 Required when verifying a netlist containing retiming or register

optimizations.

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Using the Automated Setup File

 Design Compiler records data in the automated setup file

Design Compiler
that Formality can use. To specify the file name, use the Ultra
set_svf file.svf command in Design Compiler

 To use the automated setup mode in Formality, set the Guided Gate Level
Setup Netlist
synopsys_auto_setup Tcl variable to true before reading
in the automated setup file.
 Formality uses the same command as Design Compiler
Formality
to read automated setup files: set_svf file.svf

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Loading Designs

 Formality input formats and corresponding read commands:

 Verilog (09,05,01 and 95 standards are supported) read_verilog
 VHDL (87 and 93 standards are supported) read_vhdl
 SystemVerilog read_sverilog
 Synopsys DB files read_db
 Synopsys DDC files read_ddc

 During read command –r or –i options should be specified for

reference and implementation designs respectively.

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Formality Read Design Process Flow
Read
Technology
Libraries
Load Reference
Read
Reference read_verilog –r orca.v
Designs
read_db –r saed90nm.db
Set
Top-level
set_top –auto
Design

Read Load Implementation

Technology
Libraries read_verilog –i orca_gate.v
Read read_db –i saed90nm.db
Implementation
Designs set_top orca
Set
Top-level
Design

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Reading the Reference Design

1. Read Design Files: The read_verilog command loads design into a

container. The –r option signifies the reference container
fm_shell> read_verilog –r orca1.v orca2.v

2. Read DB Files: The read_db command loads the technology library

saed90nm.db in the reference container
fm_shell> read_db –r saed90nm.db
Pure RTL does not require
any component library
3. Set Top Design: The set_top –auto command finds and links the top-level
module.
A green check mark on "1. Reference" button in the formality
window will appear, observe the log of executed commands
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Reading the Implemented Design

1. Read Design Files: The read_verilog command loads design into a

container. The –i option signifies the implementation container
Do not read in the implementation design
fm_shell> read_verilog –i orca.v until having specified the set_top command
for the reference design

2. Read DB Files: The read_db command loads the technology library

saed90nm.db in the implementation container
fm_shell> read_db –i saed90nm.db
Because the –i option is specified, this library is visible only in the
implementation container

3. Set Top Design: The set_top command links the top-level module.
fm_shell> set_top orca

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Reference and Implemented Designs
Ready for Equivalence Checking

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Performing Setup

 Set design-specific options to help Formality perform verification

 Speed up verification

 Prevent from unexpected failures

 Guidance might be needed for matching and verification

Automatically generated by DC Ultra(automated setup file .SVF)

 Auto Setup Mode handles most setup automatically

set synopsys_auto_setup true

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Black Boxes

 A black box represents logic whose function is unknown

or not contain logic.
 Can cause verification failures because input pins
become compare points in the design.
 These are modules that are not verified
 Analog circuitry

 Memory devices

 Black boxes are commonly used for blocks that are not
synthesable.

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Marking a Design as a Black Box

 Use hdlin_unresolved_modules environment variable to cause Formality to

create black boxes when it encounters unresolved or empty designs during
linking.
set hdlin_unresolved_modules black_box

 To load only the pin names and directions for designs use
set hdlin_interface_only “analog*”
Any module beginning with analog will become a black-box

 Declare a sub-design as a black-box

set_black_box RAM1

 Command report_black_boxes shows list of black-boxes

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Matching Compare Points

 The following matching techniques occur by default when user match

compares points, and they are executed in this given order:

1. Exact-name matching (name-based matching)

2. Name filtering (name-based matching)

3. Topological equivalence (non name-based matching)

4. Signature analysis (non name-based matching)

5. Compare point matching based on net names (name-based matching)

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Matching Compare Points Report

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Exact-Name Matching

 Formality matches unmatched compare points by

1. exact case-sensitive name matching
2. exact case-insensitive name matching.

 The exact-name matching technique is used by default in every

verification.

 The following design objects are matched automatically by the

Formality exact-name matching technique:
Reference: /WORK/top/AbCd_10
Implementation: /WORK/top/abcD_10

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Name Filtering Matching

 Compare points are matched by filtering out some characters in the object
names which are specified in name_match_filter_chars variable

 To turn on filtered-name matching behavior

set name_match_use_filter true

 set name_match_filter_chars variable

the default value is - `~!@#$%^&*()_-+=|\[]{}”':;<>?,./

 The following design objects are matched automatically by the Formality Name
Filtering technique:

Reference: /WORK/top/sub1/AbCd[10]
Implementation: /WORK/top/Sub1_abcD_10]

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Topological Equivalence and Net
Names Based Matching
 Formality attempts to match the remaining unmatched compare points by
topological equivalence

 If the cones of logic driving two unmatched compare points are topologically
equivalent, those compare points are matched.

 Formality matches any remaining unmatched compare points by exact and

filtered matching on their attached nets.

 Matches can be made through either directly attached driven or driving nets.

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Signature Analysis

 Signature analysis is an iterative analysis of the compare points’ functional

and topological signatures
 Functional signatures are derived from random pattern simulation
 Topological signatures are derived from fanin cone topology

 Signature analysis works well if the number of unmatched objects is limited,

but the algorithm is less likely to work if there are thousands of compare
point mismatches
 To save time in such a case, turn off the algorithm in the Formality

set signature_analysis_match_compare_points false

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Verify the Design

 Run verify command to verify the implementation design against the

reference design. The reference and implementation designs should be
read in memory.
 This command also perform matching, if matching is not performed.

 Formality classifies verification results as follows:

 Succeeded: implementation is equivalent to the reference

 Failed: implementation is not equivalent to the reference

True logic difference, or setup problem
 Inconclusive: Formality could determine whether the implementation and

reference are equivalent

Might be due to timeout or complexity

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Verify the Design (2)

 The following is an example of a verification results summary:

Matched Compare Points BBPin Loop BBNet Cut Port DFF LAT TOTAL
Passing (equivalent) 987 0 256 0 2566 3832 287 7928
Failing (not equivalent) 0 0 0 0 0 0 2 2
Not Compared
Constant reg 13 27 40
Don't verify 0 0 0 0 2 0 0 2
Unread 1 0 0 0 0 0 10 11

Constant registers are not verified

“Unread” compare points are not verified by default and
do not affect other compare points or primary outputs

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Verify the Design (3)

 Verification is incremental
 Verification can continue again after being stopped

 It is possible to match additional compare points manually and continue

with verification
 To force verification of entire design: verify -restart

 Options:
 Verification of single compare point

 Verification against a constant: verify $ref/CP –constant0

 Use set_dont_verify to exclude points from verification

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Verification Status Messages

 During verification, Formality assigns one of five types of status messages

for each compare point it identifies:

 Passing : values of the two compare point design objects are functionally equivalent

 Failing : means that Formality determined that the two design objects that constitute the
compare point are not functionally equivalent

 Aborted : Formality did not determine compare point either passing or failing due to
combinational loop or a compare point is too difficult to verify

 Unverified : An unverified point represents a compare point that has not yet been verified

 Not Verified : A Not Verified, or Not Run, point appears if there was some error that prevented
verification from running.

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Debugging Verification

 In case equivalence checking fails, one can run the "diagnose" command to
locate points which did not match. To trace the possible problem, first
determine possible error candidate ports or nets.

 There are two main verification results that require debugging:

1. Failing points which Formality detects as nonequivalent points
2. Aborted points verifications for which Formality did not come to a
conclusive result because of the complexity of the design.

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Debugging Flow Chart
Verify

Gather Information,
Determine Failure Cause Choose point to
debug
Resolve black boxes and design
issues Display pattern
window
Check setup
Display logic cone
Report Failing Points

Isolate difference
Run Diagnosis

Problem -
identified?

+
End

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Gathering Information

 When a verification run reports that the designs are not

equivalent, failure is due to either an incorrect setup or a logical
design difference between the two designs.

 Check warnings and information messages in the transcript

 Check The transcript window for verification status, black box
creation, and simulation or synthesis mismatches
 Check for unmatched compare points
 Check whether SVF guidance file read successfully

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Determining Failure Cause by
Number of Violations
 Sometimes the failure cause can be determined by examining the
number of failing, aborted and unmatched points

Number of points in each category

Unmatched Failing Aborted Possible cause
Large - - Compare point matching
problem, or black boxes
Very small Some Small Logical difference
Very small Some Large Setup problem
Very small None Some Complex circuits,
combinational loops
or limits reached

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Determining Failure Causes

 analyze_points command examine the failing points and to determine if

there is a possible setup problem

 To report whole information about failing points use –all option

analyze_points -all

 Formality generates a report of possible setup issues

 Debug process by looking for obvious problems, such as forgetting to

disable scan

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Debugging

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Isolate Difference

 Select a failing point. Right click on the failing point and click
"diagnose“
 The "Analyses" tab is enabled. Click on the "Analyses” tab.
 Select an error candidate. Right click on "Show Logic Cones". A
schematic window containing logic cones starting from the compare
points all the way back to the inputs will appear.
 The reference design in the top window and the implemented design
in the bottom window will appear. Click on the "Isolate Error
Candidates" button in the tool.

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Isolate Difference (2)

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Isolate Difference: Logic Cone Viewer

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Isolate Difference: Pattern Viewer

 The Apply Pattern feature may also be used to further diagnose the
compare points.
 Select an error candidate. Right click -> Show Patterns.
 The show patterns window shows the reference and implemented
design inputs side by side, together with input patterns which cause
the outputs under investigation to be unequal.
 Click on columns numbered 1 through 5 one by one and observe the
reference and implemented compare point values. It is obvious that
they are not equal.

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Isolate Difference: Pattern Viewer (2)

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Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 4
51 Developed By: Vazgen Melikyan
Fix the Design
Fix the implemented design and re run the verification.
Verification SUCCEEDED will appear.

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Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 4
52 Developed By: Vazgen Melikyan