1. The fan put of a 7400 NAND gate is 19.

Which type of CPLD packaging can

provide maximum number of pins on the
A. 2TTL
B. 5TTL package due to small size of the pins?
C. 8TTL A. PLCC
D. 10TTL B. QFP
Answer: Option D
C. PGA
2. The universal gate is ___________
D. BGA
Answer: Option D
A. NAND gate
B. OR gate 20. The NOR gate is OR gate followed by
C. AND gate ___________.
D. None of the above
Answer: Option A A. AND gate
B. NAND gate
3. An OR gate has 6 inputs. The number of
C. NOT gate
input words in its truth table are
D. None of the above
Answer: Option C
A. 6
B. 32 21. The NAND gate is AND gate followed by
C. 64 ___________.
D. 128
Answer: Option C A. NOT gate
No explanation is given for this question Let's
B. OR gate
Discuss on Board
C. AND gate
4. In which of the following base systems is D. None of the above
Answer: Option A
123 not a valid number?
22. Among the logic families, the family which
A. Base 10
can be used at very high frequency greater
B. Base 16
than 100 MHz in a 4 bit synchronous counter
C. Base 8
is
D. Base 3
Answer: Option D
A. TTLAS
5. In case of OR gate, no matter what the B. CMOS
number of inputs, a C. ECL
D. TTLLS
A. 1 at any input causes the output to be at logic 1
Answer: Option C
B. 1 at any input causes the output to be at logic 0
23. In Boolean algebra, the bar sign (-)
C. 0 any input causes the output to be at logic 0
indicates ___________.
D. 0 at any input causes the output to be at logic 1.
Answer: Option A
A. OR operation
6. The number of Boolean functions that can B. AND operation

be generated by n variables is equal to C. NOT operation

D. None of the above
A. 2 n Answer: Option C
B. 22n 24. A hexadecimal odometer displays F 52 F.
C. 22n - 1 The next reading will be
n-1
D. 2
Answer: Option B A. F52E
B. G52F
7. Which mechanism allocates the binary
C. F53F
value to the states in order to reduce the cost
D. F53O
of the combinational circuits? Answer: Option D
25. The binary code of (21.125)10 is
A. State Reduction
B. State Minimization A. 10101.001
C. State Assignment B. 10100.001
D. State Evaluation C. 10101.010
Answer: Option C
D. 10100.111
8. Positive logic in a logic circuit is one in
26. A NAND gate is called a universal logic
which
element because
A. logic 0 and 1 are represented by 0 and positive
voltage respectively A. It is used by everybody
B. logic 0 and, -1 are represented by negative and B. Any logic function can be realized by NAND
positive voltages respectively gates alone
C. logic 0 voltage level is higher than logic 1 C. All the minization techniques are applicable for
voltage level optimum NAND gate realization
D. logic 0 voltage level is lower than logic 1 D. Many digital computers use NAND gates.
voltage level. Answer: Option B
Answer: Option D 27. NAND. gates are preferred over others
9. Digital circuit can be made by the repeated because these
use of ___________
A. have lower fabrication area
A. OR gates B. can be used to make any gate
B. NOT gates C. consume least electronic power
C. NAND gates D. provide maximum density in a chip.
D. None of the above Answer: Option B
Answer: Option C 28. Which is the correct order of sequence for
10. Pick out the CORRECT statement: representing the input values in K-map?

A. In a positional number system, each symbol A. (00, 01, 10, 11)

represents the same value irrespective of its position
B. (00, 10, 01, 11)
B. The highest symbol in a position number system C. (00, 01, 11, 10)
as a value equal to the number of symbols in the D. (00, 10, 11, 01)
system Answer: Option C
C. It is not always possible to find the exact binary
29. The inputs of a NAND gate are connected
D. Each hexadecimal digit can be represented as a
sequence of three binary symbols. together. The resulting circuit is ___________.
Answer: Option C
A. OR gate
11. "What would happen, if smaller logic
modules are utilized for performing logical B. AND gate
functions associated with FPGA? C. NOT gate
A. Propagation delay will increase D. None of the above
B. FPGA area will increase Answer: Option C
C. Wastage of logic modules will not be
prevented 30. Digital computers are more widely used as
D. Number of interconnected paths in device compared to analog computers, because they
will decrease
" are
A. A & B
A. Less expensive
B. C&D
B. Always more accurate and faster
C. A&D
C. Useful over wider ranges of problem types
D. B & C
Answer: Option A D. Easier to maintain
Answer: Option C
12. A debouncing circuit is
31. Consider the representation of six-bit
A. An astable MV
numbers by two’s complement, one’s
B. A bistable MV
complement, or by sign and magnitude: In
C. A latch
D. A monostable MV which representation is there overflow from
Answer: Option C the addition of the integers 011000 and
13. The inverter is ___________ 011000?

A. NOT gate A. Two’s complement only

B. OR gate B. Sign and magnitude and one’s complement only
C. AND gate C. Two’s complement and one’s complement only
D. None of the above D. All three representations
Answer: Option A Answer: Option D
14. Most of the digital computers do not have 32. Excess-3 code is known as
floating point hardware because
A. Weighted code
A. Floating point hardware is costly B. Cyclic redundancy code
B. It is slower than software C. Self-complementing code
C. It is not possible to perform floating point D. Algebraic code
addition by hardware Answer: Option C
D. Of no specific reason 33. The number 10000 would appear just
Answer: Option A
immediately after
15. What is/are the configurable functions of
each and every IOBs connected around the A. FFFF (hex)
FPGA device from the operational point of B. 1111 (binary)
C. 7777 (octal)
view?
D. All of the above
A. Input operation Answer: Option D
B. Tristate output operation 34. The only function of NOT gate is to
C. Bi-directional I/O pin access ___________.
D. All of the above
Answer: Option D A. Stop signal
B. Invert input signal
16. The binary number 10101 is equivalent to C. Act as a universal gate
decimal number ___________. D. None of the above
Answer: Option B
A. 19
35. Which of the following gate is a two-level
B. 12
logic gate
C. 27
D. 21 A. OR gate
Answer: Option D
B. NAND gate
17. Assuming 8 bits for data, 1 bit for parity, I C. EXCLUSIVE OR gate
start bit and 2 stop bits, the number of D. NOT gate
characters that 1200 BPS communication line Answer: Option C
can transmit is. 36. When an input signal 1 is applied to a NOT

A. 10 CPS gate, the output is ___________.

B. 120 CPS A. 0
C. 12 CPS B. 1
D. None of the above C. Either 0 & 1
Answer: Option C
Answer: Option A D. None of the above
Answer: Option A
18. An AND gate will function as OR if 37. Storage of 1 KB means the following

A. All the inputs to the gates are “1” number of bytes

B. All the inputs are ‘0’ A. 1000
C. Either of the inputs is “1” B. 964
D. All the inputs and outputs are complemente' C. 1024
Answer: Option D
D. 1064
Answer: Option C