CONTENTS

Synchronous Sequential Logic Memory and Programmable Logic

• Flip – Flops • Random Access Memory (RAM)
1. D Flip Flop o Block Diagram
▪ With Asynchronous Reset o Contents of 1024 × 16 Memory
2. JK Flip Flop o Access Time
3. T Flip Flop o Cycle Time
• Analysis of Clocked Sequential Circuits o Memory Enable
• Mealy Models o Write Operation
• Moore Models o Read Operation
• State Reduction & Assignment o Memory Cell
• Flip Flop Excitation Tables o Diagram of 4 × 4 RAM
• Sequential Circuit Design Procedure o Coincident Decoding
o 3 – bit Binary Counter o Types of Memories
o ‘111’ Sequence Detector ▪ Sequential Access
▪ SRAM, DRAM
Registers and Counters • Read Only Memory (ROM)
• Registers o Block Diagram
o 4 – bit Register o Internal Logic of 32 × 8 ROM
o 4 – bit Register with Parallel Load o Programming ROM
o Shift Registers o Combinational Circuit Implement.
▪ 4 – bit Shift Register o Types of ROM
▪ Serial Transfer ▪ Mask Programming
▪ Serial Adder ▪ PROM
▪ 2nd Form of Serial Adder ▪ EPROM
▪ 4 – bit Universal Shift ▪ EEPROM
Register • Programmable Logic Devices
• Counters o PROM
o Ripple/Asynchronous Counters o PAL
▪ Identify Up/Down Counters o PLA
▪ Binary Ripple Up Counter • PLA Implementation
▪ Binary Ripple Down • PAL Implementation
Counter
▪ BCD Ripple Counter
▪ 3 – decade BCD Ripple
Counter
o Synchronous Counters
▪ Binary Counter
▪ BCD Counter
▪ Counter with Unused States
▪ Ring Counter
▪ Johnson Counter
 EO 301

Flip – Flops
1) D Flip Flop
Master – Slave D Flip Flop:

Positive – Edge Triggered D Flip Flop:

Graphic Symbol:
Characteristic Table:
D 𝐐(𝐭 + 𝟏) State
0 0 Reset
0 1 Set

Characteristic Equation: Q(t + 1) = D

D Flip Flop with Asynchronous Reset:

Graphic Symbol:

Characteristic Table:
R Clk D 𝐐(𝐭 + 𝟏) State
0 X X 0 Clear
1 ↑ 0 0 Reset
1 ↑ 1 1 Set
2) JK Flip Flop
Circuit Diagram:

Graphic Symbol:

Characteristic Table:
J K 𝐐(𝐭 + 𝟏) State
0 0 Q(t) No Change
0 1 0 Reset
1 0 1 Set
′ (t)
1 1 Q Complement

Characteristic Equation: Q(t + 1) = JQ′ (t) + K ′ Q(t)

3) T Flip Flop
Using JK Flip Flop:
Using D Flip Flop:

Graphic Symbol:

Characteristic Table:
T 𝐐(𝐭 + 𝟏) State
0 Q(t) No Change
0 Q′ (t) Complement

Characteristic Equation: Q(t + 1) = TQ′ (t) + T ′ Q(t)

Analysis of Clocked Sequential Circuits

Circuit Diagram:

State Diagram:
State Table:
Present State Inputs Next State
A x y A
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

State Equations:
A(t + 1) = A ⊕ x ⊕ y

Mealy Models
Output = f(Present State, Input)

• The output of the Mealy machine is the value that is present immediately before the
active edge of the clock

Moore Models
Output = f(Present State)

• In a Moore model, the outputs of the sequential circuit are synchronized with the clock,
because they depend only on flip – flop outputs, which are synchronized with the clock.
State Reduction & Assignment
Given a State Diagram, Write State Table:
Present State Next State Output
x=1 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1

Reduced State Table:

Present State Next State Output
x=1 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1

Reduced State Table:

Present State Next State Output
x=1 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1

Reduced State Diagram:

State Assignment:
State Assignment 1, Assignment 2, Assignment 3,
Binary Gray Code One – Hot
a 000 000 00001
b 001 001 00010
c 010 011 00100
d 011 010 01000
e 100 110 10000

Reduced State Table with Assignment 1:

Present State Next State Output
x=1 x=1 x=0 x=1
000 000 001 0 0
001 010 011 0 0
010 000 011 0 0
011 100 011 0 1
100 000 011 0 1

Flip Flop Excitation Tables

D Flip Flop:
𝐐(𝐭) 𝐐(𝐭 + 𝟏) 𝐃
X 0 0
X 1 1

JK Flip Flop:
𝐐(𝐭) 𝐐(𝐭 + 𝟏) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

T Flip Flop:
𝐐(𝐭) 𝐐(𝐭 + 𝟏) 𝐓
0 0 0
0 1 1
1 0 1
1 1 0
Sequential Circuit Design Procedure

Example 1: Design a 3 – bit binary counter.

State Diagram:

State Table:
Present State Next State FF Inputs
𝐀𝟐 𝐀𝟏 𝐀𝟎 𝐀𝟐 𝐀𝟏 𝐀𝟎 𝐓𝐀𝟐 𝐓𝐀𝟏 𝐓𝐀𝟐
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
K – Maps for FF Inputs and Output:

Example 2: Design a recognizer to detect the sequence ‘111’ in a binary stream using
Moore Model.

State Diagram:

State Table:
Present State Input Next State Output FF Inputs
A B x A B y 𝐃𝐀 𝐃𝐁
0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1
0 1 0 0 0 0 0 0
0 1 1 1 0 0 1 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 0 0 1 0 0
1 1 1 1 1 1 1 1
K – Maps for FF Inputs and Output:

Registers
• A register is a group of flip – flops, each one of which shares a common clock and is
capable of storing one bit of information.

• An n-bit register consists of a group of n flip – flops capable of storing n bits of binary
information.

• A counter is essentially a register that goes through a predetermined sequence of

binary states.

• The transfer of new information into a register is referred to as loading or updating the
register.

• If all the bits of the register are loaded simultaneously with a common clock pulse, we
say that the loading is done in parallel.

• To fully synchronize the system, we must ensure that all clock pulses arrive at the same
time anywhere in the system, so that all flip-flops trigger simultaneously.

• The insertion of logic gates in the path of the clock signal produces uneven propagation
delays between the master clock and the inputs of flip-flops.

• For this reason, it is advisable to control the operation of the register with the D inputs,
rather than controlling the clock in the C inputs of the flip-flops.

• When the Load input is 1, the data at the four external inputs are transferred into the
register with the next positive edge of the clock.

• When the Load input is 0, the outputs of the flip-flops are connected to their respective
inputs.
Four Bit Register:
Four Bit Register with Parallel Load:

Shift Registers
4 – bit Shift Register :
Serial Transfer from Register A to Register B:

Serial Transfer Example:

Timing Pulse Shift Register A Shift Register B
Initial value 1011 0010
After T1 1101 1001
After T2 1110 1100
After T3 0111 0110
After T4 1011 1011

Serial Adder:
• The two binary numbers to be added serially are stored in two shift registers.

• Beginning with the least significant pair of bits, the circuit adds one pair at a time
through a single full-adder (FA) circuit.

• The carry out of the full adder is transferred to a D flip-flop, the output of which is then
used as the carry input for adding the next pair of significant bits.

• The shift control enables the registers for a number of clock pulses equal to the number
of bits in the registers.
State Equations for Serial Adder:
JQ = xy
K Q = x ′ y ′ = (x + y)′
S=x⊕y⊕Q

2nd Form of Serial Adder:

4 – bit Universal Shift Register:
1. A clear control to clear the register to 0.
2. A clock input to synchronize the operations.
3. A shift – right control to enable the shift – right operation, and the serial input and
output lines associated with the shift right.
4. A shift – left control to enable the shift – left operation, and the serial input and output
lines associated with the shift left.
5. A parallel – load control to enable a parallel transfer and the n input lines associated
with the parallel transfer.
6. n parallel output lines.
7. A control state that leaves the information in the register unchanged in response to the
clock.
Characteristic Table for Universal Shift Register:
Mode Control Register Operation
𝐬𝟏 𝐬𝟎
0 0 No Change
0 1 Shift Right
1 0 Shift Left
1 1 Parallel Load

Counters
Ripple/Asynchronous Counters
Binary Ripple Up Counter:

Binary Ripple Down Counter:

• Similarly, with T flip – flop, instead of Q’ we give Q as the clock of the next flip – flop.
BCD Ripple Counter:

3 – Decade BCD Counter:

Identification of Up/Down Counters
Clock Triggering Q Type
+ve edge Q′ Up
+ve edge Q Down
–ve edge Q Up
–ve edge Q′ Down

Synchronous Counters
The design of synchronous
• Binary Counter
• BCD Counter
• Counter with Unused States

can be done in the following manner:

1. Write down the State Table.
2. Use K – Maps for finding the flip – flops input equations and output equations.
3. Draw the Circuit Diagram.

Ring Counter:
• Number of States = Number of Flip – Flops

Johnson Counter:
• Number of States = 2 × Number of Flip – Flops
Memory and Programmable Logic
• The process of storing new information into memory is referred to as a memory write
operation.

• The process of transferring the stored information out of memory is referred to as a

memory read operation.

• RAM can perform both write and read operations.

• ROM can perform only the read operation.

Random – Access Memory (RAM)

• The time it takes to transfer information to or from any desired random location is
always the same – hence the name random – access memory.

• A memory unit stores binary information in groups of bits called words.

• A memory word is a group of 1’s and 0’s and may represent a number, an instruction,
one or more alphanumeric characters, or any other binary-coded information.

Block Diagram of a Memory Unit:

• Each word in memory is assigned an identification number, called an address, starting

from 0 up to 2k − 1, where k is the number of address lines.

• The k address lines specify the word chosen among the many available.
 Unit Abbreviation Storage
Nibble – 4 bits
Byte/Octet B 8 bits
10
Kilobyte KB 2 bytes
Megabyte MB 210 KB
Gigabyte GB 210 MB
Terabyte TB 210 GB

Contents of a 𝟏𝟎𝟐𝟒 × 𝟏𝟔 Memory:

• When a word is read or written, the memory operates on all 16 bits as a single unit.

• The number of bits in the address is determined from the relationship 𝟐𝐤 ≥ 𝐦, where
m is the total number of words and k is the number of address bits needed to satisfy the
relationship.

• The access time of memory is the time required to select a word and read it.

• The cycle time of memory is the time required to complete a write operation.

• The memory enable is used to enable the particular memory chip in a multichip
implementation of a large memory.

Memory Enable Read/Write Memory Operation

0 X None
1 0 Write to selected word
1 1 Read from selected word
Write Operation:
• Apply the binary address of the desired word to the address lines.
• Apply the data bits that must be stored in memory to the data input lines.
• Activate the write input.

The memory unit will then take the bits from the input data lines and store them in the
word specified by the address lines.

Read Operation:
• Apply the binary address of the desired word to the address lines.
• Activate the read input.

The memory unit will then take the bits from the word that has been selected by the
address and apply them to the output data lines.
Memory Cell:

• The select input enables the cell for reading or writing.

• 1 in the read/write input provides the read operation by forming a path from the latch
to the output terminal.

• 0 in the read/write input provides the write operation by forming a path from the input
terminal to the latch.

𝐃𝐢𝐚𝐠𝐫𝐚𝐦 𝐨𝐟 𝐚 𝟒 × 𝟒 𝐑𝐀𝐌
Coincident Decoding:
• A decoder with k inputs and 2𝑘 outputs, requires 2𝑘 AND gates with k inputs per gate.

• The total number of gates and the number of inputs per gate can be reduced by
employing two decoders in a two – dimensional selection scheme.

Types of Memories
Sequential – Access Memory:
• The information stored in some medium is not immediately accessible, but is available
only at certain intervals of time.

• A magnetic disk or tape unit is of this type. Each memory location passes the read and
write heads in turn, but information is read out only when the requested word has been
reached.

• The time it takes to access a word depends on the position of the word with respect to
the position of the read head; therefore, the access time is variable.

Random – Access Memory:

• The access time is always the same regardless of the location of the word.
 SRAM DRAM
Static RAM. Dynamic RAM.
Internal latches store the binary Stores the binary information in the form of
information. electric charges on capacitors.
The stored information remains valid as The charge on the capacitors discharges with
long as power is applied to the unit. time, and the capacitors must be periodically
recharged by refreshing the memory.
High power consumption. Low power consumption.
Small storage capacity. Large storage capacity.
Short read and write cycles. Long read and write cycles.

• Memory units that lose stored information when power is turned off are said to be
volatile.

Read – Only Memory (ROM)

• A memory device in which permanent binary information is stored.

• The binary information must be specified by the designer and is then embedded in the
unit to form the required interconnection pattern.

• Once the pattern is established, it stays within the unit even when power is turned off
and on again.

Internal Logic of a 𝟑𝟐 × 𝟖 ROM:

Block Diagram:

• A programmable connection between two lines is logically equivalent to a switch that

can be altered to be either closed or open.

Programing the ROM according to Truth Table:

Combinational Circuit Implementation:
The circuit accepts a 3 – bit number and outputs a binary number equal to the square of
the input number.

Types of ROMs
Mask Programming:
• It is done by the semiconductor company during the last fabrication process of the unit.

• The procedure requires that the customer fill out the truth table he or she wishes the
ROM to satisfy.

• The manufacturer makes the corresponding mask for the paths to produce the 1’s and
0’s according to the customer’s truth table.

• This procedure is costly because the vendor charges the customer a special fee for
custom masking the particular ROM.

Programmable ROM (PROM):

• Initially, it contains all the fuses intact, giving all 1’s in the bits of the stored words.
• The fuses are blown by the application of a high – voltage pulse to the device through a
special pin.

• A blown fuse defines a binary 0 state and an intact fuse gives a binary 1 state.

• This procedure allows the user to program the PROM in the laboratory to achieve the
desired relationship between input addresses and stored words.

• The hardware procedure is irreversible, and once programmed, the fixed pattern is
permanent and cannot be altered.

Erasable PROM (EPROM):

• Can be restructured to the initial state even though it has been programmed previously.

• When it is placed under a special ultraviolet light for a given length of time, the
shortwave radiation discharges the internal floating gates that serve as the
programmed connections.

• After erasure, it returns to its initial state and can be reprogrammed to a new set of
values.

Electrically Erasable PROM (EEPROM):

• The previously programmed connections can be erased with an electrical signal.

• The advantage is that the device can be erased without removing it from its socket.

Combinational Programmable Logic Devices (PLDs)

PLD is an integrated circuit with programmable gates divided into an AND array and an OR
array to provide an AND – OR sum – of – product implementation.

1) Programmable ROM (PROM):

• It has a fixed AND array constructed as a decoder and a programmable OR array.

• The programmable OR gates implement the Boolean functions in sum – of – minterms

form.

2) Programmable Array Logic (PAL):

• It has a programmable AND array and a fixed OR array.

• The AND gates are programmed to provide the product terms for the Boolean
functions, which are logically summed in each OR gate.
3) Programmable Logic Array (PLA):
• It has a programmable AND array and a programmable OR array.

• The product terms in the AND array may be shared by any OR gate to provide the
required sum – of – products implementation.

Programmable Logic Array (PLA)

• Both the true value and the complement of the functions are simplified into sum – of –
products form.

F1 = AB ′ + AC + A′ BC′
F2 = (AC + BC)′

Programming Table:
Circuit Diagram:

Programmable Array Logic (PAL)

w = ABC ′ + A′ B ′ CD′
x = A + BCD
y = A′ B + CD + B ′ D′
z = ABC′ + A′ BCD′ + AC ′ D′ + A′ B ′ C ′ D = w + AC ′ D + A′B′C′D

Programming Table:
Circuit Diagram: