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18 January 2021 1442 ‫ جمادى الثانية‬5

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Digital IC Design

Lecture 11
Logical Effort of Paths

Dr. Hesham A. Omran

Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
This lecture is mainly based on “CMOS VLSI Design”, 4th edition, by N. Weste and D. Harris and
its accompanying lecture notes
 Introduction
❑ Chip designers face a bewildering array of choices
▪ What is the best circuit topology for a function?
▪ How many stages of logic give least delay?
▪ How wide should the transistors be?
???

❑ Logical effort is a method to make these decisions

▪ Uses a simple model of delay
▪ Allows back-of-the-envelope calculations
▪ Helps make rapid comparisons between alternatives

11: Logical Effort for Paths 2

 Example
❑ Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive
processor. Help Ben design the decoder for a register file.

❑ Decoder specifications:
▪ 16 word register file
▪ Each word is 32 bits wide
▪ Each bit presents load of 3 unit-sized transistors
A[3:0] A[3:0]
▪ True and complementary address inputs A[3:0] 32 bits

▪ Each input may drive 10 unit-sized transistors

4:16 Decoder
❑ Ben needs to decide:

16 words
16
Register File
▪ How many stages to use?
▪ How large should each gate be?
▪ How fast can decoder operate?

11: Logical Effort for Paths 3

 Remember: Normalized Delay
𝑅
𝑡𝑝𝑑 = 𝑘𝐶𝑝 + 𝐶𝐿
𝑘
❑ Normalized delay:
𝑹
𝝉 = 𝑹𝒊𝒏𝒗 𝑪𝒊𝒏𝒗 = ⋅ 𝟑𝒌𝑪𝒈
𝒌
𝑡𝑝𝑑 𝑪𝒑 𝒌𝑪𝒊𝒏 𝑪𝑳
𝑑= = + ⋅
𝜏 𝑪𝒊𝒏𝒗 𝒌𝑪𝒊𝒏𝒗 𝒌𝑪𝒊𝒏
=𝒑+𝒇=𝒑+𝒈⋅𝒉
❑ For inverter: 𝑝 ≈ 1 𝑎𝑛𝑑 𝑔 ≝ 1
❑ For any other gate: Plot 𝑑 vs. fanout (ℎ)
▪ 𝑝 is the y-intercept
▪ 𝑔 is the slope

11: Logical Effort for Paths 4

 Multistage Delays
❑ Path Effort Delay: Need to know both gate type 𝑔 and sizing ℎ
DF =  f i
❑ Path Parasitic Delay: Need gate type only (𝑝). Sizing not required.
P =  pi
❑ Path Delay: Can we calculate path delay without sizing info?
D =  d i = DF + P
▪ YES! ➔ Logical effort method can tell us min delay of a path!

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

11: Logical Effort for Paths 5

 Multistage Logic Networks
❑ Define three NEW path parameters, all INDEPENDENT of sizing
❑ Path Logical Effort
𝑮 = 𝚷𝒈𝒊
❑ Path Electrical Effort
𝑪𝒐𝒖𝒕−𝒑𝒂𝒕𝒉
𝑯= ≠ 𝚷𝒉𝒊
❑ Path Effort 𝑪𝒊𝒏−𝒑𝒂𝒕𝒉
𝑭 = 𝚷𝒇𝒊 = 𝚷𝒈𝒊 𝒉𝒊 = 𝚷𝒈𝒊 𝚷𝒉𝒊 ≠ 𝑮𝑯

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

11: Logical Effort for Paths 6

 Paths that Branch

G =1
H = 90 / 5 = 18 15
90
GH = 18 5
h1 = (15 +15) / 5 = 6
15
h2 = 90 / 15 = 6 90
F = g1g2h1h2 = 36 = 2GH

11: Logical Effort for Paths 7

 Paths that Branch

G =1
H = 90 / 5 = 18 15
90
GH = 18 5
h1 = (15 +15) / 5 = 6
15
h2 = 90 / 15 = 6 90
F = g1g2h1h2 = 36 = 2GH

11: Logical Effort for Paths 8

 Branching Effort
❑ Introduce branching effort
▪ Accounts for branching between stages in path
Con path + Coff path
b= 15
Con path 90
5
B =  bi
15
90
❑ Now we compute the path effort
𝑭 = 𝚷𝒇𝒊 = 𝚷𝒈𝒊 𝒉𝒊 = 𝑮𝑩𝑯

❑ Note that:
h i = BH
11: Logical Effort for Paths 9
 Multistage Delays
❑ Path Effort Delay: We need both gate type 𝑔 and sizing ℎ
DF =  f i
❑ Path Parasitic Delay: We need type only (𝑝). Sizing not required.
P =  pi
❑ Path Delay: Can we calculate path delay without sizing info?
D =  d i = DF + P
▪ YES! ➔ Logical effort method can tell us min delay of a path!
▪ We can use min delay to calculate sizing!

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

11: Logical Effort for Paths 10

 Multistage Delays
❑ To calculate path delay we need sum of 𝑓𝑖
DF =  f i P =  pi D =  d i = DF + P

❑ But sum of 𝑓𝑖 depends on sizing, which we do not know

❑ But product of 𝑓𝑖 is independent of sizing (i.e., constant)!
𝑭 = 𝚷𝒇𝒊 = 𝚷𝒈𝒊 𝒉𝒊 = 𝑮𝑩𝑯

❑ Mathematics tell us: If product of 𝑓𝑖 is constant, then we can minimize sum of 𝑓𝑖 by making
all 𝑓𝑖 equal! → 𝑓𝑖 = 𝑓መ

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z
11: Logical Effort for Paths 11
 Designing Fast Circuits
DF =  f i P =  pi D =  d i = DF + P

መ
❑ Delay is smallest when each stage bears same effort (𝑓𝑖 = 𝑓)
𝐹 = Π𝑓𝑖 = 𝑓መ 𝑁
𝟏
𝒇෠ = 𝑭𝑵
❑ Thus minimum delay of N stage path is
1
D = NF + PN

❑ This is a key result of logical effort

▪ Find fastest possible delay
▪ Doesn’t require calculating gate sizes
❑ Simulations cannot tell you something like this!
11: Logical Effort for Paths 12
 Gate Sizing
❑ How wide should the gates be for least delay?
ˆf = gh = g Cout
Cin

gi Couti
 Cini =
fˆ
❑ Working backward, apply capacitance transformation to find input capacitance of each
gate given load it drives.
❑ Check work by verifying input cap spec is met.

11: Logical Effort for Paths 13

 Example: 3-stage path
❑ Select gate sizes x and y for least delay from A to B

y
x
45
A 8
x
y B
45

11: Logical Effort for Paths 14

 Example: 3-stage path
x

y
x
45
A 8
x
y B
45

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F = GBH = 125
Best Stage Effort fˆ = 3 F = 5
Parasitic Delay P=2+3+2=7
Delay D = 3*5 + 7 = 22 = 4.4 FO4

11: Logical Effort for Paths 15

 Example: 3-stage path
x

y
x
45
A 8
x
y B
45

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F = GBH = 125
Best Stage Effort fˆ = 3 F = 5
Parasitic Delay P=2+3+2=7
Delay D = 3*5 + 7 = 22 = 4.4 FO4

11: Logical Effort for Paths 16

 Example: 3-stage path
x

y
x
45
A 8
x
y B
45

❑ Work backward for sizes

y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

11: Logical Effort for Paths 17

 Example: 3-stage path
x

y
x
45
A 8
x
y B
45

❑ Work backward for sizes

y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

❑ Verify the first stage

(10 + 10 + 10) × (4/3)/5 = 8

11: Logical Effort for Paths 18

 Example: 3-stage path
x

y
x
45
A 8
x
y B
45

❑ x = 10
❑ y = 15
45
A P: 4
P: 4
N: 4 P: 12 B
N: 6 45
N: 3

❑ Double check by adding delays of each stage

11: Logical Effort for Paths 19
 Review of Definitions

11: Logical Effort for Paths 20

 Best Number of Stages
❑ Logical Effort tells us that
▪ NANDs are better than NORs
▪ Gates with few inputs are better than gates
with many
1 1 1 1
▪ Min delay of a path
▪ How to size gates 8 4 2.8

❑ Can it tell us how many stages to use? 16 8

23

64 64 64 64

11: Logical Effort for Paths 21

 Best Number of Stages
❑ How many stages should a path use?
▪ Minimizing number of stages is not always fastest
❑ Example: drive 64-bit datapath with unit inverter
❑ Calculate min delay for 1 1 1 1
Initial Driver
N = 1, 2, 3, 4
8 4 2.8

D = NF1/N + P = N(64)1/N + N 16 8

23

Datapath Load 64 64 64 64

N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest

11: Logical Effort for Paths 22

 Best Number of Stages
❑ How many stages should a path use?
▪ Minimizing number of stages is not always fastest
❑ Example: drive 64-bit datapath with unit inverter
❑ Calculate min delay for 1 1 1 1
Initial Driver
N = 1, 2, 3, 4
8 4 2.8

D = NF1/N + P = N(64)1/N + N 16 8

❑ What about area and power? 23

▪ N = 2 is slightly slower Datapath Load 64 64 64 64

▪ But significantly less area N: 1 2 3 4

and power f:
D:
64
65
8
18
4
15
2.8
15.3
Fastest

11: Logical Effort for Paths 23

 Derivation
❑ Consider adding inverters to end of path
▪ Note that inverters do not change F=GBH, but they change P
▪ How many give least delay?
n1
D = NF +  pi + ( N − n1 ) pinv
1
N

i =1

D 1 1 1
= − F ln F + F + pinv = 0
N N N

N

❑ Define best stage effort

=F
1
N

pinv +  (1 − ln  ) = 0

11: Logical Effort for Paths 24

 Best Stage Effort
❑ Define best stage effort
=F
1
N

pinv +  (1 − ln  ) = 0
❑ No closed-form solution for 𝜌 = 𝑓መ

❑ Neglecting parasitics (pinv = 0), we find  = 𝑓መ = 2.718 (e)

❑ For pinv = 1, solve numerically for  = 𝑓መ = 3.59
❑ Optimum number of stages:
log 𝐹
෡ = log 𝜌 𝐹 =
𝑁
log 𝜌

11: Logical Effort for Paths 25

 Sensitivity Analysis
❑ How sensitive is the delay to using exactly the best number of stages?
1.6
1.51

D(N) /D(N)
1.4
1.26
1.2 1.15
1.0

(=6) ( =2.4)

0.0
0.5 0.7 1.0 1.4 2.0

N/ N
❑ 2.4 <  < 6 gives delay within 15% of optimal
▪ We can be sloppy!
▪ Designers like  = 4 (FO4 ☺)
11: Logical Effort for Paths 26
 Example, Revisited
❑ Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive
processor. Help Ben design the decoder for a register file.

❑ Decoder specifications:
▪ 16 word register file
▪ Each word is 32 bits wide
▪ Each bit presents load of 3 unit-sized transistors
A[3:0] A[3:0]
▪ True and complementary address inputs A[3:0] 32 bits

▪ Each input may drive 10 unit-sized transistors

4:16 Decoder
❑ Ben needs to decide:

16 words
16
Register File
▪ How many stages to use?
▪ How large should each gate be?
▪ How fast can decoder operate?

11: Logical Effort for Paths 27

 Decoder
❑ A 2N-word decoder consists of 2N N-input AND
gates.
❑ Therefore, the problem is reduced to designing a
suitable 4-input AND gate.
❑ F = GBH
❑ For 2-bit decoder
▪ Each input drives half the gates
▪ The other half is driven by its complement
▪ Branching = 2^N/2
❑ Load = 32-bit * 3 units/bit
❑ What about G?
▪ Make an assumption and iterate

11: Logical Effort for Paths 28

 Number of Stages
❑ Decoder effort is mainly electrical and branching
Electrical Effort: H = (32*3) / 10 = 9.6
Branching Effort: B=8

❑ If we neglect logical effort (assume G = 1)

Path Effort: F = GBH = 76.8
Assume 𝜌 = 𝑓መ = 4
Number of Stages: N = log4F = 3.1

❑ Try a 3-stage design

11: Logical Effort for Paths 29

 Number of Stages
❑ Decoder effort is mainly electrical and branching
Electrical Effort: H = (32*3) / 10 = 9.6
Branching Effort: B=8

❑ If we neglect logical effort (assume G = 1)

Path Effort: F = GBH = 76.8
Assume 𝜌 = 𝑓መ = 4
Number of Stages: N = log4F = 3.1

❑ Try a 3-stage design

11: Logical Effort for Paths 30

 Gate Sizes & Delay
Logical Effort: G = 1 * 6/3 * 1 = 2
Path Effort: F = GBH = 154
Stage Effort: fˆ = F 1/ 3 =(we assumed it was 4)
5.36
Path Delay: D = 3 fˆ + 1 + 4 + 1 = 22.1
Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7

11: Logical Effort for Paths 31

 Gate Sizes & Delay
Logical Effort: G = 1 * 6/3 * 1 = 2
Path Effort: F = GBH = 154
Stage Effort: fˆ = F 1/ 3 = 5.36 (we assumed it was 4)
Path Delay: D = 3 fˆ + 1 + 4 + 1 = 22.1
Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7

11: Logical Effort for Paths 32

 Comparison
❑ Compare many alternatives without simulations!
❑ D = N(76.8 G)1/N + P

Design N G P D 𝒇𝒐𝒑𝒕
NOR4
NAND4-INV
NAND2-NOR2
INV-NAND4-INV
NAND4-INV-INV-INV
NAND2-NOR2-INV-INV
NAND2-INV-NAND2-INV
INV-NAND2-INV-NAND2-INV
NAND2-INV-NAND2-INV-INV-INV

11: Logical Effort for Paths 33

 Comparison
❑ Compare many alternatives without simulations!
❑ D = N(76.8 G)1/N + P

Design N G P D 𝒇𝒐𝒑𝒕
NOR4 1 3 4 234 230.40
NAND4-INV 2 2 5 29.8 12.39
NAND2-NOR2 2 20/9 4 30.1 13.06
INV-NAND4-INV 3 2 6 22.1 5.36
NAND4-INV-INV-INV 4 2 7 21.1 3.52
NAND2-NOR2-INV-INV 4 20/9 6 20.5 3.61
NAND2-INV-NAND2-INV 4 16/9 6 19.7 3.42
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4 2.67
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6 2.27

11: Logical Effort for Paths 34

 Review of Definitions

11: Logical Effort for Paths 35

 Review of Logical Effort Method
1) Compute path effort
F = GBH
2) Estimate best number of stages
N = log 4 F
3) Sketch path with N stages

4) Estimate least delay 1

D = NF + PN

5) Determine best stage effort

ˆf = F N1

6) Find gate sizes gi Couti

Cini =
fˆ
11: Logical Effort for Paths 36
 Limitations of Logical Effort
❑ Chicken and egg problem
▪ Need path to compute G
▪ But don’t know number of stages without G
❑ Simplistic delay model
▪ Neglects input rise time effects
❑ Interconnect
▪ Iteration required in designs with wire
❑ Maximum speed only
▪ Not minimum area/power for constrained delay

11: Logical Effort for Paths 37

 Summary
❑ Logical effort is useful for thinking of delay in circuits
▪ Numeric logical effort characterizes gates
▪ NANDs are faster than NORs in CMOS
▪ Paths are fastest when effort delays are ~4
▪ Stage effort slightly > 4 saves power and area
▪ Path delay is weakly sensitive to stages, sizes
▪ But using fewer stages or larger sizing doesn’t mean faster paths
▪ Delay of path is about log4F FO4 inverter delays
▪ Inverters and NAND2 best for driving large caps and branches
❑ Provides language for discussing fast circuits
▪ But requires practice to master

11: Logical Effort for Paths 38

 Thank you!

11: Logical Effort for Paths 39