Memory & Programmable

Logic
Md. Zubair Alam Emon
 Memory
• Memory is a storage device that saves binary
information for later retrieval.
• Memory unit is a collection of cells capable of storing a
large quantity of binary info.
• Two types of memories:
– Random Access Memory (RAM)
• Allows memory read and memory write
– Read-Only Memory (ROM)
• Allows memory read only
• Memory Read
– Process of transferring stored info out of memory
• Memory Write
– Process of storing new info into memory
 PLD
• Programmable Logic Device (PLD)
• PLD is a read-only memory
– ROM, PLA, PAL, FPGA (Field Programmable Gate
Array)
• Data is stored in a PLD through programming
– A hardware procedure that stores the bits.
• Within a PLD, internal gates are connected via
fuse like switches.
• Programming involves blowing fuses to obtain
particular configuration of the desired logic.
 RAM
• Unlike CD/DVD/tape, memory read or
write time to any random location is same
(hence Random Access Memory)
• Stored info at each address is known as
word.

• Memory unit is specified by the number of

words it contains and the number of bits in
each word.
 RAM Structure
Block diagram of a memory
Memory Address
k address
lines 2k x n Memory Binary decimal Memory content
n data
2k words lines 0000000000 0 1011010101011101

Rd/Wr 0000000001 1 1010101110001001

n bit per word
0000000011 2 0000110101000110

1K = 210 address i.e.

.
…
1K x 16 10-bit address lines

.
…
mem 16-bits in each word

1111111101 1021 1001110100010100

64K = 216 address i.e. 1111111110 1022 0000110100011110

64K x 10 16-bit address lines
1111111111 1023 1101111001001010
mem 10-bits in each word
Content of a 1K x 16 Memory
 Write / Read Operations
• Write
– Apply the address of the desired word to the address lines.
– Apply the data bits that need to be stored to the data lines.
– Active the write input.
• Read
– Apply the address of the desired word to the address lines.
– Active the read input.

Memory Enable Rd/Wr Memory Operation

0 X None
1 0 Write to selected word
1 1 Read from selected word
 HDL
// Read and write operations of memory
// Memory size is 64 words of 4 bits each
module memory ( En, Rd_Wr, Adr, Din, Dout );
input En, Rd_Wr;
input [3:0] Din; 2-D array of 64 registers,
input [5:0] Adr; each containing 4-bit word
output reg [3:0] Dout;
reg [3:0] Mem [0:63]; // 64 x 4 memory
always @ ( En, Rd_Wr ) Transfers 4-bits data from
if( En ) selected memory word
if( Rd_Wr ) specified by address, Adr.
Dout = Mem[Adr]; // Read
else
Mem[Adr] = Din; // Write
else Transfers from 4-bits Din
Dout = 4’bz; lines into memory word
endmodule selected by address, Adr.
 SRAM read timing
• Similar to ROM read timing
 SRAM write timing

• Address must be stable before and after

write-enable is asserted.
• Data is latched on trailing edge of (WE &
CS).
 Types of Memories
• Two types:
– SRAM (Static RAM)
• Stores data in latches
• Data remains valid as long as power is applied.
• Easier to use and has shorter read/write cycle.
– DRAM (Dynamic RAM)
• Stores data on capacitors as electric charge.
• Periodical refreshing is required to keep data valid on
discharging capacitors.
• Reduced power consumption and larger storage capacity.
• Memory that lose stored info when power is
turned off are known as volatile. e.g. RAM
 Memory Decoding
Input data
select
● I3 I2 I1 I0
in
● Word 0 ● ● ●
● S out
BC BC BC BC
● R ● ● ● ●
Word 1 ● ● ●
●
Rd/Wr 2X4 BC BC BC BC
Logic Diagram Decoder
● ● ● ●
Word 2 ● ● ●
select
Memory
enable EN BC BC BC BC

Address ● ● ● ●
Word 3 ● ● ●
in BC out inputs

BC BC BC BC
Rd / Wr ● ● ● ●
Rd/Wr

Block Diagram A 4 X 4 RAM

O3 O2 O1 O0
Output data
 Memory Organization
• Previous example was a 1-D decoding and for a 4x4
RAM the 2x4 decorder needs 2 input 22=4 AND gates.
• So, for 1Kx4 RAM the 10x1024 decorder will require 10
input 210=1024 AND gates which is a very complex
circuit.
• Next we will introduce the 2D memory organization that
will reduce the circuitry.
• Usually 1D is used for ROM and 2D is used for RAM.
 Coincident Decoding
Y

2-Dimensional Decoding
Structure for a 1K-Word
Memory 5 X 32 decoder

Word 20
0 1 2 . . . . 20 . . . . 31
W (31+32)=63
● ● ● ● ●
0 ● ● ● ● ●
● ● ● ● ●
1

2
X binary address
5 X 32 decoder ● ● ● ● ● 01100 10100
12
X Y

Address #
● ● ● ● ● 12x32+20=404
31

• Selection of word with address 404 ( 01100 10100)

• Total AND gates required 5-input 32+32=64 AND gates
 Address Multiplexing
• Used in DRAMs
• MOST DRAMs have 1-bit word size.
• To reduce the number of pin in IC package designers use address
multiplexing.
• First address is given into ROW then COLUMN using RAS(Row
Address Strobe) and CAS
• A 64K (256x256=2^8x2^8) word memory is shown as an example.
So a total of 16 bit address line required. But using multiplexing it is
decreased to 8 bit.

Steps:

1. RAS=1; CAS=1 ;
2. RAS=0; CAS=1 ; 8-bit Row address given to address line.
3. RAS=1; CAS=1 ;
4. RAS=1; CAS=0 ; 8-bit Column address given to address line.
5. RAS=1; CAS=1 ;
 Address Multiplexing

8-bit column
CAS ● ○ register

8 X 256
○ decoder
RAS ●
○ ○

8-bit 256 X 256

8-bit ● 8 X 256 Rd / Wr
row memory
address decoder
register cell array

Data Data
in out
• Done in large capacity memory cells (DRAM)
 Read Only Memory
ROM
k inputs 2k
xn n outputs
(data)
Block
(address) ROM Diagram

0
1
I0 2
I1 3

..
I2 5 X 32

.
decoder
I3 28
I4 29
30
31

Internal Logic of
a 32 X 8 ROM A7 A6 A5 A4 A3 A2 A1 A0
 ROM Truth Table
Inputs Outputs
I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 1 0 1 1 0 1 1 0
0 0 0 0 1 0 0 0 1 1 1 0 1
0 0 0 1 0 1 1 0 0 0 1 0 1
0 0 0 1 1 1 0 1 1 0 0 1 0

1 1 1 0 0 0 0 0 0 1 0 0 1
1 1 1 0 1 1 1 1 0 0 0 1 0
1 1 1 1 0 0 1 0 0 1 0 1 0
1 1 1 1 1 0 0 1 1 0 0 1 1

Example: A7 (I4I3I2I1I0) = Σ ( 0, 2, 3, …, 29 )
…
A0 (I4I3I2I1I0) = Σ ( 1, 2,… 28, 31 )
 ROM Programming
Cross(x) means there is a connection

X X X X X
0 X
X X X
1
I0 X X X X
2
I1 3 X X X X

..
I2 5 X 32
decoder
I3 X X
28
I4 29 X X X X X
30 X X
31
X X X X

A7 (I4I3I2I1I0) = Σ ( 0, 2, 3, …, 29 ) A7 A6 A5 A4 A3 A2 A1 A0

Programming the ROM According to Truth Table

 Combo Ckt w/ ROM
Using a ROM design a combinational circuit that accepts a 3-bit number and
generates an output binary number equal to the square of the input number

Inputs Outputs
A2 A1 A0 B5 B4 B3 B2 B1 B0 Decimal
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0 4
0 1 1 0 0 1 0 0 1 9
1 0 0 0 1 0 0 0 0 16
1 0 1 0 1 1 0 0 1 25
1 1 0 1 0 0 1 0 0 36
1 1 1 1 1 0 0 0 1 49
Output as a function: B5 (A2A1A0) = Σ ( 6, 7) ; B4 (A2A1A0) = Σ ( 4, 5, 7) ; …..
 Combo Ckt w/ ROM
B0 = A0
B0
B1 = 0 0 B1 A2 A1 A0 B5 B4 B3 B2
A0 ● B2 0 0 0 0 0 0 0
A1 8X4 B3 0 0 1 0 0 0 0
A2 ROM B4 0 1 0 0 0 0 1
B5 0 1 1 0 0 1 0
1 0 0 0 1 0 0
Block Diagram 1 0 1 0 1 1 0
1 1 0 1 0 1 1
0
1
A0 2
3
1 1 1 1 1 0 0
A1

A2
3X8
decoder
4
5
6 Simplified Truth Table to
7
Implement with a ROM
Internal Logic of
a 8 X 4 ROM B B B B
5 4 3 2
 Types of ROMs
• PROM
– Programmable Read Only Memory
• EPROM
– Erasable Programmable Read Only Memory
• EEPROM ( E2PROM )
– Electrically Erasable Programmable Read
Only Memory
• Mask Programming
– Programmed by the manufacturer
 Combinational PLDs
Fixed
Inputs
Programmable
AND array Outputs
OR array
(decoder)

Programmable read-only memory (PROM)

Inputs
Programmable Fixed Outputs
AND array OR array

Programmable array logic (PAL)

Programmabl
Inputs
Programmable
e OR array
Outputs
AND array
Programmable logic array (PLA)
 PLA
AB’
○
X X X
F1 = AB’ + AC + A’BC’
A
X X X X AC F2 = (AC + BC)’
B ○

X X X BC
C ○
A’BC’
X X X X
X 0
X 1
C C’ B B’ A A’
F
1
F2

PLA with 3 Inputs, 4 Product Terms, and 2 Outputs

 PLA Programming Table
Outputs
Product Inputs (T) (C)
Term A B C F1 F2
AB’ 1 1 0 – 1 – T is true form of output
AC 2 1 – 1 1 1 C is complemented output
BC 3 – 1 1 – 1
A’BC’ 4 0 1 0 1 –

The output variables are

For each product term, marked with 1’s for those
inputs are marked with product terms that are
1 ( true form ), included in the function.
0 ( complemented ) Those marked with dash
– (absent) specify a blown fuse.
 PLA Example
Implement the functions with a PLA:
F1 (A, B, C) = Σ (0, 1, 2, 4) F1 = ( AB + AC + BC )’
F2 (A, B, C) = Σ (0, 5, 6, 7) F2 = AB + AC + A’B’C’

PLA Programming Table

Outputs
Product Inputs (C) (T)
term A B C F1 F2
AB 1 1 1 – 1 1 You may try finding SOP
AC 2 1 – 1 1 1 with ‘0’s. The resultant whole
SOP must be then
BC 3 – 1 1 1 – complemented.

A’B’C’ 4 0 0 0 – 1
 PAL
• Programmable Array Logic has fixed OR array
and a programmable AND array.
• Easier to program but less flexible then PLA

w ( A,B,C,D ) = Σ( 2, 12, 13 )
x ( A,B,C,D ) = Σ( 7, 8, 9, 10, 11, 12, 13, 14, 15 )
y ( A,B,C,D ) = Σ( 0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15 )
z ( A,B,C,D ) = Σ( 1, 2, 8, 12, 13 )

w = ABC’ + A’B’CD’
x = A + BCD
y = A’B + CD + B’D’
z = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D
= w + AC’D’ + A’B’C’D
 PAL Programming Table
AND Inputs

Product Term A B C D w Outputs

1 1 1 0 – – w = ABC’

2 0 0 1 0 – + A’B’CD’

3 – – – – –

4 1 – – – – x=A

5 – 1 1 1 – + BCD

6 – – – – –

7 0 1 – – – y = A’B

8 – – 1 1 – + CD

9 – 0 – 0 – + B’D’

10 – – – – 1 z=w

11 1 – 0 0 – + AC’D’

12 0 0 0 1 – + A’B’C’D
 A A’ B B’ C C’ D D’ w w’

1 x x x
Product
term ● w
2 x x x x

3 x
A ○ ● ● ○
● ●
4 x

5 x x x x

6 x All fuses intact

B ○ ● (always = 0)
●
7 x x

8 x x y

9 x x
●
C ○
●
10 x

11 x x x z

12 x x x x
D ○ ●
●

A A’ B B’ C C’ D D’ w w’
 HW
• 7-1~7-3, 7-6~7-9, 7-14, 7-15, 7-18~7-23