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RTL Design of FIFO (Synchronous + Asynchronous)

FIFO (First In First Out) is a special type of storage memory where the first data bit written into the memory is the
first to be read out.
FIFO memory is used when two systems of different data rates communicate to each other. Data can be entered
into FIFO register at one end and read taken out at the other end at another rate.
The number of rows is called depth or (number of words of FIFO) and number of bits in each row is called as
width or word length of FIFO.

FIFO Operations
Write Operation =>
The operation involves in writing or storing the data into FIFO memory till it rises any flag
conditions for not to write anymore, this condition called full condition.
✓ Full conditions are generated using full flags.
✓ To perform a write operation the data to be written is given at DIN port and WRITE_EN is to be set high
then at the next rising edge the data will be written.
Read Operation =>
Read operation performed when we want to get data out from FIFO memory until it informs
there is no more data to be read from the memory, this condition called empty condition.
✓ Empty conditions are generated using empty flags.
✓ To perform read operation, we need to set READ_EN high then at next rising edge the data to be read will
be at DOUT port.

Pointers to Control Operations

Write pointer =>
This pointer controls the write operation of the FIFO. It used to points FIFO memory location
where the data will be written.
Read Pointer =>
The read operation is controlled by read pointer. It will be pointing the location from where next
data is to be read.

Flags in FIFO
Flags are used to determine the status or to interrupt the operation of FIFO.
EMPTY Flag =>
This flag is useful to avoid the case of the invalid request of read operation when the FIFO is
already empty.
Read Pointer =>
This flag is useful to avoid the case of the invalid request of write operation when the FIFO is
already full.

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FIFO Overflow and Underflow

Overflow =>
Overflow occurs when new data is being written into FIFO memory while it is already full.
Underflow =>
Underflow occurs when data is being read from the FIFO memory while it is already empty.

Synchronous FIFO
A FIFO is a buffer with separate read and write ports for sending signals/data. In this case both ports are
controlled by the clock from same domain (i.e. same clock frequency). Usually, they are used with high clock
frequency to support high-speed systems.
In synchronous FIFO, as the read and write pointers will be incremented with the same clock it is easy to compare
them and enable the FULL and EMPTY signals accordingly.
clk rst_n

wr_ptr
wr_en nn rd_en
d_in d_out

0 1 2 3 4 - - N
full empty

rd_ptr

Signal Description
Name Description
clk Clock signal controls the timing of the FIFO operations, both the read and write
operation will perform on rising edge of clock.
rst_n It is active low asynchronous reset signal. Whenever it will be low, it resets the FIFO to
its initial state.
wr_en Whenever wr_en signal will be high, it enables writing data into the FIFO.
rd_en Whenever rd_en signal will be high, it enables reading data from the FIFO.
wr_ptr Write pointer indicates the current write position in the FIFO.
rd_ptr Read pointer indicates the current read position in the FIFO.
d_in Data to be written into FIFO is provided through the signal.
d_out Data read from FIFO is available on the signal.
full Indicates FIFO is full, and can’t accept more data.
empty Indicates FIFO is empty, and does not contain any data.

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Simulation Result =>

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RTL Schematic =>

Asynchronous FIFO
In asynchronous FIFO both the read and write ports are controlled by different clock domains. Usually,
Asynchronous FIFO is solution for Clock Domain Crossing (CDC) where if the signal/data are moving from a faster
clock domain to a slower clock domain.
In asynchronous FIFO this is slightly complicated and involves extra logic for the generation of FULL and EMPTY
signals as the read and write pointers are getting incremented with two different clocks.

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Signal Description

Name Description
wclk The clock signal for the write side of the FIFO.
rclk The clock signal for the read side of the FIFO.
wrst_n Write reset, active low signal for write side of FIFO.
rrst_n Read reset, active low signal for read side of FIFO.
waddr Write address used to keep track of the next write operation.
raddr Read address used to keep track of the next read operation.
wptr Write pointer keeps track of the current write position in the FIFO.
rptr Read pointer keeps track of the current read position in the FIFO.
winc Write increment used to indicate that a new data element is being written into the FIFO.
It is usually a pulse signal that increments the write pointer.
rinc Read increment used to indicate that a new data element is being read from the FIFO.
It is usually a pulse signal that increments the read pointer.
wdata Write Data input to the FIFO from the write side(producer). Data to be stored in the FIFO
is presented here.
rdata Read Data output to the FIFO from the read side(consumer). Data read from the FIFO is
presented here.
wempty A status signal indicating that FIFO is empty from the perspective of the write domain.
It is typically used to prevent underflow.
rfull A status signal indicating that FIFO is full from the perspective of the read domain.
It is used to prevent overflow.

Simulation Result=>

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RTL Schematic =>

Check my previous post : “RTL Design of AMBA AHB Protocol”.

“RTL Design of AXI Stream Protocol”.
“RTL Design of UART Protocol”.

✔️ For source code ping me on LinkedIn.