TC74VHC299F/FT

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74VHC299F, TC74VHC299FT
8-Bit PIPO Shift Register with Asynchronous Clear

The TC74VHC299 is an advanced high speed CMOS 8-BIT

PIPO SHIFT REGISTER fabricated with silicon gate C2MOS TC74VHC299F
technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
It has a four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and
LOAD DATA) controlled by the two selection inputs (S0, S1).
When one or both enable ( G1 , G2 ) are high, the eight I/O are
forced to the high-impedance state; however, sequential
operation or clearing of the register is not affected.
TC74VHC299FT
All inputs are equipped with protection circuits against static
discharge.

Features (Note 1) (Note 2) (Note 3)

• High speed: fmax = 160 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• ∼ tpHL
Balanced propagation delays: tpLH −
• Wide operating voltage range: VCC (opr) = 2 to 5.5 V Weight
SOP20-P-300-1.27A : 0.22 g (typ.)
• Low noise: VOLP = 1.2 V (max) TSSOP20-P-0044-0.65A : 0.08 g (typ.)
• Pin and function compatible with 74ALS299

Note 1: Do not apply a signal to A/QA to H/QH bus terminal when it is in the output mode. Damage may result.

Note 2: All floating (high impedance) A/QA to H/QH bus terminals must have their input levels fixed by means of pull
up or pull down resistors.

Note 3: A parasitic diode is formed between A/QA to H/QH bus and VCC terminals. Therefore bus terminal can not
be used to interface 5 V to 3 V systems directly.

Start of commercial production

1992-10
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Pin Assignment IEC Logic Symbol

(9) SRG 8
CLR R
S0 1 20 VCC G1 (2) &
3 EN 13
G2 (3)
G1 2 19 S1 (1)
S0 0 0
(19) M
G2 18 SL S1 1 3
3 (12)
CK C4/1→/2←
G/QG 4 17 QH’ (11) (8)
SR 1, 4D QA’
(7)
E/QE 5 16 H/QH A/QA 3, 4D
Z5
(13) 5, 13
C/QC 6 15 F/QF B/QB 3, 4D
Z6
6, 13
(6)
A/QA 7 14 D/QD C/QC
(14)
QA’ 8 13 B/QB D/QD
(5)
E/QE
CLR 9 12 CK
(15)
F/QF
GND 10 11 SR (4)
G/QG
(16)
H/QH 3, 4D
(top view) 12, 13 Z12
(18) 2, 4D (17)
SL QH’

Truth Table
Inputs
Inputs Outputs
/Outputs
Function
Mode Output Control Serial
Select
CLR CK A/QA H/QH QA’ QH’
G1 G2
S1 S0 SL SR
(Note) (Note)
Z L H H X X X X X Z Z L L
L L X L L X X X L L L L
Clear
L X L L L X X X L L L L
Hold H L L L L X X X QA0 QH0 QA0 QH0
H L H L L X H H QGn H QGn
Shift Right
H L H L L X L L QGn L QGn
H H L L L H X QBn H QBn H
Shift Left
H H L L L L X QBn L QBn L
Load H H H X X X X a h a h

Note: When one or both output controls are high, the eight input/output terminals are in the high-impedance state;
however sequential or clearing of the register is not affected.

Z: High impedance

Qn0: The level of Qn before the indicated steady-state input conditions were established.

Qnn: The level of Qn before the most recent active transition indicated by ↓ or ↑.

a, h: The level of the steady-state inputs A, H, respectively.

X: Don’t care.

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Timing Chart

CK
Mode
S0
Control
Inputs
S1

CLR
Serial SR
Data
Inputs SL

Outputs QA’

A/QA

B/QB

C/QC

D/QD
Inputs/
Outputs
E/QE

F/QF

G/QG

H/QH

Outputs QH’

SHIFT RIGHT SHIFT LEFT HOLD

CLEAR LOAD CLEAR

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System Diagram

SL QH’
17
18
CK
16
D Q H/QH
R

CK
4
D Q G/QG
R

CK
15
D Q F/QF
R

CK
5
D Q E/QE
R

CK
14
D Q D/QD
R

CK
6
D Q C/QC
R

CK
13
D Q B/QB
R

CK
7
D Q A/QA
R

1
S0

19
S1
11 12 8 9 2 3
SR CK QA’ CLR G1 G2

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Absolute Maximum Ratings (Note)

Characteristics Symbol Rating Unit

Supply voltage range VCC −0.5 to 7.0 V

DC input voltage VIN −0.5 to 7.0 V
DC bus I/O voltage
VIN/OUT −0.5 to VCC + 0.5 V
(A/QA to H/QH’)
DC output voltage
VOUT −0.5 to VCC + 0.5 V
(QA’ to QH’)
Input diode current IIK −20 mA
Output diode current IOK ±20 mA
DC output current IOUT ±25 mA
DC VCC/ground current ICC ±80 mA
Power dissipation PD 180 mW
Storage temperature Tstg −65 to 150 °C

Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).

Operating Ranges (Note)

Characteristics Symbol Rating Unit

Supply voltage VCC 2.0 to 5.5 V

Input voltage VIN 0 to 5.5 V
DC bus I/O voltage
VIN/OUT 0 to VCC V
(A/QA to H/QH)
DC output voltage
VOUT 0 to VCC V
(QA’ to QH’)
Operating temperature Topr −40 to 85 °C
0 to 100 (VCC = 3.3 ± 0.3 V)
Input rise and fall time dt/dV ns/V
0 to 20 (VCC = 5 ± 0.5 V)

Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.

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Electrical Characteristics
DC Characteristics
Ta =
Test Condition Ta = 25°C
Characteristics Symbol −40 to 85°C Unit
VCC (V) Min Typ. Max Min Max

2.0 1.50 ― ― 1.50 ―

High-level input
VIH ― VCC × VCC × V
voltage 3.0 to 5.5 ― ― ―
0.7 0.7

2.0 ― ― 0.50 ― 0.50

Low-level input
VIL ― VCC × VCC × V
voltage 3.0 to 5.5 ― ― ―
0.3 0.3
2.0 1.9 2.0 ― 1.9 ―
IOH = −50 μA 3.0 2.9 3.0 ― 2.9 ―
High-level output VIN
VOH 4.5 4.4 4.5 ― 4.4 ― V
voltage = VIH or VIL
IOH = −4 mA 3.0 2.58 ― ― 2.48 ―
IOH = −8 mA 4.5 3.94 ― ― 3.80 ―
2.0 ― 0.0 0.1 ― 0.1
IOL = 50 μA 3.0 ― 0.0 0.1 ― 0.1
Low-level output VIN
VOL 4.5 ― 0.0 0.1 ― 0.1 V
voltage = VIH or VIL
IOL = 4 mA 3.0 ― ― 0.36 ― 0.44
IOL = 8 mA 4.5 ― ― 0.36 ― 0.44

3-state output VIN = VIH or VIL

IOZ 5.5 ― ― ±0.25 ― ±2.50 μA
off-state current VOUT = VCC or GND
Input leakage
IIN VIN = 5.5 V or GND 0 to 5.5 ― ― ±0.1 ― ±1.0 μA
current
Quiescent supply
ICC VIN = VCC or GND 5.5 ― ― 4.0 ― 40.0 μA
current

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AC Characteristics (input: tr = tf = 3 ns)
Ta =
Test Condition Ta = 25°C
Characteristics Symbol −40 to 85°C Unit
VCC (V) CL (pF) Min Typ. Max Min Max
15 ― 12.2 17.2 1.0 19.8
Propagation delay 3.3 ± 0.3
tpLH 50 ― 14.7 20.7 1.0 23.3
time ― ns
tpHL 15 ― 8.5 10.8 1.0 12.0
(CK-QA’, QH’)
5.0 ± 0.5
50 ― 10.0 12.8 1.0 14.0
15 ― 13.0 19.0 1.0 22.0
Propagation delay 3.3 ± 0.3
50 ― 15.5 22.5 1.0 25.5
time tpHL ― ns
( CLR -QA’, QH’) 15 ― 9.1 11.2 1.0 13.5
5.0 ± 0.5
50 ― 10.8 13.2 1.0 15.5
15 ― 10.3 14.3 1.0 16.6
Propagation delay 3.3 ± 0.3
tpLH 50 ― 12.8 17.8 1.0 20.1
time ― ns
tpHL 15 ― 7.3 9.1 1.0 10.4
(CK-QA to QH) 5.0 ± 0.5
50 ― 8.8 11.1 1.0 12.4
15 ― 10.8 17.0 1.0 19.5
Propagation delay 3.3 ± 0.3
50 ― 13.3 20.5 1.0 23.0
time tpHL ― ns
( CLR -QA to QH) 15 ― 7.7 10.5 1.0 12.0
5.0 ± 0.5
50 ― 9.2 12.5 1.0 14.0
15 ― 13.3 16.5 1.0 19.2
3.3 ± 0.3
tpZL 50 ― 14.8 19.0 1.0 21.7
Output enable time RL = 1 kΩ ns
tpZH 15 ― 8.9 9.7 1.0 11.3
5.0 ± 0.5
50 ― 10.4 11.2 1.0 12.6
tpLZ 3.3 ± 0.3 50 ― 18.0 21.3 1.0 24.3
Output disable time RL = 1 kΩ ns
tpHZ 5.0 ± 0.5 50 ― 11.8 13.2 1.0 15.0
15 65 100 ― 55 ―
3.3 ± 0.3
Maximum clock 50 55 90 ― 50 ―
fmax ― MHz
frequency 15 125 160 ― 110 ―
5.0 ± 0.5
50 115 150 ― 100 ―
Input capacitance CIN ― ― 4 10 ― ― pF
Bus I/O capacitance
COUT ― ― 8 ― ― ― pF
(A/QA to H/QH)
Power dissipation
CPD (Note) ― 110 ― ― ― pF
capacitance

Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.

Average operating current can be obtained by the equation:

ICC (opr) = CPD·VCC·fIN + ICC

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Timing Requirements (input: tr = tf = 3 ns)
Ta =
Test Condition Ta = 25°C −40 to
Characteristics Symbol 85°C Unit
VCC (V) Typ. Limit Limit
Minimum pulse width tw (H) 3.3 ± 0.3 ― 7.0 8.0
― ns
(CK) tw (L) 5.0 ± 0.5 ― 7.0 8.0
Minimum pulse width 3.3 ± 0.3 ― 6.0 7.0
tw (L) ― ns
( CLR ) 5.0 ± 0.5 ― 6.0 7.0
Minimum set-up time 3.3 ± 0.3 ― 8.5 10.0
ts ― ns
(SL, SR) 5.0 ± 0.5 ― 5.0 5.0
Minimum set-up time 3.3 ± 0.3 ― 8.0 9.0
ts ― ns
(A to H) 5.0 ± 0.5 ― 4.0 4.0
Minimum set-up time 3.3 ± 0.3 ― 14.5 17.0
ts ― ns
(S0, S1) 5.0 ± 0.5 ― 7.0 8.0
Minimum hold time 3.3 ± 0.3 ― 1.0 1.0
th ― ns
(SL, SR) 5.0 ± 0.5 ― 1.0 1.0
Minimum hold time 3.3 ± 0.3 ― 0.5 0.5
th ― ns
(A to H) 5.0 ± 0.5 ― 1.5 1.5
Minimum hold time 3.3 ± 0.3 ― 0 0
th ― ns
(S0, S1) 5.0 ± 0.5 ― 0.5 0.5
Minimum removal time 3.3 ± 0.3 ― 5.0 6.0
trem ― ns
( CLR ) 5.0 ± 0.5 ― 4.0 4.0

Noise Characteristics (input: tr = tf = 3 ns)

Test Condition Ta = 25°C
Characteristics Symbol Unit
VCC (V) Typ. Limit
Quiet output maximum dynamic
VOLP CL = 50 pF 5.0 0.9 1.2 V
VOL
Quiet output minimum dynamic
VOLV CL = 50 pF 5.0 −0.9 −1.2 V
VOL
Minimum high level dynamic input
VIHD CL = 50 pF 5.0 ― 3.5 V
Voltage
Maximum low high level dynamic
VILD CL = 50 pF 5.0 ― 1.5 V
input Voltage

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Input Equivalent Circuit A/QA to H/QH Bus Terminal Equivalent Circuit

INPUT I/O

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 TC74VHC299F/FT
Package Dimensions

Weight: 0.22 g (typ.)

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 TC74VHC299F/FT
Package Dimensions

Weight: 0.08 g (typ.)

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 TC74VHC299F/FT

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