EECS151/251A

Spring 2018
Digital Design and
Integrated Circuits
Instructors:
John Wawrzynek and Nick Weaver

Lecture 21:
Multiplier Circuits
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 Multiplication
a3 a2 a1 a0 Multiplicand
b3 b2 b1 b0 Multiplier

X a 3b 0 a 2b 0 a1b 0 a0b 0
a3 b 1 a2b 1 a1b 1 a 0b 1 Partial
a 3b 2 a 2b 2 a1b 2 a 0b 2 products
a 3b 3 a 2b 3 a1b 3 a 0b 3

... a1b0+a0b1 a0b0 Product

Many different circuits exist for multiplication.

Each one has a different balance between
speed (performance) and amount of logic (cost).
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 “Shift and Add” Multiplier
• Sums each partial
product, one at a time.
• In binary, each partial
product is shifted
versions of A or 0.

Control Algorithm:
1. P ← 0, A ← multiplicand,
B ← multiplier
2. If LSB of B==1 then add A to P
else add 0
• Cost α n, Τ = n clock cycles.
3. Shift [P][B] right 1
• What is the critical path for
determining the min clock 4. Repeat steps 2 and 3 n-1 times.
period? 5. [P][B] has product.
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 “Shift and Add” Multiplier
Signed Multiplication:
Remember for 2’s complement numbers MSB has negative weight:

ex: -6 = 110102 = 0•20 + 1•21 + 0•22 + 1•23 - 1•24

= 0 + 2 + 0 + 8 - 16 = -6

• Therefore for multiplication:

a) subtract final partial product
b) sign-extend partial products
• Modifications to shift & add circuit:
a) adder/subtractor
b) sign-extender on P shifter register
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 Outline
❑ Combinational multiplier
❑ Latency & Throughput
▪ Wallace Tree
▪ Pipelining to increase
throughput
❑ Smaller multipliers
▪ Booth encoding
▪ Serial, bit-serial
❑ Two’s complement
multiplier

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 Unsigned
Combinational
Multiplier

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 Array Multiplier
Single cycle multiply: Generates all n partial products simultaneously.
Each row: n-bit adder with AND gates

What is the critical path?

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 Combinational Multiplier (unsigned)
X3 X2 X1 X0 multiplicand
* Y3 Y2 Y1 Y0 multiplier
--------------------
X3Y0 X2Y0 X1Y0 X0Y0
Partial products, one for each bit in
+ X3Y1 X2Y1 X1Y1 X0Y1
+ X3Y2 X2Y2 X1Y2 X0Y2 multiplier (each bit needs just one
+ X3Y3 X2Y3 X1Y3 X0Y3 AND gate)
----------------------------------------- y0
x3 x2 x1 x0
Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0
y1
x3 x2 x1 x0
z0

HA FA FA HA
y2
Propagation delay ~2N x3 x2 x1 x0
z1

FA FA FA HA

x3 x2 x1 y3
x0
z2

FA FA FA HA

z7 z6 z5 z4 z3 8
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 Carry-Save Addition
• Speeding up multiplication is a • Example: sum three numbers,
matter of speeding up the 310 = 0011, 210 = 0010, 310 = 0011
summing of the partial products.
• “Carry-save” addition can help. 310 0011
• Carry-save addition passes + 210 0010
(saves) the carries to the output, carry-save add
c 0100 = 410
rather than propagating them.
s 0001 = 110

carry-save add
310 0011
c 0010 = 210
carry-propagate add s 0110 = 610
1000 = 810
• In general, carry-save addition takes in 3 numbers and produces 2.
• Whereas, carry-propagate takes 2 and produces 1.
• With this technique, we can avoid carry propagation until final addition
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 Carry-save Circuits

• When adding sets of numbers,

carry-save can be used on all
but the final sum.
• Standard adder (carry
propagate) is used for final sum.
• Carry-save is fast (no carry
propagation) and cheap (same
cost as ripple adder)

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Array Multiplier using Carry-save Addition

Fast carry-
propagate adder

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 Carry-save Addition
CSA is associative and communitive. For example:
(((X0 + X1) + X2 ) + X3 ) = ((X0 + X1) +( X2 + X3 ))

• A balanced tree can be used to

reduce the logic delay.

• This structure is the basis of the

Wallace Tree Multiplier.
• Partial products are summed
with the CSA tree. Fast CPA
(ex: CLA) is used for final sum.
• Multiplier delay α log3/2N +
log2N

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 Increasing Throughput: Pipelining
Idea: split processing
across several clock
cycles by dividing circuit
into pipeline stages
separated by registers
that hold values passing
from one stage to the
next.

= register

Throughput = 1/4tPD,FA instead of 1/8tPD,FA 13

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 Smaller Combinational
Multipliers

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Booth Recoding: Higher-radix mult.
Idea: If we could use, say, 2 bits of the multiplier in generating each
partial product we would halve the number of columns and halve the
latency of the multiplier!
AN-1 AN-2 … A4 A3 A2 A1 A0
x BM-1 BM-2 … B3 B2 B1 B0

M/2 2

...

BK+1,K*A = 0*A → 0
Booth’s insight: rewrite 2*A
= 1*A → A
and 3*A cases, leave 4A for
= 2*A → 4A – 2A
next partial product to do! = 3*A → 4A – A 15
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 Booth recoding
(On-the-fly canonical signed digit encoding!)
current bit pair from previous bit pair

BK+1 BK BK-1 action

BK+1,K*A = 0*A → 0
0 0 0 add 0 = 1*A → A
0 0 1 add A = 2*A → 4A – 2A
0 1 0 add A = 3*A → 4A – A
0 1 1 add 2*A
1 0 0 sub 2*A
1 0 1 sub A -2*A+A
1 1 0 sub A
1 1 1 add 0 -A+A

A “1” in this bit means the previous stage needed to add 4*A. Since
this stage is shifted by 2 bits with respect to the previous stage,
adding 4*A in the previous stage is like adding A in this stage! 16
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 Bit-serial Multiplier
• Bit-serial multiplier (n2 cycles, one bit of result per n cycles):

• Control Algorithm:

repeat n cycles { // outer (i) loop

repeat n cycles{ // inner (j) loop
shiftA, selectSum, shiftHI
} Note: The occurrence of a control
shiftB, shiftHI, shiftLOW, reset signal x means x=1. The absence
} of x means x=0.

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 Signed Multipliers

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Combinational Multiplier (signed!)

(-3) * (-2)

(-3) 1 0 1 (X)
(-2) * 1 1 0 (Y)
--------------------
0 0 0 0 0 0 Y0*X = 0
+ 1 1 1 0 1 2Y1*X = -6
- 1 1 0 1 4Y2*X = -12
----------------------
(+6) 0 0 0 1 1 0

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 Combinational Multiplier (signed)
X3 X2 X1 X0
* Y3 Y2 Y1 Y0
--------------------
X3Y0 X3Y0 X3Y0 X3Y0 X3Y0 X2Y0 X1Y0 X0Y0
+ X3Y1 X3Y1 X3Y1 X3Y1 X2Y1 X1Y1 X0Y1
+ X3Y2 X3Y2 X3Y2 X2Y2 X1Y2 X0Y2
- X3Y3 X3Y3 X2Y3 X1Y3 X0Y3
-----------------------------------------
y0
Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 x3 x2 x1 x0

y1
x3 x2 x1 x0
z0

FA FA FA FA FA FA HA

x3 x2 y2
x1 x0
z1

FA FA FA FA FA HA

x3 x2 x1 y3
x0
z2

FA FA FA FA FA 1
There are tricks we can use
z7 z5
to eliminate the extra
z6 z4 z3 20
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 2’s Complement Multiplication
(Baugh-Wooley)
Step 1: two’s complement operands so high Step 3: add the ones to the partial products
order bit is –2N-1. Must sign extend partial and propagate the carries. All the sign
products and subtract the last one extension bits go away!
X3 X2 X1 X0 X3Y0 X2Y0 X1Y0 X0Y0
* Y3 Y2 Y1 Y0 + X3Y1 X2Y1 X1Y1 X0Y1
-------------------- + X2Y2 X1Y2 X0Y2
X3Y0 X3Y0 X3Y0 X3Y0 X3Y0 X2Y0 X1Y0 X0Y0 + X3Y3 X2Y3 X1Y3 X0Y3
+ X3Y1 X3Y1 X3Y1 X3Y1 X2Y1 X1Y1 X0Y1 +
+ X3Y2 X3Y2 X3Y2 X2Y2 X1Y2 X0Y2 + 1
- X3Y3 X3Y3 X2Y3 X1Y3 X0Y3 - 1 1 1 1
-----------------------------------------
Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0

Step 2: don’t want all those extra additions, so Step 4: finish computing the constants…
add a carefully chosen constant, remembering
to subtract it at the end. Convert subtraction
into add of (complement + 1). X3Y0 X2Y0 X1Y0 X0Y0
X3Y0 X3Y0 X3Y0 X3Y0 X3Y0 X2Y0 X1Y0 X0Y0 + X3Y1 X2Y1 X1Y1 X0Y1
+ 1 + X2Y2 X1Y2 X0Y2
+ X3Y1 X3Y1 X3Y1 X3Y1 X2Y1 X1Y1 X0Y1 + X3Y3 X2Y3 X1Y3 X0Y3
+ 1 + 1
+ X3Y2 X3Y2 X3Y2 X2Y2 X1Y2 X0Y2 + 1 1
+ 1
+ X3Y3 X3Y3 X2Y3 X1Y3 X0Y3
+ 1 –B = ~B + 1 Result: multiplying 2’s complement operands
+ 1 takes just about same amount of hardware as
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-
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1 1 1 1 multiplying unsigned operands!
 2’s Complement Multiplication
y0
x3 x2 x1 x0

y1
x3 x2 x1 x0
1 z0

FA FA FA HA

x3 x2 y2
x1 x0
z1

FA FA FA HA

x3 x2 x1 y3
x0
1 z2

HA FA FA FA HA

z7 z6 z5 z4 z3

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 Multiplication in Verilog
You can use the “*” operator to multiply two numbers:

wire [9:0] a,b;

wire [19:0] result = a*b; // unsigned multiplication!

If you want Verilog to treat your operands as signed two’s complement

numbers, add the keyword signed to your wire or reg declaration:
wire signed [9:0] a,b;
wire signed [19:0] result = a*b; // signed multiplication!

Remember: unlike addition and subtraction, you need different circuitry

if your multiplication operands are signed vs. unsigned. Same is true of
the >>> (arithmetic right shift) operator. To get signed operations all
operands must be signed.
wire signed [9:0] a;
wire [9:0] b;
wire signed [19:0] result = a*$signed(b);

To make a signed constant: 10’sh37C 23

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