VLSI CIRCUIT DESIGN

MODULE 5
Textbook
 K.R. Botkar, “Integrated Circuits”, Khanna Publishers.
Basic IC fabrication steps
 Wafer Preparation
 Oxidation
 Ion Implantation
 Chemical Vapour Deposition (CVD)
 Lithography
 Metallization
 Packaging
Material Preparation – Purification
Silicon ?
Wafer chip

Fig: Silicon ingots

(top) and wafers
(bottom) of
different diameters
Wafer chip

Fig: Silicon ingots

Material Preparation
 Silicon is the most abundant material on earth
 Commonly available natural sources of silicon are silica and silicates.
 Production of Electronic Grade Silicon (EGS)
Why Silicon is preferred?
• Material cost is negligible, only manufacturing cost occurs
• Ideal energy gap (1.12eV)
• Excellent quality of SiO2
 Si + O2 -->SiO2
 Si + 2H2O → SiO2 + 2H2
 Excellent (Si-SiO2) interface
 Lower defects
 Si devices can operate at a higher temperature (150oC vs 100oC)
Production of Silicon Crystal
Mettalurgical Grade Silicon (MGS)
Electronic Grade Silicon (EGS)
 RAW
MATERIAL
MGS
Reduction using carbon
(Quartzite)

Reaction
with
HCl

Reduction
CZ or FZ with
Single process Hydrogen TCS
Crystal EGS (TriChloroSilane)
Silicon
Electronic Grade Silicon (EGS)
 The starting material for Si wafer manufacture is called
Electronic grade Si (EGS).
 A polycrystalline material of high purity, is the starting

material for the preparation of single crystal silicon.

 i.e., Purest form of Si (99.99999999%)
 Impurities – B, C & residual donors.
 Pure EGS will have doping elements in ppb (parts per billion)
range, and carbon less than 2 ppm
Electronic Grade Silicon (EGS)

 EGS is purified from MGS (Metallurgical Grade Silicon)

 MGS  98% pure form

 Impurities
 Fe and Al

 Produced in Arc furnace

 Quartzite and carbon
Metallurgical Grade Si (MGS)

 Quartzite
 Relatively pure form of sand (SiO2)

 Carbon
 Coal,

 Coke,

 Wood chips.
Metallurgical Grade Si (MGS)

 Overall reaction
 SiC + SiO2  Si + SiO + CO
(solid) (solid) (liquid) (gas) (gas)

 Molten Si removed from bottom of the furnace.

 Solidified at a purity of 98%
 Purity is not enough for the manufacture of semiconductor devices
Fig: Schematic of
submerged-
electrode arc
furnace for the
production of
metallurgical-
grade silicon
(MGS).
 Production of EGS from MGS
(Anhydrous
HCL)

Trichlorosilane
production

(silicon
tetrachloride
)
Production of EGS from MGS
 MGS has to be pulverized mechanically
 Si + 3HCl  SiHCI3 + H2
(solid) (gas) (3000C) (gas) {TCS} (gas)
 Impurities are formed, SiCl4 & chlorides.
 Purification process has to be done by fractional distillation

method.
 Purified SiHCI3 is subjected to CVD (Chemical Vapor
Deposition).
Production of EGS from MGS
 Purified  CVD.
 2SiHCl3 + 2H2  2Si + 6HCl
(gas) (gas) (solid) (gas)
 At 11000C.
 A resistive-heated Si-rod called “Slim rod”, used as the
nucleation point for the deposition of silicon.
 To achieve high overall efficiency, a feedback or recycling of
reaction of by-products is done.
Production of EGS from MGS
 EGS can also be produced by pyrolysis method in which silane
(SiH4) will be reacted with heat.
 Main advantage of using silane instead of trichlorosilane is the

lower production cost and less production of harmful reaction

by-products
 SiH4 + HEAT  Si + 2H2
(gas) (solid) (gas)
Crystal Structure and Growing
 Silicon wafer, must be single crystal, but it does not represent an ideal
crystal due to:
 The wafer has finite boundaries; thus, atoms at the surfaces are incompletely
bonded as against those in the bulk of the wafer material
 The atoms are displaced from their ideal locations by thermal agitation

 Real crystals have defects which are mainly classified into:

 Point defect
 Line defect (dislocation)
 Area or planar defect
 Volume defect
Why defect are important?
 There are a lot of properties that are controlled or affected by
defects, for example:
 Electric and thermal conductivity in metals (strongly reduced by point
defects).
 Electronic conductivity in semi-conductors (controlled by substitution defects).
 Diffusion (controlled by vacancies).
 Ionic conductivity (controlled by vacancies).
 Plastic deformation in crystalline materials (controlled by dislocation).
 Colors (affected by defects).
 Mechanical strength (strongly depended on defects).
Defects in Crystals
 Point Defects
 Vacancies, Interstitial Defects, Substitution Defects
 Line Defect
 Screw Dislocation, Line/Edge Dislocation
 Area or Planar Defect
 Twin & Grain Boundaries
 Volume Defect
Defects in Crystals
 Point Defects Other points defects
Point Defects
 A vacancy is produced when an atom is missing from a normal site.
 Substitutional – one atom is replaced by as different type of atom.
 Interstitial – extra atom is inserted into the lattice structure at a
normally unoccupied position.
 Frenkel defect – ion jumps from a normal lattice point to an interstitial
site, leaving behind a vacancy (vacancy-interstitial)
 Schottky – pair of vacancies in ionically bonded material. Both anion
and cation must be missing from the lattice to maintain the crystal
neutral.
Defects in Crystals
 Line Defect
Line/Edge Dislocation Screw Dislocation
Line Defect
 Edge dislocation is an extra half plane of atoms “inserted” into the
crystal lattice.
 Screw dislocation forms when one part of crystal lattice is shifted
(through shear) relative to the other crystal part. It is called screw as
atomic planes form a spiral surface around the dislocation line.
Defects in Crystals
 Area or Planar Defect
Grain Boundaries Twin

An error in ABCABC packing sequence

– Ex: ABCABABC
Area or Planar Defect
 A Grain Boundary is a general planar defect that separates regions
of different crystalline orientation (i.e. grains) within a polycrystalline
solid. The atoms in the grain boundary will not be in perfect crystalline
arrangement.
 Essentially a reflection of atom positions across the twin plane.
 For FCC metals an error in ABCABC packing sequence
 Eg: ABCABABC
Defects in Crystals
Volume Defect
 Volumetric defects occur on a much bigger scale than the rest of the

crystal defects.
 Precipitates of impurity or dopant atom constitute volume defect.

 Every impurity introduced into the lattice has a solubility.

Crystal Structure and Growing
 Though processes the EGS obtained is highly refined, it is not suitable
enough for the manufacturing IC’s.
 Single crystal Si manufacture
 Two types:
 Czochralski (CZ) technique
 Float zone (FZ) technique

 Crystal Growing
 Phase change from solid, liquid or gas phases to crystalline solid phase
Crystal growth
CZ {Czochralski} process
FZ {Float zone} process
Crystal Structure and Growing
 Two types: Czochralski technique (CZ) Float zone (FZ) technique

Dominant technique for Mainly used for small sized

manufacturing single crystals wafers

Specially suited for the large Producing specialty wafers

wafers that are currently used that have low oxygen impurity
in IC fabrication. concentration.
Crystal Structure and Growing
 Various components of CZ process are
 Furnace

 Crystal pulling mechanism

 Ambient control – atmosphere

 Control system
Czochralski (CZ) Process
 EGS (Electronic Grade Silicon)
 Still polycrystalline Si
 CZ crystal growth process
 EGS is processed to become single crystal
 Single crystal Si
 Ingot
 Czochralsky (CZ)
process
 Heated to Si melting point –
14200.
 Seed crystal & crucible are
rotated in opposite direction.
 Temperature & pulling rate are
correctly chosen.
 Ingot diameter of 100 to 200 mm,
3 m length; several hours for
pulling the complete ingot.
 Crystal pulling is done in inert-gas
atmosphere & sometimes vacuum,
to prevent oxidation.
 CZ Process
 Consists of:
 Furnace
 Crystal pulling mechanism

 Ambient control facility

 Control system circuitry

Czochralsky (CZ) Process Apparatus
 Furnace consist of crucible, susceptor, rotational mechanism,
heating element, power supply & chamber.
 Crucible material  most important, unreactive with molten
silicon. Silicon nitride (Si3N4) & fused silica (SiO2). Also
undergoes erosion.
 Susceptor  support silica crucible. Pure graphite material.

 Furnace chamber  airtight, prevent contamination.

Czochralsky (CZ) Process Apparatus
 Crystal pulling mechanism  seed shaft or chain, rotation
mechanism & seed chuck.
 Two parameters for growth process: pull rate & crystal rotation.
 Ambient control  for crystal growth apparatus consists of gas
sources, flow control, purge tube & exhaust or vacuum system.
 Crystal growth  in inert gas (helium/argon) or vacuum
 Hotgraphite part must be protected from O2 to prevent erosion
 Gas around process should not react with the molten Silicon.

 Control system  for crystal growth; microprocessor, sensor &

control process parameters.
CZ process
Silicon Ingot Grown by CZ Method
 Photograph
courtesy of
Kayex Corp.,
300 mm Si ingot
Silicon Ingot Grown by CZ Method
CZ process

 Impurities: oxygen and carbon

 Oxygen in Si arises from dissolution of curcible during growth
 Carbon in Si arises from dissolution of its transportation from
graphite parts in furnace to melt
• p-type (B) doped CZ process  resistivity from 0.0005 to 50
ohm-cm
• n-type (As, P) doped CZ process  resistivity from 0.005 to
40 ohm-cm
FZ Process
 The production takes place under vacuum or in an inert
gaseous atmosphere.
 The process starts with a high-purity polycrystalline rod
and a monocrystalline seed crystal that are held face to
face in a vertical position and are rotated.
 With a radio frequency field both are partially melted.
 The seed is brought up from below to make contact with
the drop of melt formed at the tip of the poly rod.
 A necking process is carried out to establish a dislocation
free crystal before the neck is allowed to increase in
diameter to form a taper and reach the desired diameter
for steady-state growth.
46 Silicon Wafer Preparation
Ingot Trimming and Slicing
Wafer Polishing and Cleaning
Wafer Processing Considerations

Reference: K R Botkar,” Integrated circuits”, Khanna Publishers

Ingot Trimming & Slicing
 Extreme top & bottom portions are cut off.
 Surface is ground.
 Constant diameter of 100, 150, or 300 mm. D

 Crystallographic orientation flat.

 Along the length of ingot.
 Circular slices or wafers. Orientation flat
 600 – 1000 µm thick.
 Correct orientation of surface of wafer w.r.t. crystal plane  imp. for
successful epitaxial layer growth.
 Fig: Ingot Trimming

Silicon Flat Grinding

Single Crystal Trimming and Peripheral
Silicon Ingots Diameter Grind Grinding
Fig: Ingot Slicing

Silicon Wafer Slicing

Slicing
A diamond saw for cutting
wafers
Wafer Polishing and Cleaning
 When the wafer is sliced, its surface will be heavily damaged.
 Reasons for polishing are:
 To remove the damaged silicon from the sawn surface.
 To produce a highly planar or flat surface that will be required for the photo-
lithographic process especially when flue-line geometries are involved.
 To improve the parallel.

 Sliced wafer will have saw marks and is 0.6 to 1 mm thick

 Raw wafer  surface damage in the order of 75 micro meters.
 Lapped  to remove saw mark & to produce a flat surface
Silicon Edge Silicon Wafer Silicon Wafer Etching
Rounding Lapping

Silicon
Wafer
Inspection
Silicon Wafer Polishing
Wafer polishing & Cleaning

 Chemical etch  Acid mixture

• Nitric Acid
 Oxidize the surface
• Hydrofluoric Acid
 Dissolve the oxide
Wafer polishing & Cleaning
 Mechanical polishing
 Polished mechanically on a wheel.
 Help of Al abrasive powders.

 Mirror like finish  one side mirror like image & flat surface with
agreeable parallelism.
 After the polishing  the wafer surface damage of around 2
micro meters deep.
 Removed by an additional chemical etching stage.
Wafer Processing Considerations
 Chemical Cleaning:
 Remove organic films, heavy metals & particulars

 Aqueous mixture of  NH4OH – H2O2, HCl – H2O2, H2SO4 -

H2O2
Wafer Processing Considerations
 Gettering Treatments:
 Transition group elements which act as the metallic impurities 
interstitial or substitutional lattice sites.
 Precipitated forms of these impurities are usually silicides (electrically
conductive).
 In VLSI circuits, transition group elements decrease their performance.
 Removes the impurities or defects from the regions in a wafer where
devices are fabricated.
Wafer Processing Considerations
 Common techniques that are used for gettering treatment are:
I. Common mechanical abrasion methods like lapping and sand
blasting are carried out to damage the back surface of the
wafer
II. A focused heat beam from a Q-pulsed, Nd-YAG laser is used
to damage the wafer
III. Intrinsic gettering - when an impurity oxygen precipitates,
defects are generated
Wafer Processing Considerations
 Thermal stress minimisation:
 Wafers experience thermal stresses as they are subjected to
high-temperature furnace.
 To minimise thermal stress, wafers are withdrawn slowly from the
furnace, which minimise temperature gradient.
Thermal Oxidation
Growth mechanisms,
Dry and Wet oxidation.
Thermal Oxidation
Utility of Thermal Oxidation:
 Silicon dioxide (Silica) layer can be formed over Si wafer.

 Role of SiO2 in IC fabrication:

 Diffusion mask,
 Surface Passivation,

 Insulator,

 Gate electrode,

 Isolate.
Thermal Oxidation
Role of SiO2 in IC fabrication:
 Diffusion mask

 Permitting selective diffusion or implantation into Si wafer.

 Surface Passivation
 Protective layer (SiO2 layer).
 Protect from moisture and atmospheric contaminants.
Thermal Oxidation
Role of SiO2 in IC fabrication:
 Insulator

 Highdielectric constant 3.9.

 Metal line to pass over active Si region.

 Active gate electrode in MOS device.

 Isolate one device from another.
 Electrical isolation multilevel metallization.
Oxidation Process
Growth Mechanism
 Silicon dioxide (Silica) layer can be formed over Si wafer

 At high temperature,

 In a stream of O2 /H2O.
 Grown oxide layers, two main growth mechanisms:
 Dry oxidation &

 Wet oxidation.
Oxidation Process
 Dry oxidation:
 Si (s) + O2 (g)  SiO2 (s)
 At high temperatures in a stream of oxygen
 Wet oxidation:
 Si (s) + 2H2O (g)  SiO2 (s) + 2H2 (g)
 Thickness of Oxide layer depends on the temperature of
oxidation furnace, the length of time that the wafers are in it,
and the flow rate of oxygen.
Oxidation Process
• Both case, Si is supplied by the underlying wafer.
 Dry and wet oxidation

 High temperature (900 - 1200 0C) for growth,

 Kinetics are different

 Process is called thermal oxidation.

 Oxidation Process in IC Fabrication
 The rate of oxidation can be significantly increased by adding water
vapour to the oxygen supply to the oxidizing furnace

Oxidation time (hr) Time (min)

Fig: Growth rate of SiO2 in a dry Fig: Growth rate of SiO2 in a steam atmosphere which
oxygen atmosphere is much greater than in dry oxygen
Oxidation Process (Growth Mechanism)

Schematic cross section of the Si oxide interface showing the oxide

thickness, d’, and the thickness of Si consumed, d, to form the oxide.
The ratio of the thicknesses is inversely proportional to the densities
and directly proportional to the atomic/molecular weights.
Thermal Oxidation – Growth Mechanism
Growth rate of silicon oxide layer

Fig: (a) Oxidation of Silicon. (b) Oxide-thickness (tox) versus time for
thermal oxidation of silicon.
Thermal Oxidation – Growth Mechanism
 As the thickness of silicon dioxide is increased, the rate of diffusion
becomes slower.
 In the initial growth process, the rate of thickness is directly
proportional to the time of growth.
 However, after certain time, the thickness of oxide is proportional to
the square root of growth time.
 The rate of oxide growth using H2O as the oxidant will be about four
times faster than the rate obtained with O2.
 H2O molecule is about one-half the size of the O2 molecule
Thermal Oxidation – Growth Mechanism

Thermal Oxidation – Growth Mechanism
Growth rate of silicon oxide layer
 Rate of oxide growth

 Wet oxidation 4 times faster than dry oxidation,

 H2O molecule is one half size of O2 molecule.

 Dry oxide (O2)

 More denser,
 High dielectric strength,
 Suitable for growth of Gate in MOS.

 Dry-Wet-Dry
 Sandwich model.

https://www.youtube.com/watch?v=nzF8f6ocqXo
Basics of Thermal Oxidation
 In thermal oxidation, silicon reacts with oxygen to form silicon dioxide
(SiO2).
 To speed up the chemical reaction, it is necessary to carry out the
oxidation at high temperatures (e.g., 1000–1200°C) and inside
ultraclean furnaces.
 The oxygen used in the reaction can be introduced either as a high-
purity gas ( “dry oxidation”) or as steam ( “wet oxidation”).
 The selection of oxidation technique to be used depends on oxide
properties and the thickness of the oxide layer required.
Thermal Oxidation
Wet oxidation Dry oxidation
When oxidizing atmosphere contains When oxidizing atmosphere contains
water vapour, temperature between oxygen, temperature 12000C
9000C and 10000C
Si (s) + 2H2O (g)  SiO2 (s) + 2H2 (g) Si (s) + O2 (g)  SiO2 (s)

Thickness > 1mm Thickness < 1mm

Used to grow thick oxide layer called Used to grow thin oxide layer
field oxide layer
Dry oxidation
Dry oxidation:
 Si (s) + O2 (g)  SiO2 (s)

 Oxide thickness for Si at

different temperatures for dry
oxidation.
 Best for thin oxide layers with

a low charge at the interface.

Characteristic of the dry oxidation
 A silicon atom directly reacts with an oxygen molecule to produce one
molecule of silicon dioxide.
 Dry oxidation is also the preferred process when contamination by

sodium atoms is a concern.

Characteristic of the dry oxidation:
 Slow growth of oxide,
 High density,

 High breakdown voltage.

Wet oxidation
Wet oxidation:
 Si (s) + 2H2O (g)  SiO2 (s)
+ 2H2 (g)
 Oxide thickness for Si at
different temperatures for
wet oxidation.
 Wet oxidation is carried out
at lower temperature than
dry oxidation to get uniform
thickness.
Characteristics of wet thermal oxidation
 Water in the form of steam reacts with silicon to produce silicon
dioxide and hydrogen gas. (the oxygen is led through a bubbler vessel
filled with heated water of about 95 °C).
 This process is used to produce thick oxide layers with relatively low

temperatures and high pressure.

 This process is done by 900 to 1000°C.

Characteristics of wet thermal oxidation:

 Fast growth even on low temperatures
 Less quality than dry oxides
Dry & Wet Oxidation

Advantages Disadvantages
Dry (O2) Better Electrical Breakdown, Dense, Slow Growth Rate
Used for Gates

Wet (O2+H2O) Fast Growth Rate, good for device Somewhat Porous (sponge
isolation, contact isolation, etc... analogy) Not used for gate
oxides
In general, wet oxidation has a faster growth rate, but dry oxidation gives
better electrical characteristics
Thermal Oxidation

 In VLSI, thermal oxidation is a way to produce a thin layer of oxide on

the surface of a wafer.

 The rate of oxide growth is often predicted by the Deal-Grove model.

 Thermal oxidation may be applied to different materials, but most

commonly involves the oxidation of silicon substrates to produce silicon
dioxide.
Thermal Oxidation Process
Thermal Oxidation Process
 The thermal oxidation of silicon begins by placing the silicon wafers in a
quartz rack, commonly known as a boat, which is heated in a quartz
thermal oxidation furnace.

 The furnaces consist of a quartz tube in which the wafers are placed on
a carrier made of quartz glass.

 For heating there are several heating zones and for chemical supply
multiple pipes.
Thermal Oxidation Process
 The temperature in the furnace may be between 950 and 1250°C under
standard pressure.
 Quartz glass has a very high melting point (above 1500°C) and thus is
applicable for high temperature processes.
 A control system is needed to keep the wafers within about 19°C of the
desired temperature.
 Oxygen or steam is introduced into the thermal oxidation furnace,
depending on the type of oxidation being performed.
Thermal Oxidation Process
 Oxygen from these gases then diffuses from the surface of the
substrate through the oxide layer to the silicon layer.
 The oxygen is led to the wafers in gaseous state and reacts at

the wafer surface to form silicon dioxide.

 The composition and depth of the oxidation layer may be

precisely controlled by parameters such as time, temperature,

pressure and gas concentration.
Thermal Oxidation Process
 High temperature increases the oxidation rate, but it also
increases the impurities and movement of the junction between
the silicon and oxide layers.
 These characteristics are particularly undesirable when the
oxidation process requires multiple steps, as is the case with
complex ICs.
 A lower temperature produces an oxide layer of higher quality,
but also increases the growth time.
Thermal Oxidation Process
 The typical solution to this problem is to heat the wafers at a
relatively low temperature and high pressure to reduce the
growth time.
 An increase of one standard atmosphere (atm) decreases the
required temperature by about 20 degrees Celsius, assuming
all other factors are equal.
 Industrial applications of thermal oxidation use up to 25 atm of
pressure with a temperature between 700 and 900°C.
Thermal Oxidation Process
 The oxide growth rate is initially very fast but slows down as
oxygen must diffuse through a thicker oxide layer to reach the
silicon substrate.
 Almost 46 percent of the oxide layer penetrates the original
substrate after oxidation is complete, leaving 54 percent of the
oxide layer on top of the substrate.
Growth Mechanism (Oxide Charges)
 The interlace between silicon and silicon
dioxide contains a transition region.
 Various charges and traps are
associated with the thermally oxidized
silicon, some of which are related to the
transition region.
 A charge at the interface can induce a
charge of the opposite polarity in the
underlying Si.
Oxide Charges
 Four charges are associated
with insulators and insulator
/semiconductor interfaces:
 Mobile Ionic Charge (Qm)
 Oxide Trapped Charge (Qot)

 Interface Trapped Charge (Qit)

 Fixed Oxide Charge (Qf)

Oxide Charges
 Mobile Ionic Charge:
 BAD!!!! Leads to fluctuations in turn on voltages with time.
 Attributed to alkali ions such as K, Na, Li in oxides as well as negative ions
and heavy metals.
 Density of Qm ranges from 1010 cm-2 to 1012 cm-2.

 Oxide Trapped Charge:

 Defects in the SiO2 can result from avalanche injection, ionizing radiation or
high currents in the oxide.
 May be positive or negative, due to holes or electrons trapped in bulk of the
oxide.
Oxide Charges
 Interface Trapped Charge:
 Results from broken bonds at the Si/SiO2 interface.
 Structural defects related to the oxidation process, metallic impurities,
& bond breaking processes.
 Fixed Oxide Charge:
 Usually positive charge is located within ~30 angstroms (~3 nm) from
the interface.
 Cannot be charged or discharged.
 Determined by both temperature and ambient conditions.
Oxidation Process (Growth Mechanism)

Molecular density of SiO2

Atomic density of Si