AXI P
[Link] Configuration Fields Source
i) Write Addr Channel Signals
1 AWVALID Master
2 AWREADY Slave
3 AWADDR Master
4 AWPROT Master
5 AWID Master
6 AWLEN Master
7 AWSIZE Master
8 AWBURST Master
9 AWLOCK Master
ii) Write Data Channel Signals
10 WVALID Master
11 WREADY Slave
12 WDATA Master
13 WSTRB Master
14 WID Master
15 WLAST Master
iii) Write Response Channel Signals
16 BVALID Slave
17 BREADY Master
18 BRESP Slave
19 BID Slave
iv) Read Addr Channel Signals
20 ARVALID Master
21 ARREADY Slave
22 ARADDR Master
23 ARPROT Master
24 ARID Master
25 ARLEN Master
26 ARSIZE Master
27 ARBURST Master
28 ARLOCK Master
v) Read Data Channel Signals
29 RVALID Slave
30 RREADY Master
31 RDATA Slave
32 RRESP Slave
33 RLAST Slave
34 RID Slave
vi) Control Fields
35 write_type Config Class
36 read_type Config Class
37 delay_type Config Class
38 address_type Config Class
AXI PROTOCOL FIELDS CONFIGURATION
Description
When this signal is asserted -> channel is signaling address and
control information
When this signal is asserted -> channel is signaling address and
control information
Gives the Addr of the first transfer in Burst
Indicates Privilage and Security level and mentions whether the
transaction is data access or instr access
Identification tag for the write address group
Mentions the number of data transfers associated with the
address
Indicates size of each transfer
Mentions Burst type and how to determine the address of each
bursttransfer within the burst
Provides the atomic characterisitcs of the transfer
Indicates valid write data and strobes are available
indicates slave can accept data
The Main Data
Indicates which byte lanes hold valid data.
this signal is the ID tag of the write data transfer
Indicates last transfer in a write burst
Indicates the channel is signalling a valid write response
Indicates Master can accept write response
Indicates the status of the write transaction
Indicates ID tag of write response
Indicates channel is signaling valid read addr and control info
Slave ready to accept addr and control info
gives the addr of the first transfer in a read burst
Privilage and security level of the transaction and whether the
transaction is data scces or instr access
ID tag for read addr group of signals
Indicates exact number of transfers in a burst
Indicates size of each transfer
Indicates burst type and how to determine the addr for each
transfer withinthe burst
provides info on atomic characteristics of the transfer
Indicates the channel is signaling the required data
Indicates the master can accept the read data and resp info
Read Data
Indicates the status of read transfer
the last transfer in a read burst
ID tag for the read data group of signals gen by slave
Allows us to configure AWBURST variable
Allows us to configure AWBURST variable
Allows us to mention the delay , is customizable
Allows us to configure AxADDR variable
OCOL FIELDS CONFIGURATION
Dependency
The Address and Control info should be present in the data bus when
asserting this signal
No Direct Dependency on any Slave signals or Master Signals
No Direct Dependency on any Master signals or Slave Signals
No Direct Dependency on any other signals
No Direct Dependency on any other signals
No Dependency on any Signals
The Data should be present in the data bus when asserting this signal
No Direct dependency on any Master aor Slave signals
Note the strobe length depends upon the data bus width . The
relationship between data bus and strobe is AxDATA/8 == STROB
Comments Implementation Status
Needs to be high until the complete transfer
Needs to be high until the complete transfer
The adress has to be calculated based on the type
of burst transfer
Needs to be same as WID
AXI4 supports INCR burst length from 1 to 256
transfers. For wrapping bursts , the burst length
should be 2 ,4,9 or 16 . A burst should not cross a 4
KB address boundary and early termination of
bursts is not supported
AXI supports byte transfer i.e you can transfer data
interms of bytes only . It supports 2^n byte transfer
, where n takes value between o to 7
AXI4 supports 3 types of Burst Transfers ,they are
1)Fixed 2)INCR (increment) 3)WRAP
one byte strobe for each bytein the lane.
Needs to be same as AWID
The slave can assert the BVALID signal only when it
drives a valid write response
The signal can be of 4 types 1) OKAY 2)EXOKAY
3)SLVRR 4)DECERR
AXI4 supports INCR burst length from 1 to 256
transfers. For wrapping bursts , the burst length
should be 2 ,4,9 or 16 . A burst should not cross a 4
KB address boundary and early termination of
bursts is not supported
AXI supports byte transfer i.e you can transfer data
interms of bytes only . It supports 2^n byte transfer
, where n takes value between o to 7
AXI4 supports 3 types of Burst Transfers ,they are
1)Fixed 2)INCR (increment) 3)WRAP
The signal can be of 4 types 1) OKAY 2)EXOKAY
3)SLVRR 4)DECERR
We can mention what type of WRITE Burst we
want among the three types of burst. Used in
Configuration of the Base Class
We can mention what type of READ Burst we want
amongthe three types of burst. Used in
Configuration of the Base Class
Used to mention the delay between valid and
ready
