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Vinay Sahu - VLSI Physical Design Expert

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0% found this document useful (0 votes)
59 views2 pages

Vinay Sahu - VLSI Physical Design Expert

Uploaded by

bhalekar8962
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Name: Vinay Sahu

Email: vinaysahu1431@gmail.com
Contact No: +91-6265306183

CAREER OBJECTIVE:
To be a part of organization that gives a scope to enhance my knowledge and utilizing my skills
towards the growth of organization.

PROFESSIONAL EXPERIENCE:
 Completed Physical Design Course from october 2023 to march 2024 in Takshila Institute
of VLSI technologies.
 Good Understanding of block level Physical design and verification concepts like Floor
planning, CTS, STA, DRC/LVS, DFM etc.
 Practical exposure to Physical Design tools from IC Compiler tools.

TECHNICAL SKILLS:
 Strong understanding in the RTL to GDSII flow or design implementation.
 Good in concepts related to synthesis, place and route, CTS .
 Good knowledge and experience in Block-level Floor-planning and Physical verification.
 Working experience with tools like ICC.
 Strong knowledge in standard place and route flows ICC/Synopsys flows preferred.
 Well versed with timing constraints and STA.
 Good knowledge of Windows 7, 8 and Linux.

ACADEMIC QUALIFICATION:

Year of Percentage/
Qualification Name of Institution
Passing CGPA
B.Tech (EEE) Shri Balaji Institute of technology management 2023 7.82
Betul mp
XII Sanjivani H.S.School Betul MP 2019 55%
X Sanjivani H.S.School Betul MP 2017 72.66%

CERTIFICATIONS:
 Takshila Institute of VLSI Technologies
Title: Professional Training on Physical Design.
PROJECT WORKED ON:
Title ORCA_TOP

Tool used IC Compiler


Description
 Technology: 32nm
 No. of macros: 40
 Layer: 9
 Std. cell count: 56013
 No. of Clocks: 7
 Frequency: 416MHz

Responsibilities Iterative Floorplan, IO ports placement, Powerplanning, Placement and


CTS reviews, Routing and DRC checks.

Title ORCA_TOP_IO

Tool used IC Compiler


Description
 Technology: 28nm
 No. of macros: 30
 Layer: 9
 Std. cell count: 50000
 No. of Clocks: 7
 Frequency: 400MHz

Responsibilities Iterative Floorplanning and Power-planning


Placement and CTS optimization
Physical Verification and manual optimization
Timing Closure and ECO

ACADEMIC PROJECT:

The” Design of Boost converter using MATLAB simulation”. This project aim to Step up the input
DC voltage to some higher voltage level.

PERSONAL PROFILE:
Date of Birth : 21th Fabruary 2002
Languages Known : English, Hindi.
Permanent Address : S/o Mr Tulsiram Sahu , Near of
Ganeshji tempal Shastri ward
Sadar bazaar Betul
Madhyapradesh (460001)

Date:
Place:

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