4Mb

SMART 5 BOOT BLOCK FLASH MEMORY

FLASH MEMORY MT28F004B5

MT28F400B5
5V Only, Dual Supply (Smart 5)
0.18µm Process Technology

FEATURES
• Seven erase blocks:
16KB/8K-word boot block (protected) 40-Pin TSOP Type I 48-Pin TSOP Type I
Two 8KB/4K-word parameter blocks
Four main memory blocks
• Smart 5 technology (B5):
5V ±10% VCC
5V ±10% VPP application/production
programming1
• Advanced 0.18µm CMOS floating-gate process
• Compatible with 0.3µm Smart 5 device
• Address access time: 80ns
44-Pin SOP2
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• Byte- or word-wide READ and WRITE
(MT28F400B5, 256K x 16/512K x 8)
• Byte-wide READ and WRITE only
(MT28F004B5, 512K x 8)
• TSOP and SOP packaging options
GENERAL DESCRIPTION
The MT28F004B5 (x8) and MT28F400B5 (x16, x8)
OPTIONS MARKING are nonvolatile, electrically block-erasable (Flash),
• Timing programmable, read-only memories containing
80ns access -8 4,194,304 bits organized as 262,144 words (16 bits) or
• Configurations 524,288 bytes (8 bits). Writing or erasing the device is
512K x 8 MT28F004B5 done with a 5V VPP voltage, while all operations are
256K x 16/512K x 8 MT28F400B5
• Boot Block Starting Word Address
performed with a 5V VCC. Due to process technology
Top (3FFFFh) T advances, 5V VPP is optimal for application and pro-
Bottom (00000h) B duction programming. These devices are fabricated
• Operating Temperature Range with Micron’s advanced 0.18µm CMOS floating-gate
Extended (-40ºC to +85ºC) ET process.
• Packages The MT28F004B5 and MT28F400B5 are organized
MT28F004B5 into seven separately erasable blocks. To ensure that
Plastic 40-pin (standard) TSOP Type I VG
Plastic 40-pin (lead free) TSOP Type I VP
critical firmware is protected from accidental erasure
MT28F400B5 or overwrite, the devices feature a hardware-protected
Plastic 48-pin (standard) TSOP Type I WG boot block. Writing or erasing the boot block requires
Plastic 48-pin (lead free) TSOP Type I WP either applying a super-voltage to the RP# pin or driv-
Plastic 44-pin (standard) SOP SG2 ing WP# HIGH in addition to executing the normal
Plastic 44-pin (lead free) SOP SP2 write or erase sequences. This block may be used to
Notes: 1. This generation of devices does not support 12V VPP store code implemented in low-level system recovery.
compatibility production programming; however, 5V The remaining blocks vary in density and are written
VPP application production programming can be used and erased with no additional security measures.
with no loss of performance.
Please refer to Micron’s Web site (www.micron.com/
2. Contact factory for availability.
flash) for the latest data sheet.
Part Number Example:
MT28F400B5WG-8 T

09005aef8075d1f1 ©2002 Micron Technology, Inc.

MT28F004B5.fm - Rev. 4, Pub. 2/2004 1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
Pin Assignment (Top View)

48-Pin TSOP Type I 44-PIN SOP1

VPP 1 44 RP#
A15 1 48 A16
WP# 2 43 WE#
A14 2 47 BYTE#
A13 3 46 VSS A17 3 42 A8
A12 4 45 DQ15/(A-1) A7 4 41 A9
A11 5 44 DQ7
A6 5 40 A10
A10 6 43 DQ14
A9 7 42 DQ6 A5 6 39 A11
A8 8 41 DQ13 A4 7 38 A12
NC 9 40 DQ5 A3 8 37 A13
NC 10 39 DQ12
WE# 11 38 DQ4 A2 9 36 A14
RP# 12 37 VCC A1 10 35 A15
VPP 13 36 DQ11 A0 11 34 A16
WP# 14 35 DQ3
CE# 12 33 BYTE#
NC 15 34 DQ10
NC 16 33 DQ2 VSS 13 32 VSS
A17 17 32 DQ9 OE# 14 31 DQ15/(A-1)
A7 18 31 DQ1
DQ0 15 30 DQ7
A6 19 30 DQ8
A5 20 29 DQ0 DQ8 16 29 DQ14
A4 21 28 OE# DQ1 17 28 DQ6
A3 22 27 VSS DQ9 18 27 DQ13
A2 23 26 CE#
A1 24 25 A0 DQ2 19 26 DQ5
DQ10 20 25 DQ12
DQ3 21 24 DQ4
DQ11 22 23 VCC

Order Number and Part Marking Order Number and Part Marking
MT28F400B5WG-8 B MT28F400B5WP-8 B MT28F400B5SG-8 B MT28F400B5SP-8 B
MT28F400B5WG-8 T MT28F400B5WP-8 T MT28F400B5SG-8 T MT28F400B5SP-8 T
MT28F400B5WG-8 BET MT28F400B5WP-8 BET MT28F400B5SG-8 BET MT28F400B5SPG-8 BET
MT28F400B5WG-8 TET MT28F400B5WP-8 TET MT28F400B5SG-8 TET MT28F400B5SP-8 TET

40-Pin TSOP Type I

A16 1 40 A17
A15 2 39 VSS
A14 3 38 NC
A13 4 37 NC
A12 5 36 A10
A11 6 35 DQ7
A9 7 34 DQ6
A8 8 33 DQ5
WE# 9 32 DQ4
RP# 10 31 VCC
VPP 11 30 VCC
WP# 12 29 NC
A18 13 28 DQ3
A7 14 27 DQ2
A6 15 26 DQ1
A5 16 25 DQ0
A4 17 24 OE#
A3 18 23 VSS
A2 19 22 CE#
A1 20 21 A0

Order Number and Part Marking

MT28F004B5VG-8 B MT28F004B5VP-8 B
MT28F004B5VG-8 T MT28F004B5VP-8 T
MT28F400B5SG-8 BET MT28F004B5VP-8 BET
MT28F004B5VG-8 TET MT28F004B5VP-8 TET

Notes: 1. Contact factory for availability.

09005aef8075d1f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F004B5.fm - Rev. 4, Pub. 2/2004 2 ©2002 Micron Technology, Inc.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
Functional Block Diagram
Input
8 Buffer

BYTE#1
I/O
Control
Logic Input
7
Buffer

16KB Boot Block

Addr.
8KB Parameter Block
A0–A17/(18) Buffer/ 18 (19) 9

X - Decoder/Block Erase Control

8KB Parameter Block
Latch
A9 9
96KB Main Block
Input
(10) Buffer
128KB Main Block
Addr.
A-1
Power Counter
Input Data
(Current)
Latch/Mux DQ15/(A - 1)1
Control 128KB Main Block

16
WP# DQ8–DQ141
128KB Main Block
CE# State
Command
OE#
Execution Machine
Y-
7 DQ0–DQ7
WE# Logic Decoder Y - Select Gates
RP# 8
VCC Sense Amplifiers
VPP Write/Erase-Bit
Switch/ Compare and Verify Output
VPP Buffer
Pump

DQ15

Status Identification Output

7 Buffer
Register Register

8
Output

MUX
Buffer
8

Notes: 1. Does not apply to MT28F004B5.

09005aef8075d1f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F004B5.fm - Rev. 4, Pub. 2/2004 3 ©2002 Micron Technology, Inc.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY

PIN DESCRIPTIONS
40-PIN 48-PIN
44-PIN SOP TSOP TSOP
NUMBERS NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION
43 9 11 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle.
If WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
2 12 14 WP# Input Write Protect: Unlocks the boot block when HIGH if VPP =
5V and RP# = VIH during a WRITE or ERASE. Does not affect
WRITE or ERASE operation on other blocks.
12 22 26 CE# Input Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
44 10 12 RP# Input Reset/Power-Down: When LOW, RP# clears the status
register, sets the internal state machine (ISM) to the array
read mode and places the device in deep power-down
mode. All inputs, including CE#, are “Don’t Care,” and all
outputs are High-Z. RP# unlocks the boot block and
overrides the condition of WP# when at VHH, and must be
held at VIH during all other modes of operation.
14 24 28 OE# Input Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
33 – 47 BYTE# Input Byte Enable: If BYTE# = HIGH, the upper byte is active
through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are
High-Z, and all data is accessed through DQ0–DQ7. DQ15/
(A-1) becomes the least significant address input.
11, 10, 9, 8, 21, 20, 19, 25, 24, 23, A0–A17/ Input Address Inputs: Select a unique, 16-bit word or 8-bit byte.
7, 6, 5, 4, 18, 17, 22, 21, 20, (A18) The Q15/(A-1) input becomes the lowest order address
42, 41, 40, 16,15, 14, 8, 19, 18, 8, 7, when BYTE# = LOW (MT28F400B5) to allow for a selection
39, 38, 37, 7, 36, 6, 5, 6, 5, 4, 3, 2, of an 8-bit byte from the 524,288 available.
36, 35, 34, 3 4, 3, 2, 1, 1, 48, 17
40, 13
31 – 45 DQ15 Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input:
(A-1) Output LSB of address input when BYTE# = LOW during READ or
WRITE operation.
15, 17, 19, 25-28, 32-35 29, 31, 33, DQ0–DQ7 Input/ Data I/Os: Data output pins during any READ operation or
21, 24, 26, 35, 38, 40, Output data input pins during a WRITE. These pins are used to
28, 30 42, 44 input commands to the CEL.
16, 18, 20, – 30, 32, 34, DQ8– Input/ Data I/Os: Data output pins during any READ operation or
22, 25, 27, 36, 39, 41, DQ14 Output data input pins during a WRITE when BYTE# = HIGH. These
29 43 pins are High-Z when BYTE# is LOW.
1 11 13 VPP Supply Write/Erase Supply Voltage: From a WRITE or ERASE
CONFIRM until completion of the WRITE or ERASE, VPP
must be at VPPH (5V). VPP = “Don’t Care” during all other
operations.
23 30, 31 37 VCC Supply Power Supply: +5V ±10%.
13, 32 23, 39 27, 46 VSS Supply Ground.
– 29, 37, 38 9, 10, 15, 16 NC – No Connect: These pins may be driven or left unconnected.

09005aef8075d1f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F004B5.fm - Rev. 4, Pub. 2/2004 4 ©2002 Micron Technology, Inc.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY

TRUTH TABLE (MT28F400B5)1

DQ0– DQ8– DQ15/
FUNCTION RP# CE# OE# WE# WP# BYTE# A0 A9 VPP DQ7 DQ14 A-1
Standby H H X X X X X X X High-Z High-Z High-Z
Reset L X X X X X X X X High-Z High-Z High-Z
READ
READ (word mode) H L L H X H X X X Data-Out Data-Out Data-Out
READ (byte mode) H L L H X L X X X Data-Out High-Z A-1
Output Disable H L H H X X X X X High-Z High-Z High-Z
WRITE/ERASE (EXCEPT BOOT BLOCK)2
ERASE SETUP H L H L X X X X X 20h X X
3 H L H L X X X X VPPH D0h X X
ERASE CONFIRM
WRITE SETUP H L H L X X X X X 10h/40h X X
WRITE (word mode)4 H L H L X H X X VPPH Data-In Data-In Data-In
4 H L H L X L X X VPPH Data-In X A-1
WRITE (byte mode)
READ ARRAY5 H L H L X X X X X FFh X X
WRITE/ERASE (BOOT BLOCK)2
ERASE SETUP H L H L X X X X X 20h X X
3 VHH L H L X X X X VPPH D0h X X
ERASE CONFIRM
ERASE CONFIRM3, 6 H L H L H X X X VPPH D0h X X
WRITE SETUP H L H L X X X X X 10h/40h X X
4 VHH L H L X H X X VPPH Data-In Data-In Data-In
WRITE (word mode)
WRITE (word mode)4, 6 H L H L H H X X VPPH Data-In Data-In Data-In
WRITE (byte mode)4 VHH L H L X L X X VPPH Data-In X A-1
4, 6 H L H L H L X X VPPH Data-In X A-1
WRITE (byte mode)
READ ARRAY5 H L H L X X X X X FFh X X
DEVICE IDENTIFICATION7
Manufacturer H L L H X H L VID X 89hX 00h –
Compatibility (word
mode)8
Manufacturer H L L H X L L VID X 89h High-Z X
Compatibility (byte
mode)
Device (word mode, top H L L H X H H VID X 70h 44h –
boot)8
Device (byte mode, top H L L H X L H VID X 70h High-Z X
boot)
Device (word mode, H L L H X H H VID X 71h 44h –
bottom boot)8
Device (byte mode, H L L H X L H VID X 71h High-Z X
bottom boot)

Notes: 1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).

2. VPPH = 5V.
3. Operation must be preceded by ERASE SETUP command.
4. Operation must be preceded by WRITE SETUP command.
5. The READ ARRAY command must be issued before reading the array after writing or erasing.
6. When WP# = VIH, RP# may be at VIH or VHH.
7. A1–A8, A10–A17 = VIL.
8. Value reflects DQ8–DQ15.

09005aef8075d1f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F004B5.fm - Rev. 4, Pub. 2/2004 5 ©2002 Micron Technology, Inc.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY

TRUTH TABLE (MT28F004B5)1

FUNCTION RP# CE# OE# WE# WP# A0 A9 VPP DQ0–DQ7
Standby H H X X X X X X High-Z
RESET L X X X X X X X High-Z
READ
READ H L L H X X X X Data-Out
Output Disable H L H H X X X X High-Z
WRITE/ERASE (EXCEPT BOOT BLOCK)2
ERASE SETUP H L H L X X X X 20h
ERASE CONFIRM3 H L H L X X X VPPH D0h
WRITE SETUP H L H L X X X X 10h/40h
WRITE4 H L H L X X X VPPH Data-In
READ ARRAY5 H L H L X X X X FFh
WRITE/ERASE (BOOT BLOCK)2
ERASE SETUP H L H L X X X X 20h
ERASE CONFIRM3 VHH L H L X X X VPPH D0h
ERASE CONFIRM3, 6 H L H L H X X VPPH D0h
WRITE SETUP H L H L X X X X 10h/40h
WRITE4 VHH L H L X X X VPPH Data-In
WRITE4, 6 H L H L H X X VPPH Data-In
READ ARRAY5 H L H L X X X X FFh
7
DEVICE IDENTIFICATION
Manufacturer Compatibility H L L H X L VID X 89h
Device (top boot) H L L H X H VID X 78h
Device (bottom boot) H L L H X H VID X 79h

Notes: 1. L = VIL, H = VIH, X = VIL or VIH.

2. VPPH = 5V.
3. Operation must be preceded by ERASE SETUP command.
4. Operation must be preceded by WRITE SETUP command.
5. The READ ARRAY command must be issued before reading the array after writing or erasing.
6. When WP# = VIH, RP# may be at VIH or VHH.
7. A1–A8, A10–A18 = VIL.

09005aef8075d1f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F004B5.fm - Rev. 4, Pub. 2/2004 6 ©2002 Micron Technology, Inc.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
FUNCTIONAL DESCRIPTION
The MT28F004B5 and MT28F400B5 Flash memo- (5V) on the VPP pin, before a WRITE or ERASE will be
ries incorporate a number of features ideally suited for performed on the boot block. The remaining blocks
system firmware. The memory array is segmented into require that only the VPP voltage be present on the VPP
individual erase blocks. Each block may be erased pin before writing or erasing.
without affecting data stored in other blocks. These
memory blocks are read, written and erased with com- Hardware-Protected Boot
mands to the command execution logic (CEL). The This block of the memory array can be erased or
CEL controls the operation of the internal state written only when the RP# pin is taken to VHH or when
machine (ISM), which completely controls all WRITE, the WP# pin is brought HIGH. This provides additional
BLOCK ERASE, and VERIFY operations. The ISM pro- security for the core firmware during in-system firm-
tects each memory location from over-erasure and ware updates should an unintentional power fluctua-
optimizes each memory location for maximum data tion or system reset occur. The MT28F004B5 and
retention. In addition, the ISM greatly simplifies the MT28F400B5 are available with the boot block starting
control necessary for writing the device in-system or in at the bottom of the address space (“B” suffix) or the
an external programmer. top of the address space (“T” suffix).
The Functional Description provides detailed infor-
mation on the operation of the MT28F004B5 and Selectable Bus Size (MT28F400B5 only)
MT28F400B5 and is organized into these sections: The MT28F400B5 allows selection of an 8-bit (512K
x 8) or 16-bit (256K x 16) data bus for reading and writ-
• Overview ing the memory. The BYTE# pin is used to select the
• Memory Architecture bus width. In the x16 configuration, control data is
• Output (READ) operations read or written only on the lower eight bits (DQ0–
• Input Operations DQ7).
• Command Set Data written to the memory array utilizes all active
• ISM Status Register data pins for the selected configuration. When the x8
• Command Execution configuration is selected, data is written in byte form;
• Error Handling when the x16 configuration is selected, data is written
• WRITE/ERASE Cycle Endurance in word form.
• Power Usage
• Power-Up
Internal State Machine (ISM)
Block erase and byte/word write timing are simpli-
fied with an ISM that controls all erase and write algo-
OVERVIEW rithms in the memory array. The ISM ensures
Smart 5 Technology (B5) protection against overerasure and optimizes write
Smart 5 technology allows maximum flexibility for margin to each cell.
in-system READ, WRITE and ERASE operations. For During WRITE operations, the ISM automatically
5V-only systems, WRITE and ERASE operations may be increments and monitors WRITE attempts, verifies
executed with a VPP voltage of 5V. Due to process tech- write margin on each memory cell and updates the
nology advances, 5V VPP is optimal for application and ISM status register. When BLOCK ERASE is performed,
production programming. the ISM automatically overwrites the entire addressed
block (eliminates overerasure), increments and moni-
Seven Independently Erasable tors ERASE attempts, and sets bits in the ISM status
Memory Blocks register.
The MT28F004B5 and MT28F400B5 are organized
into seven independently erasable memory blocks that ISM Status Register
allow portions of the memory to be erased without The ISM status register enables an external proces-
affecting the rest of the memory data. A special boot sor to monitor the status of the ISM during WRITE and
block is hardware-protected against inadvertent era- ERASE operations. Two bits of the 8-bit status register
sure or writing by requiring either a super-voltage on are set and cleared entirely by the ISM. These bits indi-
the RP# pin or driving the WP# pin HIGH. One of these cate whether the ISM is busy with a WRITE or ERASE
two conditions must exist, along with the VPP voltage task and when an ERASE has been suspended. Addi-

09005aef8075d1f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F004B5.fm - Rev. 4, Pub. 2/2004 7 ©2002 Micron Technology, Inc.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
tional error information is set in three other bits: VPP remaining six blocks do not require that either of these
status, write status, and erase status. two conditions be met before WRITE or ERASE opera-
tions.
Command Execution Logic (CEL)
The CEL receives and interprets commands to the Boot Block
device. These commands control the operation of the The hardware-protected boot block provides extra
ISM and the read path (i.e., memory array, ID register security for the most sensitive portions of the firm-
or status register). Commands may be issued to the ware. This 16KB block may only be erased or written
CEL while the ISM is active. However, there are restric- when the RP# pin is at the specified boot block unlock
tions on what commands are allowed in this condition. voltage (VHH) or when the WP# pin is VIH. During a
See the Command Execution section for more detail. WRITE or ERASE of the boot block, the RP# pin must
be held at VHH or the WP# pin held HIGH until the
Deep Power-down Mode ERASE or WRITE is completed. The VPP pin must be at
To allow for maximum power conservation, the VPPH (5V) when the boot block is written to or erased.
MT28F004B5 and MT28F400B5 feature a very low cur- The MT28F004B5 and MT28F400B5 are available in
rent, deep power-down mode. To enter this mode, the two configurations and top or bottom boot block. The
RP# pin is taken to VSS ±0.2V. In this mode, the current top boot block version supports processors of the x86
draw is a maximum of 20µA at 5V VCC. Entering deep variety. The bottom boot block version is intended for
power-down also clears the status register and sets the 680X0 and RISC applications. Figure 1 illustrates the
ISM to the read array mode. memory address maps associated with these two ver-
sions.
MEMORY ARCHITECTURE
The MT28F004B5 and MT28F400B5 memory array Parameter Blocks
architecture is designed to allow sections to be erased The two 8KB parameter blocks store less sensitive
without disturbing the rest of the array. The array is and more frequently changing system parameters and
divided into seven addressable blocks that vary in size also may store configuration or diagnostic coding.
and are independently erasable. When blocks rather These blocks are enabled for erasure when the VPP pin
than the entire array are erased, total device endur- is at VPPH. No super-voltage unlock or WP# control is
ance is enhanced, as is system flexibility. Only the required.
ERASE function is block-oriented. All READ and
WRITE operations are done on a random-access basis. Main Memory Blocks
The boot block is protected from unintentional The four remaining blocks are general-purpose
ERASE or WRITE operations with a hardware protec- memory blocks and do not require a super-voltage on
tion circuit that requires a super-voltage be applied to RP# or WP# control to be erased or written. These
RP# or that the WP# pin be driven HIGH before erasure blocks are intended for code storage, ROM-resident
is commenced. The boot block is intended for the core applications or operating systems that require in-sys-
firmware required for basic system functionality. The tem update capability.

09005aef8075d1f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F004B5.fm - Rev. 4, Pub. 2/2004 8 ©2002 Micron Technology, Inc.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
Figure 1
Memory Address Maps

Bottom Boot Top Boot

MT28F004B5/400B5xx-xxB MT28F004B5/400B5xx-xxT

WORD ADDRESS BYTE ADDRESS WORD ADDRESS BYTE ADDRESS

3FFFFh 7FFFFh 3FFFFh 7FFFFh
16KB Boot Block
3E000h 7C000h
128KB Main Block 3DFFFh 7BFFFh
3D000h 7A000h 8KB Parameter Block
3CFFFh 79FFFh
30000h 60000h 3C000h 78000h 8KB Parameter Block
2FFFFh 5FFFFh 3BFFFh 77FFFh

96KB Main Block

128KB Main Block
30000h 60000h
2FFFFh 5FFFFh
20000h 40000h
1FFFFh 3FFFFh
128KB Main Block

128KB Main Block

20000h 40000h
1FFFFh 3FFFFh
10000h 20000h
0FFFFh 1FFFFh
128KB Main Block
96KB Main Block

04000h 08000h 10000h 20000h

03FFFh 07FFFh 0FFFFh 1FFFFh
03000h 06000h 8KB Parameter Block
02FFFh 05FFFh 8KB Parameter Block
02000h 04000h 128KB Main Block
01FFFh 03FFFh
16KB Boot Block
00000h 00000h 00000h 00000h

09005aef8075d1f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F004B5.fm - Rev. 4, Pub. 2/2004 9 ©2002 Micron Technology, Inc.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
OUTPUT (READ) OPERATIONS
The MT28F004B5 and MT28F400B5 feature three REGISTER may be given to return to the status register
different types of READS. Depending on the current read mode. All commands and their operations are
mode of the device, a READ operation produces data described in the Command Set and Command Execu-
from the memory array, status register or device iden- tion sections.
tification register. In each of these three cases, the
WE#, CE# and OE# inputs are controlled in a similar Identification Registers
manner. Moving between modes to perform a specific A READ of the two 8-bit device identification regis-
read is described in the Command Execution section. ters requires the same input sequencing as a READ of
the array. WE# must be HIGH, and OE# and CE# must
Memory Array be LOW. However, ID register data is output only on
To read the memory array, WE# must be HIGH, and DQ0–DQ7, regardless of the condition of BYTE# on the
OE# and CE# must be LOW. Valid data is output on the MT28F400B5. A0 is used to decode between the two
DQ pins when these conditions have been met and a bytes of the device ID register; all other address inputs
valid address is given. Valid data remains on the DQ are “Don’t Care.” When A0 is LOW, the manufacturer
pins until the address changes, or until OE# or CE# compatibility ID is output, and when A0 is HIGH, the
goes HIGH, whichever occurs first. The DQ pins con- device ID is output. DQ8–DQ15 are High-Z when
tinue to output new data after each address transition BYTE# is LOW. When BYTE# is HIGH, DQ8–DQ15 are
as long as OE# and CE# remain LOW. 00h when the manufacturer compatibility ID is read
The MT28F400B5 features selectable bus widths. and 44h when the device ID is read.
When the memory array is accessed as a 256K x 16, To get to the identification register read mode,
BYTE# is HIGH, and data will be output on DQ0– READ IDENTIFICATION may be issued while the
DQ15. To access the memory array as a 512K x 8, device is in certain other modes. In addition, the iden-
BYTE# must be LOW, DQ8–DQ14 are High-Z, and all tification register read mode can be reached by apply-
data is output on DQ0–DQ7. The DQ15/(A - 1) pin ing a super-voltage (VID) to the A9 pin. Using this
becomes the lowest order address input so that method, the ID register can be read while the device is
524,288 locations can be read. in any mode. When A9 is returned to VIL or VIH, the
After power-up or RESET, the device is automati- device returns to the previous mode.
cally in the array read mode. All commands and their
operations are described in the Command Set and INPUT OPERATIONS
Command Execution sections. The DQ pins are used either to input data to the
array or to input a command to the CEL. A command
Status Register input issues an 8-bit command to the CEL to control
Performing a READ of the status register requires the mode of operation of the device. A WRITE is used
the same input sequencing as a READ of the array to input data to the memory array. The following sec-
except that the address inputs are “Don’t Care.” The tion describes both types of inputs. More information
status register contents are always output on DQ0– describing how to use the two types of inputs to write
DQ7, regardless of the condition of BYTE# on the or erase the device is provided in the Command Execu-
MT28F400B5. DQ8–DQ15 are LOW when BYTE# is tion section.
HIGH, and DQ8–DQ14 are High-Z when BYTE# is
LOW. Data from the status register is latched on the Commands
falling edge of OE# or CE#, whichever occurs last. If the To perform a command input, OE# must be HIGH,
contents of the status register change during a READ of and CE# and WE# must be LOW. Addresses are “Don’t
the status register, either OE# or CE# may be toggled Care” but must be held stable, except during an ERASE
while the other is held LOW to update the output. CONFIRM (described in a later section). The 8-bit
Following a WRITE or ERASE, the device automati- command is input on DQ0–DQ7, while DQ8–DQ15 are
cally enters the status register read mode. In addition, “Don’t Care” on the MT28F400B5. The command is
a READ during a WRITE or ERASE produces the status latched on the rising edge of CE# (CE#-controlled) or
register contents on DQ0–DQ7. When the device is in WE# (WE#-controlled), whichever occurs first. The
the erase suspend mode, a READ operation produces condition of BYTE# on the MT28F400B5 has no effect
the status register contents until another command is on a command input.
issued, while in certain other modes, READ STATUS

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 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
Memory Array Selectable bus sizing applies to WRITEs as it does to
A WRITE to the memory array sets the desired bits READs on the MT28F400B5. When BYTE# is LOW (byte
to logic 0s but cannot change a given bit to a logic 1 mode), data is input on DQ0–DQ7, DQ8–DQ14 are
from a logic 0. Setting any bits to a logic 1 requires that High-Z and DQ15 becomes the lowest order address
the entire block be erased. To perform a WRITE, OE# input. When BYTE# is HIGH (word mode), data is
must be HIGH, CE# and WE# must be LOW, and VPP input on DQ0–DQ15.
must be set to VPPH. Writing to the boot block also
requires that the RP# pin be at VHH or WP# be HIGH. COMMAND SET
A0–A17/(A18) provide the address to be written, while To simplify writing of the memory blocks, the
the data to be written to the array is input on the DQ MT28F004B5 and MT28F400B5 incorporate an ISM
pins. The data and addresses are latched on the rising that controls all internal algorithms for the WRITE and
edge of CE# (CE#-controlled) or WE# (WE#-con- ERASE cycles. An 8-bit command set is used to control
trolled), whichever occurs first. A WRITE must be pre- the device. Details on how to sequence commands are
ceded by a WRITE SETUP command. Details on how to provided in the Command Execution section. Table 1
input data to the array are described in the Write lists the valid commands.
Sequence section.

Table 1: Command Set

COMMAND HEX CODE DESCRIPTION
RESERVED 00h This command and all unlisted commands are invalid and should not be
called. These commands are reserved to allow for future feature
enhancements.
READ ARRAY FFh Must be issued after any other command cycle before the array can be read.
It is not necessary to issue this command after power-up or RESET.
IDENTIFY DEVICE 90h Allows the device ID and manufacturer compatibility ID to be read. A0 is
used to decode between the manufacturer compatibility ID (A0 = LOW) and
device ID (A0 = HIGH).
READ STATUS REGISTER 70h Allows the status register to be read. Please refer to Table 2 for more
information on the status register bits.
CLEAR STATUS REGISTER 50h Clears status register bits 3–5, which cannot be cleared by the ISM.
ERASE SETUP 20h The first command given in the two-cycle ERASE sequence. The ERASE is not
completed unless followed by ERASE CONFIRM.
ERASE CONFIRM/RESUME D0h The second command given in the two-cycle ERASE sequence. Must follow
an ERASE SETUP command to be valid. Also used during an ERASE SUSPEND
to resume the ERASE.
WRITE SETUP 40h or 10h The first command given in the two-cycle WRITE sequence. The write data
and address are given in the following cycle to complete the WRITE.
ERASE SUSPEND B0h Requests a halt of the ERASE and puts the device into the erase suspend
mode. When the device is in this mode, only READ STATUS REGISTER, READ
ARRAY and ERASE RESUME commands may be executed.

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 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
ISM STATUS REGISTER
The 8-bit ISM status register (see Table 2) is polled ISM. The erase, write and VPP status bits must be
to check for WRITE or ERASE completion or any cleared using CLEAR STATUS REGISTER. If the Vpp
related errors. During or following a WRITE, ERASE or status bit (SR3) is set, the CEL does not allow further
ERASE SUSPEND, a READ operation outputs the sta- WRITE or ERASE operations until the status register is
tus register contents on DQ0–DQ7 without prior com- cleared. This enables the user to choose when to poll
mand. While the status register contents are read, the and clear the status register. For example, the host sys-
outputs are not updated if there is a change in the ISM tem may perform multiple BYTE WRITE operations
status unless OE# or CE# is toggled. If the device is not before checking the status register instead of checking
in the write, erase, erase suspend or status register read after each individual WRITE. Asserting the RP# signal
mode, READ STATUS REGISTER (70h) can be issued to or powering down the device also clears the status
view the status register contents. register.
All of the defined bits are set by the ISM, but only
the ISM and erase suspend status bits are reset by the

Table 2: Status Register

STATUS
BIT # STATUS REGISTER BIT DESCRIPTION
SR7 ISM STATUS The ISMS bit displays the active status of the state machine during
1 = Ready WRITE or BLOCK ERASE operations. The controlling logic polls this bit
0 = Busy to determine when the erase and write status bits are valid.
SR6 ERASE SUSPEND STATUS Issuing an ERASE SUSPEND places the ISM in the suspend mode and
1 = ERASE suspended sets this and the ISMS bit to “1.” The ESS bit remains “1” until an
0 = ERASE in progress/completed ERASE RESUME is issued.
SR5 ERASE STATUS ES is set to “1” after the maximum number of ERASE cycles is executed
1 = BLOCK ERASE error by the ISM without a successful verify. ES is only cleared by a CLEAR
0 = Successful BLOCK ERASE STATUS REGISTER command or after a RESET.
SR4 WRITE STATUS WS is set to “1” after the maximum number of WRITE cycles is
1 = WORD/BYTE WRITE error executed by the ISM without a successful verify. WS is only cleared by a
0 = Successful WORD/BYTE WRITE CLEAR STATUS REGISTER command or after a RESET.
SR3 VPP STATUS VPPS detects the presence of a VPP voltage. It does not monitor VPP
1 = No VPP voltage detected continuously, nor does it indicate a valid VPP voltage. The VPP pin is
0 = VPP present sampled for 5V after WRITE or ERASE CONFIRM is given. VPPS must be
cleared by CLEAR STATUS REGISTER or by a RESET.
SR0-2 RESERVED Reserved for future use.

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 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
COMMAND EXECUTION
Commands are issued to bring the device into dif- first cycle. The next cycle is the WRITE, during which
ferent operational modes. Each mode allows specific the write address and data are issued and VPP is
operations to be performed. Several modes require a brought to VPPH. Writing to the boot block also
sequence of commands to be written before they are requires that the RP# pin be brought to VHH or that the
reached. The following section describes the proper- WP# pin be brought HIGH at the same time VPP IS
ties of each mode, and Table 3 lists all command brought to VPPH. The ISM will now begin to write the
sequences required to perform the desired operation. word or byte. VPP must be held at VPPH until the write
is completed (SR7 = 1).
Read Array While the ISM executes the WRITE, the ISM status
The array read mode is the initial state of the device bit (SR7) is at “0,” and the device does not respond to
upon power-up and after a RESET. If the device is in any commands. Any READ operation produces the
any other mode, READ ARRAY (FFh) must be given to status register contents on DQ0–DQ7. When the ISM
return to the array read mode. Unlike the WRITE status bit (SR7) is set to a logic 1, the write is complete,
SETUP command (40h), READ ARRAY does not need and the device goes into the status register read mode
to be given before each individual read access. until another command is given.
After the ISM has initiated the WRITE, it cannot be
Identify Device aborted except by a RESET or by powering down the
IDENTIFY DEVICE (90h) may be written to the CEL part. Doing either during a WRITE corrupts the data
to enter the identify device mode. While the device is being written. If only the WRITE SETUP command has
in this mode, any READ produces the device ID when been given, the WRITE may be nullified by performing
A0 is HIGH and manufacturer compatibility ID when a null WRITE. To execute a null WRITE, FFh must be
A0 is LOW. The device remains in this mode until written when BYTE# is LOW, or FFFFh must be written
another command is given. when BYTE# is HIGH. When the ISM status bit (SR7) is
set, the device is in the status register read mode until
another command is issued.
WRITE Sequence
Two consecutive cycles are needed to write data to
the array. WRITE SETUP (40h or 10h) is given in the

Table 3: Command Sequences

BUS FIRST CYCLE SECOND CYCLE
CYCLES
COMMANDS REQ’D OPERATION ADDRESS DATA OPERATION ADDRESS DATA NOTES
READ ARRAY 1 WRITE X FFh 1
IDENTIFY DEVICE 3 WRITE X 90h READ IA ID 2, 3
READ STATUS REGISTER 2 WRITE X 70h READ X SRD 4
CLEAR STATUS REGISTER 1 WRITE X 50h
ERASE SETUP/CONFIRM 2 WRITE X 20h WRITE BA D0h 5, 6
ERASE SUSPEND/RESUME 2 WRITE X B0h WRITE X D0h
WRITE SETUP/WRITE 2 WRITE X 40h WRITE WA WD 6, 7
ALTERNATE WORD/BYTE 2 WRITE X 10h WRITE WA WD 6, 7
WRITE

Notes: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL to enable Flash array READ cycles.
2. IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.
3. ID = Identify Data.
4. SRD = Status Register Data.
5. On x16 (X00) devices BA = Block Address (A12–A17), on x8 (00X) devices BA = Block Address (A13–A18).
6. Addresses are “Don’t Care” in first cycle but must be held stable.
7. WA = Address to be written; WD = Data to be written to WA.

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SMART 5 BOOT BLOCK FLASH MEMORY
ERASE Sequence ERASE Suspension
Executing an ERASE sequence sets all bits within a The only command that may be issued while an
block to logic 1. The command sequence necessary to ERASE is in progress is ERASE SUSPEND. This com-
execute an ERASE is similar to that of a WRITE. To pro- mand enables other commands to be executed while
vide added security against accidental block erasure, pausing the ERASE in progress. When the device has
two consecutive command cycles are required to ini- reached the erase suspend mode, the erase suspend
tiate an ERASE of a block. In the first cycle, addresses status bit (SR6) and ISM status bit (SR7) is set. The
are “Don’t Care,” and ERASE SETUP (20h) is given. In device may now be given a READ ARRAY, ERASE
the second cycle, VPP must be brought to VPPH, an RESUME or READ STATUS REGISTER command. After
address within the block to be erased must be issued, READ ARRAY has been issued, any location not within
and ERASE CONFIRM (D0H) must be given. If a com- the block being erased may be read. If ERASE RESUME
mand other than ERASE CONFIRM is given, the write is issued before SR6 has been set, the device immedi-
and erase status bits (SR4 and SR5) are set, and the ately proceeds with the ERASE in progress.
device is in the status register read mode.
After the ERASE CONFIRM (D0h) is issued, the ISM ERROR HANDLING
starts the ERASE of the addressed block. Any READ After the ISM status bit (SR7) has been set, the VPP
operation outputs the status register contents on (SR3), write (SR4) and erase (SR5) status bits may be
DQ0–DQ7. VPP must be held at VPPH until the ERASE is checked. If one or a combination of these three bits
completed (SR7 = 1). When the ERASE is completed, has been set, an error has occurred. The ISM cannot
the device is in the status register read mode until reset these three bits. To clear these bits, CLEAR STA-
another command is issued. Erasing the boot block TUS REGISTER (50H) must be given. If the VPP status
also requires that either the RP# pin be set to VHH or bit (SR3) is set, further WRITE or ERASE operations
the WP# pin be held HIGH at the same time VPP is set cannot resume until the status register is cleared.
to VPPH. Table 4 lists the combination of errors.

Table 4: Status Register Error Decode1

STATUS BITS
SR5 SR4 SR3 ERROR DESCRIPTION
0 0 0 No errors
0 0 1 VPP voltage error
0 1 0 WRITE error
0 1 1 WRITE error, VPP voltage not valid at time of WRITE
1 0 0 ERASE error
1 0 1 ERASE error, VPP voltage not valid at time of ERASE CONFIRM
1 1 0 Command sequencing error or WRITE/ERASE error
1 1 1 Command sequencing error, VPP voltage error, with WRITE and ERASE errors

Notes: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.

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 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE ENDURANCE POWER-UP
The MT28F004B5 and MT28F400B5 are designed The likelihood of unwanted WRITE or ERASE opera-
and fabricated to meet advanced firmware storage tions is minimized because two consecutive cycles are
requirements. To ensure this level of reliability, VPP required to execute either operation. However, to reset
must be at 5V ±10% during WRITE or ERASE cycles. the ISM and to provide additional protection while VCC
Due to process technology advances, 5V VPP is optimal is ramping, one of the following conditions must be
for application and production programming. met:
• RP# must be held LOW until VCC is at valid func-
POWER USAGE tional level; or
The MT28F004B5 and MT28F400B5 offer several • CE# or WE# may be held HIGH and
power-saving features that may be utilized in the array RP# must be toggled from VCC-GND-VCC.
read mode to conserve power. Deep power-down After a power-up or RESET, the status register is
mode is enabled by bringing RP# LOW. Current draw reset, and the device enters the array read mode.
(ICC) in this mode is a maximum of 20µA at 5V VCC.
When CE# is HIGH, the device enters standby mode. In Figure 2:
this mode, maximum ICC current is 130µA at 5V. If CE# Power-Up/Reset Timing Diagram
is brought HIGH during a WRITE or ERASE, the ISM
continues to operate, and the device consumes the
RP#
respective active power until the WRITE or ERASE is
Note 1
completed.
VCC
(5V) t
AA

Address VALID

Data VALID

t
RWH

UNDEFINED

NOTE: 1. VCC must be within the valid operating range before RP#
goes HIGH.

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SMART 5 BOOT BLOCK FLASH MEMORY
Self-Timed WRITE Sequence Complete WRITE
(WORD or BYTE WRITE)1 STATUS-CHECK Sequence

Start Start (WRITE completed)

NO
SR3 = 0? VPP Error 4, 5
WRITE 40h or 10h
YES

NO
VPP = 5V SR4 = 0? BYTE/WORD WRITE Error5

YES

WRITE Word or Byte WRITE Successful

Address/Data

STATUS REGISTER
READ

NO
SR7 = 1?

YES

Complete Status2
Check (optional)

WRITE Complete 3

Notes: 1. Sequence may be repeated for additional BYTE or WORD WRITEs.

2. Complete status check is not required. However, if SR3 = 1, further WRITEs are inhibited until the status register
is cleared.
3. Device will be in status register read mode. To return to the array read mode, the FFh command must be issued.
4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further
WRITE or ERASE operations are allowed by the CEL.
5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.

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SMART 5 BOOT BLOCK FLASH MEMORY
Self-Timed BLOCK ERASE Sequence1 Complete BLOCK ERASE
STATUS-CHECK Sequence
Start
Start (ERASE completed)

WRITE 20h
NO
SR3 = 0? VPP Error 5, 6

YES
VPP = 5V
YES
SR4, 5 = 1? Command Sequence Error6

WRITE D0h,
NO
Block Address
NO
SR5 = 0? BLOCK ERASE Error6
STATUS REGISTER
ERASE
Busy

READ YES

NO ERASE Successful
NO
SR7 = 1? Suspend ERASE?

YES YES

Complete Status 2 Suspend 4

Check (optional) Sequence

ERASE Resumed

ERASE Complete 3

Notes: 1. Sequence may be repeated to erase additional blocks.

2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register
is cleared.
3. To return to the array read mode, the FFh command must be issued.
4. Refer to the ERASE SUSPEND flowchart for more information.
5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further
WRITE or ERASE operations are allowed by the CEL.
6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.

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SMART 5 BOOT BLOCK FLASH MEMORY
ERASE SUSPEND/RESUME Sequence

Start (ERASE in progress)

WRITE B0h
(ERASE SUSPEND)

VPP = 5V

STATUS REGISTER
READ

NO
SR7 = 1?

YES

NO
SR6 = 1?

YES
ERASE Completed
WRITE FFh
(READ ARRAY)

Done NO
Reading?

YES

WRITE D0h
(ERASE RESUME)

Resume ERASE

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 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute
Voltage on VCC Supply Relative to VSS ....-0.5V to +6V** Maximum Ratings” may cause permanent damage to
Input Voltage Relative to VSS ....................-0.5V to +6V** the device. This is a stress rating only, and functional
VPP Voltage Relative to VSS ...................... -0.5V to +5.5V† operation of the device at these or any other condi-
RP# or A9 Pin Voltage tions above those indicated in the operational sections
Relative to Vss ................................... -0.5V to +12.6V† of this specification is not implied. Exposure to abso-
Temperature Under Bias..........................-40ºC to +85ºC lute maximum rating conditions for extended periods
Storage Temperature (plastic) ...............-55ºC to +125ºC may affect reliability.
Power Dissipation ....................................................... 1W **VCC, input and I/O pins may transition to -2V for
<20ns and VCC + 2V for <20ns.
†Voltage may pulse to -2V for <20ns and 14V for <20ns.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC READ OPERATING

CONDITIONS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

5V Supply Voltage VCC 4.5 5.5 V 1
Input High (Logic 1) Voltage, all inputs VIH 2 VCC + 0.5 V 1
Input Low (Logic 0) Voltage, all inputs VIL -0.5 0.8 V 1
Device Identification Voltage, A9 VID 10 12.6 V 1
VPP Supply Voltage VPP -0.5 5.5 V 1

DC OPERATING CHARACTERISTICS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

OUTPUT VOLTAGE LEVELS (TTL) VOH1 2.4 – V
Output High Voltage (IOH = -2.5mA) VOL – 0.50 V 1
Output Low Voltage (IOL = 5.8mA)
OUTPUT VOLTAGE LEVELS (CMOS) VOH2 VCC - 0.4 – V 1
Output High Voltage (IOH = -100µA)
INPUT LEAKAGE CURRENT IL -1 1 µA
Any input (0V ≤ VIN ≤ VCC);
All other pins not under test = 0V
INPUT LEAKAGE CURRENT: IID – 500 µA
VHH INPUT (10V ≤ VHH ≤ 12.6V = VID)
INPUT LEAKAGE CURRENT: IHH – 500 µA
RP# INPUT (10V ≤ RP# ≤ 12.6V = VHH)
OUTPUT LEAKAGE CURRENT IOZ -10 10 µA
(DOUT is disabled; 0V ≤ VOUT ≤ VCC)

Notes: 1. All voltages referenced to VSS.

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SMART 5 BOOT BLOCK FLASH MEMORY

CAPACITANCE
(TA = +25ºC; f = 1 MHz)

PARAMETER/CONDITION SYMBOL MAX UNITS

Input Capacitance CI 9 pF
Output Capacitance CO 12 pF

READ AND STANDBY CURRENT DRAIN

(Note: 1) Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

PARAMETER/CONDITION SYMBOL MAX UNITS NOTES

READ CURRENT: WORD-WIDE, TTL INPUT LEVELS ICC1 55 mA 2, 3
(CE# = VIL; OE# = VIH; f = 10 MHz; Other inputs = VIL or VIH;
RP# = VIH)
READ CURRENT: WORD-WIDE, CMOS INPUT LEVELS ICC2 50 mA 2, 3
(CE# ≤ 0.2V; OE# ≥ VCC - 0.2V; f = 10 MHz; Other inputs ≤ 0.2V or ≥ VCC
- 0.2V; RP# ≥ VCC - 0.2V)
READ CURRENT: BYTE-WIDE, TTL INPUT LEVELS ICC3 55 mA 2, 3
(CE# = VIL; OE# = VIH; f = 10 MHz; Other inputs = VIL or VIH;
RP# = VIH)
READ CURRENT: BYTE-WIDE, CMOS INPUT LEVELS ICC4 50 mA 2, 3
(CE# ≤ 0.2V; OE# ≥ VCC - 0.2V; f = 10 MHz; Other inputs ≤ 0.2V or ≥ VCC
- 0.2V; RP# = VCC - 0.2V)
STANDBY CURRENT: TTL INPUT LEVELS ICC5 2 mA
VCC power supply standby current (CE# = RP# = VIH;
Other inputs = VIL or VIH)
STANDBY CURRENT: CMOS INPUT LEVELS ICC6 130 µA
VCC power supply standby current (CE# = RP# = VCC - 0.2V)
DEEP POWER-DOWN CURRENT: VCC SUPPLY (RP# = VSS ±0.2V) ICC8 20 µA
STANDBY OR READ CURRENT: VPP SUPPLY (VPP ≤ 5.5V) IPP1 ±15 µA
DEEP POWER-DOWN CURRENT: VPP SUPPLY (RP# = VSS ±0.2V) IPP2 5 µA

Notes: 1. Vcc = MAX during Icc tests.

2. Icc is dependent on cycle rates.
3. Icc is dependent on output loading. Specified values are obtained with the outputs open.

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READ TIMING PARAMETERS

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +5V ±10%

AC CHARACTERISTICS -8/-8 ET
PARAMETER SYMBOL MIN MAX UNITS NOTES
t
Read cycle time RC 80 ns
t
Access time from CE# ACE 80 ns 1
tAOE 40 ns 1
Access time from OE#
tAA 80 ns
Access time from address
t
RP# HIGH to output valid delay RWH 1,000 ns
t
OE# or CE# HIGH to output in High-Z OD 20 ns
t
Output hold time from OE#, CE# or address change OH 0 ns
tRP 60 ns
RP# LOW pulse width

Notes: 1. OE# may be delayed by tACE - tAOE after CE# falls before tACE is affected.

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SMART 5 BOOT BLOCK FLASH MEMORY
AC TEST CONDITIONS
Input pulse levels ..................................0.4V to 2.4V
Input rise and fall times ................................. <10ns
Input timing reference level ................ 0.8V and 2V
Output timing reference level ............. 0.8V and 2V
Output load ...................1 TTL gate and CL = 100pF

WORD-WIDE READ CYCLE1

VIH
A0–A17/(A18) VALID ADDRESS
VIL
tRC

tAA

VIH
CE#
VIL
tACE

VIH
OE#
VIL

VIH
WE#
VIL
tOD

tAOE tOH

VIH
DQ0–DQ15 VALID DATA
VIL
tRWH

VIH
RP#
VIL

DON’T CARE

UNDEFINED

TIMING PARAMETERS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

-8/-8 ET -8/-8 ET

SYMBOL MIN MAX UNITS SYMBOL MIN MAX UNITS

t 80 ns t 1,000 ns
RC RWH
tACE 80 ns tOD 20 ns
t 40 ns t 0 ns
AOE OH
t 80 ns
AA

Notes: 1. BYTE# = HIGH (MT28F400B5 only).

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SMART 5 BOOT BLOCK FLASH MEMORY
BYTE-WIDE READ CYCLE1

VIH
(A - 1)-A17/(A18) VALID ADDRESS
VIL
tRC

tAA

VIH
CE#
VIL
tACE

VIH
OE#
VIL

VIH
WE#
VIL
tOD

tAOE tOH

VIH
DQ0-DQ7 VALID DATA
VIL

VIH
DQ8-DQ14 HIGH-Z
VIL

tRWH

VIH
RP#
VIL

DON’T CARE

UNDEFINED

TIMING PARAMETERS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
Extended Temperature (-40ºC ≤ TA≤ +85ºC)

-8/-8 ET -8/-8 ET

SYMBOL MIN MAX UNITS SYMBOL MIN MAX UNITS

t 80 ns t 1,000 ns
RC RWH
t 80 ns t 20 ns
ACE OD
tAOE 40 ns tOH 0 ns
t 80 ns
AA

Notes: 1. BYTE# = LOW (MT28F400B5 only).

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RECOMMENDED DC WRITE/ERASE CONDITIONS1

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +5V ±10%

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

VPP WRITE/ERASE lockout voltage VPPLK – 1.5 V 2
VPP voltage during WRITE/ERASE operation VPPH 4.5 5.5 V 3
Boot block unlock voltage VHH 10 12.6 V
VCC WRITE/ERASE lockout voltage VLKO 2 – V

WRITE/ERASE CURRENT DRAIN

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +5V ±10%

PARAMETER/CONDITION SYMBOL MAX UNITS NOTES

WORD WRITE CURRENT: VCC SUPPLY ICC9 25 mA 4
WORD WRITE CURRENT: VPP SUPPLY IPP4 20 mA 4
BYTE WRITE CURRENT: VCC SUPPLY ICC10 25 mA 5
BYTE WRITE CURRENT: VPP SUPPLY IPP5 20 mA 5
ERASE CURRENT: VCC SUPPLY ICC11 30 mA
ERASE CURRENT: VPP SUPPLY IPP6 40 mA
ERASE SUSPEND CURRENT: VCC SUPPLY ICC12 10 mA 6
(ERASE suspended)
ERASE SUSPEND CURRENT: VPP SUPPLY IPP7 200 µA
(ERASE suspended)

Notes: 1. WRITE operations are tested at VCC/VPP voltages equal to or less than the previous ERASE, and READ operations
are tested at VCC voltages equal to or less than the previous WRITE.
2. Absolute WRITE/ERASE protection when VPP ≤ VPPLK.
3. When 5V VCC and VPP are used, VCC cannot exceed VPP by more than 500mV during WRITE and ERASE
operations.
4. Applies to MT28F400B5 only.
5. Applies to MT28F004B5 and MT28F400B5 with BYTE = LOW.
6. Parameter is specified when device is not accessed. Actual current draw will be ICC12 (5V VCC) plus read current if
a READ is executed while the device is in erase suspend mode.

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SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS: WE#- (CE#-)CONTROLLED WRITES
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +5V ±10% or
+5V ±5%

AC CHARACTERISTICS -8/-8 ET
PARAMETER SYMBOL MIN MAX UNITS NOTES
WRITE cycle time tWC 80 ns
WE# HIGH pulse width t
WPH (tCPH) 30 ns
WE# pulse width t
WP (tCP) 50 ns
Address setup time to WE# HIGH tAS 50 ns
Address hold time from WE# HIGH tAH 0 ns
Data setup time to WE# HIGH tDS 50 ns
Data hold time from WE# HIGH tDH 0 ns
CE# setup time to WE# LOW tCS (tWS) 0 ns
CE# hold time from WE# HIGH tCH (tWH) 0 ns
VPP setup time to WE# HIGH tVPS1 200 ns 1
RP# HIGH to WE# LOW delay tRS 1,000 ns
RP# at VHH or WP# HIGH setup time to WE# HIGH tRHS 100 ns 2
WRITE duration (WORD or BYTE WRITE) tWED1 4.5 µs 3
Boot BLOCK ERASE duration tWED2 100 ms 2, 3
Parameter BLOCK ERASE duration tWED3 100 ms 3
Main BLOCK ERASE duration tWED4 500 ms 3
WE# HIGH to busy status (SR7 = 0) tWB 200 ns 4
VPP hold time from status data valid tVPH 0 ns 3
RP# at VHH or WP# HIGH hold time from status data valid tRHH 0 ns 2
Boot block relock delay time tREL 100 ns 5

WORD/BYTE WRITE AND ERASE DURATION CHARACTERISTICS

PARAMETER TYP MAX UNITS NOTES
Boot/parameter BLOCK ERASE time 0.5 7 s 6
Main BLOCK ERASE time 1.5 14 s 6
Main BLOCK WRITE time (byte mode) 1 – s 6, 7, 8
Main BLOCK WRITE time (word mode) 1 – s 6, 7, 8

Notes: 1. Measured with VPP = VPPH = 5V.

2. RP# should be held at VHH or WP# held HIGH until boot block WRITE or ERASE is complete.
3. WRITE/ERASE times are measured to valid status register data (SR7 = 1).
4. Polling status register before tWB is met may falsely indicate WRITE or ERASE completion.
tREL is required to relock boot block after WRITE or ERASE to boot block.
5.
6. Typical values measured at TA = +25ºC.
7. Assumes no system overhead.
8. Typical WRITE times use checkerboard data pattern.

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WRITE/ERASE CYCLE
WE#-CONTROLLED WRITE/ERASE
VIH
A0–A17/(A18) Note 1 AIN
VIL
tAS tAH tAS tAH

VIH
CE#
VIL
tCS tCH
VIH
tWC
OE#
VIL
tWP tWED1/2/3/4
tWPH

VIH
tWB
WE#
VIL
tDH tDH
tDS tDS
VIH
DQ0–DQ7/ CMD CMD/ Status Status CMD
2
DQ0–DQ15 VIL in Data-in (SR7=0) (SR7=1) in
tRS tRHS tRHH
VHH [Unlock boot block]

VIH
RP# 3
VIL
[Unlock boot block]
VIH
3
WP#
VIL
tVPS1 tVPH

VPPH [5V VPP]

VPPLK
VPP
VIL

WRITE or ERASE (block)

WRITE or ERASE
WRITE SETUP or address asserted, and Command for next
executed, status register
ERASE SETUP input WRITE data or ERASE operation issued
checked for completion
CONFIRM issued

DON’T CARE

TIMING PARAMETERS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
Extended Temperature (-40ºC ≤ TA≤ +85ºC)
-8/-8 ET -8/-8 ET
SYMBOL MIN MAX UNITS SYMBOL MIN MAX UNITS
t
WC 4 80 ns t
RS 1,000 ns
tWPH4 30 ns tRHS 100 ns
t
WP 4 50 ns t
WED1 4.5 µs
tAS 50 ns tWED2 100 ms
tAH 0 ns tWED3 100 ms
t
DS 50 ns t
WED4 500 ms
tDH 0 ns tWB 200 ns
t
CS 0 ns t
VPH 0 ns
tCH 0 ns tRHH 0 ns
tVPS1 200 ns

Notes: 1. Address inputs are “Don’t Care” but must be held stable.
2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit
(MT28F400B5 only).

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SMART 5 BOOT BLOCK FLASH MEMORY
3. Either RP# at VHH or WP# HIGH unlocks the boot block.
4. Measurements tested under AC Test Condition 1, VCC = 5V ±10%.

09005aef8075d1f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F004B5.fm - Rev. 4, Pub. 2/2004 27 ©2002 Micron Technology, Inc.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE
CE#-CONTROLLED WRITE/ERASE
VIH
A0–A17/(A18) Note 1 AIN
VIL
tAS tAH tAS tAH

VIH
WE#
VIL
tWS tWH
VIH
tWC
OE# VIL
tCP tWED1/2/3/4
tCPH

VIH
CE#
VIL tWB
tDH
tDH
tDS tDS
VIH
DQ0–DQ7/ CMD CMD/ Status Status CMD
DQ0–DQ15 2 VIL in Data-in (SR7=0) (SR7=1) in
tRS tRHS tRHH
VHH [Unlock boot block]

VIH
RP# 3
VIL
[Unlock boot block]
VIH
3
WP#
VIL
tVPS1 tVPH

VPPH [5V VPP]

VPPLK
VPP
VIL
WRITE or ERASE (block)
WRITE or ERASE
WRITE SETUP or address asserted, and Command for next
executed, status register
ERASE SETUP input WRITE data or ERASE operation issued
checked for completion
CONFIRM issued

DON’T CARE

TIMING PARAMETERS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
Extended Temperature (-40ºC ≤ TA≤ +85ºC)
-8/-8 ET -8/-8 ET
SYMBOL MIN MAX UNITS SYMBOL MIN MAX UNITS
t
WC 4 80 ns t
RS 1,000 ns
t
WPH 4 30 ns t
RHS 100 ns
t
WP4 50 ns t
WED1 4.5 µs
tAS 50 ns tWED2 100 ms
tAH 0 ns tWED3 100 ms
t
DS 50 ns t
WED4 500 ms
t
DH 0 ns t
WB 200 ns
t
CS 0 ns t
VPH 0 ns
t
CH 0 ns t
RHH 0 ns
t
VPS1 200 ns

Notes: 1. Address inputs are “Don’t Care” but must be held stable.
2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit
(MT28F400B5 only).
3. Either RP# at VHH or WP# HIGH unlocks the boot block.

09005aef8075d1f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F004B5.fm - Rev. 4, Pub. 2/2004 28 ©2002 Micron Technology, Inc.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
4. Measurements tested under AC Test Condition 1, VCC = 5V ±10%.

44-PIN PLASTIC SOP1

(600 mil)

1.113 (28.27)
1.107 (28.12)
.007 (0.18)
.020 (0.50)
.050 (1.27) .005 (0.13)
.015 (0.38)
TYP

.643 (16.34)
.620 (15.74)

.499 (12.68)
.493 (12.52)

PIN #1 INDEX
.030 (0.76) SEE DETAIL A

.004 (0.10)

.106 (2.70) MAX .016 (0.40)

.010 (0.25)

GAGE PLANE

.010 (0.25)

DETAIL A
.0315 (0.80)
(ROTATED 90 CW)
.066 (1.72)

Notes: 1. Contact factory for availability

2. All dimensions in millimeters MAX/MIN or typical where noted.
3. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side.

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SMART 5 BOOT BLOCK FLASH MEMORY
40-PIN PLASTIC TSOP I
(10mm x 20mm)
.795 (20.20)
.780 (19.80)
.727 (18.47)
.0197 (0.50)
.721 (18.31) .010 (0.25)
TYP
1 40

PIN #1 INDEX

.397 (10.08)
.010 (0.25) .391 (9.93)
.006 (0.15)

20 21

.010 (0.25)

.004 (0.10)
.007 (0.18)
.005 (0.13)
GAGE
.047 (1.20)
PLANE
MAX
SEE DETAIL A
.008 (0.20)
.002 (0.05)
.024 (0.60)
.016 (0.40)

DETAIL A .0315 (0.80)

Notes: 1. All dimensions in millimeters MAX/MIN or typical where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side.

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MT28F004B5.fm - Rev. 4, Pub. 2/2004 30 ©2002 Micron Technology, Inc.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
48-PIN PLASTIC TSOP I1
(12mm x 20mm)
.795 (20.20)
.780 (19.80)
.727 (18.47)
.0197 (0.50)
TYP .721 (18.31) .010 (0.25)
1 48

PIN #1 INDEX

.475 (12.07)
.469 (11.91)

.010 (0.25)
.006 (0.15)

24 25

.010 (0.25)

.004 (0.10)
.007 (0.18)
SEE DETAIL A
.005 (0.12) GAGE
PLANE
.047 (1.20) MAX
.008 (0.20)
.002 (0.05)
.024 (0.60)
.016 (0.40)

DETAIL A .0315 (0.80)

Notes: 1. All dimensions in millimeters MAX/MIN or typical where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side.

DATA SHEET DESIGNATIONS

No Mark This data sheet contains minimum and maximum limits specified over the complete power supply
and temperature range for production devices. Although considered final, these specifications are
subject to change, as further product development and data characterization sometimes occur.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.

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MT28F004B5.fm - Rev. 4, Pub. 2/2004 31 ©2002 Micron Technology, Inc.
 4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
REVISION HISTORY
Rev. 4 ................................................................................................................................................................................3/04
• Added lead-free packaging options

Rev. 3 ................................................................................................................................................................................8/02
• Removed PRELIMINARY designation
• Changed tRS (MIN) from 600ns to 1,000ns
• Changed VOL (MAX)from 0.45V to 0.50V

Rev. 2, PRELIMINARY....................................................................................................................................................12/01
• Updated input capacitance specification
• Updated tRWH specification

Original document, PRELIMINARY, Rev. 1....................................................................................................................7/01

09005aef8075d1f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F004B5.fm - Rev. 4, Pub. 2/2004 32 ©2002 Micron Technology, Inc.