Question Paper
Exam Date & Time: 09-Dec-2023 (09:30 AM - 12:30 PM)
MANIPAL ACADEMY OF HIGHER EDUCATION
THIRD SEMESTER B.TECH. DEGREE EXAMINATIONS - NOVEMBER / DECEMBER 2023
SUBJECT: ECE 2124- DIGITAL SYSTEM DESIGN
DIGITAL SYSTEM DESIGN [ECE 2124]
Marks: 50 Duration: 180 mins.
A
Answer all the questions.
Missing data may be suitably assumed.
1A) Implement f(A,B,C,D) = Σ (0,3,5,9) using optimised number 2 to 4 decoders and additional gate (4)
1B) Implement a full adder using two half-adder circuits and one OR gate (3)
1C) Implement a two input NAND gate with Transistor Transistor Logic (TTL) (3)
2A) Design a combinational circuit for conversion of code 2 4 2 1 to 8 4 2 1 code (4)
2B) Design a 3-bit asynchronous down counter using T Flip Flops. (3)
2C) Illustrate how SR flip flop can be converted to JK flip flop. Also write characteristic equations for the (3)
JK flip flop
3A) Design a sequence detector to detect 1010 with overlapping using Moore model with positive edge (4)
triggered D flip flop
3B) Design 4 bit universal shift register which can handle following functionalities (3)
3C) Write dataflow Verilog code for the 4 to 1 Multiplexer with Delay (3)
4A) Write a structural Verilog code for 8:1 multiplexer using 2:1 multiplexer. (4)
4B) Write a sequential Verilog code for 8: 3 Priority encoder using case statement (3)
4C) Write the Verilog code for a 3 input AND gate as a user defined primitive (UDP) (3)
5A) Implement the following circuit using ACT-2 Sequential module (4)
Page 1 of 2
5B) Implement the following combinational circuit using Xilinx FPGA. Determine the number of CLB's (3)
and LUT's required. Show the contents in the SRAM cell.
5C) Explain ASIC Design (3)
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Scheme of Evaluation
1A Implement f(A,B,C,D) = Σ (0,3,5,9) using optimised number 2 to 4 decoders and additional gate (4M)
Any other equivalent logical diagram will also be considered and full marks will be awarded.
2x4 decoder design 2M
Logic gate for implementing function 2M
1B Implement a full adder using two half-adder circuits and one OR gate (3M)
Half - Adder circuit diagram 1M
Full Adder with Half-Adder 2M
1C Implement a two input NAND gate with Transistor Transistor Logic (TTL) 3M
correct circuit 3 M
Mistakes in the circuit only 1M will be awarded.
2A Design a combinational circuit for conversion of code 2 4 2 1 to 8 4 2 1 code 4M
Full marks (4M) will be awarded for the correct truth table, K-maps, and circuit diagram.
If don’t care condition is not considered in truth table and k-maps and the circuit is designed
- 3M
2B Design a 3-bit asynchronous down counter using T Flip Flops. 3M
Take output from Q’ terminal of FF
Other possible solutions will also be considered 3M
Wrong design will be awarded 1 M
2C Illustrate how SR flip flop can be converted to JK flip flop. Also write characteristic equations for the JK
flip flop
1M
1.5M
Characteristic equation
0.5M
3A Design a sequence detector to detect 1010 with overlapping using Moore model with positive edge
triggered D flip flop
1M
1M
Transition table
1+1M
K-Map and Circuit diagram
3B Design 4 bit universal shift register which can handle following functionalities
3M
3C Write dataflow Verilog code for the 4 to 1 Multiplexer with Delay
module mux_4to1_delay(
input [3:0] data_inputs,
input [1:0] select, 1M
output output_data
);
wire #5 output_data;
assign output_data = (select == 2'b00) ? data_inputs[0] : 2M
(select == 2'b01) ? data_inputs[1] :
(select == 2'b10) ? data_inputs[2] :
(select == 2'b11) ? data_inputs[3] :
1'b0; // Default case, in case select is not within expected range
endmodule
4A Write a structural Verilog code for 8:1 multiplexer using 2:1 multiplexer
module mux_8to1 (
input wire [7:0] data_inputs,
input wire [2:0] select, 1M
output wire output_data
);
wire [1:0] mux_level1_output, mux_level2_output;
// First level of 2-to-1 multiplexers
mux_2to1 u1 (.a(data_inputs[0]), .b(data_inputs[1]), .sel(select[0]),
.y(mux_level1_output[0]));
mux_2to1 u2 (.a(data_inputs[2]), .b(data_inputs[3]), .sel(select[0]), 2M
.y(mux_level1_output[1]));
mux_2to1 u3 (.a(data_inputs[4]), .b(data_inputs[5]), .sel(select[0]),
.y(mux_level1_output[2]));
mux_2to1 u4 (.a(data_inputs[6]), .b(data_inputs[7]), .sel(select[0]),
.y(mux_level1_output[3]));
// Second level of 2-to-1 multiplexers
mux_2to1 u5 (.a(mux_level1_output[0]), .b(mux_level1_output[1]), .sel(select[1]),
.y(mux_level2_output[0]));
mux_2to1 u6 (.a(mux_level1_output[2]), .b(mux_level1_output[3]), .sel(select[1]),
.y(mux_level2_output[1]));
// Third level of 2-to-1 multiplexer
mux_2to1 u7 (.a(mux_level2_output[0]), .b(mux_level2_output[1]), .sel(select[2]),
.y(output_data));
endmodule
module mux_2to1 (
input wire a, b, sel, 1M
output wire y
);
assign y = (sel) ? b : a; // 2-to-1 MUX logic
endmodule
4B Write a sequential Verilog code for 8: 3 Priority encoder using case statement
module priorityEncoder_8to3(
input enable,
input [7:0] data,
output reg [2:0] code,
output reg valid
);
1--Mark
always @(posedge clk or posedge reset) begin
if (reset) begin
code <= 3'b0;
valid <= 1'b0;
end else if (enable) begin
casez (data)
8'b00000001: code <= 3'b111; valid <= 1'b1;
8'b0000001x: code <= 3'b110; valid <= 1'b1;
8'b000001xx: code <= 3'b101; valid <= 1'b1;
8'b00001xxx: code <= 3'b100; valid <= 1'b1;
8'b0001xxxx: code <= 3'b011; valid <= 1'b1;
8'b001xxxxx: code <= 3'b010; valid <= 1'b1;
8'b01xxxxxx: code <= 3'b001; valid <= 1'b1;
8'b1xxxxxxx: code <= 3'b000; valid <= 1'b1;
default: begin
code <= 3'b0;
valid <= 1'b0;
end
endcase
end
end
endmodule
2 Marks
4C Write the Verilog code for a 3 input AND gate as a user defined primitive (UDP)
primitive udp_and3 ( output z1, input x1, x2, x3 ); 1Mark
table
// x1 x2 x3 : z1
0 0 0 : 0
0 0 1 : 0
0 1 0 : 0
0 1 1 :0
1 0 0 :0
1 0 1 : 0
1 1 0 :0
1 1 1 :1
endtable
endprimitive
2Marks
5A Implement the following circuit using ACT-2 Sequential module
Transparent Low Latch
C2=0, C1=1 and Clr=1
4 Marks (Consider Alternate Circuit)
5B Implement the following combinational circuit using Xilinx FPGA. Determine the number of CLB's
and LUT's required. Show the contents in the SRAM cell
F0=i0i1+i2
F1=i2+i3
i0 i1 i2 F0
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
i2 i3 F1
0 0 0
0 1 1
1 0 1
1 1 1
Total No of CLB=1, No. of LUT=2, Mode-FG, The content of LUT 1 is the F0 and
F1 column of Truth Table, Inputs to top LUT are i0,i1,i2 and fourth input is don’t care,
Inputs to bottom LUT are i2, i3 and remaining 2 inputs are don’t care
1.5 Marks for truth table, 0.5 Marks for No of CLB and LUT, 2 Marks for
circuit
5C Explain ASIC Design
3 Marks (Consider alternate answers)
