CS 2003

Computer Organization and Architecture

Prepared by
Dr. Manju Mathew
1
Lecture Objectives
• Summarize the topics covered so far
• Introduce Instruction Set Architecture (ISA)

2
Computer system analysis
• General purpose computers are modified versions of Von Neumann machine
• All computers follow almost similar basic structure
– CPU (ALU, Registers and CU)
– Memory System ( primary and secondary)
– I/O units
– Bus for interconnection

• All computers perform four important functions

– Data Processing
– Data transfer
– Data storage
– Proper Control

3
Organization and Architecture

• Computer Architecture tell us WHAT the computer does

• Organization tells us HOW the computer does

• Architecture design is done prior to organizational design

• Architecture involves the design of instructions and datatypes and is considered as high level
design

• Organization involves design and selection of hardware components and is the low level
design

• Computer Architecture serves as the mediator between software and hardware

4
 Computer Registers
• Special Purpose Registers
– Located in the processor for specific purpose
– Takes part in the execution of an instruction
– Program Counter, Instruction Register, Address Register, Data Register
– Accumulator or processor register
– No direct access for the user

• General Purpose Registers

– For temporary storage of input data or result
– Number of registers is a trade off between processor speed and hardware complexity
– B, C, D, E , H, L

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Microoperations
• Data transfer operations
– Register transfer (MOV B,A)
– Memory transfer ( MOV M,A)

• Arithmetic operations
– Addition, subtraction, Incrementer, Decrementer ( ADD, SUB, INR, DCR)

• Logic operations
– NOT, OR, Ex-OR, AND (CMA, ORA, XRA , ANI)

• Shift operations
– Arithmetic shift
– Logical shift
– Circular shift

• Register Transfer Language (RTL) is used to represent microoperations 6

Computer Arithmetic
• Integer arithmetic
– Integer data representation
– Addition and subtraction of integers
– Integer multiplication
– Integer division

• Floating point arithmetic

– Fractional data representation
– IEEE 754 floating point format
– Floating point addition/subtraction
– Multiplication and division

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Program and Instruction
• Program
– A set of related statements written in any high level language to
accomplish a specific task ( simple or complex)

• Program statement
– Single line of code within a program
– corresponds to a few number of microoperations
– Computer identifies the microoperations by compiling the program

• Instruction
– Single line of assembly language code indicating one or two micro operation
– The binary equivalent of the assembly code is termed as machine instruction
(object code)
– Computer executes machine instructions in the specified order 8
C Program Example
#include<stdio.h> To include the i/o library

int main() To set the starting of execution –main function call

{ Block of statements within main function begin

int a,b,c; Allocating 4 bytes of memory for variables a, b and c

a=45; storing the value 45 to memory location a

b=25; storing the value 25 to memory location b

c=a+b; Add the contents of a and b and store the sum in

memory location c
printf("Sum %d",c);
Display the content of c to output screen
return 0;
End of main function
}
End of program
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Assembly codes
_main:
pushl %ebp
movl %esp, %ebp
andl $-16, %esp
subl $32, %esp
call ___main  Calling the subroutine ‘main’
movl $45, 28(%esp)  storing the data 45 to a memory location with address 28 + [esp]
movl $25, 24(%esp)  storing the data 25 to a memory location with address 24 +[esp]( memory write)
movl 24(%esp), %eax  moving the content of memory location to accumulator register (memory read)
movl 28(%esp), %edx  moving the content of memory location to data (D) register (memory read)
addl %edx, %eax  add the contents of accumulator and D register and store the sum in accumulator
movl %eax, 20(%esp)  store the sum to a memory location with address ‘20’ +[esp]
call _printf
movl $0, %eax
leave
ret
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 Instruction
• Binary equivalent of the assembly code

• It contains the information required by the processor for execution

• Format depends on the architecture design

• Most crucial part in ISA is the formulation of machine instructions

• Two main elements for most of the machine instructions

– Operation code (opcode) , mandatory for all instructions
– Operand ( can be address of memory or can be data itself)

Operation code (opcode) Operand

Instruction ( binary word)

Note: there can be instructions without operand part but only opcode
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Opcode

 Specifies the operation to be performed

 Essential part of a machine instruction

 Number of bits in the opcode depends on ISA

 Decoding of these bits are done by the control unit of the processor

 Number of bits in the opcode plays a key role in the formulation of maximum possible
instructions in the instruction set of a specific processor

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Operands
• Specifies the data or address required for the operation

• Data can be numerical or non - numerical

Numerical – integer numbers or real numbers

Non numerical – character ( text ) or logical ( true or false)

• If the data is given explicitly, it is termed as immediate operand

• Address reference given as operand can be

Source reference 13
Classification of Instructions
I. Data Transfer Instructions

II. Arithmetic Instructions

III. Logical and shift Instructions

IV. Program sequencing Instructions ( Transfer of control)

V. Input/ Output Instructions

VI. Conversion Instructions

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Instruction Cycle
– Time taken to complete the execution of one machine instruction

• Instruction Cycle involves

– Instruction fetch
Reading the instruction from program memory and loading it into instruction
register
-- Instruction Decode
The content of IR is passed to the control unit and is decoded to generate
necessary control signals

– Instruction Execution
• Register read/ memory read
• Arithmetic/Logic/Shift operations
• Register write/memory write
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NOTE: Instruction execution process depends on the type of the instruction

Instruction Fetch Memory location having address 0800

Instruction
Memory
00111110
01010001

Decoder
PC
IR

MAR

Data bus carries instruction (00111110)

Address Bus carries 0800 16

 Instruction Decode
• Decoding the content of IR (For a 32 bit MIPS processor )
b3 b0
1

Opcode to Register Register Immediate value ( 16 bit)

Control Unit Select1 Select 2

Decoding of instruction will be taken place according to the instruction format

Opcode bits are transferred to the control unit for generating necessary control signals

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Instruction Set Architecture (ISA)
• Computer Architecture is often termed as ISA

– The design procedure that encompasses all steps towards the

formation and finalization of machine instruction set of a computer is

termed ISA design

• Play key role in the processor design

– Instruction format
– Number of instructions
– Addressing modes
– Datatypes
– Timing and control
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• Different manufacturers design processors with different ISA
Classification of ISA
• Broadly into two categories
– CISC ( Complex Instruction Set Computer) Architecture
– RISC ( Reduced Instruction Set Computer) Architecture

• Examples of CISC
– Motorola 68000
– IBM 370
– Intel processors

• Examples of RISC
– MIPS - used in automotives
– ARM – used in mobile phones

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CISC instruction example
• Consider the C program statement

c=a+b;

Its assembly code equivalent in CISC could be like

mov c,b  move the content of memory location b to memory location c

add c,a  add the contents of c and a and store the sum in c

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CISC Features
1. Instruction length is not limited to one word of the memory

2. Operands of arithmetic/logic instructions can be in registers or in memory

3. Instruction set is large

4. Instruction length is variable and decoding is complex

5. Control unit is microprogrammed – code expansion is feasible

6. Processing speed is low

7. Memory access can be done as part of arithmetic/ logic instructions

8. Pipelining/parallel processing is difficult

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RISC approach
• Architecture evolved in late 1970s
• Key points in RISC approach are
– Limit the length of each machine instruction to one word in memory
– To limit the length of arithmetic and logic instructions, both operands are either
stored in registers or one operand would be provided as part of the instruction
– Load/Store architecture for memory access

Reason behind RISC

- Reuse of instructions instead of writing separate instructions for
different tasks

- Higher performance in terms of speed 22

 RISC
• Consider the C program statement s

c=a+b;

Its machine instruction equivalent in RISC could be like

Load R1, A
Load R2, B
add R3, R1,R2
Store R3, C

In RISC processors, machine instructions does not resemble the high level instruction

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RISC Features
1. Instruction length is limited to one word of the memory

2. Operands of arithmetic/logic instructions should be placed in registers or should

be given along with instruction ( immediate operand)

3. Instruction set is small

4. Instruction length is fixed and decoding is easy

5. Parallel processing/pipelining of instructions is easy

6. Control unit is hardwired  code expansion is not feasible

7. High speed of processing as instructions are simple

8. Memory access is done with the help of load/store instructions

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Load /Store
• Load  This keyword implies transferring data from main memory to any
specific register within CPU
• In 8085, the assembly code is of the form LDA address1
( Load the accumulator with the content of a memory location specified by
address1)
• Store This keyword implies transferring data to main memory from any
specific register within CPU
• In 8085, the assembly code is of the form STA address2
To execute these type of instructions, each memory location must have
unique physical address ( possible with semiconductor memory technology)

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 Registers
Core
Memory hierarchy
• Based on location, size, speed and cost L1 Core
Cache

• Registers are the smallest in size and closest to ALU

L2 Cache
• L1 and L2 cache within the core

• L1 has both instruction cache and data cache L3 cache Processor

• L2 is similar to L1 but has lower speed but higher size

• L3 cache is arranged each core within CPU Main Memory

• Cache memory is made up of Static RAM technology

• Main memory is very large compared to cache

Auxiliary (Secondary) Memory
• Auxiliary memory denotes magnetic storage 26
Main memory system
• Random Access Memory (RAM)
• Semiconductor memory (volatile)
• Capacity up to 64GB
• Converted into virtual memory
• Technology used is dynamic RAM

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Main Memory locations and addresses

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DRAM Memory Technology
• Very simple and cheap but slow
• One capacitor and one transistor for each cell
• To write data, word line =1 , T gets on
• For writing 1, Bit line =1 ( Vss =3.3V)
• Capacitor charges through T towards 3.3V
• Capacitor keeps the charge even after the word line is turned off
• Presence of charge = 1
• Absence of charge = 0

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 Bit, byte and word
 Bit – 0 or 1
 Byte – group of 8 bits
 Word – normally group of 4 bytes ( 2 bytes – halfword , 8 bytes - double
word)
 Memory can be accessed byte by byte
 Successive addresses refer to successive byte locations in memory
 Terminology used is byte addressable memory
 32 bit computer have 4 byte locations in each word row Byte
b3 b0
1

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Byte Addressing
• Two ways of addressing
– Little endian
– Big endian

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