Karan Umredkar
2x1 mux using AND gate
Truth Table :
A B Y
1 1 1
1 0 0
0 1 0
0 0 0
Design Code :
module 2x1_AND(
input wire a,
input wire b,
output reg y
);
// 2:1 Mux implementation
always @(a or b )
if (a)
y <= b; // AND operation when select is 1
else
y <= 0; // Output 0 when select is 0
endmodule
Schematic Design :
Karan Umredkar
2x1 mux using OR gate
Truth Table :
A B Y
1 1 1
1 0 1
0 1 1
0 0 0
Design Code :
module 2x1_OR (
input wire a,
input wire b,
output reg y
);
// 2:1 Mux implementation
always @(a or b )
if (a)
y <= 1; // AND operation when select is 1
else
y <= b; // Output 0 when select is 0
endmodule
Schematic Design :
Karan Umredkar
2x1 mux using NOR gate
Truth Table :
A B Y
1 1 0
1 0 0
0 1 0
0 0 1
Design Code :
module 2x1_NOR (
input wire a,
input wire b,
output reg y
);
// 2:1 Mux implementation
always @(a or b )
if (a)
y <= 0; // AND operation when select is 1
else
y <= ~b; // Output 0 when select is 0
endmodule
Schematic Design :
Karan Umredkar
2x1 mux using NAND gate
Truth Table :
A B Y
1 1 0
1 0 1
0 1 1
0 0 1
Design Code :
module 2x1_NAND (
input wire a,
input wire b,
output reg y
);
// 2:1 Mux implementation
always @(a or b )
if (a)
y <= ~b; // AND operation when select is 1
else
y <= 1; // Output 0 when select is 0
endmodule
Schematic Design :
Karan Umredkar
2x1 mux using EX-OR gate
Truth Table :
A B Y
1 1 0
1 0 1
0 1 1
0 0 0
Design Code :
module 2x1_EX_OR (
input wire a,
input wire b,
output reg y
);
// 2:1 Mux implementation
always @(a or b )
if (a)
y <= ~b; // AND operation when select is 1
else
y <= b; // Output 0 when select is 0
endmodule
Schematic Design :
Karan Umredkar
2x1 mux using EX-NOR gate
Truth Table :
A B Y
1 1 1
1 0 0
0 1 0
0 0 1
Design Code :
module 2x1_EX_NOR (
input wire a,
input wire b,
output reg y
);
// 2:1 Mux implementation
always @(a or b )
if (a)
y <= b; // AND operation when select is 1
else
y <= ~b; // Output 0 when select is 0
endmodule
Schematic Design :
Karan Umredkar
2x1 mux using NOT gate
Truth Table :
A Y
1 0
0 1
Design Code :
module 2x1_NOT (
input wire a,
output reg y
);
// 2:1 Mux implementation
always @(a)
if (a)
y <= 0; // AND operation when select is 1
else
y <= 1; // Output 0 when select is 0
endmodule
Schematic Design :
