Sri Lanka Institute of Information Technology
B.Sc. Eng. (Hons) Degree
End of Semester Examination
Year 3, Semester II (2022)
EC3102 – Advanced Digital Design
Duration: 2 hours + 10 minutes (reading time)
Instructions to Candidates:
This paper has 4 questions on 6 pages (including the cover page). Answer
ALL questions.
This paper accounts for 60% of the module.
Questions DO NOT carry equal marks.
Faculty approved non-programmable calculators are allowed.
You are allowed to carry a single A4 sheet with equations and other relevant
information into the examination hall. You may write on both sides of the
paper. Your EN number should be clearly written on the top right-hand
corner of this sheet. The sheet must be attached to the answer script.
Page 1 of 6
Question 01 [32 marks]
A fluid storage tank is given in Figure 1. The level of liquid needs to be maintained at a specific
level using the inlet and outlet valves. Also, the temperature of the liquid must be kept within
a certain range. An alarm switches ON if any of the level or temperature sensors fail.
Inlet valve
VINLET
LH
High-level sensor
LL
A
Alarm Control Logic
and Interface
Outlet
Low- valve
Heating Temperature
level Sensors
VOUTLET TC H sensor element
TH
Figure 1
Basic system operation and requirements:
• The outputs of the system control the fluid input, fluid output and fluid temperature.
• The control logic operates an inlet valve that allows fluid to flow into the tank until a
high-level sensor is activated by being immersed in fluid. When the high-level sensor
is immersed (activated), the control logic closes the inlet valve. The output of each
sensor is HIGH when it is immersed in the fluid and is LOW when not immersed. When
the high-level sensor output is LOW the control logic produces a HIGH and the inlet
valve opens. When the high-level sensor output is HIGH, the control logic produces a
LOW and the inlet valve closes.
• Temperature of the fluid must be maintained within a specified temperature range. It
must be in this range before the outlet valve opens. Two temperature sensors are
available to determine the range. One temperature sensor produces a HIGH when the
fluid is too hot, and an alarm is activated. The other sensor produces a HIGH when the
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fluid is too cold and heating element turns ON. Otherwise, the heating element remains
turned OFF.
• The control logic opens the outlet valve when the low-level sensor is immersed
(produces a HIGH output) and the fluid is at a proper temperature (both sensor outputs
are LOW). This valve is kept open as long as these two conditions are satisfied.
• When the fluid level drops below the low-level sensor (producing a LOW) or either of
the temperature sensor outputs is LOW, the control logic closes the outlet valve.
• Failures: if the control system detects the failure in any of the sensors, or a too-hot
condition, an alarm is activated. A level-sensor failure is indicated when the high-level
sensor is active, and the low-level sensor is not active. A temperature sensor failure is
indicated when both are active at the same time.
You are required to design the control logic of this system.
(a) Based on the above description, complete the tables given on page 4. Detach this sheet
from the question paper and attach to your answer script.
(i) Table 1.1 (inputs to the control logic) (2 marks)
(ii) Table 1.2 (outputs from the control logic) (2 marks)
(iii)Table 1.3 (truth table for the tank control logic) (8 marks)
(b) Obtain the simplified Boolean expressions for the inlet and outlet valve logics using a
suitable method. (4 marks)
(c) Design the two circuits using logic gates. (5 marks)
(d) Write the VHDL codes for the two circuits using behavioral model. (11 marks)
Page 3 of 6
ATTACH THIS PAGE TO YOUR ANSWERSCRIPT Student ID: EN………………….
Table 1.1 – Inputs to the control logic
Variable Description Active Level (Fill this column) Comments
LH High-level sensor Sensor is immersed
LL Low-level sensor Sensor is immersed
TH High-temperature sensor Temperature too
hot
TC Low-temperature sensor Temperature too
cold
Table 1.2 – Outputs from control logic
Variable Description Active Level (Fill this column) Comments
VINLET Inlet valve Valve open
VOUTLET Outlet valve Valve open
H Heating element Heat on
A Alarm Sensor failure or
too hot condition
Table 1.3 – truth table for the tank control logic
Inputs Outputs (Fill empty cells) Comments
LH LL TH TC VINLET VOUTLET H A
0 0 0 0 Fill/heat off
0 0 0 1 Fille/heat on
0 0 1 0 Fill/heat off/alarm
0 0 1 1 0 0 0 1 Temp sensor fault/alarm
0 1 0 0 1 1 0 0 Fill and drain/heat off
0 1 0 1 Fill/heat on
0 1 1 0 Fill/heat off/alarm
0 1 1 1 0 0 0 1 Temperature sensor fault/alarm
1 0 0 0 0 0 0 1 Level-sensor fault/alarm
1 0 0 1 0 0 0 1 Level-sensor fault/alarm
1 0 1 0 0 0 0 1 Level-sensor fault/alarm
1 0 1 1 0 0 0 1 Multiple sensor fault/alarm
1 1 0 0 Drain/ heat off
1 1 0 1 Heat on
1 1 1 0 Heat off
1 1 1 1 0 0 0 1 Temperature senor fault/alarm
Page 4 of 6
Question 02 [20 marks]
The following state diagram shows an irregular binary sequence pattern.
001
(S1)
111 010
(S7) (S2)
101
(S5)
Figure 2
a) Design a counter using J-K flipflops. In your answer the following details must be
included.
(i) Next-state table for the state diagram (2 marks)
(ii) Simplification steps (3 marks)
(iii)Diagram of the design using J-K flipflops (5 marks)
(iv) VHDL code using an appropriate programming model. State the reason for your
choice of model. (8 marks)
b) If the circuit gets into an invalid state, will it always return to a valid state? Explain.
(2 marks)
Question 03 [27 marks]
(a) Design a signed-magnitude adder circuit VHDL using behavioural model. (12 marks)
(b) Design a testing circuit using VHDL to verify and validate the performance of your circuit.
Explain how this testing circuit validates the performance of the circuit in (a). (15 marks)
Page 5 of 6
Question 04 [21 marks]
Consider the digital circuit in Figure 3 and the relevant timing characteristics for the
components given in Table 3. Calculate the following for the overall circuit.
a) Propagation delay, Clock to Output (minimum)
b) Propagation delay, Clock to Output (maximum)
c) Propagation delay, Input to Output (minimum)
d) Propagation delay, Input to Output (maximum)
e) Setup Time (Data input before clock)
f) Hold Time (Data input after clock)
g) Maximum Clock rate (or its reciprocal, minimum clock period)
(3 marks x 7 = 21 marks)
Figure 3
Table 3 - Gate delay characteristics
Device Minimum Maximum Setup Hold
Propagation Delay Propagation Delay Time Time
D Flipflop 2 ns 6 ns 4 ns 2 ns
AND gate 2 ns 4 ns - -
OR gate 2 ns 3 ns - -
2-input NOR gate 2 ns 3 ns - -
3-input NOR gate 1 ns 2 ns - -
End of Question Paper
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