Student Forum 2021 - Sustainable Energy

A Study on MOSFET Gate Driver Circuit

The-Tiep Pham1,*, Dong-Thanh Vu1, Van-Qui Nguyen1, Viet-Quan Pham1, Van-Sy Vu1,
Tat-Thang Le2 and Duy-Dinh Nguyen1
1
Hanoi University of Science and Technology, Viet Nam
2
Seoul National University of Science and Technology, South Korea
*
Corresponding author E-mail: tiep.pt181784@[Link]
ABSTRACT VISHAY, etc. [1-3]. In [3], the time-related parameters
Gate driver circuit of the metal-oxide-semiconductor field- including turn-on delay, current rise time, voltage fall
effect transistors (MOSFETs) are important. If the gate driver
time, turn-off delay, voltage rise time, current fall time,
circuit is designed carefully and properly, the switching time can
be controlled which leads to an optimized switching loss and a were provided, however, effects of parasitic elements
reduction of Electromagnetic Interference, etc. Gate resistors are were ignored. In [4], although effects of the parasitic
the key parameters that decide the performance of the MOSFET, inductance were considered, the gate voltage was zero-
hence they need to be optimized. In this paper, the MOSFET gate biased. For the newly emerged wide band gap devices like
driver circuit is presented. The gate resistors are calculated with
SiC MOSFETs which are usually driven with a negative
some simple mathematic equations on a special region called the
"plateau region". To determine the switching loss, time biased gate drive voltage, the aforementioned calculation
parameters including turn-on delay, turn-off delay, current rise is inappropriate.
time, current fall time, voltage rise time, and voltage fall time,
are estimated in consideration of parasitic elements such as stray In this paper, a generic estimation model of dynamic
inductance, parasitic inductance at the drain, and source. parameters of MOSFET is presented considering the
LTSpice ⅩⅦ simulations are then conducted to verify the effect of parasitic elements. The paper is structured as
estimation method of the dynamic performance of the MOSFET follows: basic of MOSFET characteristic is presented in
in accordance with the gate driver design. Discussions and
section Ⅱ, design MOSFET gate driver is described in
conclusions on the effects of the gate drive circuit design on the
transient voltage and current are provided in comparison section Ⅲ, then these parameter's estimation can be found
between the calculations and simulation. As confirmed by in section Ⅳ, the simulation is shown in section Ⅴ, and
simulation, estimation results are less than 13% error compared finally, some conclusions are given in section Ⅵ.
to simulation values except for voltage rise time and voltage fall
time. The reason is that the gate-to-drain parasitic capacitor Ⅱ. Basic MOSFET characteristic
which is highly nonlinear is linearized in the calculation for Firstly, it is necessary to look at a MOSFET in
simplification. However, these calculations can be used for the isolation view by models itself and some important
preliminary design of the drive circuit that helps reduce adjusting parameters. But the model that describe all the
time in the experiment.
functionalities of the MOSFET from an application point
Keywords: gate driver circuit, time switching parameters, of view would be very complicated. In this paper, the
plateau region, Double Pulse Test, parasitic ringing, EMI. switching model of MOSFET is focused in detail, it can
Ⅰ. Introduction be modeled as figure 1 with the appearance of the parasitic
MOSFETs can be seen as the devices that change the components that influences the switching performance
world. They can be found in many power electronics including a gate-to-drain capacitance (𝐶𝑔𝑑 ), gate-to-
converters ranging from low power applications such as source capacitance (𝐶𝑔𝑠 ), drain-to-source capacitance
the microchip to high power applications such as (𝐶𝑑𝑠 ), the parasitic gate resistance (𝑅𝐺,𝑖𝑛𝑡 ) and the package
renewable energy, electric vehicle supply equipment, etc. inductance at the drain (𝐿𝑑 ) and source (𝐿𝑠 ) terminals.
In general, in order to turn on or off a MOSFET, the gate- When the state of MOSFET is changed, these capacitors
source voltage is driven above or below a certain threshold are charged or discharged by the current flow to the gate
voltage associated with the MOSFET. It becomes more through the gate resistors. While value of 𝐶𝑔𝑠 does not
challenging in real world applications requiring high
change much and can be seen as constant value in the
voltage and high switching frequency due to the effects of
working range. But values of 𝐶𝑔𝑑 and 𝐶𝑑𝑠 are highly
parasitic components. Therefore, it is necessary to do a
nonlinear with the drain-source voltage [5] and they can
thorough investigation on the transition process of the
be estimated by (3).
MOSFETs aiming for properly design the gate drive
circuit and for estimating their dynamic performance.
𝑉𝐷𝑆,𝑠𝑝𝑒𝑐
Detail analysis on the transition process of MOSFETs can 𝐶𝑅𝑆𝑆,𝑎𝑣𝑒 = 2𝐶𝑟𝑠𝑠,𝑠𝑝𝑒𝑐 √ (1)
be found in application notes from TI, TOSHIBA, and 𝑉𝐷𝑆,𝑂𝐹𝐹

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𝑉𝐷𝑆,𝑠𝑝𝑒𝑐 They can be found in the datasheet and will be analyzed

𝐶𝑂𝑆𝑆,𝑎𝑣𝑒 = 2𝐶𝑜𝑠𝑠,𝑠𝑝𝑒𝑐 √ (2) in more detail in section Ⅴ.
𝑉𝐷𝑆,𝑂𝐹𝐹
𝐶𝑔𝑑 = 𝐶𝑅𝑆𝑆,𝑎𝑣𝑒 , 𝐶𝑔𝑠 = 𝐶𝑖𝑠𝑠 − 𝐶𝑟𝑠𝑠,𝑠𝑝𝑒𝑐 Secondly, the gate charge mechanism is analyzed step
𝐶𝑑𝑠 = 𝐶𝑂𝑆𝑆,𝑎𝑣𝑒 − 𝐶𝑅𝑆𝑆,𝑎𝑣𝑒 (3) by step to show how the MOSFET can be turned on. It is
fundamental to calculate the dynamic time parameters. To
Where 𝐶𝑖𝑠𝑠 , 𝐶𝑟𝑠𝑠,𝑠𝑝𝑒𝑐 , 𝐶𝑜𝑠𝑠,𝑠𝑝𝑒𝑐 are available in datasheet better understand the fundamental procedures, the
with the drain-source voltage is 𝑉𝐷𝑆,𝑠𝑝𝑒𝑐 and 𝑉𝐷𝑆,𝑂𝐹𝐹 is the parasitic inductances of the circuit are ignored
drain-source voltage when turning-off in real application. temporarily. And they are discussed in more detail in
section Ⅴ. In this analysis, the simplest model of clamped
inductive switching (fig. 2) is used because most of the
MOSFET used in switch-mode power supplies work in
this operating mode. Based on this model, turn-on and off
procedures are presented in figure 3. The turn-on process
is explained, and the reverse procedures can be applied for
the turn-off process.

Figure 1. The switching model of the MOSFET.

Moreover, there are some important parameters that

directly affect to switching process of the MOSFET such
as 𝑅𝐺,𝑖𝑛𝑡 , threshold voltage (𝑉𝑡ℎ ), and transfer
conductance (𝑔𝑓𝑠 ). With 𝑅𝐺,𝑖𝑛𝑡 , it is located between Figure 2. The clamped inductive switching model
parasitic capacitors and gate driver circuit, so when
designing the gate resistors, it must be considered to
obtain more accurately desired value. 𝑉𝑡ℎ is a critical
characteristic, it can be found in the datasheet which is
defined at 250 C and very low current, typically at 250 𝜇𝐴.
One thing that is rarely mentioned fact about 𝑉𝑡ℎ is its
about -7 mV/0C temperature coefficient [1]. Finally, 𝑔𝑓𝑠
is also important. The transconductance of the MOSFET
is its small-signal gain in the linear region of its region.
Every time the MOSFET is turned on or off, it must go
through its linear operating mode where the current is
determined by the gate-source voltage. It is useful when
calculating the current fall and rise time (it will be shown
in section Ⅴ) and 𝑔𝑓𝑠 is expressed by (4), where 𝐼𝑑 is the
Figure 3. MOSFET turn-on time intervals
drain-to-source current. 𝑉𝑔𝑠 is the gate-source voltage.
𝑑𝐼𝑑 At the first interval (0 < 𝑡 < 𝑡1 ), the input capacitance
𝑔𝑓𝑠 =
𝑑𝑉𝑔𝑠 (4) (𝐶𝑔𝑠 , 𝐶𝑔𝑑 ) is charged up through the gate resistance
Based on (4), the approximation of the Miller Plateau (including the parasitic resistor, external gate resistor, and
voltage (𝑉𝑝𝑙 ) can be calculated by (5) with 𝐼𝐷 is the drain- driver IC resistor). Hence, the gate-source voltage rises
to-source current at the steady state. from 0 to 𝑉𝑡ℎ . At the output, the drain-source voltage (𝑉𝑑𝑠 )
𝐼𝐷 and the drain-to-source current (𝐼𝑑𝑠 ) remain unchanged.
𝑉𝑝𝑙 = 𝑉𝑡ℎ +
𝑔𝑓𝑠 (5) This interval is called the turn-on delay interval. Once the
Other important parameters like 𝐿𝑑 and 𝐿𝑠 directly affect gate-source voltage is charged to 𝑉𝑡ℎ , the second interval
to the current rise/fall time and spike voltage at the output. (𝑡1 < 𝑡 < 𝑡2 ) occurs to rise 𝑉𝑔𝑠 from 𝑉𝑡ℎ to the Miller

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Plateau voltage (𝑉𝑝𝑙 ) in the same way as the first interval. (7)
𝐸𝑜𝑛 = ∫ 𝑉𝑔𝑠 𝐼𝑔 𝑑𝑡 = ∫ 𝑉𝑔𝑠 𝑑𝑄
This is the linear operation of the MOSFET because the
output current and the gate voltage are proportional with 𝐸𝑅,𝑜𝑛 = 𝐸 − 𝐸𝑜𝑛 (8)
the specific transconductance (𝑔𝑓𝑠 ). At the output, the 𝐸𝑅,𝑜𝑓𝑓 = 𝐸𝑜𝑛 (9)
current rapidly changes and reaches the load current while
𝐸𝑙𝑜𝑠𝑠 = 𝐸𝑅,𝑜𝑛 + 𝐸𝑅,𝑜𝑓𝑓 = 𝐸 (10)
𝑉𝑑𝑠 is almost unchanged at the previous level. Then, the
special region happens in the third interval called the 𝑃𝐺,𝑙𝑜𝑠𝑠 = 𝐸 × 𝑓𝑠𝑤 = ∆𝑉𝐺 × 𝑄𝐺 × 𝑓𝑠𝑤 (11)
Miller Plateau region. When the gate-source voltage is ∆𝑉𝐺 is the swing of supply voltage, 𝐼𝑔 is the gate current,
already charged to the voltage level (𝑉𝑝𝑙 ) which can
𝑄𝐺 is the total gate charge need to supply, 𝑉𝑔𝑠 is the gate-
handle the entire load current and force the body diode off
source voltage, 𝐸 is the total energy supplied by power
that allows the drain-source voltage to drop while the gate-
source, 𝐸𝑜𝑛 is the stored energy in the capacitors, 𝐸𝑅,𝑜𝑛
source voltage (𝑉𝑔𝑠 ) is remained quite flat at 𝑉𝑝𝑙 and the
and 𝐸𝑅,𝑜𝑓𝑓 are the energy loss of the gate resistors when
drain-to-source current remains at the load current. In this
turning on and off, 𝑓𝑠𝑤 is the switching frequency.
interval, most of the gate current discharges for 𝐶𝑔𝑑 to
facilitate the rapid voltage change of the drain-source Ⅲ. Design MOSFET gate driver
terminals. Finally, the gate-source voltage is continuously
charged up to the power supply voltage to finish the As shown in the previous section, several steps
happen to be able to turn on or off the MOSFET. So, it is
process. At the output side, the current remains at the load
hard to drive the MOSFET with the exact turn-on and off
current, and the drain-source voltage is determined by the
time. Moreover, the gate current is controlled by the gate
on-resistance (𝑅𝐷𝑆,𝑂𝑁 ) of MOSFET. resistors (turn-on and off resistors), therefore,
The turn-on or off process results in some unexpected loss preliminarily designing the gate resistors is important
because the parasitic capacitors need the energy to charge before choosing the driver IC. In this part, an easy way for
calculating the gate resistances is presented.
up. The energy loss can be intuitively observed in figure
4. Total energy supplied by the power source is calculated In figure 5, the simplified gate driver circuit is shown,
by (6) and shown as rectangular area. The store turning- 𝑅𝐺,𝑂𝑁 and 𝑅𝐺,𝑂𝐹𝐹 are external resistors using when
on energy of input capacitors is determined by (7) and turning-on and off, respectively.
emphasized as gray area. The rest of energy is absorbed
by gate resistors and determined by (8). When turning off,
all stored energy in the input capacitors is discharged
through the gate resistors shown by (9). So total energy
and power loss of the gate driver circuit can be calculated
by (10) and (11).

Figure 5. The simplify MOSFET gate driver circuit.

At the gate voltage curve showing in figure 3, there is a

Miller Plateau region in which the gate-source voltage is
quite flat and close to its average value. So, it can be used
to preliminarily calculate the resistors value.
Firstly, choose the gate voltage rise and fall time
depending on the datasheet and application. Then, the
average turn-on and off currents can be determined by
Figure 4. MOSFET gate loss
(11) and (12).
𝐸 = ∫ ∆𝑉𝐺 × 𝐼𝑔 𝑑𝑡 𝑄𝐺 (11)
𝐼𝐺,𝑂𝑁 =
(6) 𝑡𝑟
= ∆𝑉𝐺 × ∫ 𝐼𝑔 𝑑𝑡 = ∆𝑉𝐺 × 𝑄𝐺 𝑄𝐺 (12)
𝐼𝐺,𝑂𝐹𝐹 =
𝑡𝑓

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Secondly, choose IC driver base on the following 𝑔𝑓𝑠 𝐿𝑠𝑜𝑢𝑟𝑐𝑒

considerations: = 𝑅𝐺 𝐶𝑖𝑠𝑠 @ 𝑉𝐷𝑆,𝑂𝐹𝐹 𝑙𝑛 [(1 + )
𝑅𝐺 𝐶𝑖𝑠𝑠 @ 𝑉𝐷𝑆,𝑂𝐹𝐹
1. The capability of the IC driver (𝐼𝑠𝑖𝑛𝑘 > 𝐼𝐺,𝑂𝑁 , 𝑉𝐺𝑆,𝑂𝑁 − 𝑉𝑡ℎ (16)
𝐼𝑠𝑜𝑢𝑟𝑐𝑒 > 𝐼𝐺,𝑂𝐹𝐹 ) × ]
𝑉𝐺𝑆,𝑂𝑁 − 𝑉𝑝𝑙
2. Output power of the gate driver is bigger than the
gate power dissipated (𝑃𝐷𝑅,𝑜𝑢𝑡 > ∆𝑉𝐺 × 𝑄𝐺 × 𝑓𝑠𝑤 ) 𝑡𝑑,𝑂𝐹𝐹 = 𝑡4 = 𝑅𝐺 × 𝐶𝑖𝑠𝑠 @ 𝑉𝐷𝑆,𝑂𝑁
3. Propagation delay time is much small than the 𝑉𝐺𝑆,𝑂𝐹𝐹 − 𝑉𝐺𝑆,𝑂𝑁 (17)
× ln ( )
switching time. 𝑉𝐺𝑆,𝑂𝐹𝐹 − 𝑉𝑝𝑙
4. Consider the output sink & source resistor and
𝑉𝐷𝑆 (18)
some feature such as miller clamp output, etc. 𝑡𝑟𝑣 = 𝑡5 = 𝑅𝐺 𝐶𝑔𝑑
𝑉𝑝𝑙 − 𝑉𝐺𝑆,𝑂𝐹𝐹
Thirdly, the gate-source voltage is fixed at 𝑉𝑝𝑙 , the
turn-on and off resistors can be found by (13), (14). 𝑡𝑓𝑖 = 𝑡6
𝑔𝑓𝑠 𝐿𝑠𝑜𝑢𝑟𝑐𝑒
𝑉𝐺,𝑂𝑁 − 𝑉𝑝𝑙 − 𝑉𝑆𝐷,𝑂𝑁 (13) = 𝑅𝐺 𝐶𝑖𝑠𝑠 @ 𝑉𝐷𝑆,𝑂𝐹𝐹 × ln [(1 + ) (19)
𝑅𝐺,𝑂𝑁 = − 𝑅𝐺,𝑖𝑛𝑡 − 𝑅𝐷𝑅,𝑠𝑖𝑛𝑘 𝑅𝐺 𝐶𝑖𝑠𝑠 @ 𝑉𝐷𝑆,𝑂𝐹𝐹
𝐼𝐺,𝑜𝑛 𝑉𝐺𝑆,𝑂𝐹𝐹 − 𝑉𝑝𝑙
𝑉𝑝𝑙 − 𝑉𝐺,𝑂𝐹𝐹 − 𝑉𝑆𝐷,𝑂𝐹𝐹 (14) × ]
𝑅𝐺,𝑂𝐹𝐹 = − 𝑅𝐺,𝑖𝑛𝑡 − 𝑅𝐷𝑅,𝑠𝑟𝑐 𝑉𝐺𝑆,𝑂𝐹𝐹 − 𝑉𝑡ℎ
𝐼𝐺,𝑂𝐹𝐹
Where 𝑉𝐺,𝑂𝑁 and 𝑉𝐺,𝑂𝐹𝐹 are the supply voltage at turning
on and off state, 𝑉𝑆𝐷,𝑂𝑁 , and 𝑉𝑆𝐷,𝑂𝐹𝐹 are the diode forward
voltage of diode 𝐷𝑂𝑁 and 𝐷𝑂𝐹𝐹 in Figure 5, 𝑅𝐷𝑅,𝑠𝑖𝑛𝑘 and
𝑅𝐷𝑅,𝑠𝑟𝑐 are the output sink and source resistance of IC
driver.
Finally, some components are added for protecting
functions such as the zenner and pull-down gate resistor,
etc.
Ⅳ. Parameter’s estimation
Switching time parameters including turn-on delay
(𝑡𝑑,𝑂𝑁 ), current rise time (𝑡𝑟𝑖 ), voltage fall time (𝑡𝑓𝑣 ), turn- Figure 6. Turn on the process of the MOSFET

off delay (𝑡𝑑,𝑂𝐹𝐹 ), current fall time (𝑡𝑓𝑖 ), voltage rise time
(𝑡𝑟𝑣 ) are important parameters for calculating the
switching loss of MOSFET, estimated the effect of the
voltage or current spike, and Miller turn-on phenomenal,
etc. So, this part will show the estimated calculations for
them.
The switching model of the MOSFET is shown in
figure 1 with considering the other parasitic elements such
as the package inductance at drain and source terminal and
stray inductance of PCB wire. Turning-on and off
processes are shown by Figures 6 and 7. Based on Figures
6, 7 and the previous analysis about the turn-on and off Figure 7. Turn off process of the MOSFET.
process, the switching time parameters can be From the equations (14 - 19), the switching loss of the
approximately calculated. The results of these estimations MOSFET and the peak of drain-source voltage when
are shown by equation (14 - 19). turning-off can be estimated by equations (20 - 22).
𝑡𝑑,𝑂𝑁 = 𝑡1 = 𝑅𝐺 × 𝐶𝑖𝑠𝑠 @ 𝑉𝐷𝑆,𝑂𝐹𝐹 1 (20)
𝑉𝐺𝑆,𝑂𝑁 − 𝑉𝐺𝑆,𝑂𝐹𝐹 (14) 𝐸𝑠𝑤,𝑂𝑁 = ×𝐼 × 𝑉𝐷𝑆,𝑂𝐹𝐹 × (𝑡𝑟𝑖 + 𝑡𝑓𝑣 )
× 𝑙𝑛 ( ) 2 𝐷𝑆,𝑂𝑁
𝑉𝐺𝑆,𝑂𝑁 − 𝑉𝑡ℎ 1 (21)
𝐸𝑠𝑤,𝑂𝐹𝐹 = × 𝐼𝐷𝑆,𝑂𝑁 × 𝑉𝐷𝑆,𝑂𝐹𝐹 × (𝑡𝑟𝑣 + 𝑡𝑓𝑖 )
2
𝑉𝐷𝑆,𝑂𝐹𝐹 𝑑𝑖 𝑑𝑖 (22)
𝑡𝑓𝑢 = 𝑅𝐺 𝐶𝑔𝑑 𝑉𝐷𝑆,𝑂𝐹𝐹,𝑝𝑒𝑎𝑘 = 𝑉𝐷𝑆,𝑂𝐹𝐹 + 𝑑𝑠 𝐿𝑠𝑡𝑟𝑎𝑦 + 𝐿 𝐿
(15) 𝑑𝑡 𝑑𝑡
𝑉𝐺𝑆,𝑂𝑁 − 𝑉𝑝𝑙
With
𝑡𝑟𝑖 = 𝑡2 𝐸𝑠𝑤,𝑂𝑁 , 𝐸𝑠𝑤,𝑂𝐹𝐹 are the energy loss when turning on and
off.

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𝑉𝐷𝑆,𝑂𝑁 , 𝑉𝐷𝑆,𝑂𝐹𝐹 are the drain-source voltage when the blue, black, and red curves, respectively. The
MOSFET is turned on and off at a steady state, comparations table is shown in table 2. `
𝑉𝐷𝑆,𝑂𝐹𝐹,𝑝𝑒𝑎𝑘 is the peak drain-source voltage during the From the simulation results, it is noted that the
turn-off transient, waveforms have the ringing caused by the parasitic
𝐼𝐷𝑆,𝑂𝑁 is the drain-to-source current when the MOSFET is inductance. These ringing can be reduced by several
conducted at a steady state, solutions such as increasing the gate resistors, adding the
𝑖𝑑𝑠 is the instance current flowing from drain-to-source. snubber circuit, or reducing the switching frequency, etc.
𝐿𝑠𝑡𝑟𝑎𝑦 is stray inductance by PCB wire, The first two solutions are recommended; however, the
power loss is increased due to the addition of the external
𝑖𝐿 , 𝐿 is the load current and load inductance, respectively.
circuit. During turning-off, the drain-source voltage rises
During turning-on, the spike of drain-to-source much slower than what is seen in figure 7. That is because
current may occur because of the reverse recovery current the gate-to-drain capacitance is changed caused by
of the body diode in case of having both high and low side changing the drain-source voltage in this simulation while
MOSFET. Although the reverse recovery current is the gate-to-drain capacitance is considered as almost
dependent on the changing of the drain-to-source current, constant in figure 7. Moreover, thanks to the miller-clamp
it can be simply predicted as (23). feature of IC driver 1ED3122MU12H, the miller turn-on
phenomenal is avoided.
𝐼𝐷𝑆,𝑂𝑁,𝑝𝑒𝑎𝑘 = 𝐼𝐿𝑜𝑎𝑑 + 𝐼𝑟𝑟,𝑝𝑒𝑎𝑘 (23)
With 𝐼𝑑𝑠,𝑜𝑛,𝑝𝑒𝑎𝑘 , 𝐼𝐿𝑜𝑎𝑑 , 𝐼𝑟𝑟,𝑝𝑒𝑎𝑘 are the peak turn-on
current, load current and reverse recovery current of body
diode, respectively.
Ⅴ. Simulation
To verify the estimated calculations in section Ⅳ, the
simulation is conducted by the "Double Pulse Test (DPT)"
circuit in LTSpice ⅩⅦ application. The DPT circuit (fig.
8) can be seen as a test circuit to make sure the switches
satisfied the working condition of the system. The load is
purely inductive, and the top switch is turned off by the
negative voltage. There are two pulses supplied to the Figure 8. Double Pulse Test circuit.
bottom switch, the first pulse is used to raise the load
current to the normal operating point. The second one is
the main pulse test in which the currents and voltages are
measured. This test is conducted during a short time
(about ten microseconds). So, the IC driver is chosen
mainly basing on the sink and source currents. Moreover,
the heatsink is not added because the rising temperature is
insignificant. Three parameters are measured which are
the gate-to-source voltage (𝑉𝑔𝑠 ). drain-to-source voltage
(𝑉𝑑𝑠 ) and drain-to-source current (𝐼𝑑𝑠 ). The switching time
parameters can be determined and compared to the Figure 9. Double pulse test and load current
estimated calculations.
Table 1. The testing parameters
In this simulation, the testing parameters are listed in
the Table 1. Infineon IC driver 1ED3122MU12H is used Parameters Value
to drive the MOSFET. 1ED3122MU12H has the miller Device under test Wolfspeed
clamp feature to able to avoid the self-turn-on C2M0025120D
phenomenal. The rise and fall time of gate-to-source Load current 50 A
voltages are chosen at 150 ns and 100 ns, resulting in the Load inductance 60 𝜇𝐻
value of turn-on and off resistors are approximately 6 Ω DC bus voltage 400 V
and 10 Ω. The other parameters are added for protecting
such as zenner, the pull-down resistor, etc. The pulse test
As shown in Table 2, the theory and simulation are closed
and corresponding load current are shown in figure 9.
with the errors are smaller than 13% except for the voltage
The switching time parameters are estimated by equations raise and fall time. That is because the gate-to- drain
(14 – 19) compared with the simulation measurement capacitance is highly nonlinear; meanwhile the formular
results shown in figure 10-15 with the 𝑉𝑔𝑠 , 𝑉𝑑𝑠 , 𝐼𝑑𝑠 are the in (3) is used as the constant capacitance for easy
calculation purposes.

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Figure 10. Measure the turn-on delay interval. Figure 11. Measure the current rise time. Figure 12. Measure the voltage fall time.

Figure 13. Measure the turn-off delay interval. Figure 14. Measure the current fall time. Figure 15. Measure the voltage rise time.

Ⅵ. Conclusions
During the turn-on process, there is the current spike The fast and simple way to preliminary design the
caused by the reverse recovery current of the body diode elements of the gate driver circuit is shown in this paper.
with the peak of 67 A which is close to the theoretical The equations for estimating the switching time
result of 65.5 A, and the drain-source voltage at the parameters are provided and verifying by simulation, the
transient is dropped because the positive voltage drops on calculation results have error of 13% compared to the
the parasitic inductor with the flow of positive current is simulation results except for the voltage rise and fall time.
chosen from the drain to the source terminal. This means The reason is the gate-to-drain capacitance being highly
the power loss can be reduced but during the turning-off nonlinear, while it is considered as a constant value when
process, the drain-source voltage spike resulted from the calculating. Moreover, the drain-source voltage, current
negative voltage drop on the parasitic inductance can be spike and the Miller-turn-on phenomenal are mentioned to
damaged the MOSFET. The measure of this spike is 475 make sure the MOSFET could operate under the worst
V, which is close to the calculation result. The turn-off conditions.
energy loss has an error because the drain-source voltage
waveform is shifted to the right as explanation above, References
however, the simulation result is smaller than the [1]. Laszlo Balogh, “Fundamentals of MOSFET and
calculation result, so it has a safe margin for the design. IGBT Gate Driver Circuits”, TI Application Report, mar.
2017.
Table 2. The comparison between the theory and [2]. “MOSFET Gate Driver Circuit”, TOSHIBA
simulation Application Note, 2018.
Parameters Theoretical Simulation [3]. Sanjay Havanur, “Power MOSFET Basics:
results results Understanding the Turn-On Process”, VISHAY
𝑡𝑑,𝑂𝑁 12.0 ns 12.1 ns Application Note, Jun. 2015.
[4]. “Power MOSFET Basics: Understanding Gate Charge
𝑡𝑟𝑖 79.2 ns 69.2 ns
and using it to Assess Switching Performance”, VISHAY
𝑡𝑓𝑣 12.1 ns 8.72 ns
Application Note, Feb. 2016.
𝑡𝑑,𝑂𝐹𝐹 15.4 ns 13.8 ns [5]. “Estimating MOSFET Parameters from the Data
𝑡𝑟𝑣 6.43 ns 31.8 ns Sheet”, TI Application Note, 2002.
𝑡𝑓𝑖 59.4 ns 61.1 ns
𝐼𝐷𝑆,𝑂𝑁,𝑝𝑒𝑎𝑘 65.5 A 67 A
𝑉𝐷𝑆𝑆,𝑂𝐹𝐹,𝑝𝑒𝑎𝑘 460 V 475 V
𝐸𝑠𝑤,𝑙𝑜𝑠𝑠,𝑂𝑁 0.913 mJ 0.926 mJ
𝐸𝑠𝑤,𝑙𝑜𝑠𝑠,𝑂𝐹𝐹 0.659 mJ 0.373 mJ