A B C D E

1 LCFC Confidential 1

Customer Product name

2 E14 Gen4 Intel/E15 Gen4 Intel 2

Project Code:
JE442/JE542
Board Number:
NM-E211
3 3

Customer Project name:

Mercury/Mars3.0

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 COVER PAGE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 1 of 108
A B C D E
 A B C D E

DDR4
GDDR6 GDDR6 GPU P28 PCIE GEN4 x4
DDR4 3200Mhz 3200Mhz
P25

Channel A SODIMM
VRAM 1/2GB *2 GN18-S5
1 1

SPI SPI ROM DDR4 3200Mhz P26

DDR4 MEM DOWN
Channel B
LCD P47
eDP x 2 3200Mhz 1/2GB *4
Touch Panel (Optional) I2C
DMIC eDP cable PCIE GEN 3 x4
Camera(Digital MIC)
USB 2.0 x 1
M.2 Slot for SSD P63

LENOVO LED Logo PCIE GEN 4 x4

LED signal
M.2 Slot for SSD P63
HDMI 2.0 P49 HDMI 2.0
HDMI Conn. P50 Retimer
PS8409
CNVi
USB 2.0 x 1 PCIE GEN1x 1 P71
Power switch
SN1702001RTER USB 2.0 x 1 M.2 WLAN
P57 USB 3.2 GEN1 x 1
2

Type A Conn. 2

USB 3.2 GEN1 with AOU

Intel HDA Codec
P66
2CH Speaker

CC PD Controller P51 SMLink Alder Lake P Realtek

MIC IN/GND
HP R/L Univeral Jack
TPS65994 ALC3287
I2C EEPROM
SBU,CC CC Protect SBU
Type C Conn. P53
USB C TCP-AUX P82
PD/DP/USB/TBT
BB Retimer
P52 TCP-MAIN RTC battery
SPI
SPI ROM
USB 2.0 switch USB2.0
TS3USB31ERSER
IO_Board
I2C TOUCH FPR
eSPI BUS Power Button
P76 USB 2.0 x 1
3
G-sensor & 3

P78
44 PIN Cable Finger Print
P76 P79
Thermal I2C PCIe GEN1x 1
Sensor Embedded Controller GBE LAN MDI RJ45 Conn.
SMLink
ITE I219V
P81 PS2 P81 PS2
Track Point Click Pad IT8227E-256/CX LQFP 128P
MB conn IO conn
USB 2.0 x 1 USB2.0
Conn.
Flash ROM SPI
P77 P81 64MB P27
FAN Int. KB
P82 5 PIN Cable
TPM P27

I2C Earphone Board 15'' Only

4 4

USB 2.0 x 1

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 BLOCK DIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 2 of 108
A B C D E
 5 4 3 2 1

TI RT
BQ25710RSNR RT6310BGQUF +3VALW/10A Richtek
D D
Battery Charger EN +3VALW RT8068AZQW +1.0VGS/2A
TYPE-C PGOOD
Buck-Boost FOR SYS VRM EN +1.0VGS
PGOOD
FOR GPU

+1.8VALW/4A

SMBus

+2.5V/1A

SY +5VALW/10A Richtek
SY8370C1TMC LV5116BGQW
Batt. MOSFET +1.2V/8A
EN +5VALW SYS PMIC
PGOOD
C FOR SYS VRM C

+0.6VS/1A

+VCCIN_AUX/14A
EN

MPS
MP2941AGL-Z
Battery +1.2V/+1.25V FBVDDQ/11A
polymer FOR VRAM
EN PGOOD
3S1P

Richtek
B
RT8816CGQW B

Controller+Driver+MOS NVVDD/35A

FOR GPU Core(2PHASE)

EN PGOOD

Richtek
VCCCORE/47A
RT3624BEGQW
Controller+DR.MOS VCCGT/23A

FOR CPU Core(2+1)Phase

EN PGOOD

A A

<Variant Name>

Security Classification LC Future Center Secret Data Title

Issued Date Deciphered Date Power Block Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 3 of 108
5 4 3 2 1
 1 2 3 4 5

Voltage Rails ( O --> Means ON , X --> Means OFF )

HSIO Matrix
Power Plane HSIO PORT Function
1 TYPE-C TBT4
V9B+ +5VS
2 EARPHONE
+3VL +5VALW +3VALW_PCH 1.2V +3VS
A 3 IOB USB A

+5VL +3VALW +1.8VALW +VCCST_CPU +1.8VS 4 NC

5 NC
USB2.0
6 FINGER PRINTER
State 7 Camera
8 NC
9 USB3.2 AOU
S0 O O O O O 10 WLAN
1 USB3.2 AOU Port
2 NC
S0Ix USB3.0
O O O O O 3 NC
4 NC
5 NC
S4/S5 DC O O O X X 6 WLAN
7 NC
PCH 8 LAN
S4/S5
DEEP SLEEP O O X X X PCIE3 9
10
SSD1
11
S4/S5 AC O O O X X 12
B 0 B

CPU 1
S4/S5 SSD2
AC ONLY O O O X X PCIE4-A 2
3
0
CPU 1
GPU
PCIE4-B 2
3

CPU 0-3
NC
PCIE5
SMBUS Control Table 4-7

CPU A eDP
DDI
B HDMI
0 TYPE-C TBT4
EC SMBus1 address PCH SMB address
CPU 1 NC
Device Address Device Address
TCP 2 NC
GPU(GN18-S5) 1001_110 SO-DIMM 1010_000
3 NC
G-Sensor(LIS2DWLTR) 0011_000 Click Pad TBD
Thermal Sensor(F75303M) 1001_101

C
PCH SML0 address C
Thermal Sensor(NCT7718) 1001_100
Device Address
Battery 0001_011 BB Re-timer 0X56
Charger 0001_001 LAN 0XC8

EC SMBus4 address PCH SML1 address

Device Address
Device Address
PD 0X23/27
PD TBD
HDMI Retimer 0x10-0x2F
PMIC 0x34
CPU I2C2 address
Device
Touch Panel
Address
TBD www.teknisi-indonesia.com

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 DDR4 SUB CHANNEL-A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 4 of 108
1 2 3 4 5
 5 4 3 2 1

GPU
GN18-S5 GN20-S5
OPT_GN18S@ OPT_GN20S@

UG11 UG11

D
S IC GN18-S5-A1 BGA 771P GPU MP 01 ! S IC GN20-S5-A1 BGA 771P GPU MP 01 ! D
SA0000C7B40 SA0000C7C50

VRAM PN RAMCFG[2:0]
STRAP 2 STRAP 1 STRAP 1 STRAP 0
V2G_SAM@ V2G_SAM@ V2G_SAM@ V2G_SAM@ V2G_SAM@
Samsung 8Gb(0x0)
UG15 UG16 RG3106 RG3105 RG3104

S IC D6 8G/1750 K4Z80325BC-HC14 FBGA 01! S IC D6 8G/1750 K4Z80325BC-HC14 FBGA 01! S RES 1/20W 100K +-5% 0201 S RES 1/20W 100K +-5% 0201 S RES 1/20W 100K +-5% 0201
SA00009L410 SA00009L410 SD0431003YT SD0431003YT SD0431003YT

V2G_HYX0@ V2G_HYX0@ V2G_HYX0@

V2G_HYX0@ V2G_HYX0@

RG3106 RG3102 RG3104

UG15 UG16

S RES 1/20W 100K +-5% 0201 S RES 1/20W 100K +-5% 0201 S RES 1/20W 100K +-5% 0201
Hynix 8Gb(0x2)
S IC D6 256MX32 H56C8H24AIR-S2C 01 ! S IC D6 256MX32 H56C8H24AIR-S2C 01 !
SD0431003YT SD0431003YT SD0431003YT
SA0000B4E00 SA0000B4E00

V2G_HYX1@ V2G_HYX1@ V2G_HYX1@ V2G_HYX1@ V2G_HYX1@

C C

UG15 UG16 RG3103 RG3105 RG3101

S IC D6 256MX32 H56G32CS4DX005 FBGA 01!

SA0000C8K00
S IC D6 256MX32 H56G32CS4DX005 FBGA 01!
SA0000C8K00
S RES 1/20W 100K +-5% 0201
SD0431003YT
S RES 1/20W 100K +-5% 0201
SD0431003YT
S RES 1/20W 100K +-5% 0201
SD0431003YT
Hynix 8Gb(0x5)
V4G_SAM@ V4G_SAM@ V4G_SAM@ V4G_SAM@ V4G_SAM@ V4G_SAM@

UG15 UG16 RG3106 RG3105 RG3102 RG3104

S IC D6 16G/1750 K4ZAF325BM-HC14 01 ! S IC D6 16G/1750 K4ZAF325BM-HC14 01 ! S RES 1/20W 100K +-5% 0201 S RES 1/20W 100K +-5% 0201 S RES 1/20W 100K +-5% 0201 S RES 1/20W 100K +-5% 0201
Samsung 16Gb(0x9)
SA00009QV20 SA00009QV20
SD0431003YT SD0431003YT SD0431003YT SD0431003YT

V4G_MIC@ V4G_MIC@ V4G_MIC@ V4G_MIC@ V4G_MIC@

UG15 UG16 RG3103 RG3102 RG3101

S IC D6 4GB MT61K512M32KPA-14 :C MP 01 ! S IC D6 4GB MT61K512M32KPA-14 :C MP 01 ! S RES 1/20W 100K +-5% 0201 S RES 1/20W 100K +-5% 0201 S RES 1/20W 100K +-5% 0201
Micron 16Gb(0x7)
SA0000C0940 SA0000C0940
SD0431003YT SD0431003YT SD0431003YT

V4G_HYX@ V4G_HYX@ V4G_HYX@ V4G_HYX@ V4G_HYX@ V4G_HYX@

B
UG15 UG16 RG3106 RG3105 RG3104 RG3101
Hynix 16Gb(0x8) B
S IC D6 16G H56G42AS2DX014N BGA MP 01 ! S IC D6 16G H56G42AS2DX014N BGA MP 01 ! S RES 1/20W 100K +-5% 0201 S RES 1/20W 100K +-5% 0201 S RES 1/20W 100K +-5% 0201 S RES 1/20W 100K +-5% 0201
SA0000CMU10 SA0000CMU10
SD0431003YT SD0431003YT SD0431003YT SD0431003YT

X76
X76_V2G_SAM@ X76_V2G_HYX0@ X76_V2G_HYX1@ X76_V4G_SAM@ X76_V4G_MIC@ X76_V4G_HYX@

ZZZ9 ZZZ8 ZZZ11 ZZZ10 ZZZ13 ZZZ12

ALT. GROUP PARTS SAMSUNG V2G JE442 ALT. GROUP PARTS HYNIX V2G JE442 ALT. GROUP PARTS HYNIX2 V2G JE442 ALT. GROUP PARTS SAMSUNG V4G JE442 ALT. GROUP PARTS MICRON V4G JE442 ALT. GROUP PARTS HYNIX V4G JE442
X764EU01004 X764EU01005 X764EU0100A X764EU01009 X764EU0100B X764EU0100C

OPT_GN20S@

UG12

A A
S IC FL 16M W25Q16JWSNIQ SOIC 8P
SA0000AU500

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 5 of 108
5 4 3 2 1
 A B C D E

Virtual Symbol_EE BOM Structure

PANEL_E14@ PANEL_E15@ PCB_E14@ PCB_E14@ PCB_E15@ PCB_E15@ PCB_E15@
BOM Structure Description
@ Not stuff
ZZZ1 ZZZ1 ZZZ ZZZ ZZZ ZZZ ZZZ
PCB@ For PCB part
PCB PCB JE442 NM-E211 NS-E211
DAZ2E700100
PCB JE542 NM-E211 NS-E212/E213
DAZ2E600100
PCB JE442 NM-E211 REV1 M/B
DA80001AQ10
PCB JE442 NS-E211 REV1 IO/B
DA80001AS10
PCB JE542 NM-E211 REV1 M/B
DA80001AR10
PCB JE542 NS-E212 REV1 IO/B
DA80001AT10
PCB JE542 NS-E213 REV1 EARPHONE/B
DA80001AU10
ME@ For ME part

1 EMC@ For EMC part 1

EMC_NS@ For EMC not stuff part

U28_I7_SQS@ U28_I5_SQS@
CPU UC1 UC1
RF@ For RF part
RF_NS@ For RF not stuff part
S IC FJ8071504786607 SRLD6 L0 2.1G 01 ! S IC FJ8071504787907 SRLD9 L0 1.7G 01 ! For Finger Print
SA0000D0P10 SA0000D0Q10
FPR@
NON-FPR@ For Non Finger Print
TPM@ For TPM
U15_I7@ U15_I5@ U15_I5S@ U15_I3@ U15_I3S@ For Non TPM
NON-TPM@
UC1 UC1 UC1 UC1 UC1 For U28 I7 CPU
U28_I7@
U28_I5@ For U28 I5 CPU
S IC FJ8071504826607 SRLFP R0 1.7G 01 ! S IC FJ8071504826802 SRLFQ R0 1.3G 01 ! S IC FJ8071504826803 SRLFR R0 1.3G 01 ! S IC FJ8071504827100 SRLFT R0 1.2G 01 ! S IC FJ8071504827101 SRLFU R0 1.2G 01 !
SA0000D2130 SA0000D1S40 SA0000D2P20 SA0000D2S30 SA0000D2T20 For U15 I7 CPU
U15_I7@
U15_I5@ For U15 I5 CPU
U15_I5S@ For U15 I5S CPU
BOARD ID:6,5 U15_I3@ For U15 I3 CPU
U15_I3S@ For U15 I3S CPU
D8G_SAM@ D8G_SAM@ D8G_SAM@ D8G_SAM@ D8G_SAM@ D8G_SAM@
D8G_MIC@ For 16Gb Micron Memory X76
UD1 UD2 UD3 UD4 RC4229 RC4221 For 16Gb Hynix Memory X76
D8G_HYX@
D8G_SAM@ For 16Gb Samsung Memory X76
S IC D4 1GX16/3200 K4AAG165W B-BCW E 01 ! S IC D4 1GX16/3200 K4AAG165W B-BCW E 01 ! S IC D4 1GX16/3200 K4AAG165W B-BCW E 01 ! S IC D4 1GX16/3200 K4AAG165W B-BCW E 01 ! S RES 1/20W 10K +-5% 0201 S RES 1/20W 10K +-5% 0201
SA0000C6N00 SA0000C6N00 SA0000C6N00 SA0000C6N00 SD0431002YT SD0431002YT

UMA@ For UMA part

DRAM D8G_HYX@ D8G_HYX@ D8G_HYX@ D8G_HYX@ D8G_HYX@ D8G_HYX@
2
OPT@ For GPU part 2
/Board ID For GPU not Stuff part
UD1 UD2 UD3 UD4 RC4222 RC4228
OPT_NS@
OPT_EMC@ For GPU EMC part
S IC D4 16G/3200 H5ANAG6NCJR-XNC 96P 01! S IC D4 16G/3200 H5ANAG6NCJR-XNC 96P 01! S IC D4 16G/3200 H5ANAG6NCJR-XNC 96P 01! S IC D4 16G/3200 H5ANAG6NCJR-XNC 96P 01! S RES 1/20W 10K +-5% 0201 S RES 1/20W 10K +-5% 0201 For GPU RF part
SA0000B5K00 SA0000B5K00 SA0000B5K00 SA0000B5K00 SD0431002YT SD0431002YT
OPT_RF@
OPT_RF_NS@ For GPU RF not stuff part
OPT_GN18S@ For GN18-S5 part
D8G_MIC@ D8G_MIC@ D8G_MIC@ D8G_MIC@ D8G_MIC@ D8G_MIC@
OPT_GN18S_NS@ For GN18-S5 not stuff part
UD1 UD2 UD3 UD4 RC4229 RC4228 For GN20-S5 part
OPT_GN20S@
OPT_GN20S_NS@ For GN20-S5 not stuff part
S IC D4 16GB/3200 MT40A1G16RC-062E:B 01! S IC D4 16GB/3200 MT40A1G16RC-062E:B 01! S IC D4 16GB/3200 MT40A1G16RC-062E:B 01! S IC D4 16GB/3200 MT40A1G16RC-062E:B 01! S RES 1/20W 10K +-5% 0201 S RES 1/20W 10K +-5% 0201
SA0000A4K10 SA0000A4K10 SA0000A4K10 SA0000A4K10 SD0431002YT SD0431002YT For 4G Samsung VRAM X76
V4G_SAM@
V2G_SAM@ For 2G Samsung VRAM X76
V2G_HYX0@ For 2G Hynix VRAM X76
D8G_KSN@ D8G_KSN@ D8G_KSN@ D8G_KSN@ D8G_KSN@ D8G_KSN@
OPT_RT8816@ For GPU Power
UD1 UD2 UD3 UD4 RC4229 RC4228 For GPU Power
OPT_RT8816NS@
OPT_UP1666@ For GPU Power
S IC D4 16G/3200 MT40A1G16RC-062E:B 01 ! S IC D4 16G/3200 MT40A1G16RC-062E:B 01 ! S IC D4 16G/3200 MT40A1G16RC-062E:B 01 ! S IC D4 16G/3200 MT40A1G16RC-062E:B 01 ! S RES 1/20W 10K +-5% 0201 S RES 1/20W 10K +-5% 0201
SA0000A4K30 SA0000A4K30 SA0000A4K30 SA0000A4K30 SD0431002YT SD0431002YT For GPU Power
OPT_UPI1666@
OPT_UPI1666NS@ For GPU Power
OPT_US5650@ For GPU Power
OPT_NCP45492@ For GPU Power
X76_D8G_MIC@ X76_D8G_HYX@ X76_D8G_SAM@ X76_D8G_KSN@
U15@ For U15 CPU Power
3 3
ZZZ2 ZZZ2 ZZZ2 ZZZ2 For U28 CPU Power
X76 U28@
ALT. GROUP PARTS MICRON D8G JE442 ALT. GROUP PARTS HYNIX D8G JE442 ALT. GROUP PARTS SAMSUNG D8G JE442 ALT. GROUP PARTS D8G KINGSTON JE442
X764EU01001 X764EU01002 X764EU01003 X764EU0100D

memory down SPD

Vender Capacity Types Board ID[6:5]

Samsung 16Gb 1R*SDP*16Gb 01

4
Hynix 16Gb 1R*SDP*16Gb 10 4

Micron 16Gb 1R*SDP*16Gb 00

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 BLOCK DIAGRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 6 of 108
A B C D E
 5 4 3 2 1

?
D D
?

UC1A BMAP_REV = ?

W3 BE8 TCP0_CRX_DTX1_P
DDIA_TXP_3 TCP0_TXRX_P1 TCP0_CRX_DTX1_N TCP0_CRX_DTX1_P
AA3 BE6
AA1 DDIA_TXN_3 TCP0_TXRX_N1 BG8 TCP0_CRX_DTX0_P TCP0_CRX_DTX1_N
DDIA_TXP_2 TCP0_TXRX_P0 TCP0_CRX_DTX0_N TCP0_CRX_DTX0_P
AB1 BG6
CPU_EDP_TX1_P AB3 DDIA_TXN_2 TCP0_TXRX_N0 AY3 TCP0_CTX_DRX1_P TCP0_CRX_DTX0_N
CPU_EDP_TX1_P CPU_EDP_TX1_N DDIA_TXP_1 TCP0_TX_P1 TCP0_CTX_DRX1_N TCP0_CTX_DRX1_P
AD3 BB3
CPU_EDP_TX1_N CPU_EDP_TX0_P AF1 DDIA_TXN_1 TCP0_TX_N1 BD3 TCP0_CTX_DRX0_P TCP0_CTX_DRX1_N Type-C PortA
CPU_EDP_TX0_P CPU_EDP_TX0_N AD1 DDIA_TXP_0 TCP0_TX_P0 BE3 TCP0_CTX_DRX0_N TCP0_CTX_DRX0_P
eDP Port CPU_EDP_TX0_N DDIA_TXN_0 TCP0_TX_N0 TCP0_CTX_DRX0_N TBT4
BB1 TCP0_AUX_P
CPU_EDP_AUX_P AF3 TCP0_AUX_P BD1 TCP0_AUX_N TCP0_AUX_P
CPU_EDP_AUX_P CPU_EDP_AUX_N DDIA_AUXP TCP0_AUX_N TCP0_AUX_N
AG3
CPU_EDP_AUX_N DDIA_AUXN AV8
ER23 TCP1_TXRX_P1 AV6
GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1
ET23 AY8
GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0 AY6
CPU_EDP_HPD TCP1_TXRX_N0
CPU_EDP_HPD EV25 AP3
GPP_E14/DDSP_HPDA/DISP_MISC_A TCP1_TX_P1 AR3
CPU_HDMI_CLK_P AP6 TCP1_TX_N1 AU3
CPU_HDMI_CLK_P CPU_HDMI_CLK_N DDIB_TXP_3 TCP1_TX_P0
AP8 AW3
CPU_HDMI_CLK_N CPU_HDMI_TX0_P AM6 DDIB_TXN_3 TCP1_TX_N0 AR1
CPU_HDMI_TX0_P CPU_HDMI_TX0_N DDIB_TXP_2 TCP1_AUX_P
AM8 AU1
CPU_HDMI_TX0_N CPU_HDMI_TX1_P DDIB_TXN_2 TCP1_AUX_N
AK6
HDMI Port CPU_HDMI_TX1_P CPU_HDMI_TX1_N AK8 DDIB_TXP_1 BN8
CPU_HDMI_TX1_N CPU_HDMI_TX2_P DDIB_TXN_1 TCP2_TXRX_P1
AH6 BN6
CPU_HDMI_TX2_P CPU_HDMI_TX2_N AH8 DDIB_TXP_0 TCP2_TXRX_N1 BL8
CPU_HDMI_TX2_N DDIB_TXN_0 TCP2_TXRX_P0 BL6
AE6 TCP2_TXRX_N0 BK3
AE8 DDIB_AUXP TCP2_TX_P1 BM3
DDIB_AUXN TCP2_TX_N1 BG3
CPU_DDC_CLK EK46 TCP2_TX_P0 BH3
CPU_DDC_CLK CPU_DDC_DATA GPP_H15/DDPB_CTRLCLK/PCIE_LINK_DOWN TCP2_TX_N0
EL46 BH1
CPU_DDC_DATA GPP_H17/DDPB_CTRLDATA TCP2_AUX_P BK1
CPU_HDMI_HPD EB47 TCP2_AUX_N
CPU_HDMI_HPD GPP_A18/DDSP_HPDB/DISP_MISCB
C BW8 C
DV54 TCP3_TXRX_P1 BW6
DV52 GPP_A21/DDPC_CTRLCLK TCP3_TXRX_N1 BU8
GPP_A22/DDPC_CTRLDATA TCP3_TXRX_P0 BU6
CPU_TBT_LSX0_TXD ER26 TCP3_TXRX_N0 BU3
CPU_TBT_LSX0_TXD CPU_TBT_LSX0_RXD GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD/BSSB_LS0_RX TCP3_TX_P1
CPU_TBT_LSX0_RXD ET26 BV3
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD/BSSB_LS0_TX
STRAP TCP3_TX_N1 BN3
TCP3_TX_P0
EL26 BR3
GPP_E21 EN26 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD/BSSB_LS1_RX TCP3_TX_N0 BR1
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD/BSSB_LS1_TX
STRAP TCP3_AUX_P BU1
HDMI_RT_RST_R TCP3_AUX_N
FC37
HDMI_RT_RST_R GPP_D10 EV37 GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/BSSB_LS2_RX/GSPI2_CS0# AL3
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/BSSB_LS2_TX/GSPI2_CLK
STRAP VSS1 AM1 TCRCOMPN
EY37 TCP_RCOMP
GPP_D12 FA37 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/BSSB_LS3_RX/GSPI2_MISO AF32 DSI_DE_TE_2
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/BSSB_LS3_TX/GSPI2_MOSI
STRAP DISP_UTILS_2
RC4281 1 @ 2 1/20W_0_5%_0201 CPU_ANS_EN DY54 AJ1 DDIA_RCOMP
EC_ANS GPP_A17/DISP_MISCC DDIA_RCOMP DDIB_RCOMP
EB49 AL1
EB51 GPP_A19/DDSP_HPD1/DISP_MISC1 DDIB_RCOMP
GPP_A20/DDSP_HPD2/DISP_MISC2 DJ1

1/20W_150_1%_0201

1/20W_150_1%_0201

1/20W_100K_1%_0201

1/20W_2.2K_1%_0201
1

2
USB_OC1_N DY47 DISP_UTILS_1
USB_OC1_N DY49 GPP_A14/USB_OC1#/DDSP_HPD3/DISP_MISC3

RC1103

RC1102

RC1101

RC1104
GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4
CPU_EDP_ENVDD ET21
CPU_EDP_ENVDD CPU_EDP_ENBKL EN21 VDDEN
CPU_EDP_ENBKL

1
CPU_EDP_PWM EDP_BKLTEN
EL21
CPU_EDP_PWM EDP_BKLTCTL
1 OF 22
INTEL_ADL-P-682_BGA1744
@

B +3VALW_PCH +3VALW_PCH +3VALW_PCH +3VALW_PCH +3VALW_PCH B

1

RC1118 RC1116 RC1119 RC1117 RC4242 1 2 1/20W_10K_5%_0201 USB_OC1_N

@ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201
RC4292 1 2 1/20W_2.2K_5%_0201 CPU_DDC_CLK
RC4272 1 2 1/20W_2.2K_5%_0201 CPU_DDC_DATA
2

GPP_D10 GPP_D12 CPU_TBT_LSX0_RXD GPP_E21

1

RC1122 RC1120 RC1123 RC1121

@ 1/20W_20K_5%_0201 @ 1/20W_20K_5%_0201 1/20W_20K_5%_0201 @ 1/20W_20K_5%_0201
2

@
CPU_EDP_PWM RC1113 1 2 1/20W_100K_5%_0201

CC406 1 2 0.33U_6.3V_M_X5R_0201
@
GPP_D10: GPP_E19(CPU_TBT_LSX0_RXD):
Rising edge of RSMRST# DDP2 I2C /TBT_LSX1 /BBSB_LS1 pins VCC configuration CPU_EDP_ENBKL RC1114 1 2 1/20W_100K_5%_0201
This strap has a 20 kohm ± 30% internal pull-down. Rising edge of RSMRST#
0 = DDP3_I2C / TBT_LSX2 / BBSB_LS2 pins at 1.8V This strap has a 20 kohm ± 30% internal pull-down. CC2204 1 2 0.33U_6.3V_M_X5R_0201
@
1 = DDP3_I2C / TBT_LSX2 / BBSB_LS2 pins at 3.3V 0 = DDP1 I2C / TBT_LSX0 / BBSB_LS0 pins at 1.8V
Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 1 = DDP1 I2C / TBT_LSX0 / BBSB_LS0 pins at 3.3V CPU_EDP_ENVDD RC1115 1 2 1/20W_100K_5%_0201
2. This signal is in the primary well. Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts.
2. This signal is in the primary well. CC2205 1 2 0.33U_6.3V_M_X5R_0201
@

GPP_D12: GPP_E21 :
Rising edge of RSMRST# DDP2 I2C /TBT_LSX1 /BBSB_LS1 pins VCC configuration
This strap has a 20 kohm ± 30% internal pull-down. Rising edge of RSMRST#
A A
0 = DDP4_I2C / TBT_LSX3 / BBSB_LS3 pins at 1.8V This strap has a 20 kohm ± 30% internal pull-down.
1 = DDP4_I2C / TBT_LSX3 / BBSB_LS3 pins at 3.3V 0 = DDP2 I2C / TBT_LSX1 / BBSB_LS1 pins at 1.8V
Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 1 = DDP2 I2C / TBT_LSX1 / BBSB_LS1 pins at 3.3V
2. This signal is in the primary well. Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts.
2. This signal is in the primary well.

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 7 of 108
5 4 3 2 1
 5 4 3 2 1

DDRA_DQ[63:0]

?
?

UC1B BMAP_REV = ?
DDR4(IL) / DDR4(NIL) / DDR5(NIL) / LP4x-LP5(NIL)
DDRA_DQ7 DH58 DDR4 CD49 DDRA_CLK1_P
D DDRA_DQ6 DDR0_DQ_0_7/DDR0_DQ_0_7/DDR0_DQ_0_7/DDR0_DQ_0_7 DDR0_CLK_P_1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P/DDR1_CLK_P_1 DDRA_CLK1_N DDRA_CLK1_P D
DG57 CD48
DDRA_DQ5 DH56 DDR0_DQ_0_6/DDR0_DQ_0_6/DDR0_DQ_0_6/DDR0_DQ_0_6 DDR0_CLK_N_1/DDR3_CLK_N/DDR3_CLK_N/DDR3_CLK_N/DDR1_CLK_N_1 CH61 DDRA_CLK1_N
DDRA_DQ4 DDR0_DQ_0_5/DDR0_DQ_0_5/DDR0_DQ_0_5/DDR0_DQ_0_5 NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P/DDR1_CLK_P_0
DG60 CF61
Byte0[0~7] DDRA_DQ3 DL60 DDR0_DQ_0_4/DDR0_DQ_0_4/DDR0_DQ_0_4/DDR0_DQ_0_4 NC/DDR2_CLK_N/DDR2_CLK_N/DDR2_CLK_N/DDR1_CLK_N_0 CN49
DDRA_DQ2 DK56 DDR0_DQ_0_3/DDR0_DQ_0_3/DDR0_DQ_0_3/DDR0_DQ_0_3 NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P/DDR0_CLK_P_1 CN48
DDRA_DQ1 DL57 DDR0_DQ_0_2/DDR0_DQ_0_2/DDR0_DQ_0_2/DDR0_DQ_0_2 NC/DDR1_CLK_N/DDR1_CLK_N/DDR1_CLK_N/DDR0_CLK_N_1 CU61 DDRA_CLK0_P
DDRA_DQ0 DK58 DDR0_DQ_0_1/DDR0_DQ_0_1/DDR0_DQ_0_1/DDR0_DQ_0_1 DDR0_CLK_P_0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P_0 CR61 DDRA_CLK0_N DDRA_CLK0_P
DDRA_DQ15 DDR0_DQ_0_0/DDR0_DQ_0_0/DDR0_DQ_0_0/DDR0_DQ_0_0 DDR0_CLK_N_0/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK_N_0 DDRA_CLK0_N
DA58
DDRA_DQ14 CY57 DDR0_DQ_1_7/DDR0_DQ_1_7/DDR0_DQ_1_7/DDR0_DQ_1_7 DDR4 CF51
DDRA_DQ13 DDR0_DQ_1_6/DDR0_DQ_1_6/DDR0_DQ_1_6/DDR0_DQ_1_6 NC/DDR3_CKE_0/DDR3_WCK_P/DDR3_WCK_P/NC
DB56 CH51
DDRA_DQ12 CY60 DDR0_DQ_1_5/DDR0_DQ_1_5/DDR0_DQ_1_5/DDR0_DQ_1_5 NC/DDR3_CKE_1/DDR3_WCK_N/DDR3_WCK_N/NC CE57
Byte1[8~15] DDRA_DQ11 DE60 DDR0_DQ_1_4/DDR0_DQ_1_4/DDR0_DQ_1_4/DDR0_DQ_1_4 NC/DDR2_CKE_0/DDR2_WCK_P/DDR2_WCK_P/NC CF58
DDRA_DQ10 DD56 DDR0_DQ_1_3/DDR0_DQ_1_3/DDR0_DQ_1_3/DDR0_DQ_1_3 NC/DDR2_CKE_1/DDR2_WCK_N/DDR2_WCK_N/NC CR51
DDRA_DQ9 DE57 DDR0_DQ_1_2/DDR0_DQ_1_2/DDR0_DQ_1_2/DDR0_DQ_1_2 NC/DDR1_CKE_0/DDR1_WCK_P/DDR1_WCK_P/NC CU51
DDRA_DQ8 DDR0_DQ_1_1/DDR0_DQ_1_1/DDR0_DQ_1_1/DDR0_DQ_1_1 NC/DDR1_CKE_1/DDR1_WCK_N/DDR1_WCK_N/NC
DD58 CR58
DDRA_DQ23 DG50 DDR0_DQ_1_0/DDR0_DQ_1_0/DDR0_DQ_1_0/DDR0_DQ_1_0 NC/DDR0_CKE_0/DDR0_WCK_P/DDR0_WCK_P/NC CP57
DDRA_DQ22 DG47 DDR1_DQ_0_7/DDR0_DQ_2_7/DDR0_DQ_2_7/DDR1_DQ_0_7 NC/DDR0_CKE_1/DDR0_WCK_N/DDR0_WCK_N/NC
DDRA_DQ21 DH48 DDR1_DQ_0_6/DDR0_DQ_2_6/DDR0_DQ_2_6/DDR1_DQ_0_6 DDR4(IL) / DDR4(NIL) BN51 DDRA_DQS7_P
DDRA_DQ20 DG53 DDR1_DQ_0_5/DDR0_DQ_2_5/DDR0_DQ_2_5/DDR1_DQ_0_5 DDR1_DQSP_3/DDR0_DQSP_7/DDR1_DQSP_3/DDR3_DQSP_1 BL51 DDRA_DQS7_N DDRA_DQS7_P
Byte2[16~23] DDRA_DQ19 DL53 DDR1_DQ_0_4/DDR0_DQ_2_4/DDR0_DQ_2_4/DDR1_DQ_0_4 DDR1_DQSN_3/DDR0_DQSN_7/DDR1_DQSN_3/DDR3_DQSN_1
BW51 DDRA_DQS6_P DDRA_DQS7_N
DDRA_DQ18 DDR1_DQ_0_3/DDR0_DQ_2_3/DDR0_DQ_2_3/DDR1_DQ_0_3 DDR1_DQSP_2/DDR0_DQSP_6/DDR1_DQSP_2/DDR3_DQSP_0 DDRA_DQS6_N DDRA_DQS6_P
DK48 BU51
DDRA_DQ17 DM47 DDR1_DQ_0_2/DDR0_DQ_2_2/DDR0_DQ_2_2/DDR1_DQ_0_2 DDR1_DQSN_2/DDR0_DQSN_6/DDR1_DQSN_2/DDR3_DQSN_0 BL61 DDRA_DQS5_P DDRA_DQS6_N
DDRA_DQ16 DDR1_DQ_0_1/DDR0_DQ_2_1/DDR0_DQ_2_1/DDR1_DQ_0_1 DDR0_DQSP_3/DDR0_DQSP_5/DDR1_DQSP_1/DDR2_DQSP_1 DDRA_DQS5_N DDRA_DQS5_P
DL50 BN61
DDRA_DQ31 CY50 DDR1_DQ_0_0/DDR0_DQ_2_0/DDR0_DQ_2_0/DDR1_DQ_0_0 DDR0_DQSN_3/DDR0_DQSN_5/DDR1_DQSN_1/DDR2_DQSN_1 BU61 DDRA_DQS4_P DDRA_DQS5_N
DDRA_DQ30 DDR1_DQ_1_7/DDR0_DQ_3_7/DDR0_DQ_3_7/DDR1_DQ_1_7 DDR0_DQSP_2/DDR0_DQSP_4/DDR1_DQSP_0/DDR2_DQSP_0 DDRA_DQS4_N DDRA_DQS4_P
CY47 BW61
DDRA_DQ29 DDR1_DQ_1_6/DDR0_DQ_3_6/DDR0_DQ_3_6/DDR1_DQ_1_6 DDR0_DQSN_2/DDR0_DQSN_4/DDR1_DQSN_0/DDR2_DQSN_0 DDRA_DQS3_P DDRA_DQS4_N
DB48 DC51
DDRA_DQ28 DA53 DDR1_DQ_1_5/DDR0_DQ_3_5/DDR0_DQ_3_5/DDR1_DQ_1_5 DDR1_DQSP_1/DDR0_DQSP_3/DDR0_DQSP_3/DDR1_DQSP_1 DB51 DDRA_DQS3_N DDRA_DQS3_P
Byte3[24~31] DDRA_DQ27 DE53 DDR1_DQ_1_4/DDR0_DQ_3_4/DDR0_DQ_3_4/DDR1_DQ_1_4 DDR1_DQSN_1/DDR0_DQSN_3/DDR0_DQSN_3/DDR1_DQSN_1
DK51 DDRA_DQS2_P DDRA_DQS3_N
DDRA_DQ26 DC48 DDR1_DQ_1_3/DDR0_DQ_3_3/DDR0_DQ_3_3/DDR1_DQ_1_3 DDR1_DQSP_0/DDR0_DQSP_2/DDR0_DQSP_2/DDR1_DQSP_0 DH51 DDRA_DQS2_N DDRA_DQS2_P
DDRA_DQ25 DDR1_DQ_1_2/DDR0_DQ_3_2/DDR0_DQ_3_2/DDR1_DQ_1_2 DDR1_DQSN_0/DDR0_DQSN_2/DDR0_DQSN_2/DDR1_DQSN_0 DDRA_DQS1_P DDRA_DQS2_N
DE47 DB61
DDRA_DQ24 DDR1_DQ_1_1/DDR0_DQ_3_1/DDR0_DQ_3_1/DDR1_DQ_1_1 DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1 DDRA_DQS1_N DDRA_DQS1_P
DE50 DC61
DDRA_DQ39 BU58 DDR1_DQ_1_0/DDR0_DQ_3_0/DDR0_DQ_3_0/DDR1_DQ_1_0 DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1 DH61 DDRA_DQS0_P DDRA_DQS1_N
DDRA_DQ38 DDR0_DQ_2_7/DDR0_DQ_4_7/DDR1_DQ_0_7/DDR2_DQ_0_7 DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0 DDRA_DQS0_N DDRA_DQS0_P
BT57 DK61
DDRA_DQ37 BU56 DDR0_DQ_2_6/DDR0_DQ_4_6/DDR1_DQ_0_6/DDR2_DQ_0_6 DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0 DDRA_DQS0_N
DDRA_DQ36 BT60 DDR0_DQ_2_5/DDR0_DQ_4_5/DDR1_DQ_0_5/DDR2_DQ_0_5 DDR4 CM60 DDRA_MA5
Byte4[32~39] DDRA_DQ35 BY60 DDR0_DQ_2_4/DDR0_DQ_4_4/DDR1_DQ_0_4/DDR2_DQ_0_4 DDR0_MA_5/DDR0_CA_5/DDR0_CA_6/DDR0_CA_0/NC CL55 DDRA_MA7 DDRA_MA5
DDRA_DQ34 BW56 DDR0_DQ_2_3/DDR0_DQ_4_3/DDR1_DQ_0_3/DDR2_DQ_0_3 DDR0_MA_7/DDR0_CA_4/DDR0_CA_5/DDR0_CA_1/NC CM57 DDRA_MA6 DDRA_MA7
DDRA_DQ33 DDR0_DQ_2_2/DDR0_DQ_4_2/DDR1_DQ_0_2/DDR2_DQ_0_2 DDR0_MA_6/DDR0_CA_3/DDR0_CA_4/DDR0_CS_1/NC DDRA_MA8 DDRA_MA6
C BY57 CP60 C
DDRA_DQ32 BW58 DDR0_DQ_2_1/DDR0_DQ_4_1/DDR1_DQ_0_1/DDR2_DQ_0_1 DDR0_MA_8/DDR0_CA_2/DDR0_CA_3/DDR0_CS_0/DDR0_CA_9 CU58 DDRA_MA8
DDRA_DQ47 BL58 DDR0_DQ_2_0/DDR0_DQ_4_0/DDR1_DQ_0_0/DDR2_DQ_0_0 NC/DDR0_CA_1/DDR0_CA_1/DDR0_CA_5/DDR0_CA_0 CU56
DDRA_DQ46 BK57 DDR0_DQ_3_7/DDR0_DQ_5_7/DDR1_DQ_1_7/DDR2_DQ_1_7 NC/DDR0_CA_0/DDR0_CA_0/DDR0_CA_6/DDR0_CA_1 CM47 DDRA_BA1
DDRA_DQ45 BL56 DDR0_DQ_3_6/DDR0_DQ_5_6/DDR1_DQ_1_6/DDR2_DQ_1_6 DDR0_BA_1/DDR1_CA_5/DDR1_CA_6/DDR1_CA_0/DDR0_CA_10 CM53 DDRA_MA16 DDRA_BA1
DDRA_DQ44 DDR0_DQ_3_5/DDR0_DQ_5_5/DDR1_DQ_1_5/DDR2_DQ_1_5 DDR0_MA_16/DDR1_CA_4/DDR1_CA_5/DDR1_CA_1/DDR0_CA_8 DDRA_MA15 DDRA_MA16
BK60 CT46
Byte5[40~47] DDRA_DQ43 BP60 DDR0_DQ_3_4/DDR0_DQ_5_4/DDR1_DQ_1_4/DDR2_DQ_1_4 DDR0_MA_15/DDR1_CA_3/DDR1_CA_4/DDR1_CS_1/DDR0_CA_7 CP53 DDRA_MA14 DDRA_MA15
DDRA_DQ42 DDR0_DQ_3_3/DDR0_DQ_5_3/DDR1_DQ_1_3/DDR2_DQ_1_3 DDR0_MA_14/DDR1_CA_2/DDR1_CA_3/DDR1_CS_0/DDR0_CA_11 DDRA_CS1_N DDRA_MA14
BN56 CW47
DDRA_DQ41 DDR0_DQ_3_2/DDR0_DQ_5_2/DDR1_DQ_1_2/DDR2_DQ_1_2 DDR0_CS_1/DDR1_CA_1/DDR1_CA_1/DDR1_CA_5/DDR0_CA_2 DDRA_ODT1 DDRA_CS1_N
BP57 CV53
DDRA_DQ40 BN58 DDR0_DQ_3_1/DDR0_DQ_5_1/DDR1_DQ_1_1/DDR2_DQ_1_1 DDR0_ODT_1/DDR1_CA_0/DDR1_CA_0/DDR1_CA_6/DDR0_CA_3 CC60 DDRA_CKE0 DDRA_ODT1
DDRA_DQ55 DDR0_DQ_3_0/DDR0_DQ_5_0/DDR1_DQ_1_0/DDR2_DQ_1_0 DDR0_CKE_0/DDR2_CA_5/DDR2_CA_6/DDR2_CA_0/NC DDRA_CKE1 DDRA_CKE0
BT50 CB55
DDRA_DQ54 BT47 DDR1_DQ_2_7/DDR0_DQ_6_7/DDR1_DQ_2_7/DDR3_DQ_0_7 DDR0_CKE_1/DDR2_CA_4/DDR2_CA_5/DDR2_CA_1/NC CC57 DDRA_BG0 DDRA_CKE1
DDRA_DQ53 DDR1_DQ_2_6/DDR0_DQ_6_6/DDR1_DQ_2_6/DDR3_DQ_0_6 DDR0_BG_0/DDR2_CA_3/DDR2_CA_4/DDR2_CS_1/NC DDRA_BG1 DDRA_BG0
BU48 CE60
DDRA_DQ52 DDR1_DQ_2_5/DDR0_DQ_6_5/DDR1_DQ_2_5/DDR3_DQ_0_5 DDR0_BG_1/DDR2_CA_2/DDR2_CA_3/DDR2_CS_0/DDR1_CA_4 DDRA_MA12 DDRA_BG1
BT53 CH56
Byte6[48~55] DDRA_DQ51 BY53 DDR1_DQ_2_4/DDR0_DQ_6_4/DDR1_DQ_2_4/DDR3_DQ_0_4 DDR0_MA_12/DDR2_CA_1/DDR2_CA_1/DDR2_CA_5/DDR1_CA_12 CH58 DDRA_MA9 DDRA_MA12
DDRA_DQ50 DDR1_DQ_2_3/DDR0_DQ_6_3/DDR1_DQ_2_3/DDR3_DQ_0_3 DDR0_MA_9/DDR2_CA_0/DDR2_CA_0/DDR2_CA_6/DDR1_CA_7 DDRA_MA9
BW48 CC53
DDRA_DQ49 CA47 DDR1_DQ_2_2/DDR0_DQ_6_2/DDR1_DQ_2_2/DDR3_DQ_0_2 NC/DDR3_CA_5/DDR3_CA_6/DDR3_CA_0/DDR1_CS_1 CC47
DDRA_DQ48 DDR1_DQ_2_1/DDR0_DQ_6_1/DDR1_DQ_2_1/DDR3_DQ_0_1 NC/DDR3_CA_4/DDR3_CA_5/DDR3_CA_1/DDR1_CS_0
BY50 CE53 +3VALW
DDRA_DQ63 BJ50 DDR1_DQ_2_0/DDR0_DQ_6_0/DDR1_DQ_2_0/DDR3_DQ_0_0 NC/DDR3_CA_3/DDR3_CA_4/DDR3_CS_1/DDR1_CA_0 CH46
DDRA_DQ62 BJ47 DDR1_DQ_3_7/DDR0_DQ_7_7/DDR1_DQ_3_7/DDR3_DQ_1_7 NC/DDR3_CA_2/DDR3_CA_3/DDR3_CS_0/DDR1_CA_6 CK47 DDRA_MA10
DDRA_DQ61 DDR1_DQ_3_6/DDR0_DQ_7_6/DDR1_DQ_3_6/DDR3_DQ_1_6 DDR0_MA_10/DDR3_CA_1/DDR3_CA_1/DDR3_CA_5/DDR1_CA_8 DDRA_BA0 DDRA_MA10
BL48 CJ53
DDRA_BA0

2
DDRA_DQ60 BK53 DDR1_DQ_3_5/DDR0_DQ_7_5/DDR1_DQ_3_5/DDR3_DQ_1_5 DDR0_BA_0/DDR3_CA_0/DDR3_CA_0/DDR3_CA_6/DDR1_CA_10
+1.2V
DDRA_DQ59 BP53 DDR1_DQ_3_4/DDR0_DQ_7_4/DDR1_DQ_3_4/DDR3_DQ_1_4 DDR4 CV60 DDRA_MA3
Byte7[56~63] DDRA_DQ58 BN48 DDR1_DQ_3_3/DDR0_DQ_7_3/DDR1_DQ_3_3/DDR3_DQ_1_3 DDR0_MA_3/DDR0_CS_1/DDR0_CS_0/DDR0_CA_3/DDR0_CS_1 CR56 DDRA_MA4 DDRA_MA3
DDRA_DQ57 BP47 DDR1_DQ_3_2/DDR0_DQ_7_2/DDR1_DQ_3_2/DDR3_DQ_1_2 DDR0_MA_4/DDR0_CS_0/DDR0_CA_2/DDR0_CA_2/DDR0_CA_12 CU48 DDRA_MA13 DDRA_MA4
RC15
DDRA_DQ56 DDR1_DQ_3_1/DDR0_DQ_7_1/DDR1_DQ_3_1/DDR3_DQ_1_1 DDR0_MA_13/DDR1_CS_1/DDR1_CS_0/DDR1_CA_3/DDR0_CA_5 DDRA_ODT0 DDRA_MA13
BP50 CM50 1/20W_100K_5%_0201

1
DDRA_ODT0

2
DDR1_DQ_3_0/DDR0_DQ_7_0/DDR1_DQ_3_0/DDR3_DQ_1_0 DDR0_ODT_0/DDR1_CS_0/DDR1_CA_2/DDR1_CA_2/DDR0_CA_6 CJ57 DDRA_ACT_N
DDR0_ACT_N/DDR2_CS_1/DDR2_CS_0/DDR2_CA_3/DDR1_CA_9 DDRA_ACT_N
CF56 RC4293
NC/DDR2_CS_0/DDR2_CA_2/DDR2_CA_2/DDR1_CA_2 CH48 DDRA_PARITY DDR_VTT_PG_CTRL
DDR0_PAR/DDR3_CS_1/DDR3_CS_0/DDR3_CA_3/DDR1_CA_3 DDRA_PARITY 1/20W_1K_5%_0201 DDR_VTT_PG_CTRL
CC50 DDRA_MA2
DDR0_MA_2/DDR3_CS_0/DDR3_CA_2/DDR3_CA_2/DDR1_CA_1 DDRA_MA2

1
DDR4 CV50 DDRA_CS0_N C
DDR0_CS_0/NC/DDR1_CS_1/DDR1_CA_4/DDR0_CA_4 DDRA_MA0 DDRA_CS0_N
CJ50 2 QC1
DDR0_MA_0/NC/DDR3_CS_1/DDR3_CA_4/DDR1_CA_5 DDRA_MA1 DDRA_MA0
CV57 B MMBT3904WH_SOT323-3
DDR0_MA_1/NC/DDR0_CS_1/DDR0_CA_4/DDR0_CS_0 CJ60 DDRA_MA11 DDRA_MA1 E
DDRA_MA11

3
DDR0_MA_11/NC/DDR2_CS_1/DDR2_CA_4/DDR1_CA_11
DDR4 BF61
DDR0_ALERT_N BG60 DDRA_VREF_CA_CPU
B DDR0_VREF_CA0 DDRA_VREF_CA_CPU B
BG50 DDR_PG_CTRL
DDR_VTT_CTL EE53
DRAM_RESET#
RC802

2
A56 DDR_COMP 2 1
DDR_COMP_1 B56 1/20W_100_1%_0201 RC16
DDR_COMP_2
@ 1/20W_10K_5%_0201
2 OF 22
INTEL_ADL-P-682_BGA1744

1
@
+1.2V

1
RC17
1/20W_470_5%_0201

2
DRAMRST_N RC622 1 @ 2 0_0201_5% DRAMRST_N_R
DRAMRST_N_R

www.teknisi-indonesia.com

A A

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 8 of 108
5 4 3 2 1
 5 4 3 2 1

D D

DDRB_DQ[0..63]
?
?

UC1C BMAP_REV = ?

DDRB_DQ7 BB58 DDR4(IL) / DDR4(NIL) DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5

V48
DDRB_DQ6 DDR0_DQ_4_7/DDR1_DQ_0_7/DDR2_DQ_0_7/DDR4_DQ_0_7 DDR1_CLK_P_1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P/DDR3_CLK_P_1
BA57 V49
DDRB_DQ5 BB56 DDR0_DQ_4_6/DDR1_DQ_0_6/DDR2_DQ_0_6/DDR4_DQ_0_6 DDR1_CLK_N_1/DDR7_CLK_N/DDR7_CLK_N/DDR7_CLK_N/DDR3_CLK_N_1 AB61
DDRB_DQ4 BA60 DDR0_DQ_4_5/DDR1_DQ_0_5/DDR2_DQ_0_5/DDR4_DQ_0_5 NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P/DDR3_CLK_P_0 Y61
Byte0[0~7] DDRB_DQ3 BE60 DDR0_DQ_4_4/DDR1_DQ_0_4/DDR2_DQ_0_4/DDR4_DQ_0_4 NC/DDR6_CLK_N/DDR6_CLK_N/DDR6_CLK_N/DDR3_CLK_N_0
AG49
DDRB_DQ2 BD56 DDR0_DQ_4_3/DDR1_DQ_0_3/DDR2_DQ_0_3/DDR4_DQ_0_3 NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P/DDR2_CLK_P_1 AG48
DDRB_DQ1 DDR0_DQ_4_2/DDR1_DQ_0_2/DDR2_DQ_0_2/DDR4_DQ_0_2 NC/DDR5_CLK_N/DDR5_CLK_N/DDR5_CLK_N/DDR2_CLK_N_1 DDRB_CLK0_P
BE57 AL61
DDRB_DQ0 DDR0_DQ_4_1/DDR1_DQ_0_1/DDR2_DQ_0_1/DDR4_DQ_0_1 DDR1_CLK_P_0/DDR4_CLK_P/DDR4_CLK_P/DDR4_CLK_P/DDR2_CLK_P_0 DDRB_CLK0_N DDRB_CLK0_P
BD58 AJ61
DDRB_DQ15 AR58 DDR0_DQ_4_0/DDR1_DQ_0_0/DDR2_DQ_0_0/DDR4_DQ_0_0 DDR1_CLK_N_0/DDR4_CLK_N/DDR4_CLK_N/DDR4_CLK_N/DDR2_CLK_N_0 DDRB_CLK0_N
DDRB_DQ14 AP57 DDR0_DQ_5_7/DDR1_DQ_1_7/DDR2_DQ_1_7/DDR4_DQ_1_7 DDR4 AB51
DDRB_DQ13 AR56 DDR0_DQ_5_6/DDR1_DQ_1_6/DDR2_DQ_1_6/DDR4_DQ_1_6 NC/DDR7_CKE_0/DDR7_WCK_P/DDR7_WCK_P/NC Y51
DDRB_DQ12 AP60 DDR0_DQ_5_5/DDR1_DQ_1_5/DDR2_DQ_1_5/DDR4_DQ_1_5 NC/DDR7_CKE_1/DDR7_WCK_N/DDR7_WCK_N/NC W57
Byte1[8~15] DDRB_DQ11 AV60 DDR0_DQ_5_4/DDR1_DQ_1_4/DDR2_DQ_1_4/DDR4_DQ_1_4 NC/DDR6_CKE_0/DDR6_WCK_P/DDR6_WCK_P/NC Y58
DDRB_DQ10 AU56 DDR0_DQ_5_3/DDR1_DQ_1_3/DDR2_DQ_1_3/DDR4_DQ_1_3 NC/DDR6_CKE_1/DDR6_WCK_N/DDR6_WCK_N/NC AL51
DDRB_DQ9 DDR0_DQ_5_2/DDR1_DQ_1_2/DDR2_DQ_1_2/DDR4_DQ_1_2 NC/DDR5_CKE_0/DDR5_WCK_P/DDR5_WCK_P/NC
AV57 AJ51
DDRB_DQ8 AU58 DDR0_DQ_5_1/DDR1_DQ_1_1/DDR2_DQ_1_1/DDR4_DQ_1_1 NC/DDR5_CKE_1/DDR5_WCK_N/DDR5_WCK_N/NC AJ58
DDRB_DQ23 BA50 DDR0_DQ_5_0/DDR1_DQ_1_0/DDR2_DQ_1_0/DDR4_DQ_1_0 NC/DDR4_CKE_0/DDR4_WCK_P/DDR4_WCK_P/NC AH57
DDRB_DQ22 AY47 DDR1_DQ_4_7/DDR1_DQ_2_7/DDR2_DQ_2_7/DDR5_DQ_0_7 NC/DDR4_CKE_1/DDR4_WCK_N/DDR4_WCK_N/NC
DDRB_DQ21 BB48 DDR1_DQ_4_6/DDR1_DQ_2_6/DDR2_DQ_2_6/DDR5_DQ_0_6 DDR4(IL) / DDR4(NIL) N51 DDRB_DQS7_P
DDRB_DQ20 DDR1_DQ_4_5/DDR1_DQ_2_5/DDR2_DQ_2_5/DDR5_DQ_0_5 DDR1_DQSP_7/DDR1_DQSP_7/DDR3_DQSP_3/DDR7_DQSP_1 DDRB_DQS7_N DDRB_DQS7_P
BA53 L51
Byte2[16~23] DDRB_DQ19 BE53 DDR1_DQ_4_4/DDR1_DQ_2_4/DDR2_DQ_2_4/DDR5_DQ_0_4 DDR1_DQSN_7/DDR1_DQSN_7/DDR3_DQSN_3/DDR7_DQSN_1 N61 DDRB_DQS6_P DDRB_DQS7_N
DDRB_DQ18 DDR1_DQ_4_3/DDR1_DQ_2_3/DDR2_DQ_2_3/DDR5_DQ_0_3 DDR1_DQSP_6/DDR1_DQSP_6/DDR3_DQSP_2/DDR7_DQSP_0 DDRB_DQS6_N DDRB_DQS6_P
BD48 L61
DDRB_DQ17 DDR1_DQ_4_2/DDR1_DQ_2_2/DDR2_DQ_2_2/DDR5_DQ_0_2 DDR1_DQSN_6/DDR1_DQSN_6/DDR3_DQSN_2/DDR7_DQSN_0 DDRB_DQS5_P DDRB_DQS6_N
BE47 A43
DDRB_DQ16 BE50 DDR1_DQ_4_1/DDR1_DQ_2_1/DDR2_DQ_2_1/DDR5_DQ_0_1 DDR0_DQSP_7/DDR1_DQSP_5/DDR3_DQSP_1/DDR6_DQSP_1 A44 DDRB_DQS5_N DDRB_DQS5_P
DDRB_DQ31 DDR1_DQ_4_0/DDR1_DQ_2_0/DDR2_DQ_2_0/DDR5_DQ_0_0 DDR0_DQSN_7/DDR1_DQSN_5/DDR3_DQSN_1/DDR6_DQSN_1 DDRB_DQS4_P DDRB_DQS5_N
C AP50 A49 C
DDRB_DQ30 AP47 DDR1_DQ_5_7/DDR1_DQ_3_7/DDR2_DQ_3_7/DDR5_DQ_1_7 DDR0_DQSP_6/DDR1_DQSP_4/DDR3_DQSP_0/DDR6_DQSP_0 A51 DDRB_DQS4_N DDRB_DQS4_P
DDRB_DQ29 DDR1_DQ_5_6/DDR1_DQ_3_6/DDR2_DQ_3_6/DDR5_DQ_1_6 DDR0_DQSN_6/DDR1_DQSN_4/DDR3_DQSN_0/DDR6_DQSN_0 DDRB_DQS3_P DDRB_DQS4_N
AR48 AU51
DDRB_DQ28 DDR1_DQ_5_5/DDR1_DQ_3_5/DDR2_DQ_3_5/DDR5_DQ_1_5 DDR1_DQSP_5/DDR1_DQSP_3/DDR2_DQSP_3/DDR5_DQSP_1 DDRB_DQS3_N DDRB_DQS3_P
AP53 AR51
Byte3[24~31] DDRB_DQ27 AV53 DDR1_DQ_5_4/DDR1_DQ_3_4/DDR2_DQ_3_4/DDR5_DQ_1_4 DDR1_DQSN_5/DDR1_DQSN_3/DDR2_DQSN_3/DDR5_DQSN_1 BD51 DDRB_DQS2_P DDRB_DQS3_N
DDRB_DQ26 DDR1_DQ_5_3/DDR1_DQ_3_3/DDR2_DQ_3_3/DDR5_DQ_1_3 DDR1_DQSP_4/DDR1_DQSP_2/DDR2_DQSP_2/DDR5_DQSP_0 DDRB_DQS2_N DDRB_DQS2_P
AU48 BB51
DDRB_DQ25 AW47 DDR1_DQ_5_2/DDR1_DQ_3_2/DDR2_DQ_3_2/DDR5_DQ_1_2 DDR1_DQSN_4/DDR1_DQSN_2/DDR2_DQSN_2/DDR5_DQSN_0 AR61 DDRB_DQS1_P DDRB_DQS2_N
DDRB_DQ24 DDR1_DQ_5_1/DDR1_DQ_3_1/DDR2_DQ_3_1/DDR5_DQ_1_1 DDR0_DQSP_5/DDR1_DQSP_1/DDR2_DQSP_1/DDR4_DQSP_1 DDRB_DQS1_N DDRB_DQS1_P
AV50 AU61
DDRB_DQ39 DDR1_DQ_5_0/DDR1_DQ_3_0/DDR2_DQ_3_0/DDR5_DQ_1_0 DDR0_DQSN_5/DDR1_DQSN_1/DDR2_DQSN_1/DDR4_DQSN_1 DDRB_DQS0_P DDRB_DQS1_N
C49 BB61
DDRB_DQ38 E48 DDR0_DQ_6_7/DDR1_DQ_4_7/DDR3_DQ_0_7/DDR6_DQ_0_7 DDR0_DQSP_4/DDR1_DQSP_0/DDR2_DQSP_0/DDR4_DQSP_0 BD61 DDRB_DQS0_N DDRB_DQS0_P
DDRB_DQ37 DDR0_DQ_6_6/DDR1_DQ_4_6/DDR3_DQ_0_6/DDR6_DQ_0_6 DDR0_DQSN_4/DDR1_DQSN_0/DDR2_DQSN_0/DDR4_DQSN_0 DDRB_DQS0_N
F49
DDRB_DQ36 B48 DDR0_DQ_6_5/DDR1_DQ_4_5/DDR3_DQ_0_5/DDR6_DQ_0_5 DDR4 AE60 DDRB_MA5
Byte4[32~39] DDRB_DQ35 B52 DDR0_DQ_6_4/DDR1_DQ_4_4/DDR3_DQ_0_4/DDR6_DQ_0_4 DDR1_MA_5/DDR4_CA_5/DDR4_CA_6/DDR4_CA_0/NC AE55 DDRB_MA7 DDRB_MA5
DDRB_DQ34 DDR0_DQ_6_3/DDR1_DQ_4_3/DDR3_DQ_0_3/DDR6_DQ_0_3 DDR1_MA_7/DDR4_CA_4/DDR4_CA_5/DDR4_CA_1/NC DDRB_MA6 DDRB_MA7
F51 AF57
DDRB_DQ33 E52 DDR0_DQ_6_2/DDR1_DQ_4_2/DDR3_DQ_0_2/DDR6_DQ_0_2 DDR1_MA_6/DDR4_CA_3/DDR4_CA_4/DDR4_CS_1/NC AH60 DDRB_MA8 DDRB_MA6
DDRB_DQ32 DDR0_DQ_6_1/DDR1_DQ_4_1/DDR3_DQ_0_1/DDR6_DQ_0_1 DDR1_MA_8/DDR4_CA_2/DDR4_CA_3/DDR4_CS_0/DDR2_CA_9 DDRB_MA8
C51 AL56
DDRB_DQ47 E41 DDR0_DQ_6_0/DDR1_DQ_4_0/DDR3_DQ_0_0/DDR6_DQ_0_0 NC/DDR4_CA_1/DDR4_CA_1/DDR4_CA_5/DDR2_CA_1 AL58
DDRB_DQ46 DDR0_DQ_7_7/DDR1_DQ_5_7/DDR3_DQ_1_7/DDR6_DQ_1_7 NC/DDR4_CA_0/DDR4_CA_0/DDR4_CA_6/DDR2_CA_0 DDRB_BA1
C42 AE47
DDRB_DQ45 DDR0_DQ_7_6/DDR1_DQ_5_6/DDR3_DQ_1_6/DDR6_DQ_1_6 DDR1_BA_1/DDR5_CA_5/DDR5_CA_6/DDR5_CA_0/DDR2_CA_10 DDRB_RAS_N DDRB_BA1
F43 AE53
DDRB_DQ44 B41 DDR0_DQ_7_5/DDR1_DQ_5_5/DDR3_DQ_1_5/DDR6_DQ_1_5 DDR1_MA_16/DDR5_CA_4/DDR5_CA_5/DDR5_CA_1/DDR2_CA_8 AK46 DDRB_CAS_N DDRB_RAS_N
Byte5[40~47] DDRB_DQ43 B46 DDR0_DQ_7_4/DDR1_DQ_5_4/DDR3_DQ_1_4/DDR6_DQ_1_4 DDR1_MA_15/DDR5_CA_3/DDR5_CA_4/DDR5_CS_1/DDR2_CA_7 AH53 DDRB_WE_N DDRB_CAS_N
DDRB_DQ42 F44 DDR0_DQ_7_3/DDR1_DQ_5_3/DDR3_DQ_1_3/DDR6_DQ_1_3 DDR1_MA_14/DDR5_CA_2/DDR5_CA_3/DDR5_CS_0/DDR2_CA_11 AM47 DDRB_WE_N
DDRB_DQ41 E46 DDR0_DQ_7_2/DDR1_DQ_5_2/DDR3_DQ_1_2/DDR6_DQ_1_2 DDR1_CS_1/DDR5_CA_1/DDR5_CA_1/DDR5_CA_5/DDR2_CA_2 AM53
DDRB_DQ40 C45 DDR0_DQ_7_1/DDR1_DQ_5_1/DDR3_DQ_1_1/DDR6_DQ_1_1 DDR1_ODT_1/DDR5_CA_0/DDR5_CA_0/DDR5_CA_6/DDR2_CA_3 T55 DDRB_CKE0
DDRB_DQ55 L58 DDR0_DQ_7_0/DDR1_DQ_5_0/DDR3_DQ_1_0/DDR6_DQ_1_0 DDR1_CKE_0/DDR6_CA_5/DDR6_CA_6/DDR6_CA_0/NC T60 DDRB_CKE0
DDRB_DQ54 DDR1_DQ_6_7/DDR1_DQ_6_7/DDR3_DQ_2_7/DDR7_DQ_0_7 DDR1_CKE_1/DDR6_CA_4/DDR6_CA_5/DDR6_CA_1/NC DDRB_BG0
K57 W60
DDRB_DQ53 L56 DDR1_DQ_6_6/DDR1_DQ_6_6/DDR3_DQ_2_6/DDR7_DQ_0_6 DDR1_BG_0/DDR6_CA_3/DDR6_CA_4/DDR6_CS_1/DDR3_CA_4 U57 DDRB_BG1 DDRB_BG0
DDRB_DQ52 DDR1_DQ_6_5/DDR1_DQ_6_5/DDR3_DQ_2_5/DDR7_DQ_0_5 DDR1_BG_1/DDR6_CA_2/DDR6_CA_3/DDR6_CS_0/NC DDRB_MA12 DDRB_BG1
K60 AB58
Byte6[48~55] DDRB_DQ51 P60 DDR1_DQ_6_4/DDR1_DQ_6_4/DDR3_DQ_2_4/DDR7_DQ_0_4 DDR1_MA_12/DDR6_CA_1/DDR6_CA_1/DDR6_CA_5/DDR3_CA_7 AC60 DDRB_MA9 DDRB_MA12
DDRB_DQ50 N56 DDR1_DQ_6_3/DDR1_DQ_6_3/DDR3_DQ_2_3/DDR7_DQ_0_3 DDR1_MA_9/DDR6_CA_0/DDR6_CA_0/DDR6_CA_6/DDR3_CA_11 T53 DDRB_MA9
DDRB_DQ49 DDR1_DQ_6_2/DDR1_DQ_6_2/DDR3_DQ_2_2/DDR7_DQ_0_2 NC/DDR7_CA_5/DDR7_CA_6/DDR7_CA_0/DDR3_CS_1
P57 T47
DDRB_DQ48 N58 DDR1_DQ_6_1/DDR1_DQ_6_1/DDR3_DQ_2_1/DDR7_DQ_0_1 NC/DDR7_CA_4/DDR7_CA_5/DDR7_CA_1/DDR3_CS_0 W53
DDRB_DQ63 K50 DDR1_DQ_6_0/DDR1_DQ_6_0/DDR3_DQ_2_0/DDR7_DQ_0_0 NC/DDR7_CA_3/DDR7_CA_4/DDR7_CS_1/DDR3_CA_0 AA46
DDRB_DQ62 F58 DDR1_DQ_7_7/DDR1_DQ_7_7/DDR3_DQ_3_7/DDR7_DQ_1_7 NC/DDR7_CA_2/DDR7_CA_3/DDR7_CS_0/DDR3_CA_6 AC47 DDRB_MA10
DDRB_DQ61 F54 DDR1_DQ_7_6/DDR1_DQ_7_6/DDR3_DQ_3_6/DDR7_DQ_1_6 DDR1_MA_10/DDR7_CA_1/DDR7_CA_1/DDR7_CA_5/DDR3_CA_8 AC53 DDRB_BA0 DDRB_MA10
DDRB_DQ60 DDR1_DQ_7_5/DDR1_DQ_7_5/DDR3_DQ_3_5/DDR7_DQ_1_5 DDR1_BA_0/DDR7_CA_0/DDR7_CA_0/DDR7_CA_6/DDR3_CA_10 DDRB_BA0
L48
DDRB_DQ59 H56 DDR1_DQ_7_4/DDR1_DQ_7_4/DDR3_DQ_3_4/DDR7_DQ_1_4 DDR4 AM57 DDRB_MA3
Byte7[56~63] DDRB_DQ58 K53 DDR1_DQ_7_3/DDR1_DQ_7_3/DDR3_DQ_3_3/DDR7_DQ_1_3 DDR1_MA_3/DDR4_CS_1/DDR4_CS_0/DDR4_CA_3/DDR2_CS_1 AJ56 DDRB_MA4 DDRB_MA3
B DDRB_DQ57 DDR1_DQ_7_2/DDR1_DQ_7_2/DDR3_DQ_3_2/DDR7_DQ_1_2 DDR1_MA_4/DDR4_CS_0/DDR4_CA_2/DDR4_CA_2/DDR2_CA_12 DDRB_MA13 DDRB_MA4 B
P50 AK48
DDRB_DQ56 P53 DDR1_DQ_7_1/DDR1_DQ_7_1/DDR3_DQ_3_1/DDR7_DQ_1_1 DDR1_MA_13/DDR5_CS_1/DDR5_CS_0/DDR5_CA_3/DDR2_CA_5 AE50 DDRB_ODT0 DDRB_MA13
DDR1_DQ_7_0/DDR1_DQ_7_0/DDR3_DQ_3_0/DDR7_DQ_1_0 DDR1_ODT_0/DDR5_CS_0/DDR5_CA_2/DDR5_CA_2/DDR2_CA_6 DDRB_ACT_N DDRB_ODT0
AC57
DDR1_ACT_N/DDR6_CS_1/DDR6_CS_0/DDR6_CA_3/DDR3_CA_9 Y56 DDRB_ACT_N
NC/DDR6_CS_0/DDR6_CA_2/DDR6_CA_2/DDR3_CA_2 DDRB_PARITY
AA48
DDR1_PAR/DDR7_CS_1/DDR7_CS_0/DDR7_CA_3/DDR3_CA_3 DDRB_MA2 DDRB_PARITY
T50
DDR1_MA_2/DDR7_CS_0/DDR7_CA_2/DDR7_CA_2/DDR3_CA_1 DDRB_MA2
DDR4 AM50 DDRB_CS0_N
DDR1_CS_0/NC/DDR5_CS_1/DDR5_CA_4/DDR2_CA_4 AC50 DDRB_MA0 DDRB_CS0_N
DDR1_MA_0/NC/DDR7_CS_1/DDR7_CA_4/DDR3_CA_5 DDRB_MA1 DDRB_MA0
AM60
DDR1_MA_1/NC/DDR4_CS_1/DDR4_CA_4/DDR2_CS_0 DDRB_MA11 DDRB_MA1
AB56
DDR1_MA_11/NC/DDR6_CS_1/DDR6_CA_4/DDR3_CA_12 DDRB_MA11
DDR4 BG57
DDR1_ALERT_N BG55
DDR1_VREF_CA0 DDRB_VREF_CA_CPU
3 OF 22
INTEL_ADL-P-682_BGA1744
@

A A

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 9 of 108

5 4 3 2 1
 5 4 3 2 1

+VCCST_CPU

2
RC1261 1 2 1/20W_1K_5%_0201 CPU_H_THRMTRIP_N
+VCCST_CPU
RC1259
1/20W_1K_5%_0201

1
RC1260 1 2 1/16W_499_1%_0402 H_PROCHOT_N_R
H_PROCHOT_N

D D
CC1201 1 2

0.1U_6.3V_K_X5R_0201

+VCCST_CPU +VCCST_CPU +VCCST_CPU

1
RC1203 RC21
1/20W_1K_5%_0201 1/20W_100_1%_0201
@ RC57
1/20W_51_5%_0201

2
CPU_CATERR_N PROC_PRDY_N PROC_PREQ_N

?
?

UC1V BMAP_REV = ?

TC7822 PAD @ 1 CPU_CATERR_N AF15 R6 CPU_JTAG_TRST_N

CPU_PECI CATERR# PROC_JTAG_TRST# CPU_JTAG_TMS CPU_JTAG_TRST_N
DG3 U8 CPU_JTAG_TMS
CPU_PECI H_PROCHOT_N_R AK32 PECI PROC_JTAG_TMS AA6 CPU_JTAG_TDO
CPU_H_THRMTRIP_N PROCHOT# PROC_JTAG_TDO CPU_JTAG_TDI CPU_JTAG_TDO
AH32 W8
THERMTRIP# PROC_JTAG_TDI CPU_JTAG_TCK CPU_JTAG_TDI
N6
CPU_PROC_POPIRCOMP DV60 PROC_JTAG_TCK CPU_JTAG_TCK
RC1201 1 2 1/20W_49.9_1%_0201
PCH_DMI_RCOMP PROC_POPIRCOMP PCH_JTAG_JTAGX
RC1202 1 2 1/20W_49.9_1%_0201 DG1 N8
PCH_TP_OPIICCOBS DMI_RCOMP PCH_JTAGX PCH_JTAG_TMS PCH_JTAG_JTAGX
TH2988 PAD @ 1 DV11 U6
PCH_TP_OPIICCCTL TP_3 PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TMS
TH2989 PAD @ 1 DV10 AA8
TP_2 PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TDO
W6
PCH_DBG_PMODE ET14 PCH_JTAG_TDI FB6 PCH_JTAG_TCK PCH_JTAG_TDI
DBG_PMODE PCH_JTAG_TCK PCH_JTAG_TRST_N PCH_JTAG_TCK
C R8 C
PCH_TBT_FORCE_PWR_R PCH_PROC_TRST# PCH_JTAG_TRST_N
RC1246 1 @ 2 0_0201_5% EB56
PCH_TBT_FORCE_PWR GPP_B4/PROC_GP3/ISH_GP5B PROC_PREQ_N
EB57 L6 PAD 1 @ TH3041
IR_FW_FLASH_EN FB23 GPP_B3/PROC_GP2/ISH_GP4B PROC_PREQ# L8 PROC_PRDY_N PAD 1 @ TH3042
IR_FW_FLASH_EN IR_CAM_DTCT_N EY23 GPP_E7/PROC_GP1 PROC_PRDY#
IR_CAM_DTCT_N GPP_E3/PROC_GP0
AF25 CPU_EAR_N
GPP_H2 ET46 EAR#
GPP_H1 GPP_H2 GPP_F7
EL48 EN28
GPP_H0 EK48 GPP_H1 GPP_F7 ET28
GPP_H0 GPP_F9/BOOTMPC EF28 GPP_F10
GPP_F10
DY61
DW56 GPP_B15/TIME_SYNC0/ISH_GP7
PCH_BEEP GPP_B14/SPKR/TIME_SYNC1/SATA_LED#/ISH_GP6
22 OF 22
INTEL_ADL-P-682_BGA1744
@
+3VS_CAM

1/20W_10K_5%_0201 2 1 RC203 IR_CAM_DTCT_N

1/20W_100K_5%_0201 1 2 RC4157 IR_FW_FLASH_EN

+3VALW_PCH +3VALW_PCH +3VALW_PCH

Pin Straps
1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201
1

GPP_H0: Boot Strap 1

1

+3VALW_PCH +3VALW_PCH +VCCST_CPU

GPP_H1: Boot Strap 2
RC1255

RC1249

RC1251

B B
@ GPP_H2: Boot Strap 3

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
@ @ Boot Strap, Rising edge of RSMRST#

1
+3VALW_PCH
These straps has a 20 kohm ± 30% internal pull-down.
2

1
RC1254
They are bit [3:1] of a total of 4-bit encoded pin straps
2

GPP_H0 @ RC1262

RC1257
GPP_H1 for boot configuration. RC1234 1 @ 2 1/20W_1K_5%_0201 PCH_BEEP @ 1/20W_1K_5%_0201
GPP_H2 Refer to Boot Strap 0 (on GPP_C5) for the encoding.

2
Notes: 1. The internal pull-down is disabled after EAR

2
1/20W_20K_5%_0201

1/20W_20K_5%_0201
1

RSMRST# de-asserts. GPP_B14: Stall CPU reset sequence

1/20W_20K_5%_0201

2. This signal is in the primary well. Rising edge of PCH_PWROK GPP_F7 GPP_F10 CPU_EAR_N
RC1256

RC1250

RC1252

until de-asserted:
@ @ * 0000 = Master Attached Flash Configuration (BIOS / CSME on SPI). eSPI is enabled The strap has a 20 kohm ± 30% internal pull-down. - 1 = (Default) Normal
@ 0010 = Master Attached Flash Configuration (BIOS / CSME on SPI). eSPI is disabled 0 = Disable Top Swap mode. (Default) Operation; No stall.

1/20W_20K_5%_0201

1/20W_20K_5%_0201
1

1
0100 = BIOS on eSPI Peripheral Channel; CSME on master attached SPI 1 = Enable Top Swap mode. This inverts an address on access to SPI - 0 = Stall
2

RC1263

RC1253

RC1258
1000 = Slave Attached Flash Configuration (BIOS / CSME on eSPI attached device). and firmware hub, so the processor believes it fetches the alternate @ @ @ 1/20W_1K_5%_0201
1100 = BIOS on eSPI peripheral Channel; CSME on slave attached SPI. boot block instead of the original boot-block. PCH will invert A16
(default) for cycles going to the upper two 64-KB blocks in the FWH

2
or the appropriate address lines (A16, A17, or A18) as selected
in Top Swap Block size soft strap.
Notes:
1. The internal pull-down is disabled after PCH_PWROK is high.
2. Software will not be able to clear the Top Swap bit until the system
is rebooted.
+VCC1P05_OUT_FET
3. The status of this strap is readable using the Top Swap bit
(Bus0, Device31, Function0, offset DCh, bit4).
4. This signal is in the primary well. GPP_F7 and GPP_F10:
Reserved, Rising edge of RSMRST#
RC4214 1 @ 2 1/20W_1K_1%_0201 PCH_DBG_PMODE RC1204 1 @ 2 1/20W_1K_1%_0201 This strap has a 20 kohm ± 30% internal pull-down.
This strap should sample LOW. There should NOT be any onboard
DBG_PMODE: device driving it to opposite direction during strap sampling.
Reserved Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts.
Rising edge of RSMRST# 2. This signal is in the primary well.
This strap has a 20 kohm ± 30% internal pull-up.
This strap should sample high. There should NOT be any on-board device
driving it to opposite direction during strap sampling.
Notes:1. The internal pull-up is disabled after RSMRST# deasserts.
A 2. This signal is in the primary well. A

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 10 of 108
5 4 3 2 1
 5 4 3 2 1

?
?

UC1E BMAP_REV = ?

PCH_SPI0_CLK RC4207 1 @ 2 0_0201_5% PCH_SPI0_CLK_R EG56 EL38 PCH_SMB_CLK

PCH_SPI0_CLK PCH_SPI0_IO3 1 2 PCH_SPI0_IO3_R EC59 SPI0_CLK GPP_C0/SMBCLK EK38 PCH_SMB_DATA
RC4208 @ 0_0201_5%
PCH_SPI0_IO3 PCH_SPI0_IO2 PCH_SPI0_IO2_R SPI0_IO3 GPP_C1/SMBDATA PCH_SMB_ALERT_N
PCH_SPI0_IO2
PCH_SPI0_SO
PCH_SPI0_SI

PCH_SPI0_CS0_N
PCH_SPI0_SO
PCH_SPI0_SI

PCH_SPI0_CS0_N
RC4209
RC4210
RC4211

RC4212 1
1
1
1
@
@
@

@
2
2
2
0_0201_5%
0_0201_5%
0_0201_5%

2 0_0201_5%
PCH_SPI0_MISO_R
PCH_SPI0_MOSI_R
EC61
EF59
EF57
EG58
PCH_SPI0_CS0_N_R EF61
SPI0_IO2
SPI0_MISO
SPI0_MOSI
SPI0_CS1#
SPI0_CS0#
GPP_C2/SMBALERT#

GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
EN38

EE38
EF38
EH38
SML0CLK
SML0DATA
PCH_SML0_ALERT_N
Pin Straps
PCH_SPI0_CS2_N RC4243 1 @ 2 0_0201_5% PCH_SPI0_CS2_N_R EF56
PCH_SPI0_CS2_N SPI0_CS2#
ET38 SML1CLK
FC28 GPP_C6/SML1CLK ER38 SML1DATA
PCH_F1_LED_N GPP_E11/THC0_SPI1_CLK/GSPI0_CLK GPP_C7/SML1DATA PCH_SML1_ALERT_N
F1_LED_N RC4199 1 @ 2 0_0201_5% EF23 EF41 +3VALW_PCH
PCH_ECLPM_BREAK EE23 GPP_E2/THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT#
PCH_ECLPM_BREAK FPR_DET_N GPP_E1/THC0_SPI1_IO2 PCH_ESPI_CLK_R
RC4262 1 @ 2 0_0201_5% EL23 DT49 RC79 2 1 1/20W_49.9_1%_0201
FPR_DET_N GPP_E12/THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO GPP_A9/ESPI_CLK PCH_ESPI_IO3_R PCH_ESPI_CLK
EN23 DP52 RC80 1 2 1/20W_15_5%_0201 RC1727 1 2 1/20W_2.2K_5%_0201 PCH_SMB_ALERT_N RC1708 1 @ 2 1/20W_2.2K_5%_0201
EC_WAKE_N 2 1/20W_0_5%_0201 EC_WAKE_N_R GPP_E13/THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI GPP_A3/ESPI_IO3/SUSACK# PCH_ESPI_IO2_R PCH_ESPI_IO3
EC_WAKE_N RC4179 1 @ FA28 DT54 RC82 1 2 1/20W_15_5%_0201
PCH_WLAN_WAKE_N EY25 GPP_E10/THC0_SPI1_CS#/GSPI0_CS0# GPP_A2/ESPI_IO2/SUSWARN#/SUSPWRDNACK PCH_ESPI_IO1_R PCH_ESPI_IO2
DT44 RC83 1 2 1/20W_15_5%_0201 RC1705 1 @ 2 1/20W_2.2K_5%_0201 PCH_SML0_ALERT_N RC1720 1 @ 2 1/20W_2.2K_5%_0201
PCH_WLAN_WAKE_N GPP_E6 EH23 GPP_E17/THC0_SPI1_INT# GPP_A1/ESPI_IO1 DP51 PCH_ESPI_IO0_R 1 2 PCH_ESPI_IO1
RC85 1/20W_15_5%_0201
GPP_E6/THC0_SPI1_RST# GPP_A0/ESPI_IO0
DP44 PCH_ESPI_CS_N_R 1 2 PCH_ESPI_IO0 2 1/20W_2.2K_5%_0201 PCH_SML1_ALERT_N RC1709 1
RC3276 1/20W_15_5%_0201 RC1711 1 @ 2 1/20W_2.2K_5%_0201
D BOARD_ID2 GPP_A4/ESPI_CS0# PCH_ESPI_CS0_N D
EN33 DT46
BOARD_ID6 EN36 GPP_F11/THC1_SPI2_CLK/GSPI1_CLK GPP_A23/ESPI_CS1# DT51 PCH_ESPI_RST_N
BOARD_ID5 GPP_F15/GSXSRESET#/THC1_SPI2_IO3 GPP_A10/ESPI_RESET# CPU_USM_EN_5V PCH_ESPI_RST_N
EL36 DP47 RC4276 1 @ 2 1/20W_0_5%_0201
BOARD_ID4 ET33 GPP_F14/GSXDIN/THC1_SPI2_IO2 GPP_A5/ESPI_ALERT0# DP54 CPU_USM_EN_3V USM_EN_5V
RC4277 1 @ 2 1/20W_0_5%_0201
BOARD_ID3 EL31 GPP_F13/GSXSLOAD/THC1_SPI2_IO1/GSPI1_MISIO/I2C1A_SDA GPP_A6/ESPI_ALERT1# USM_EN_3V
BOARD_ID7 GPP_F12/GSXDOUT/THC1_SPI2_IO0/GSPI1_MOSI/I2C1A_SCL
EL33 GPP_C2 /SMBALERT#
BOARD_ID9 ET36 GPP_F16/GSXCLK/THC1_SPI2_CS#/GSP1_CS0#
BOARD_ID8 GPP_F18/THC1_SPI2_INT# Rising edge of RSMRST#
ER33 The strap has a 20 kohm ± 30% internal pull-down. GPP_C5 /SML0ALERT#
GPP_F17/THC1_SPI2_RST#
CPU_CL_CLK 0 = Disable Intel ME Crypto Transport Layer Security Rising edge of RSMRST#
RC4237 1 @ 2 1/20W_0_5%_0201 CPU_CL_CLK_R EE26 The strap has a 20 kohm ± 30% internal pull-down.
CPU_CL_CLK CPU_CL_DATA 2 1/20W_0_5%_0201 CPU_CL_DATA_R CL_CLK (TLS) cipher suite (no confidentiality). (Default)
RC4238 1 @ EF26 This is bit 0(LSB) of a total of 4-bit encoded pin straps
CPU_CL_DATA CPU_CL_RST_N RC4239 1 @ 2 1/20W_0_5%_0201 CPU_CL_RST_N_R EH26 CL_DATA 1 = Enable Intel ME Crypto Transport Layer Security
CPU_CL_RST_N CL_RST# (TLS) cipher suite (with confidentiality). Must be for boot configuration. Used in with Boot Strap1,2,3 (GPP_H[0:2])
5 OF 22 pulled up to support Intel AMT with TLS. 0 = eSPI Enable (for EC). (Default)
Notes: 1. The internal pull-down is disabled after RSMRST# 1 = eSPI Disable (for EC).
INTEL_ADL-P-682_BGA1744 de-asserts.
@ 2. This signal is in the primary well.
+1.8VALW

GPP_B23 /SML1ALERT#
Rising edge of RSMRST#
1/20W_100K_5%_0201

Board ID for IOB This strap has a 20 kOhm ± 30% internal pull-down.
RC4270

0 = 38.4 MHz clock (direct from crystal) (default)

1

NON-FPR FPR
1 = 19.2 MHz clock (derived from 38.4 MHz crystal)
@
Notes: 1. The internal pull-down is disabled after RSMRST#
de-asserts. +3VALW_PCH
FPR_DET_N 1 0 2. When used as PCHHOT# and strap low, a 150K
2

pull-up is needed to ensure it does not override

CPU_CL_RST_N 2 1 CPU_CL_RST_N_R the internal pull-down strap sampling.
@ DC6 3. This signal is in the primary well.

1
RB521CM-30T2R_VMN2M-2
R710 1 2 FPR_DET_N RC1721
+3VALW_PCH
1/20W_100K_5%_0201 1/20W_20K_5%_0201

Glitch Free Requirements:

2
Cap or pull-down resistor is required GPP_E6
+3VALW_PCH
100K for 3.3V Signaling Mode
75K for 1.8V Signaling Mode

1
PCH_SPI0_CLK RC1704 1 2 1/20W_100K_5%_0201 1/20W_4.7K_5%_0201 1 2 RC1715 PCH_SPI0_MOSI_R RC1702
@ 1/20W_4.7K_5%_0201
+3VS 1/20W_100K_5%_0201 2 1 RC1726 PCH_SPI0_IO2_R
+3VALW_PCH RPC6 +3VS CC1701 1 2 5P_50V_B_NPO_0402

2
RPC5 1 4 1/20W_100K_5%_0201 2 1 RC1701 PCH_SPI0_IO3_R
1 4 2 3 SODIMM SE00001AG0T EMC_NS@
2 3 SPI0_MOSI (PCH_SPI0_MOSI_R ):
1 1/16W_4.7K_5%_4P2R_0404 Click pad Rising edge of RSMRST#
C 1/16W_10K_5%_4P2R_0404 QC12 C
External pull-up is required. Recommend 4.7 kohm pull up. GPP_E6:
This strap should sample HIGH. There should NOT be any onboard JTAG ODT Disable
device driving it to opposite direction during strap sampling. Rising edge of RSMRST#
PCH_SMB_CLK SMB_CLK_3VS This strap does not have an internal pull-up or pull-down.
3 2 SPI0_IO2 and SPI0_IO3:
SMB_CLK_3VS External pull-up is recommended
+1.8VALW Rising edge of RSMRST# 0=> JTAG ODT is disabled
External pull-up is required. 1=> JTAG ODT is enabled
1 L2SK3541M3T5G_SOT723-3 Recommend 100K if pulled up to 3.3V or 75K if pulled up to 1.8V.
QC14 This strap should sample HIGH. There should NOT be any onboard

2
ESPI_CS0_N Internal PU 20K
RC66 1 @ 2 1/20W_0_5%_0201 RC1707
device driving it to opposite direction during strap sampling.
@ 1/20W_10K_5%_0201
PCH_SMB_DATA 3 2 SMB_DATA_3VS
SMB_DATA_3VS

1
PCH_ESPI_CS0_N PCH_ESPI_RST_N
L2SK3541M3T5G_SOT723-3

1
RC1723 RC1728
RC67 1 @ 2 1/20W_0_5%_0201 @ 1/20W_75K_5%_0201 1/20W_75K_5%_0201

2
+3VALW_PCH
pull-up at IOB
+3VALW
@ RPC13
1 4 LAN
2

2 3
G

1/16W_2.2K_5%_4P2R_0404

SML0CLK 1 6
S

LAN_SML0_CLK
D

QC705A @ +3VALW_PCH
L2N7002KDW1T1G_SOT363-6
SB000013A00
RC4273 1 @ 2 0_0201_5% 1/20W_4.7K_5%_0201 2 1 RC1710 PCH_SPI0_CS0_N
5
G

1/20W_150K_5%_0201 2 1 RC1706 PCH_SPI0_CS2_N

SML0DATA 4 3
S

LAN_SML0_DATA
D

QC705B @ +3VALW_PCH +1.8VALW

L2N7002KDW1T1G_SOT363-6
SB000013A00
RC4174 1 2 1/20W_100K_5%_0201 PCH_ECLPM_BREAK Board ID Description Stuff R
B RC4274 1 @ 2 0_0201_5% B
000 EVT
001 FVT RC1801

1/20W_10K_5%_0201
1

2 UMA@ 1

1
1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_75K_5%_0201

1/20W_10K_5%_0201
RC4224

RC4232
Board_ID 010 SIT RC1815
@

RC1801

RC1824

RC4218

RC4219

RC4220

RC4221

RC4222

RC4223
[2,1,0]
011 SITR RC4225 @ @

2
BB RETIMER 100 SVT

TPM_NS@
MD_NS@

MD_NS@
OPT_GN20S@
+3VALW_PCH 3VALW_TBTA
3VALW_TBTA
pull-up near retimer
RPC4 0 DIS RC4226
Board_ID3
RPC3 1 4
1 4 2 3 1 UMA RC4219 BOARD_ID0
BOARD_ID0
2

2 3 BOARD_ID1
G

BOARD_ID1 BOARD_ID2
1/16W_1K_5%_4P2R_0404 1/16W_2.2K_5%_4P2R_0404 BOARD_ID3
0 GN18S RC4227 BOARD_ID4
Board_ID4
SML0CLK 6 1 PCH_SML0_CLK BOARD_ID5
S

PCH_SML0_CLK BOARD_ID6
D

1 GN20S RC4220 BOARD_ID7

@ QC706A
L2N7002KDW1T1G_SOT363-6 BOARD_ID8
SB000013A00 000 Micron RC4229 RC4228 BOARD_ID9
5
G

001 Samsung

1/20W_10K_5%_0201
1

OPT@ 1

2 EAR@ 1

2 TPM@ 1

1
RC4229 RC4221

OPT_GN18S@

1/20W_1K_5%_0201

1/20W_1K_5%_0201

1/20W_1K_5%_0201
1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201
RC1806

RC1815

RC4225

RC4226

RC4227

RC4228

RC4229

RC4230

RC4231

RC4233
PCH_SML0_DATA
Board_ID 010 SK Hynix
SML0DATA 3 4 [2,6,5] @
S

PCH_SML0_DATA
@ @ @
D

100 Micron 2 RC4222 RC4228

@ QC706B

2
L2N7002KDW1T1G_SOT363-6 X11 no mem down
SB000013A00 RC4222 RC4221

0 Earphone RC4230 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9
SML0CLK RC1717 1 @ 2 1/20W_0_5%_0201 PCH_SML0_CLK Board_ID7 No
1 Earphone
SML0DATA RC1733 1 @ 2 1/20W_0_5%_0201 PCH_SML0_DATA

0 TPM RC4231
Board_ID8
PD CONTROLLER 1 NO TPM RC4224

RPC1 +3VALW_PCH VCC3_LDO_PD RPC2

1 4 1 4
A
+3VALW_PCH
2 3 2 3
VCC3_LDO_PD
Board_ID9 Reserved A

1/16W_2.2K_5%_4P2R_0404
UC3 1/16W_2.2K_5%_4P2R_0404
1 8
VCCA VCCB
SML1CLK 2 7 PCH_SML1_CLK
A0 B0 PCH_SML1_CLK
SML1DATA 3 6 PCH_SML1_DATA
A1 B1 PCH_SML1_DATA
4 5 RC1703 1 2 1/20W_10K_5%_0201
GND OE +3VALW_PCH

FXMA2102UMX_U-MLP8_1P2X1P4

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
2 1/20W_0_5%_0201 PCH_SML1_CLK
Issued Date 2012/07/01 Deciphered Date 2014/07/01
SML1CLK RC1729 1 @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
SML1DATA RC1713 1 @ 2 1/20W_0_5%_0201 PCH_SML1_DATA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Friday, March 11, 2022 Sheet 11 of 108
5 4 3 2 1
 5 4 3 2 1

?
?

UC1F BMAP_REV = ?
D D
DEBUG_UART0_TXD EN48 EY28 GPU_EVENT_N
DEBUG_UART0_RXD GPP_H11/UART0_TXD/M2_SKT2_CFG1 GPP_D14/ISH_UART0_TXD/I2C4B_SCL GPU_EVENT_N
EN46 EV28
CAPSLK_LED_N PCH_CAPS_LED_N GPP_H10/UART0_RXD/M2_SKT2_CFG0 GPP_D13/ISH_UART0_RXD/I2C4B_SDA PANEL_SIZE_CTL
RC1812 1 @ 2 0_0201_5% EL41 EY36
CAPSLK_LED_N F4_LED_N PCH_F4_LED_N GPP_H13/I2C7_SCL/UART0_CTS#/M2_SKT2_CFG3/ISH_GP7B/DEVSLP1B GPP_D16/ISH_UART0_CTS#/I2C7B_SCL TPM_IRQ_N PANEL_SIZE_CTL
F4_LED_N RC4198 1 @ 2 0_0201_5% EK41 EW36
GPP_H12/I2C7_SDA/UART0_RTS#/M2_SKT2_CFG2/ISH_GP6B/DEVSLP0B GPP_D15/ISH_UART0_RTS#/I2C7B_SDA TPM_IRQ_N
FP_PWRON_N RC4290 1 @ 2 1/20W_0_5%_0201 FP_PWRON_N_R EW30 FA34 TOUCH_EN
FP_PWRON_N TOUCH_PWRON GPP_D18/UART1_TXD/ISH_UART1_TXD GPP_D3/ISH_GP3/BK3/SBK3 TOUCH_INT_N TOUCH_EN
TOUCH_PWRON EV34 EY30
GPP_D17/UART1_RXD/ISH_UART1_RXD GPP_D2/ISH_GP2/BK2/SBK2 EY31 TOUCH_RST_N TOUCH_INT_N
LAN_DET_N GPP_D1/ISH_GP1/BK1/SBK1 TOUCH_RST_N
LAN_DET_N EH46 EV31 PXS_RST_N_R RC805 1 @ 2 0_0201_5% PXS_RST_N
GPP_H5/I2C0_SCL GPP_D0/ISH_GP0/BK0/SBK0 PXS_RST_N
EF46
GPP_H4/I2C0_SDA DR61 GPPC_RCOMP RC1804 1 2 1/20W_200_1%_0201
FN_LED_N PCH_FN_LED_N GPPC_RCOMP
FN_LED_N RC4263 1 @ 2 0_0201_5% EH43
NUMLOCK_LED_N PCH_NUMLOCK_LED_N EF43 GPP_H7/I2C1_SCL
NUMLOCK_LED_N RC4264 1 @ 2 0_0201_5%
GPP_H6/I2C1_SDA
PCH_I2C2_SCL DT57
PCH_I2C2_SCL PCH_I2C2_SDA DT56 GPP_B6/ISH_I2C0_SCL/I2C2_SCL
TOUCH PANEL PCH_I2C2_SDA GPP_B5/ISH_I2C0_SDA/I2C2_SDA
FB_GC6_EN_R DR56
FB_GC6_EN_R PXS_PWREN PXS_PWREN_R GPP_B8/ISH_I2C1_SCL/I2C3_SCL
RC804 1 @ 2 0_0201_5% DR58
PXS_PWREN GPP_B7/ISH_I2C1_SDA/I2C3_SDA
VGA_PWRGD EN43
VGA_PWRGD PCH_VGA_ALERT_N GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
EL43
PCH_VGA_ALERT_N GPP_H8/I2C4_SDA/CNV_MFUART2_RXD

teknisi-indonesia.com
DN60
NVVDD_PWROK DN57 GPP_B17/I2C5_SCL/ISH_I2C2_SCL
NVVDD_PWROK GPP_B16/I2C5_SDA/ISH_I2C2_SDA
6 OF 22
INTEL_ADL-P-682_BGA1744
@

+3VS_TOUCH

RG54 2 1 1/20W_10K_5%_0201 TOUCH_INT_N

C C
+3VS
+3VS
GPU_EVENT_N RC813 1 OPT@ 2 1/20W_10K_5%_0201
PXS_PWREN_R RC807 1 OPT@ 2 1/20W_10K_5%_0201
RC817 1 @ 2 1/20W_10K_5%_0201 +3VALW_PCH
RC808 1 @ 2 1/20W_10K_5%_0201

RC4240 1DEBUG@ 2 1/20W_2.2K_5%_0201 DEBUG_UART0_RXD TP6307 1 @

OPT@
PXS_RST_N CC1410 1 2 0.01U_10V_K_X7R_0201 RC4241 1DEBUG@ 2 1/20W_2.2K_5%_0201 DEBUG_UART0_TXD TP6308 1 @

RC4302 1 TPM@ 2 1/20W_10K_5%_0201 TPM_IRQ_N

NVVDD_PWROK RC820 1 UMA@ 2 1/20W_10K_5%_0201

FB_GC6_EN_R RC812 1 @ 2 1/20W_10K_5%_0201 FP_PWRON_N RC4158 1 @ 2 1/20W_10K_5%_0201

Board ID for IOB

without LAN with LAN

B B
LAN_DET_N 1 0

R711 1 2 LAN_DET_N
+3VALW_PCH
1/20W_100K_5%_0201

A A

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 12 of 108
5 4 3 2 1
 5 4 3 2 1

?
?
UC1G BMAP_REV = ?
D PCH_HDA_BCLK PCH_HDA_BCLK_R CPU_WLAN_PERST_N D
RC1833 1 2 1/20W_33_5%_0201 ER56 EY34
CPU_WLAN_PERST_N
PCH_HDA_BCLK PCH_HDA_SYNC PCH_HDA_SYNC_R GPP_R0/HDA_BCLK/I2S0_SCLK/DMIC_CLK_B0/HDAPROC_BCLK GPP_D19/I2S_MCLK1_OUT
RC1814 1 2 1/20W_33_5%_0201 EP60
PCH_HDA_SYNC PCH_HDA_SDO PCH_HDA_SDO_R GPP_R1/HDA_SYNC/I2S0_SFRM/DMIC_CLK_B1
RC1828 1 2 1/20W_33_5%_0201 ER57 EV53
PCH_HDA_SDO PCH_HDA_SDIN0 ER59 GPP_R2/HDA_SDO/I2S0_TXD/HDAPROC_SDO GPP_S0/SNDW0_CLK/I2S1_SCLK EY53
PCH_HDA_SDIN0 GPP_R3/HDA_SDI0/I2S0_RXD/HDAPROC_SDI GPP_S1/SNDW0_DATA/I2S1_SFRM
ER53 FA50 PCH_DMIC_CLK_R RC4266 1 2 1/20W_33_5%_0201
GPP_R4/HDA_RST#/I2S2_SCLK/DMIC_CLK_A0 GPP_S2/SNDW1_CLK/DMIC_CKL_A0/I2S1_TXD PCH_DMIC_DATA PCH_DMIC_CLK
ET53 FC50 DMIC
BOARD_ID0 GPP_R5/HDA_SDI1/I2S2_SFRM/DMIC_DATA0 GPP_S3/SNDW1_DATA/DMIC_DATA0/I2S1_RXD PCH_DMIC_DATA
EB44
BOARD_ID0 BOARD_ID1 EB46 GPP_R6/I2S2_TXD/DMIC_CLK_A1 EV50
BOARD_ID1 GPP_R7/I2S2_RXD/DMIC_DATA1 GPP_S4/SNDW2_CLK/DMIC_CLK_B0 CNVI_EN_N
EY50 CNVI_EN_N
DV51 GPP_S5/SNDW2_DATA/DMIC_CLK_B1
PCH_BT_OFF_N_R DV47 GPP_A11/PMC_I2C_SDA EW48
GPP_A13/PMC_I2C_SCL GPP_S6/SNDW3_CLK/DMIC_CLK_A1 EY48
SNDW_RCOMP GPP_S7/SNDW3_DATA/DMIC_DATA1
RC1820 1 2 1/20W_200_1%_0201 FA53
SNDW_RCOMP_1
FC53
SNDW_RCOMP_2
7 OF 22
INTEL_ADL-P-682_BGA1744
@

+3VALW
+1.8VALW

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1
Pin Straps @
RC4245
1/20W_100K_5%_0201

2
1 1

CC3670

CC3671
2
C C
+1.8VALW PCH_BT_OFF_N 1 3 PCH_BT_OFF_N_R
PCH_BT_OFF_N 2 2
RC1822 1 2 1/20W_1K_5%_0201
QC5 @
RC1821 1 @ 2 0_0201_5% PCH_HDA_SDO_R LSI1012XT1G_SC-89-3
ME_FLASH
RC4256 1 @ 2 0_0201_5%
GPP_R2/HDA_SDO (PCH_HDA_SDO_R)
The strap has a 20 kohm ± 30% internal pull-down.
0 = Enable security measures defined in the Flash Descriptor. (Default)
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external pull-
add split cap for DMIC at 6/29
Signal:CPU_BT_OFF_M_N
up in manufacturing/debug environments ONLY. Voltage Level:1.8V
LSI1012XT1G_SC-89-3
Vds max=20V
Vgs max=+/- 6V
Vgs(th)=0.45V/0.9V(min/max)
Rds(ON)=1.25ohm(max,Vgs=1.8 V)
Id=350mA(TA =25 C )
PCH_HDA_BCLK PCH_DMIC_CLK Ton Delay=5ns
Rise time=5ns
PCH_HDA_SYNC PCH_DMIC_DATA

100P_50V_K_X7R_0201

100P_50V_K_X7R_0201
22P_25V_J_NPO_0201_MURATA

22P_25V_J_NPO_0201_MURATA

EMC@ 1 EMC@ 1 EMC_NS@1 EMC_NS@1

CC902 CC901 CC3667 CC3668

2 2 2 2

B B

A A

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Saturday, March 12, 2022 Sheet 13 of 108
5 4 3 2 1
 5 4 3 2 1

?
?

UC1I BMAP_REV = ?

PCIE3_SSD_TX12_P DY10 EM5 USB20_10_P

PCIE3_SSD_TX12_P PCIE3_SSD_TX12_N DY11 PCIE12_TXP/SATA1_TXP USB2P_10 EM6 USB20_10_N USB20_10_P
PCIE3_SSD_TX12_N PCIE3_SSD_RX12_P EA4 PCIE12_TXN/SATA1_TXN USB2N_10 USB20_10_N BT WLAN
PCIE3_SSD_RX12_P PCIE3_SSD_RX12_N EA6 PCIE12_RXP/SATA1_RXP EL18 USB20_9_P
PCIE3_SSD_RX12_N PCIE12_RXN/SATA1RXN USB2P_9 USB20_9_N USB20_9_P
EN18
PCIE3_SSD_TX11_P EB10 USB2N_9 USB20_9_N AOU USB
PCIE3_SSD_TX11_P PCIE3_SSD_TX11_N EB11 PCIE11_TXP/SATA0_TXP EN1
PCIE3_SSD_TX11_N PCIE3_SSD_RX11_P PCIE11_TXN/SATA0_TXN USB2P_8
EC5 EN3
PCIE GEN3 SSD PCIE3_SSD_RX11_P
PCIE3_SSD_RX11_N
PCIE3_SSD_RX11_N EC6 PCIE11_RXP/SATA0_RXP
PCIE11_RXN/SATA0_RXN
USB2N_8
ER16 USB20_7_P
D PCIE3_SSD_TX10_P USB2P_7 USB20_7_N USB20_7_P D
ED10 ET16
PCIE3_SSD_TX10_P PCIE3_SSD_TX10_N ED11 PCIE10_TXP/UFS11_TXP USB2N_7 USB20_7_N CAMERA
PCIE3_SSD_TX10_N PCIE3_SSD_RX10_P PCIE10_TXN/UFS11_TXN USB20_6_P
EC1 EP4
PCIE3_SSD_RX10_P PCIE3_SSD_RX10_N EC3 PCIE10_RXP/UFS11_RXP USB2P_6 EP6 USB20_6_N USB20_6_P
PCIE3_SSD_RX10_N PCIE10_RXN/UFS11_RXN USB2N_6 USB20_6_N Finger Printer
PCIE3_SSD_TX9_P EF10 FA15
PCIE3_SSD_TX9_P PCIE3_SSD_TX9_N EF11 PCIE9_TXP/UFS10_TXP USB2P_5 FC15
PCIE3_SSD_TX9_N PCIE3_SSD_RX9_P PCIE9_TXN/UFS10_TXN USB2N_5
EF5
PCIE3_SSD_RX9_P PCIE3_SSD_RX9_N EF6 PCIE9_RXP/UFS10_RXP ER5
PCIE3_SSD_RX9_N PCIE9_RXN/UFS10_RXN USB2P_4
ER6
PCIE3_LAN_C_RX3_P PCIE3_LAN_RX3_P USB2N_4
PCIE3_LAN_C_RX3_P CC10 1 2 0.1U_10V_K_X5R_0201 EH10
PCIE3_LAN_C_RX3_N PCIE3_LAN_RX3_N PCIE8_TXP USB20_3_P
PCIE3_LAN_C_RX3_N CC11 1 2 0.1U_10V_K_X5R_0201 EH11 ER18 USB20_3_P
PCIE3_LAN_TX3_P EF1 PCIE8_TXN USB2P_3 ET18 USB20_3_N
LAN PCIE3_LAN_TX3_P
PCIE3_LAN_TX3_N
PCIE3_LAN_TX3_N EF3 PCIE8_RXP USB2N_3 USB20_3_N IOB USB
PCIE8_RXN USB20_2_P
EH16 USB20_2_P
EL10 USB2P_2 EK16 USB20_2_N
EL11 PCIE7_TXP USB2N_2 USB20_2_N EARPHONE
PCIE7_TXN USB20_1_P
EG4 EL16
EG6 PCIE7_RXP USB2P_1 EN16 USB20_1_N USB20_1_P
PCIE7_RXN USB2N_1 USB20_1_N TBT4 TYPE-C
PCIE3_WLAN_TX6_P EN10 FC25 USB_OC0_N
PCIE3_WLAN_TX6_P PCIE3_WLAN_TX6_N EN11 PCIE6_TXP GPP_E9/USB_OC0#/ISH_GP4 DY51 USB_OC2_N USB_OC0_N
PCIE3_WLAN_TX6_N PCIE3_WLAN_RX6_P PCIE6_TXN GPP_A16/USB_OC3#/ISH_GP5 USB_OC2_N
EJ5
WLAN PCIE3_WLAN_RX6_P
PCIE3_WLAN_RX6_N
PCIE3_WLAN_RX6_N EJ6 PCIE6_RXP
PCIE6_RXN GPP_E5/DEVSLP1/SRCCLK_OE6#
FA25 PCH_SATA_1_DEVSLP RC4204 1 @ 2 1/20W_0_5%_0201
SATA_1_DEVSLP
FC22
ER10 GPP_E4/DEVSLP0/SRCCLK_OE9#
ER11 PCIE5_TXP DY1 MPHY_RCOMPP RC1601 1 2 1/20W_100_1%_0201
PCIE5_TXN MPHY_RCOMPP MPHY_RCOMPN
EJ1 DY3
EJ3 PCIE5_RXP MPHY_RCOMPN
PCIE5_RXN EF18 USB2_VBUSSENSE RC1604 1 2 1/20W_10K_5%_0201
FB10 USB_VBUSSENSE EF16 USB2_ID RC1603 1 2 1/20W_10K_5%_0201
FA9 PCIE4_TXP/USB32_4_TXP USB_ID FB20 USB2_COMP RC1602 1 2 1/16W_113_1%_0402
EV16 PCIE4_TXN/USB32_4_TXN USB2_COMP
EY16 PCIE4_RXP/USB32_4_RXP DL8
PCIE4_RXN/USB32_4_RXN UFS_RESET#
EW11
EY11 PCIE3_TXP/USB32_3_TXP
PCIE3_TXN/USB32_3_TXN
C EW17 C
EY17 PCIE3_RXP/USB32_3_RXP
PCIE3_RXN/USB32_3_RXN +3VALW_PCH
FA12
FC12 PCIE2_TXP/USB32_2_TXP
PCIE2_TXN/USB32_2_TXN
FA18
FC18 PCIE2_RXP/USB32_2_RXP USB_OC0_N
RC4234 1 2 1/20W_10K_5%_0201
PCIE2_RXN/USB32_2_RXN USB_OC2_N
RC4235 1 2 1/20W_10K_5%_0201
USB32_TX1_P EV12 RC4236 1 @ 2 1/20W_10K_5%_0201 PCH_SATA_1_DEVSLP
USB32_TX1_P USB32_TX1_N EY12 PCIE1_TXP/USB32_1_TXP
USB32_TX1_N USB32_RX1_P PCIE1_TXN/USB32_1_TXN
EV19
USB3.0 AOU USB32_RX1_P USB32_RX1_N EY19 PCIE1_RXP/USB32_1_RXP
PCIE1_RXN/USB32_1_RXN
USB32_RX1_N
9 OF 22
INTEL_ADL-P-682_BGA1744
@

?
?

UC1H BMAP_REV = ?

PCIE4_SSD_TXA3_P A20 C33

PCIE4_SSD_TXA3_P PCIE4_SSD_TXA3_N PCIEX4_A_TX_P_3 PCIEX8_TX_P_7
C20 D33
PCIE4_SSD_TXA3_N PCIE4_SSD_RXA3_P M22 PCIEX4_A_TX_N_3 PCIEX8_TX_N_7 J33
PCIE4_SSD_RXA3_P PCIE4_SSD_RXA3_N PCIEX4_A_RX_P_3 PCIEX8_TX_P_6
M24 G33
PCIE4_SSD_RXA3_N PCIEX4_A_RX_N_3 PCIEX8_TX_N_6 C30
PCIE4_SSD_TXA2_P G20 PCIEX8_TX_P_5 D30
PCIE4_SSD_TXA2_P PCIE4_SSD_TXA2_N PCIEX4_A_TX_P_2 PCIEX8_TX_N_5
F20 J30
PCIE4_SSD_TXA2_N PCIE4_SSD_RXA2_P V22 PCIEX4_A_TX_N_2 PCIEX8_TX_P_4 G30
PCIE4_SSD_RXA2_P PCIE4_SSD_RXA2_N PCIEX4_A_RX_P_2 PCIEX8_TX_N_4
U22 C26
PCIE GEN4 SSD PCIE4_SSD_RXA2_N
PCIE4_SSD_TXA1_P A17
PCIEX4_A_RX_N_2 PCIEX8_TX_P_3
PCIEX8_TX_N_3
D26
J26
PCIE4_SSD_TXA1_P PCIE4_SSD_TXA1_N PCIEX4_A_TX_P_1 PCIEX8_TX_P_2
C17 G26
PCIE4_SSD_TXA1_N PCIE4_SSD_RXA1_P AC22 PCIEX4_A_TX_N_1 PCIEX8_TX_N_2 C23
PCIE4_SSD_RXA1_P PCIE4_SSD_RXA1_N PCIEX4_A_RX_P_1 PCIEX8_TX_P_1
AA22 D23
B PCIE4_SSD_RXA1_N PCIEX4_A_RX_N_1 PCIEX8_TX_N_1 B
J23
PCIE4_SSD_TXA0_P G17 PCIEX8_TX_P_0 G23
PCIE4_SSD_TXA0_P PCIE4_SSD_TXA0_N PCIEX4_A_TX_P_0 PCIEX8_TX_N_0
F17
PCIE4_SSD_TXA0_N PCIE4_SSD_RXA0_P M18 PCIEX4_A_TX_N_0 M39
PCIE4_SSD_RXA0_P PCIE4_SSD_RXA0_N PCIEX4_A_RX_P_0 PCIEX8_RX_P_7
M19 M37
PCIE4_SSD_RXA0_N PCIEX4_A_RX_N_0 PCIEX8_RX_N_7 U37
PCIEX4_A_B_RCOMP_N F6 PCIEX8_RX_P_6 V37
2 1 PCIEX4_A_RCOMP_P A6 PCIEX4_RCOMP_N PCIEX8_RX_N_6 AA37
SD00003A60T RC703
C6 PCIEX4_A_RCOMP_P_1 PCIEX8_RX_P_5 AC37
1/16W_2.2K_0.1%_0402_THIN_50PPM
PCIEX4_B_RCOMP_P PCIEX4_A_RCOMP_P_2 PCIEX8_RX_N_5
RC702 2 1 A5 U32
D6 PCIEX4_B_RCOMP_P_1 PCIEX8_RX_P_4 V32
1/16W_2.2K_0.1%_0402_THIN_50PPM
PCIEX4_B_RCOMP_P_2 PCIEX8_RX_N_4 AA32
PEG_GPU_C_RXB3_P PEG_GPU_RXB3_P PCIEX8_RX_P_3
OPT@ CC3663 1 2 0.22U_6.3V_K_X5R_0201 A14 AC32
PEG_GPU_C_RXB3_P PEG_GPU_C_RXB3_N PEG_GPU_RXB3_N PCIEX4_B_TXP_3 PCIEX8_RX_N_3
OPT@ CC3664 1 2 0.22U_6.3V_K_X5R_0201 C14 M29
PEG_GPU_C_RXB3_N PEG_GPU_TXB3_P PCIEX4_B_TXN_3 PCIEX8_RX_P_2
V17 M27
PEG_GPU_TXB3_P PEG_GPU_TXB3_N PCIEX4_B_RXP_3 PCIEX8_RX_N_2
U17 U27
PEG_GPU_TXB3_N PCIEX4_B_RXN_3 PCIEX8_RX_P_1 V27
PEG_GPU_C_RXB2_P PEG_GPU_RXB2_P PCIEX8_RX_N_1
OPT@ CC3661 1 2 0.22U_6.3V_K_X5R_0201 G14 AA27
PEG_GPU_C_RXB2_P PEG_GPU_C_RXB2_N PEG_GPU_RXB2_N PCIEX4_B_TXP_2 PCIEX8_RX_P_0
OPT@ CC3662 1 2 0.22U_6.3V_K_X5R_0201 F14 AC27
PEG_GPU_C_RXB2_N PEG_GPU_TXB2_P PCIEX4_B_TXN_2 PCIEX8_RX_N_0
AC17
PEG_GPU_TXB2_P PEG_GPU_TXB2_N PCIEX4_B_RXP_2 PCIEX8_RCOMP_P
AA17 A8
PCIE GEN4 GPU PEG_GPU_C_RXB1_P
PEG_GPU_TXB2_N
OPT@ CC3659 1 2 0.22U_6.3V_K_X5R_0201 PEG_GPU_RXB1_P A11
PCIEX4_B_RXN_2 PCIEX8_RCOMP_P_1
PCIEX8_RCOMP_P_2
C8
D8 PCIEX8_RCOMP_N RC4267 1 2
This RCOMP should be connected even if
PEG_GPU_C_RXB1_P PCIEX4_B_TXP_1 PCIEX8_RCOMP_N the CPU PCIe interface is not used
PEG_GPU_C_RXB1_N OPT@ CC3660 1 2 0.22U_6.3V_K_X5R_0201 PEG_GPU_RXB1_N C11 1/20W_150_1%_0201
PEG_GPU_C_RXB1_N PEG_GPU_TXB1_P PCIEX4_B_TXN_1
M13
PEG_GPU_TXB1_P PEG_GPU_TXB1_N PCIEX4_B_RXP_1
M14
PEG_GPU_TXB1_N PCIEX4_B_RXN_1
PEG_GPU_C_RXB0_P OPT@ CC3657 1 2 0.22U_6.3V_K_X5R_0201 PEG_GPU_RXB0_P G11
PEG_GPU_C_RXB0_P PEG_GPU_C_RXB0_N PEG_GPU_RXB0_N PCIEX4_B_TXP_0
OPT@ CC3658 1 2 0.22U_6.3V_K_X5R_0201 F11
PEG_GPU_C_RXB0_N PEG_GPU_TXB0_P PCIEX4_B_TXN_0
V12
PEG_GPU_TXB0_P PEG_GPU_TXB0_N PCIEX4_B_RXP_0
U12
PEG_GPU_TXB0_N PCIEX4_B_RXN_0
8 OF 22
INTEL_ADL-P-682_BGA1744
@

A A

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 14 of 108
5 4 3 2 1
 5 4 3 2 1

D D

?
?

UC1J BMAP_REV = ?

AD41 FC46 CNVI_WT_D1_P CNVI_WT_D1_P

AB41 CSI_D_DP_1/CSI_C_DP_2 CNV_WT_D1P FA46 CNVI_WT_D1_N
CSI_D_DN_1/CSI_C_DN_2 CNV_WT_D1N CNVI_WT_D1_N
AG41 EV43 CNVI_WT_D0_P CNVI_WT_D0_P
CSI_D_DP_0/CSI_C_DP_3 CNV_WT_D0P
AF41 EY43 CNVI_WT_D0_N CNVI_WT_D0_N
J41 CSI_D_DN_0/CSI_C_DN_3 CNV_WT_D0N EV47 CNVI_WT_CLK_P
CSI_D_CLK_P CNV_WT_CLKP CNVI_WT_CLK_P
L41 EY47 CNVI_WT_CLK_N CNVI_WT_CLK_N
CSI_D_CLK_N CNV_WT_CLKN
P44 EV40 CNVI_WR_D1_P
CSI_C_DP_1 CNV_WR_D1P CNVI_WR_D1_P
M44 EY40 CNVI_WR_D1_N
T41 CSI_C_DN_1 CNV_WR_D1N EW42CNVI_WR_D0_P CNVI_WR_D1_N
CSI_C_DP_0 CNV_WR_D0P CNVI_WR_D0_P
P41 EY42 CNVI_WR_D0_N
CSI_C_DN_0 CNV_WR_D0N CNVI_WR_D0_N
J44 FA43 CNVI_WR_CLK_P
K44 CSI_C_CLK_P CNV_WR_CLKP FC43 CNVI_WR_CLK_N CNVI_WR_CLK_P
CSI_C_CLK_N CNV_WR_CLKN CNVI_WR_CLK_N
W41 FC40 CNV_WT_RCOMP 1/20W_150_1%_0201 1 2 RC2103
AA41 CSI_B_DP_1 CNV_WT_RCOMP
C38 CSI_B_DN_1 EK33 CNVI_BRI_RSP follow CRB & PDG EMPTY
CSI_B_DP_0 GPP_F1/CNV_BRI_RSP/UART2_RXD CNVI_BRI_RSP
A38 EH33 CNVI_BRI_DT_R RC2107 1 @ 2 0_0201_5% internal pull-up, no need external
CSI_B_DN_0 GPP_F0/CNV_BRI_DT/UART2_RTS# CNVI_BRI_DT need check CNVIo schme check list
G39 ER31 CNVI_RGI_RSP CNVI_RGI_RSP
F39 CSI_B_CLK_P GPP_F3/CNV_RGI_RSP/UART2_CTS# EN31 CNVI_RGI_DT_R RC2105 1 @ 2 0_0201_5%
CNVI_RGI_DT
CSI_B_CLK_N GPP_F2/CNV_RGI_DT/UART2_TXD
C36 EF36 CNVI_MODEM_CLKREQ
A36 CSI_A_DP_1/CSI_B_DP_2 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ EH36 CNVI_MODEM_CLKREQ
CSI_A_DN_1/CSI_B_DN_2 GPP_F6/CNV_PA_BLANKING
C G37 ET31 CNVI_RF_RESET_N C
E37 CSI_A_DP_0/CSI_B_DP_3 GPP_F4/CNV_RF_RESET# CNVI_RF_RESET_N
F36 CSI_A_DN_0/CSI_B_DN_3
G36 CSI_A_CLK_P
CSI_A_CLK_N
1/20W_150_1%_0201 2 1 RC2106 CSI_RCOMP A55
B54 CSI_RCOMP_1
CSI_RCOMP_2
ET41
ER41 GPP_H22/IMGCLKOUT3
GPP_H21/IMGCLKOUT2
EN41
UART_WLAN_WAKE_PCH FA31 GPP_H20/IMGCLKOUT1
UART_WLAN_WAKE_PCH GPP_D4/IMGCLKOUT0/BK4/SBK4
10 OF 22
INTEL_ADL-P-682_BGA1744
@

+1.8VALW
Pin Straps +1.8VALW

RC2108 1 @ 2 1/20W_20K_5%_0201 CNVI_BRI_RSP

RC2104 1 @ 2 1/20W_20K_5%_0201 CNVI_RGI_RSP

RC4254 1 @ 2 1/20W_1K_5%_0201 CNVI_BRI_DT_R RC4252 1 @ 2 1/20W_20K_5%_0201

RC2102 1 2 1/20W_75K_5%_0201 CNVI_RF_RESET_N

RC2101 1 @ 2 1/20W_75K_5%_0201 CNVI_MODEM_CLKREQ

B B

GPP_F0 /CNV_BRI_DT /UART2_RTS#(CNV_BRI_DT_R)

XTAL Frequency Selection, Rising edge of RSMRST#
This strap has a 20 kohm ± 30% internal pull-down.
This strap should not be pulled high since 24 MHz crystal is not
supported on the PCH.
0 = 38.4 MHz (default)
1 = 24 MHz
Notes:
1. The internal pull-down is disabled after RSMRST# de-asserts.
2. This signal is in the primary well.

GPP_F2 /CNV_RGI_DT /UART2_TXD(CNV_RGI_DT_R):

M.2 CNVI MODES, Rising edge of RSMRST#
This strap does not have an internal pull-up or pull-down.
A weak external pull-up is required.
0 = Integrated CNVi enabled.
1 = Integrated CNVi disabled.
Note: When a RF companion chip is connected to the
PCH CNVi interface, the device internal pulldown
resistor will pull the strap low to enable CNVi interface.

A A

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 15 of 108
5 4 3 2 1
 5 4 3 2 1

All processor based platforms are required to provide a 38.4MHz input to

the PCH to enable the PCH to generate all of its internal reference clocks
and all of the single-ended and differential platform clock outputs

XTAL_PCH_38P4M_IN RC3290 1 @ 2 0_0402_5% XTAL_PCH_38P4M_IN_R +3VS

PCH_RTCX1
D D
EXC24CH500U_4P
4 3 RC1902 1 2 1/16W_10M_5%_0402 PCH_RTCX2
4 3

1 2 YC1 RC4202 1 OPT@ 2 1/20W_10K_5%_0201 GPU_CLKREQ_N

1 2
1 2
LC901 EMC_NS@
1 32.768KHZ_9PF_9H03200062 1
XTAL_PCH_38P4M_OUT RC3291 1 @ 2 0_0402_5% XTAL_PCH_38P4M_OUT_R
CC1901 CC1902 RC1907 1 2 1/20W_10K_5%_0201 GPU_CLKREQ_N
12P_50V_J_NPO_0402 15P_50V_J_NPO_0402 OPT_NS@
2 2

XTAL_PCH_38P4M_IN_R RC1022 1 2 1/16W_200K_1%_0402XTAL_PCH_38P4M_OUT_R

YC3

4 3 +3VALW_PCH
NC1 OSC2
1 2
OSC1 NC2 LAN_CLKREQ_N
C
RC3323 1 2 1/20W_10K_5%_0201
C
1 1
CC706 CC707
10P_50V_J_NPO_0402 38.4MHZ_10PF_7R38400001 10P_50V_J_NPO_0402
+3VALW
2 2

RC4313 1 @ 2 1/20W_10K_5%_0201 LAN_CLKREQ_N

?
?
CLKOUT_PCIE_P/N[4,3,0] add at 2/23
UC1K BMAP_REV = ?
must be used for PCIE GEN4 support
DP1 DY46
CLKOUT_PCIE_P6 GPP_A12/SATAXPCIE1/SATAGP1/SRCCLKREQ9B# SSD_SATA_PCIE_DET1_N
DP3 EV22
CLKOUT_PCIE_N6 GPP_E0/SATAXPCIE0/SATAGP0/SRCCLKREQ9# EY22 SSD_SATA_PCIE_DET1_N
CLK_PCIE5_LAN_P GPP_E16/RSVD_TP/SRCCLKREQ8#
CLK_PCIE5_LAN_P DU5 EB54
CLK_PCIE5_LAN_N CLKOUT_PCIE_P5 GPP_A8/SRCCLKREQ7#
LAN CLK_PCIE5_LAN_N DU6 EF31
CLKOUT_PCIE_N5 GPP_F19/SRCCLKREQ6# ET43 LAN_CLKREQ_N
GPP_H23/SRCCLKREQ5# LAN_CLKREQ_N
DP5 ER48
DP6 CLKOUT_PCIE_P4 GPP_H19/SRCCLKREQ4# FC34 GPU_CLKREQ_N
CLKOUT_PCIE_N4/UFS_REF_CLK GPP_D8/SRCCLKREQ3#
FC31 WLAN_CLKREQ_N GPU_CLKREQ_N
B WLAN_CLKREQ_N B
CLK_PCIE3_GPU_P GPP_D7/SRCCLKREQ2# SSD1_CLKREQ_N
DN10 FB36
CLK_PCIE3_GPU_P CLK_PCIE3_GPU_N DN11 CLKOUT_PCIE_P3 GPP_D6/SRCCLKREQ1# FB29 SSD2_CLKREQ_N SSD1_CLKREQ_N
GPU CLK_PCIE3_GPU_N CLKOUT_PCIE_N3 GPP_D5/SRCCLKREQ0# SSD2_CLKREQ_N
CLK_PCIE2_WLAN_P DR4 EV6 XTAL_PCH_38P4M_OUT
CLK_PCIE2_WLAN_P CLK_PCIE2_WLAN_N DR6 CLKOUT_PCIE_P2 XTAL_OUT
EV8 XTAL_PCH_38P4M_IN
WLAN CLK_PCIE2_WLAN_N CLKOUT_PCIE_N2 XTAL_IN
CLK_PCIE1_SSD_P DU1 EJ61 SUSCLK
CLK_PCIE1_SSD_P CLK_PCIE1_SSD_N CLKOUT_PCIE_P1 GPD8/SUSCLK SUSCLK
M.2 SSD1 DU3
CLK_PCIE1_SSD_N CLKOUT_PCIE_N1 EV58 PCH_RTCX2
CLK_PCIE0_SSD_P RTCX2 PCH_RTCX1
DT10 EV56
CLK_PCIE0_SSD_P CLK_PCIE0_SSD_N CLKOUT_PCIE_P0 RTCX1
M.2 SSD2 DT11 RC3292 1 @ 2 0_0201_5%
CLK_PCIE0_SSD_N CLKOUT_PCIE_N0 FA55 RTC_RST_N EC_RTC_RST_N
RTCRST# RTC_RST_N
CLK_BIASREF DJ3 FB56 SRTC_RST_N SRTC_RST_N
XCLK_BIASREF SRTCRST#
EB52
GPP_A7/SRCCLK_OE7#
1

EW23 FPR_RESET
GPP_E15/RSVD_TP/SRCCLK_OE8# FPR_RESET
RC1909
1/20W_60.4_1%_0201 11 OF 22
INTEL_ADL-P-682_BGA1744

www.teknisi-indonesia.com
2

A A

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 16 of 108
5 4 3 2 1
 5 4 3 2 1

?
?

UC1L BMAP_REV = ?

PCH_PM_SLP_SUS_N EN53 EM61 PWRBTN_N RC1267 1 @ 2 0_0201_5% PBTN_OUT_N

PCH_PM_SLP_SUS_N SLP_SUS# GPD3/PWRBTN# PBTN_OUT_N
EM56 BATLOW_N
SLP_S5_N GPD0/BATLOW# PCH_AC_PRESENT
TH2985 @ 1 PAD EG60 EJ59
PCH_PM_SLP_S4_N SLP_S4_N GPD10/SLP_S5# GPD1/ACPRESENT PCH_AC_PRESENT
RC1266 1 @ 2 0_0201_5% EP56
PCH_PM_SLP_S4_N PCH_PM_SLP_S3_N SLP_S3_N GPD5/SLP_S4# PCH_PD_I2C_INT_N
RC1237 1 @ 2 0_0201_5% EM59 EA56
PCH_PM_SLP_S3_N SLP_A_N GPD4/SLP_S3# GPP_B11/PMCALERT# CPU_C10_GATE_H_N PCH_PD_I2C_INT_N
@ 1 PAD EM57 ER46
PCH_PM_SLP_WLAN_N TH2982 GPD6/SLP_A# GPP_H18/PROC_C10_GATE#
PCH_PM_SLP_WLAN_N EJ57 ET48
D GPD9/SLP_WLAN# GPP_H3/SX_EXIT_HOLDOFF# D
PCH_PM_SLP_S0_N RC1223 1 @ 2 0_0201_5% SLP_S0_N DW59 ET51 WAKE_N RC1224 1 @ 2 1/20W_0_5%_0201 EC_WAKE_N
PCH_PM_SLP_S0_N GPP_B12/SLP_S0# WAKE# EC_WAKE_N
PCH_PM_SLP_LAN_N RC4269 1 @ 2 0_0201_5% SLP_LAN_N EK53 RC4181 1 @ 2 1/20W_0_5%_0201 PCIE_WAKE_N
PCH_PM_SLP_LAN_N SLP_LAN# EP58 LAN_WAKE_N_PCH PCIE_WAKE_N
PCH_RSMRST_N GPD2/LAN_WAKE# PCH_LANPHYPC LAN_WAKE_N_PCH
EH53 EJ56 RC4268 1 @ 2 0_0201_5% LANPHYPC
PCH_SYS_RESET_N RSMRST# GPD11/LANPHYPC LANPHYPC
+3VALW_PCH RC2423 1 2 EK26
PCH_PLT_RST_N DW57 SYS_RESET# EK60
1/20W_10K_5%_0201 GPD7
GPP_B13/PLTRST# GPD7
EC_RSMRST_N RC4261 2 @ 1 1/20W_0_5%_0201 PCH_DPWROK_R EE48 FA22 CPU_WLAN_OFF_N
EC_RSMRST_N EC_SYS_PWROK SYS_PWROK_R DSW_PWROK GPP_E8/SLP_DRAM# CPU_WLAN_OFF_N
EC_SYS_PWROK RC1243 1 @ 2 0_0201_5% EK23
EC_PCH_PWROK PCH_PWROK_R SYS_PWROK VCCST_PWRGD
EC_PCH_PWROK RC1213 1 @ 2 0_0201_5% EH51 DJ8
PCH_PWROK VCCST_PWRGD DK4 VCCST_OVERRIDE_R VCCST_OVERRIDE
RC1248 1 @ 2 0_0201_5%
RTC_INTRUDER_N VCCST_OVERRIDE VCCST_OVERRIDE
DY44
SPI_VCC_SEL EL53 INTRUDER# EH28
SPIVCCIOSEL GPP_F20/EXT_PWR_GATE#
EH31
TP_CPUPWRGD GPP_F21/EXT_PWR_GATE2#
@ 1 PAD BG11
TH2987 PROCPWRGD
12 OF 22
INTEL_ADL-P-682_BGA1744
@

+VCCPDSW_3P3

+VCCST_CPU RC1221 1 2 1/20W_100K_5%_0201 PWRBTN_N

RC1210 1 2 1/20W_100K_5%_0201 WAKE_N

2

RC1216 1 2 1/20W_100K_5%_0201 BATLOW_N +VCCPRTC_3P3

RC1265 PCH_PLT_RST_N
1 2 1/20W_100K_5%_0201 PCH_DPWROK PCH_PLT_RST_N
1/20W_1K_5%_0201 RC2443 @

1
1 follow Y550 pull high, PDG/EDS Pull Up
RC1264
1

1
RC4289 1 2 1/20W_4.7K_5%_0201 LAN_WAKE_N_PCH CC1202 RC1230 CRB SPI select strap
VCCST_PWRGD 1 2 220P_25V_K_X7R_0201 1/20W_100K_5%_0201 RC1226
EC_VCCST_PWRGD
C 1/20W_1M_5%_0201 C
2
EMC_NS@

2
1/20W_60.4_1%_0201

2
RTC_INTRUDER_N
+3VALW_PCH

1U_6.3V_M_X5R_0201
Emergency Power Loss Early De-assertion of DSW_PWROK control circuit 1

1
CC1205
RC3302 1 @ 2 0_0201_5% PCH_RSMRST_N
EC_RSMRST_N SLP_S0_N
RC1236 1 2 1/20W_100K_5%_0201 @ RC1238
@ 1/20W_1M_5%_0201
RC1233 2 1 1/20W_10K_5%_0201 PCH_PD_I2C_INT_N 2

2
+3VALW_PCH
PCH_DPWROK_R RC1225 1 @ 2 0_0201_5% PCH_DPWROK RC1208 1 2 1/20W_100K_5%_0201 PCH_PM_SLP_SUS_N
PCH_DPWROK
RC1205 1 2 1/20W_100K_5%_0201 SLP_S4_N

2
1
RC1239 1 2 1/20W_100K_5%_0201 SLP_S3_N RC2206
CC1203 @ 1/20W_10K_5%_0201
0.1U_10V_K_X5R_0201 RC1214 1 @ 2 1/20W_100K_5%_0201 PCH_PM_SLP_WLAN_N
2

1
RC1241 1 @ 2 1/20W_10K_5%_0201 PCH_AC_PRESENT

RC4291 1 2 1/20W_100K_5%_0201 SLP_LAN_N CPU_C10_GATE_H_N TH30401 PAD

@

1
RC2444 1 2 1/20W_10K_5%_0201 SYS_PWROK_R

RC1247 1 2 1/20W_10K_5%_0201 PCH_PWROK_R RC2204

1/20W_100K_5%_0201
RC149 1 2 1/20W_100K_5%_0201 PCH_RSMRST_N

2
RC1232 2 1 1/20W_100K_5%_0201 PCH_DPWROK_R

B B

Pin Straps
+VCCPDSW_3P3 +VCCPDSW_3P3
2

RC1218 RC1207
@ 1/20W_100K_5%_0201 @ 1/20W_4.7K_5%_0201
1

SPI_VCC_SEL
GPD7
1
2

RC1220
1/20W_4.7K_5%_0201
RC1227
1/20W_10K_5%_0201
2
1

GPD7:
Rising edge of DSW_PWROK SPIVCCIOSEL(SPI_VCC_SEL):
This strap has a 20Kohm±30% internal pull-down SPI Operation Voltage Select
This strap should sample LOW. There should Rising edge of DSW_PWROK
not be any on-board device driving it to opposite direction There is no internal pull-up or pull-down on the strap. An
during strap sampling. external resistor is required.
A A
NOTES: 1. The internal pull-down is disabled after 0 = SPI voltage is 3.3V (4.7 kohm pull-down to GND)
DSW_PWROK is high. 1 = SPI voltage is 1.8V (4.7K pull-up to DSW_3P3)
2. This signal is in the DSW well.

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 17 of 108
5 4 3 2 1
 5 4 3 2 1

+VCC1P8A_LDO +VCC1P8A_CPU

RC2424 1 @ 2 1/16W_0_5%_0402
+VCCST_CPU
+1.8VALW

0.1U_10V_K_X5R_0201
RC4275 1 @ 2 1/16W_0_5%_0402

1/16W_100_1%_0402

1/16W_100_1%_0402
1

1
D D
RC4265 1 @ 2 0_0402_5%

CC1303

RC1302

RC1303
RC1304
2 1/16W_56.2_1%_0402
1 1

2
@ @ @
CC1301 CC1302
SVID_DATA 10U_6.3V_M_X5R_0402 22U_6.3V_M_X5R_0603
SVID_DATA SVID_CLK 2 2
SVID_CLK SVID_ALERT_N
SVID_ALERT_N

?
?
? +1.2V +VCCGT
+VCCCORE ? +VCCCORE UC1O BMAP_REV = ?

UC1M BMAP_REV = ? AD61 CP44

AG61 VDD2_1 VCCGT_1 CR45
BA44 CF8 AN61 VDD2_2 VCCGT_2 CT44
VCCCORE_1 VCCCORE_51 VDD2_3 VCCGT_3
BB43 CF9 AP41 CU43
BB45 VCCCORE_2 VCCCORE_52 CG14 AP44 VDD2_4 VCCGT_4 CU45
BC44 VCCCORE_3 VCCCORE_53 CG4 AR43 VDD2_5 VCCGT_5 CV4
BD43 VCCCORE_4 VCCCORE_54 CH1 AR45 VDD2_6 VCCGT_6 CV44
BD45 VCCCORE_5 VCCCORE_55 CH3 AT44 VDD2_7 VCCGT_7 CW1
BE44 VCCCORE_6 VCCCORE_56 CK11 AU43 VDD2_8 VCCGT_8 CW11
BH43 VCCCORE_7 VCCCORE_57 CK12 AU45 VDD2_9 VCCGT_9 CW12
VCCCORE_8 VCCCORE_58 VDD2_10 VCCGT_10
BK43 CK4 AV44 CW3
BK44 VCCCORE_9 VCCCORE_59 CK6 AY61 VDD2_11 VCCGT_11 CW6
BL45 VCCCORE_10 VCCCORE_60 CK8 BH61 VDD2_12 VCCGT_12 CW8
VCCCORE_11 VCCCORE_61 VDD2_13 VCCGT_13
C BM44 CK9 BR61 CW9 C
BN11 VCCCORE_12 VCCCORE_62 CL1 CA61 VDD2_14 VCCGT_14 CY14
BN12 VCCCORE_13 VCCCORE_63 CL14 CC44 VDD2_15 VCCGT_15 CY4
BN45 VCCCORE_14 VCCCORE_64 CL3 CD43 VDD2_16 VCCGT_16 CY44
BP14 VCCCORE_15 VCCCORE_65 CM11 CD61 VDD2_17 VCCGT_17 DA1
VCCCORE_16 VCCCORE_66 VDD2_18 VCCGT_18
BR11 CM12 CE44 DA3
BR12 VCCCORE_17 VCCCORE_67 CM4 CF43 VDD2_19 VCCGT_19 DA43
VCCCORE_18 VCCCORE_68 VDD2_20 VCCGT_20
BT14 CM6 CF45 DB45
BT44 VCCCORE_19 VCCCORE_69 CM8 CG44 VDD2_21 VCCGT_21 DC1
BU11 VCCCORE_20 VCCCORE_70 CM9 CH45 VDD2_22 VCCGT_22 DC11
VCCCORE_21 VCCCORE_71 VDD2_23 VCCGT_23
BU12 CN1 CK61 DC12
BU43 VCCCORE_22 VCCCORE_72 CN14 CN61 VDD2_24 VCCGT_24 DC3
BU45 VCCCORE_23 VCCCORE_73 CN3 CW61 VDD2_25 VCCGT_25 DC4
BV14 VCCCORE_24 VCCCORE_74 CP1 DF61 VDD2_26 VCCGT_26 DC44
BV44 VCCCORE_25 VCCCORE_75 CP11 J61 VDD2_27 VCCGT_27 DC6
BW12 VCCCORE_26 VCCCORE_76 CP12 R61 VDD2_28 VCCGT_28 DC8
BW43 VCCCORE_27 VCCCORE_77 CP3 +VCC1P05_OUT V61 VDD2_29 VCCGT_29 DC9
VCCCORE_28 VCCCORE_78 VDD2_30 VCCGT_30
BW45 CP4 DD1
BY1 VCCCORE_29 VCCCORE_79 CP6 AR14 VCCGT_31 DD14
BY44 VCCCORE_30 VCCCORE_80 CP8 AT12 VCC1P05_OUT_1 VCCGT_32 DD3
CA1 VCCCORE_31 VCCCORE_81 CP9 VCC1P05_OUT_2 VCCGT_33 DD43
CA3 VCCCORE_32 VCCCORE_82 CR4 CM44 VCCGT_34 DD45
CB12 VCCCORE_33 VCCCORE_83 +VCC1P8A_CPU EA14 RSVD_TP_32 VCCGT_35 DE11
CC14 VCCCORE_34 CT3 VCORE_VCC_SENSE RSVD_TP_48 VCCGT_36 DE12
CC3 VCCCORE_35 VCC_SENSE CT1 VCORE_VSS_SENSE E61 VCCGT_37 DE4
VCCCORE_36 VSS_SENSE VCC1P8_PROC_8 VCCGT_38
CD11 G61 DE6
CD12 VCCCORE_37 R9 SVID_DATA H59 VCC1P8_PROC_9 VCCGT_39 DE8
VCCCORE_38 VIDSOUT SVID_CLK VCC1P8_PROC_10 VCCGT_40
CD6 U9 AH44 DE9
CD8 VCCCORE_39 VIDSCK W9 SVID_ALERT_N +VCC1P05_OUT AJ45 VCC1P8_PROC_1 VCCGT_41 DF1
CD9 VCCCORE_40 VIDALERT# AK44 VCC1P8_PROC_2 VCCGT_42 DF14
VCCCORE_41 VCC1P8_PROC_3 VCCGT_43
CE1 AU14 AL45 DF3
CE14 VCCCORE_42 VCC1P05_OUT_3 AM41 VCC1P8_PROC_4 VCCGT_44 DG4
CE3 VCCCORE_43 DJ6 VCCSTPWRGOODTCSS_R VCC1P8_PROC_5 VCCGT_45
RC1308 1 @ 2 0_0201_5% AM44
VCCCORE_44 VCCST_PWRGD_SX VCCST_OVERRIDE VCC1P8_PROC_6
CE4 AN43
CF1 VCCCORE_45 VCC1P8_PROC_7
VCCCORE_46 VCCGT_VCC_SENSE
CF11 CV1
CF12 VCCCORE_47 VCCGT_VSS_SENSE CV3 VCCGT_SENSE
CF3 VCCCORE_48 VSSGT_SENSE
B
CF6 VCCCORE_49 B
15 OF 22
VCCCORE_50
INTEL_ADL-P-682_BGA1744
13 OF 22
@
INTEL_ADL-P-682_BGA1744
@

CRB place to CPU

CRB place to CPU
+VCCCORE

VCCIN_SENSE VCCGT_SENSE
+VCCGT
1

1
RC1307
1/16W_100_1%_0402 RC1305
1/16W_100_1%_0402
2

VCORE_VCC_SENSE

2
VCCGT_VCC_SENSE
VCORE_VSS_SENSE
VCCGT_VSS_SENSE
1

1
RC1301
1/16W_100_1%_0402 RC1306
1/16W_100_1%_0402
2

2
A A

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 18 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU (8/9) PWR,BYPASS
Date: Wednesday, March 02, 2022 Sheet 19 of 108
5 4 3 2 1
 5 4 3 2 1

+VCC1P05_OUT_FET
+VCCLDOSTD_OUT_0P85
+1.8VALW +VCCPRIM_1P8 +1.8VALW +VCCA_CLKLDO_1P8
Need stuff
@ 1.533A 2 0.135A
JH2 1 2 JUMP_43X79 RC1418 1 @ 2 0_5%_0603
1 2
CC1413

1U_6.3V_M_X5R_0201

10U_6.3V_M_X5R_0402

1
1 1 2.2U_6.3V_M_X5R_0402 1

1
RC1419 1 1 2 LC1401

RC4312

CC1414
add at 6/24 @ @ 1/20W_1M_5%_0201 RC1410 RC1408 RC1401
1/20W_1M_5%_0201 1U_6.3V_M_X5R_0201 @ @ 0_0402_5%
+VCCIN_AUX_FIL 2 2 2 0.68UH_SDTT25201B-R68MS_3.3A_20%

2
VCCA_CLKLDO_R

22U_6.3V_M_X5R_0603

47U_6.3V_M_X5R_0603

1U_6.3V_M_X5R_0201
1 1 1

CC3669

CC1407

CC1404
D D

10U_6.3V_M_X5R_0402
2 2 2@
1 1

47U_6.3V_M_X5R_0603
RC1420

CC1408
@ +3VALW_PCH +VCCPRIM_3P3 +VCCDPHY_1P24 22mA
Need stuff
2 2 @ 0.287A PDG: VCCDPHY_1P24

4.7U_6.3V_M_X5R_0402
JH4 1 2 JUMP_43X39 1 4.7u_0402 *1
1 2
PDG: VCCA_CLKLDO_1P8

CC1406
Require minimum power plane

1U_6.3V_M_X5R_0201

10U_6.3V_M_X5R_0402
1
1 1 width of 3mm from BGA to

1/20W_1M_5%_0201

CC1405

CC1409
2 Capacitor. Require immediate Inductor by default is a placeholder. If stuffed, the
@ @ @ 680nF

RC1417
GND reference inductor needs to meet following requirement:
2 2
(Placeholder) 1 Rated at least 150mA; DCR = 0.036Ohm +/- 20%

2
Option 1: stuff with 0 ohm if the inductor is not stuffed.
0 ohm_0603 1 Option 2: stuff 100 mohm if the inductor stuffed
100 mohm_0603

Place the cap near to package pin DR15 and DR12

47u_0603 1 right after signal breakout

?
?
+VCCIN_AUX +VCCPRIM_1P8 +3VALW +VCCPDSW_3P3
UC1N BMAP_REV = ?
8mA
AL20 DW20 RC1412 1 @ 2 0_0402_5%
AL32 VCCIN_AUX_1 VCCPRIM_1P8_1 DW22
AN20 VCCIN_AUX_2 VCCPRIM_1P8_2 DW27
AN22 VCCIN_AUX_3 VCCPRIM_1P8_3 DW30
AN30 VCCIN_AUX_4 VCCPRIM_1P8_4 DY21 +3VALW_PCH
VCCIN_AUX_5 VCCPRIM_1P8_5
CRB place to CPU AN32 DY23

1U_6.3V_M_X5R_0201
AN37 VCCIN_AUX_6 VCCPRIM_1P8_6 DY26 RC1407 1 @ 2 1/16W_0_5%_0402
AP17 VCCIN_AUX_7 VCCPRIM_1P8_7 DY28 1
+VCCIN_AUX AP27 VCCIN_AUX_8 VCCPRIM_1P8_8
DY31

CC1401
C C
AP30 VCCIN_AUX_9 VCCPRIM_1P8_9 EB18 @
VCCIN_AUX_10 VCCPRIM_1P8_12
AUX_CPU_SENSE AP32
AP37 VCCIN_AUX_11 VCCPRIM_1P8_13
EB21
EB23 PDG: VCCDSW_3P3 2
1

B3 VCCIN_AUX_12 VCCPRIM_1P8_14 EB28

VCCIN_AUX_13 VCCPRIM_1P8_15 Placeholder 1* 0402 capacitor on primary side
RC1403 D3 EC14 as close as possible to the vias.
E1 VCCIN_AUX_14 VCCPRIM_1P8_16 EC16
1/16W_100_1%_0402 VCCIN_AUX_33 VCCPRIM_1P8_17
F1 EC23
F3 VCCIN_AUX_36 VCCPRIM_1P8_18 EC26
2

G3 VCCIN_AUX_37 VCCPRIM_1P8_19 EE14

VCCIN_AUX_38 VCCPRIM_1P8_20
H4 EE28 +VCCPRIM_3P3
VCCIN_AUX_VCCSENSE J1 VCCIN_AUX_39 VCCPRIM_1P8_21 EG14
VCCIN_AUX_VCCSENSE VCCIN_AUX_40 VCCPRIM_1P8_22
J3 FB33
VCCIN_AUX_VSSSENSE L1 VCCIN_AUX_41 VCCPRIM_1P8_23 VCCRTC +VCCPRTC_3P3
VCCIN_AUX_VSSSENSE VCCIN_AUX_42
L3 DV41
N3 VCCIN_AUX_43 VCCPRIM_3P3_1 DW40 RC1422 1 @ 2 0_0402_5%
1

VCCIN_AUX_44 VCCPRIM_3P3_2 EB33

1U_6.3V_K_X5R_0402

0.1U_10V_K_X5R_0201
VCCPRIM_3P3_3
RC1413 DH45 EC31

1/20W_100K_5%_0201
1
DJ41 VCCIN_AUX_15 VCCPRIM_3P3_5 EC33
1/16W_100_1%_0402 VCCIN_AUX_16 VCCPRIM_3P3_6 1 1
DJ44 EE31

RC1415

CC1402

CC1403
DK40 VCCIN_AUX_17 VCCPRIM_3P3_7
@
2

DK43 VCCIN_AUX_18 FB45

DK45 VCCIN_AUX_19 RSVD_24 2 2

2
DL44 VCCIN_AUX_20 FB52
VCCIN_AUX_21 VCCLDOSTD_0P85 +VCCLDOSTD_OUT_0P85
DM1
VCCIN_AUX_22
DM14 EJ14 +VCCA_CLKLDO_1P8
DM43 VCCIN_AUX_23 VCCA_CLKLDO_1P8_1 EM14
VCCIN_AUX_24 VCCA_CLKLDO_1P8_2
DP41
DP42 VCCIN_AUX_25 FB39
VCCIN_AUX_26 VCCDPHY_1P24 +VCCDPHY_1P24
DR14
VCCIN_AUX_27
DR40 BN43
DT41 VCCIN_AUX_28 RSVD_TP_27 AY11
DU14 VCCIN_AUX_29 RSVD_TP_17 BP44
DU40 VCCIN_AUX_30 RSVD_TP_28 BL12
+VCCIN_AUX_FIL VCCIN_AUX_31 RSVD_TP_26
DV2 CN43
VCCIN_AUX_32 RSVD_TP_33
ED2 BJ11
EL2 VCCIN_AUX_34 RSVD_TP_23
DESIGN NOTE:
P1 VCCIN_AUX_35 EB36
B VCCIN_AUX_FLTR VCCPRIM1P05_OUT_PCH_1 +VCC1P05_OUT_PCH B
EC36 MIPI DSI not used. So VCC_MIPILP
VCCIN_AUX_VSSSENSE AH30 VCCPRIM1P05_OUT_PCH_3 EE41 is floating as per PDG +VCCDSW_1P05 +VCCST_CPU
VCCIN_AUX_VCCSENSE VSSINAUX_SENSE VCCDSW_1P05 +VCCDSW_1P05
AF30 V1
VCCINAUX_SENSE VCC_MIPILP EB38
VCCPRIM1P05_OUT_PCH_2 +VCC1P05_OUT_PCH 6mA
EF21 EE36 1 1 1
EH21 VCC_VNNEXT_1P05_1 VCCPRIM1P05_OUT_PCH_4
@
VCC_VNNEXT_1P05_2 EC38
+VCCPRTC_3P3 CC1412 CC1416 CC1411
EE18 VCCRTC EB42 V3P3A_DSW_R RC4 1 2 0_0402_5%
@ +VCCPDSW_3P3 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201
EE21 VCC_V1P05EXT_1P05_1 VCCPDSW_3P3 EE33 2 2 2
VCC_V1P05EXT_1P05_2 VCCPGPPR +VCCPGPPR
GPPC_B2_VRALERT_N DT59 EB41
GPPC_B2_VRALERT_N GPP_B2/VRALERT# VCCPRIM_3P3_4 +VCCPRIM_3P3
EK31 DY41
GPP_F22/VNN_CTRL VCCPRIM_1P8_10 +VCCPRIM_1P8
EL28 DY42
GPP_F23/V1P05_CTRL VCCPRIM_1P8_11
VCCIN_AUX_VID0 EA60 EU1
VCCIN_AUX_VID0 VCCIN_AUX_VID1 GPP_B0/CORE_VID0 VCC1P05_PROC_1 +VCCST_CPU
EA58 EU4
VCCIN_AUX_VID1 GPP_B1/CORE_VID1 VCC1P05_PROC_2
EV3 +VCC1P05_OUT_FET
VCC1P05_OUT_FET_1 EW1
VCC1P05_OUT_FET_2 +VCCPRIM_1P8 +VCCPGPPR
EY1
VCC1P05_OUT_FET_3
22mA
AM15 RC1402 1 @ 2 0_0402_5%
VCC_DISPIO +VCC1P05_OUT

teknisi-indonesia.com
BJ12
RSVD_TP_24 BK14
RSVD_TP_25 BF14 +VCCPRIM_3P3
RSVD_TP_20
14 OF 22 RC4311 1 @ 2 1/16W_0_5%_0402
INTEL_ADL-P-682_BGA1744
@

+3VALW_PCH
2

A A
RC1421
RB521CM-30T2R_VMN2M-2 1/20W_100K_5%_0201
1

DC5 2 1 GPPC_B2_VRALERT_N
H_PROCHOT_N
2 1

1 @ 2
Security Classification LCFC Highly Confidential Information Title
RC1414 1/20W_0_5%_0201
X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU (8/9) PWR,BYPASS
Date: Wednesday, March 02, 2022 Sheet 20 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title
<Title>

Size Document Number Rev

C <Doc> <RevCode>

Date: Wednesday, March 02, 2022 Sheet 21 of 108

5 4 3 2 1
 5 4 3 2 1

D D

? ? ? ?
? ? ? ?
?
UC1P BMAP_REV = ? UC1Q BMAP_REV = ? UC1R BMAP_REV = ? UC1S BMAP_REV = ? ?

A3 AL15 BF58 CD58 DC47 ED58 F56 M36 UC1D BMAP_REV = ?

A10 VSS_2 VSS_75 AL17 BG1 VSS_148
VSS_221 CE51 DC54 VSS_294 VSS_367 ED6 F59 VSS_441
VSS_515 M47
A21 VSS_3 VSS_76 AL22 BG12 VSS_149
VSS_222 CE55 DC57 VSS_295 VSS_368 ED60 F9 VSS_442
VSS_516 M57 AF27
VSS_4 VSS_77 VSS_150
VSS_223 VSS_296 VSS_369 VSS_443
VSS_517 RSVD_1
A23 AL4 BG44 CF47 DC59 ED8 FA40 M59 AH20
A25 VSS_5 VSS_78 AL41 BG52 VSS_151
VSS_224 CF49 DE44 VSS_297 VSS_370 EE16 FA7 VSS_444
VSS_518 N1 AK22 RSVD_2
A26 VSS_6 VSS_79 AL54 BG9 VSS_152
VSS_225 CF54 DE51 VSS_298 VSS_371 EE43 FB1 VSS_445
VSS_519 N4 AK40 RSVD_4
VSS_7 VSS_80 VSS_153
VSS_226 VSS_299 VSS_372 VSS_446
VSS_520 RSVD_6
A28 AM11 BH4 CG57 DE55 EE51 FB14 N40 AL30
A30 VSS_8 VSS_81 AM3 BH46 VSS_154
VSS_227 CG59 DF43 VSS_300 VSS_373 EF13 FB26 VSS_447
VSS_521 N41 AL40 RSVD_7
VSS_9 VSS_82 VSS_155
VSS_228 VSS_301 VSS_374 VSS_448
VSS_522 RSVD_8
A31 AM51 BH48 CH11 DF46 EF8 FB42 N48 BG47
A33 VSS_10 VSS_83 AM55 BH58 VSS_156
VSS_229 CH12 DF48 VSS_302 VSS_375 EH13 FB48 VSS_449
VSS_523 N54 BG53 RSVD_9
A40 VSS_11 VSS_84 AM9 BJ51 VSS_157
VSS_230 CH54 DF58 VSS_303 VSS_376 EH8 FB59 VSS_450
VSS_524 N9 DT42 RSVD_10
VSS_12 VSS_85 VSS_158
VSS_231 VSS_304 VSS_377 VSS_451
VSS_525 RSVD_13
A47 AN17 BJ55 CH6 DG11 EK21 FB61 P11 EE46
A53 VSS_13 VSS_86 AN40 BJ6 VSS_159
VSS_232 CH8 DG12 VSS_305 VSS_378 EK28 FC2 VSS_452
VSS_526 P16 EF33 RSVD_15
A60 VSS_14 VSS_87 AN46 BJ8 VSS_160
VSS_233 CH9 DG51 VSS_306 VSS_379 EK36 FC55 VSS_453
VSS_527 P21 EH41 RSVD_16
AA11 VSS_15 VSS_88 AN48 BJ9 VSS_161
VSS_234 CJ14 DG55 VSS_307 VSS_380 EK43 FC56 VSS_454
VSS_528 P26 RSVD_20
AA21 VSS_16 VSS_89 AN58 BL11 VSS_162
VSS_235 CJ4 DG6 VSS_308 VSS_381 EK51 FC58 VSS_455
VSS_529 P3 4 OF 22
VSS_17 VSS_90 VSS_163
VSS_236 VSS_309 VSS_382 VSS_456
VSS_530
AA26 AP1 BL4 CJ44 DG8 EK56 FC60 P31
AA31 VSS_18 VSS_91 AP15 BL54 VSS_164
VSS_237 CK1 DG9 VSS_310 VSS_383 EK58 G21 VSS_457
VSS_531 P35 INTEL_ADL-P-682_BGA1744
AA35 VSS_19 VSS_92 AP20 BL9 VSS_165
VSS_238 CK3 DH4 VSS_311 VSS_384 EL13 G25 VSS_458
VSS_532 P47 @
AA40 VSS_20 VSS_93 AP22 BM1 VSS_166
VSS_239 CK43 DH54 VSS_312 VSS_385 EL4 G28 VSS_459
VSS_533 P51
AA44 VSS_21 VSS_94 AP25 BM14 VSS_167
VSS_240 CK46 DJ47 VSS_313 VSS_386 EL6 G31 VSS_460
VSS_534 P55
AA57 VSS_22 VSS_95 AP35 BM47 VSS_168
VSS_241 CK48 DJ57 VSS_314 VSS_387 EL8 G34 VSS_461
VSS_535 R12
AA59 VSS_23 VSS_96 AP51 BM57 VSS_169
VSS_242 CK51 DJ59 VSS_315 VSS_388 EN13 G42 VSS_462
VSS_536 R17
VSS_24 VSS_97 VSS_170
VSS_243 VSS_316 VSS_389 VSS_463
VSS_537
AB16 AP55 BM59 CK55 DK14 EN8 G43 R22
AB21 VSS_25 VSS_98 AP9 BN1 VSS_171
VSS_244 CK58 DK54 VSS_317 VSS_390 EP14 G50 VSS_464
VSS_538 R27
AB26 VSS_26 VSS_99 AR4 BN54 VSS_172
VSS_245 CM52 DL10 VSS_318 VSS_391 ER1 H1 VSS_465
VSS_539 R32
VSS_27VSS_100 VSS_173
VSS_246 VSS_319 VSS_392 VSS_466
VSS_540
C AB31 AR54 BN9 CN46 DL11 ER13 H13 R37 C
AB35 VSS_28VSS_101 AT47 BP4 VSS_174
VSS_247 CN58 DL13 VSS_320 VSS_393 ER21 H16 VSS_467
VSS_541 R44
AB54 VSS_29VSS_102 AT57 BP51 VSS_175
VSS_248 CP51 DM4 VSS_321 VSS_394 ER28 H18 VSS_468
VSS_542 R48
AC4 VSS_30VSS_103 AT59 BP55 VSS_176
VSS_249 CP55 DM41 VSS_322 VSS_395 ER3 H34 VSS_469
VSS_543 R58
AC40 VSS_31VSS_104 AT6 BR43 VSS_177
VSS_250 CR43 DM46 VSS_323 VSS_396 ER36 H37 VSS_470
VSS_544 T1
VSS_32VSS_105 VSS_178
VSS_251 VSS_324 VSS_397 VSS_471
VSS_545
AC44 AT8 BR46 CR47 DM48 ER43 H52 T11
AC51 VSS_33VSS_106 AU54 BR48 VSS_179
VSS_252 CR49 DM51 VSS_325 VSS_398 ER51 H58 VSS_472
VSS_546 T16
VSS_34VSS_107 VSS_180
VSS_253 VSS_326 VSS_399 VSS_473
VSS_547
AC55 AV11 BR58 CR54 DM55 ER61 H6 T21
AC6 VSS_35VSS_108 AV4 BR6 VSS_181
VSS_254 CT11 DM58 VSS_327 VSS_400 ER8 H8 VSS_474
VSS_548 T26
AC8 VSS_36VSS_109 AV9 BR8 VSS_182
VSS_255 CT57 DM6 VSS_328 VSS_401 EU11 H9 VSS_475
VSS_549 T3
VSS_37VSS_110 VSS_183
VSS_256 VSS_329 VSS_402 VSS_476
VSS_550
AD21 AW1 BR9 CT59 DM61 EU56 J11 T31
AD26 VSS_38VSS_111 AW14 BT4 VSS_184
VSS_257 CT6 DN13 VSS_330 VSS_403 EU58 J14 VSS_477
VSS_551 T35
AD31 VSS_39VSS_112 AW51 BT51 VSS_185
VSS_258 CT8 DN40 VSS_331 VSS_404 EU8 J17 VSS_478
VSS_552 T40
AD35 VSS_40VSS_113 AW55 BT55 VSS_186
VSS_259 CT9 DN8 VSS_332 VSS_405 EV14 J20 VSS_479
VSS_553 T52
AD46 VSS_41VSS_114 AY1 BU54 VSS_187
VSS_260 CU4 DP46 VSS_333 VSS_406 EV20 J21 VSS_480
VSS_554 U16
AD48 VSS_42VSS_115 AY43 BU9 VSS_188
VSS_261 CU54 DP49 VSS_334 VSS_407 EV26 J25 VSS_481
VSS_555 U21
AD58 VSS_43VSS_116 AY46 BV1 VSS_189
VSS_262 CV14 DT13 VSS_335 VSS_408 EV33 J28 VSS_482
VSS_556 U26
VSS_44VSS_117 VSS_190
VSS_263 VSS_336 VSS_409 VSS_483
VSS_557
AE12 AY48 BV47 CW43 DT52 EV39 J31 U31
AE17 VSS_45VSS_118 AY51 BV57 VSS_191
VSS_264 CW46 DT8 VSS_337 VSS_410 EV4 J36 VSS_484
VSS_558 U35
AE22 VSS_46VSS_119 AY55 BV59 VSS_192
VSS_265 CW48 DV13 VSS_338 VSS_411 EV45 J39 VSS_485
VSS_559 U44
AE27 VSS_47VSS_120 AY58 BW4 VSS_193
VSS_266 CW51 DV4 VSS_339 VSS_412 EV52 J47 VSS_486
VSS_560 U46
AE32 VSS_48VSS_121 AY9 BW54 VSS_194
VSS_267 CW55 DV44 VSS_340 VSS_413 EV59 J48 VSS_487
VSS_561 V3
AE37 VSS_49VSS_122 B34 BW9 VSS_195
VSS_268 CW58 DV49 VSS_341 VSS_414 EW61 J51 VSS_488
VSS_562 V40
AE40 VSS_50VSS_123 B4 BY3 VSS_196
VSS_269 CY51 DV56 VSS_342 VSS_415 EY14 J55 VSS_489
VSS_563 V41
AE44 VSS_51VSS_124 B43 C1 VSS_197
VSS_270 CY55 DV58 VSS_343 VSS_416 EY20 K4 VSS_490
VSS_564 V51
VSS_52VSS_125 VSS_198
VSS_271 VSS_344 VSS_417 VSS_491
VSS_565
AE52 B50 C21 D11 DV6 EY26 L12 V55
AE9 VSS_53VSS_126 B58 C25 VSS_199
VSS_272 D14 DV8 VSS_345 VSS_418 EY3 L13 VSS_492
VSS_566 V58
VSS_54VSS_127 VSS_200
VSS_273 VSS_346 VSS_419 VSS_493
VSS_567
AF4 B61 C28 D17 DW14 EY33 L15 W1
AF46 VSS_55VSS_128 BA4 C31 VSS_201
VSS_274 D20 DW25 VSS_347 VSS_420 EY39 L17 VSS_494
VSS_568 W11
AG1 VSS_56VSS_129 BB12 C34 VSS_202
VSS_275 D21 DW35 VSS_348 VSS_421 EY4 L18 VSS_495
VSS_569 W16
VSS_57VSS_130 VSS_203
VSS_276 VSS_349 VSS_422 VSS_496
VSS_570
AG51 BB54 C40 D25 DY13 EY45 L20 W21
AG55 VSS_58VSS_131 BB6 C47 VSS_204
VSS_277 D28 DY33 VSS_350 VSS_423 EY52 L22 VSS_497
VSS_571 W26
AG58 VSS_59VSS_132 BB8 C9 VSS_205
VSS_278 D31 DY36 VSS_351 VSS_424 EY56 L23 VSS_498
VSS_572 W31
AH9 VSS_60VSS_133 BB9 CA14 VSS_206
VSS_279 D4 DY38 VSS_352 VSS_425 EY58 L27 VSS_499
VSS_573 W35
AJ3 VSS_61VSS_134 BC14 CA43 VSS_207
VSS_280 D53 DY52 VSS_353 VSS_426 EY59 L30 VSS_500
VSS_574 W44
VSS_62VSS_135 VSS_208
VSS_281 VSS_354 VSS_427 VSS_501
VSS_575
AJ41 BC47 CA46 D56 DY8 EY6 L33 Y12
AJ47 VSS_63VSS_136 BC57 CA48 VSS_209
VSS_282 D58 E43 VSS_355 VSS_428 EY9 L35 VSS_502
VSS_576 Y17
AJ49 VSS_64VSS_137 BC59 CA51 VSS_210
VSS_283 D59 E50 VSS_356 VSS_429 F21 L36 VSS_503
VSS_577 Y22
B
AJ54 VSS_65VSS_138 BD4 CA55 VSS_211
VSS_284 D9 EB13 VSS_357 VSS_430 F23 L38 VSS_504
VSS_578 Y27 B
AK20 VSS_66VSS_139 BD54 CA58 VSS_212
VSS_285 DA11 EB26 VSS_358 VSS_431 F26 L40 VSS_505
VSS_579 Y32
AK25 VSS_67VSS_140 BE1 CB4 VSS_213
VSS_286 DA12 EB31 VSS_359 VSS_432 F28 L54 VSS_506
VSS_580 Y37
AK30 VSS_68VSS_141 BE12 CB6 VSS_214
VSS_287 DA6 EB8 VSS_360 VSS_433 F30 L9 VSS_507
VSS_581 Y4
VSS_69VSS_142 VSS_215
VSS_288 VSS_361 VSS_434 VSS_508
VSS_582
AK37 BE51 CB8 DA8 EC21 F33 M16 Y45
AK4 VSS_70VSS_143 BE55 CB9 VSS_216
VSS_289 DA9 EC28 VSS_362 VSS_435 F4 M21 VSS_509
VSS_583 Y47
AK57 VSS_71VSS_144 BE9 CC1 VSS_217
VSS_290 DB14 ED13 VSS_363 VSS_436 F40 M26 VSS_510
VSS_584 Y49
AK59 VSS_72VSS_145 BF46 CC52 VSS_218
VSS_291 DB4 ED4 VSS_364 VSS_437 F46 M31 VSS_511
VSS_585 Y54
AK9 VSS_73VSS_146 BF48 CD46 VSS_219
VSS_292 DB54 ED56 VSS_365 VSS_438 F47 M32 VSS_512
VSS_586
VSS_74VSS_147 VSS_220
VSS_293 VSS_366 VSS_439 VSS_513
F52 M34
VSS_440 VSS_514
16 OF 22 17 OF 22
18 OF 22 19 OF 22
INTEL_ADL-P-682_BGA1744
INTEL_ADL-P-682_BGA1744
@ INTEL_ADL-P-682_BGA1744 INTEL_ADL-P-682_BGA1744
@
@ @

A A

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PCH (8/8) VSS
Date: Wednesday, March 02, 2022 Sheet 22 of 108
5 4 3 2 1
 5 4 3 2 1

?
?

UC1U BMAP_REV = ?

TC7819 PAD @ 1 CFG15 AF37 A58 DDR_TP9 1 @ PAD TH3011

CFG_15 RSVD_TP_1 DDR_TP10
TC7818 PAD @ 1 CFG14 AH35 B59 1 @ PAD TH3032
1 AF35 CFG_14 RSVD_TP_18 D61 DDR_TP11 1 @
TC7817 PAD @ CFG13 PAD TH3033
1 CFG12 AH37 CFG_13 RSVD_TP_36
TC7816 PAD @
1 AH25 CFG_12 AF40 Digital_TP1 1 @
TC7815 PAD @ CFG11 PAD TH3034
1 AF20 CFG_11 RSVD_TP_4 AH40 Digital_TP2 1 @
TC7814 PAD @ CFG10 PAD TH3035
1 AH22 CFG_10 RSVD_TP_5
TC7813 PAD @ CFG9
1 AK17 CFG_9 DG44
TC7812 PAD @ CFG8
1 CFG7 AJ15 CFG_8 RSVD_TP_37 DH43
TC7811 PAD @
CFG_7 RSVD_TP_39
TC7810 PAD @ 1 CFG6 AH17
1 CFG5 AG15 CFG_6 BB11
TC7809 PAD @
D
TC7808
TC7807
TC7806
TC7805
PAD
PAD
PAD
PAD
@
@
@
@
1
1
1
1
CFG4
CFG3
CFG2
CFG1
AD11
AC12
AA12
AD16
CFG_5
CFG_4
CFG_3
CFG_2
VSS_588
VSS_589

RSVD_23
BE11

FB3
FC6
Pin STRAPS D

1 AA16 CFG_1 RSVD_25

TC7804 PAD @ CFG0
CFG_0 DY5 +3VS
CFG_RCOMP F8 RSVD_TP_46 DY6
CFG_RCOMP RSVD_TP_47
TC7820 PAD @ 1 CFG17 AF22 FC9
CFG_17 RSVD_27
TC7821 PAD @ 1 CFG16 AF17 FC7
CFG_16 RSVD_26

1
RC2460 1 2 1/20W_10K_5%_0201 BPM#_3 AF12 FB4
+VCC_CFG_PU_OUT BPM#_2 BPM#_3 RSVD_TP_53
RC2458 1 2 1/20W_10K_5%_0201 AH12 FC4
1 2 BPM#_1 AK12 BPM#_2 RSVD_TP_55
RC2459 1/20W_10K_5%_0201 @ RC2416
1 2 BPM#_0 AL12 BPM#_1 DT61 GPP_B18_NO_REBOOT
RC2457 1/20W_10K_5%_0201 1/20W_1K_5%_0201
BPM#_0 GPP_B18/ADR_COMPLETE

2
2
AK27 R4
AH27 RSVD_5 RSVD_28 AC9
RC1002
RSVD_3 RSVD_TP_3 GPP_B18_NO_REBOOT
1/20W_49.9_1%_0201 Place near PCH
CFG_VSS_590 AY12 DL1
VSS_587 RSVD_11
AT9 DL3
1

2
AT11 RSVD_TP_16 RSVD_12
RC1004 AP11 RSVD_TP_15 EU61
GPP_B18_NO_REBOOT
@ 0_0201_5% AP12 RSVD_TP_13 RSVD_22
EC18 Rising edge of PCH_PWROK
RSVD_TP_14 RSVD_14
BA14
RSVD_TP_19
The strap has a 20 kohm ± 30% internal pull-down.
DV46 0 = Disable ¨No Reboot〃 mode. (Default)

1
CT12 VSS_590 DV42
CR14 RSVD_TP_35 TP_4 DT47 1 = Enable ¨No Reboot〃 mode (PCH will disable the TCO Timer system
EK18 RSVD_TP_34 TP_1
CB11 reboot feature). This function is useful when running ITP/XDP.
EH18 RSVD_TP_51 RSVD_TP_30 BW11
RSVD_TP_50 RSVD_TP_29
AL25 AK35
AN25 RSVD_TP_6 SKTOCC#
RSVD_TP_10 AN27
RSVD_TP_11 AL27
RSVD_TP_7
AL35
RSVD_TP_8 AN35
RSVD_TP_12
C C
EL51
GPP_T3 EN51
GPP_T2
21 OF 22
INTEL_ADL-P-682_BGA1744
@

?
?

UC1T BMAP_REV = ?

EF48 BF43 DDR_TP1 1 @ PAD TH3031

RSVD_17 RSVD_TP_21 AA9
EF51 RSVD_TP_2 DJ9 +VCC_CFG_PU_OUT
RSVD_18 RSVD_TP_42
TH3036 PAD @ 1 ANA_TP1 FB58 DJ12 DDR_TP2 1 @ PAD TH3024
ANA_TP2 RSVD_TP_54 RSVD_TP_41
TH3037 PAD @ 1 EY61 AV12 1
RSVD_TP_52 VCC_CFG_PU_OUT CH43 DDR_TP3 1 @ PAD TH3025
EH48 RSVD_TP_31 DH14 DDR_TP4 1 @ PAD TH3026 CC3665
EF53 RSVD_21 RSVD_TP_38 DW32 DDR_TP5 1 @ PAD TH3027 0.1U_10V_K_X5R_0201
RSVD_19 RSVD_TP_43 BH14 DDR_TP6 1 2
@ PAD TH3028
DJ11 RSVD_TP_22 DW37 DDR_TP7 1 @ PAD TH3029
RSVD_TP_40 RSVD_TP_44 DDR_TP8
AL37 1 @ PAD TH3030
ANA_TP3 RSVD_TP_9
TH3038 PAD @ 1 EB16
ANA_TP4 RSVD_TP_49
TH3039 PAD @ 1 DY18
RSVD_TP_45
20 OF 22
INTEL_ADL-P-682_BGA1744
@

Pin Name Description Termination Resistor

B B
CFG[0,1] RSVD None

PCI Express* Pull-up to VCC_CFG_PU_OUT/

+VCC_CFG_PU_OUT CFG[2] Static x8(PEG 10/11) Lanes Pull-down-Platform design 1K
Numbering Reversal dependent

CFG[3] RSVD None

RC4285 1 2 1/20W_1K_5%_0201 CFG15 RC4286 1 @ 2 1/20W_1K_5%_0201
RC2432 1 2 1/20W_1K_5%_0201 CFG14 RC2439 1 @ 2 1/20W_1K_5%_0201
CFG[4] RSVD None

RC2434 1 2 1/20W_1K_5%_0201 CFG10 RC1009 1 @ 2 1/20W_1K_5%_0201 CFG[6:5] RSVD None

RC2433 1 2 1/20W_1K_5%_0201 CFG9 RC1011 1 @ 2 1/20W_1K_5%_0201

CFG[8:7] RSVD None

Pull-up to
CFG[10:9] RSVD VCC_CFG_PU_OUT

RC2431 1 2 1/20W_1K_5%_0201 CFG2 RC2435 1 @ 2 1/20W_1K_5%_0201 1K

CFG[13:11] RSVD None

PEG60 Lane Reversal: Pull-up to VCC_CFG_PU_OUT/

CFG[14] -1- (Default)Normal Pull-down-Platform design 1K
-0-Reversed dependent

PEG62 Lane Reversal: Pull-up to VCC_CFG_PU_OUT/

CFG[15] -1- (Default)Normal Pull-down-Platform design 1K
-0-Reversed dependent

A CFG[17:16] RSVD None A

Security Classification LCFC Highly Confidential Information Title

X60-TGL-H
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU (4/9) PM,XDP,CLK,CFG
Date: Wednesday, March 02, 2022 Sheet 23 of 108
5 4 3 2 1
 5 4 3 2 1

TABLE : CPU ITP DEBUG REPORT

Individual DCI 2.0

No use Port w/o connector +VCCST_CPU

R591 NO ASM NO ASM ASM

D D
@ 1 PAD RC2410 1 @ 2 0_0201_5% PCH_JTAG_TCK
R593 NO ASM NO ASM ASM

1/20W_100_1%_0201

1/20W_51_1%_0201

1/20W_51_1%_0201
ITH14 PCH_JTAG_TCK

2
R594 NO ASM NO ASM ASM RC2402 2 1 1/20W_51_1%_0201

RC2403

RC2417

RC2421
@
@ @
R595 NO ASM NO ASM ASM
R596 NO ASM NO ASM ASM

1
RC2415 1 @ 2 0_0201_5% XDP_TDO PAD 1 @
R657 NO ASM NO ASM ASM PCH_JTAG_TDO ITH9
RC2412 1 @ 2 0_0201_5% XDP_TDI PAD 1 @
R658 NO ASM NO ASM ASM PCH_JTAG_TDI ITH10
RC2405 1 @ 2 0_0201_5% XDP_TMS PAD 1 @
PCH_JTAG_TMS ITH11
R102 NO ASM ASM NO ASM RC2406 1 @ 2 0_0201_5% PCH_PROC_RST_N PAD 1 @
PCH_JTAG_TRST_N ITH12
R597 NO ASM ASM NO ASM RC2419 1 @ 2 0_0201_5% XDP_TCK0 PAD 1 @
PCH_JTAG_JTAGX ITH13
R9907 NO ASM ASM ASM
JXDP1 NO ASM ASM NO ASM

1/20W_51_1%_0201

1/20W_51_1%_0201
2

2
RC2420

RC2407
C70 NO ASM ASM NO ASM @
@
R96 NO ASM ASM NO ASM

1
+VCCST_CPU
R101 NO ASM ASM NO ASM

1
R9909 NO ASM ASM ASM
R9910 NO ASM ASM ASM DEFENSIVE A0 PO BOARDS.

1/20W_51_1%_0201
R9916 NO ASM ASM ASM INTERNAL 60 - 100OHM ODT TO GND

1/20W_51_1%_0201

2
RC2411

RC2422
R99 NO ASM ASM ASM @ @
R9912 NO ASM ASM ASM
C C

1
R9934 NO ASM ASM ASM
R9930 NO ASM ASM ASM
R9931 NO ASM ASM ASM
R9932 NO ASM ASM ASM
RC2404 1 @ 2 0_0201_5% XDP_TDO
R9933 NO ASM ASM ASM CPU_JTAG_TDO
RC2413 1 @ 2 0_0201_5% XDP_TDI
CPU_JTAG_TDI
RC2418 1 @ 2 0_0201_5% XDP_TMS
CPU_JTAG_TMS
LOGIC RC2414 1 @ 2 0_0201_5% XDP_TCK0
CPU_JTAG_TCK
RC2408 1 @ 2 0_0201_5% PCH_PROC_RST_N
TABLE : PCH ITP DEBUG REPORT CPU_JTAG_TRST_N

1/20W_51_1%_0201
RC2401
No use Individual DCI 2.0

1/20W_51_1%_0201
2
Port w/o connector

RC2409
@

1
R93 NO ASM ASM NO ASM

1
JXDP1 NO ASM ASM NO ASM
R9917 NO ASM ASM NO ASM
R101 NO ASM ASM NO ASM
R9908 NO ASM ASM NO ASM
R9911 NO ASM ASM NO ASM
B R9913 NO ASM ASM NO ASM B

R9915 NO ASM ASM NO ASM

LOGIC

www.teknisi-indonesia.com

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Wednesday, March 02, 2022 Sheet 24 of 108
5 4 3 2 1
 5 4 3 2 1

DDRA_DQ[63:0]
D D
DDRA_MA[16:0] +1.2V
+1.2V +1.2V +2.5V_DDR +1.2V +1.2V +0.6VS

2
+1.2V
RD1 +1.2V
JDIMM1A JDIMM1B 1/20W_240_1%_0201

1
1 2 DDRA_MA3 131 132 DDRA_MA2
DDRA_DQ62 VSS_1 VSS_2 DDRA_DQ61 DDRA_MA1 A3 A2 EVENT_N_1
3 4 133 134 RD3
5 DQ5 DQ4 6 135 A1 EVENT_n/NF 136 1/16W_1K_1%_0402
DDRA_DQ58 VSS_3 VSS_4 DDRA_DQ63 DDRA_CLK0_P VDD_9 VDD_10 DDRA_CLK1_P
7 8 137 138
9 DQ1 DQ0 10 DDRA_CLK0_P DDRA_CLK0_N 139 CK0_t CK1_t/NF 140 DDRA_CLK1_N DDRA_CLK1_P
Byte7[56~63]

2
DDRA_DQS7_N 11 VSS_5 VSS_6
12 DDRA_CLK0_N 141 CK0_c CK1_c/NF
142 DDRA_CLK1_N
DDRA_DQS7_N DDRA_DQS7_P DQS0_C DM0_n/DBl0_n DDRA_PARITY VDD_11 VDD_12 DDRA_MA0
13 14 143 144
DDRA_DQS7_P 15 DQS0_t VSS_7 16 DDRA_DQ57 DDRA_PARITY Parity A0
DDRA_DQ60 VSS_8 DQ6 M_VREF_CA_DIMMA
17 18 1/16W_2_1%_0402 1 2 RD7
DQ7 VSS_9 DDRA_DQ59 DDRA_BA1 DDRA_MA10 DDRA_VREF_CA_CPU
19 20 145 146
DDRA_DQ56 21 VSS_10 DQ2
22 DDRA_BA1 147 BA1 A10/AP
148
DQ3 VSS_11 VDD_13 VDD_14 1
23 24 DDRA_DQ46 DDRA_CS0_N 149 150 DDRA_BA0
DDRA_DQ47 25 VSS_12 DQ12 26 DDRA_CS0_N DDRA_MA14 151 CS0_n BA0 152 DDRA_MA16 DDRA_BA0
CD6

1
DQ13 VSS_13 DDRA_DQ44 A14/WE_n A16/RAS_n
27 28 153 154 0.022U_25V_K_X7R_0402_YAGEO

1
DDRA_DQ45 29 VSS_14 DQ8 30 DDRA_ODT0 155 VDD_15 VDD_16 156 DDRA_MA15 2 RD11
DDRA_ODT0

1
DQ9 VSS_15 DDRA_DQS5_N DDRA_CS1_N ODT0 A15/CAS_n DDRA_MA13
31 32 157 158 1/16W_1K_1%_0402 @ CD7
VSS_16 DQS1_c DDRA_DQS5_P DDRA_DQS5_N DDRA_CS1_N CS1_n A13
33 34 159 160 RD12 0.1U_16V_K_X7R_0402_MURATA
Byte5[40~47]

2
35 DM1_n/DBl_n DQS1_t 36 DDRA_DQS5_P DDRA_ODT1 161 VDD_17 VDD_18 162 1/16W_24.9_1%_0402
DDRA_ODT1

2
DDRA_DQ40 VSS_17 VSS_18 DDRA_DQ41 ODT1 C0/CS2_n/NC M_VREF_CA_DIMMA
37 38 163 164
39 DQ15 DQ14 40 165 VDD_19 VREFCA 166 SA2_CHA_P

2
DDRA_DQ42 VSS_19 VSS_20 DDRA_DQ43 C1/CS3_n/NC SA2
41 42 167 168
DQ10 DQ11 DDRA_DQ31 VSS_53 VSS_54 DDRA_DQ30
43 44 169 170 1 2

2.2U_6.3V_M_X5R_0402

0.1U_10V_K_X7R_0402
DDRA_DQ37 45 VSS_21 VSS_22 46 DDRA_DQ38 171 DQ37 DQ36 172 +1.2V @

CD1

CD2
DQ21 DQ20 DDRA_DQ28 VSS_55 VSS_56 DDRA_DQ29
47 48 173 174
DDRA_DQ39 49 VSS_23 VSS_24 50 DDRA_DQ36 175 DQ33 DQ32 176
DQ17 DQ16 DDRA_DQS3_N VSS_57 VSS_58 2 1
51 52 177 178
Byte4[32~39] DDRA_DQS4_N 53 VSS_25 VSS_26
54
DDRA_DQS3_N DDRA_DQS3_P 179 DQS4_c DM4_n/DBl4_n
180
DDRA_DQS4_N DDRA_DQS4_P 55 DQS2_c DM2_n/DBl2_n 56 Byte3[24~31] DDRA_DQS3_P 181 DQS4_t VSS_59 182 DDRA_DQ26
DDRA_DQS4_P DQS2_t VSS_27 DDRA_DQ34 DDRA_DQ27 VSS_60 DQ39
57 58 183 184
DDRA_DQ33 59 VSS_28 DQ22 60 185 DQ38 VSS_61 186 DDRA_DQ25
DQ23 VSS_29 DDRA_DQ32 DDRA_DQ24 VSS_62 DQ35
61 62 187 188
DDRA_DQ35 VSS_30 DQ18 DQ34 VSS_63 DDRA_DQ14
63 64 189 190
65 DQ19 VSS_31 66 DDRA_DQ55 DDRA_DQ15 191 VSS_64 DQ45 192
DDRA_DQ52 VSS_32 DQ28 DQ44 VSS_65 DDRA_DQ12
67 68 193 194
69 DQ29 VSS_33 70 DDRA_DQ53 DDRA_DQ13 195 VSS_66 DQ41 196
DDRA_DQ54 VSS_34 DQ24 DQ40 VSS_67 DDRA_DQS1_N
71 72 197 198
DQ25 VSS_35 DDRA_DQS6_N VSS_68 DQS5_c DDRA_DQS1_P DDRA_DQS1_N
73 74 199 200
75 VSS_36 DQS3_c 76 DDRA_DQS6_P DDRA_DQS6_N 201 DM5_n/DBl5_n DQS5_t 202 DDRA_DQS1_P Byte1[8~15]
77 DM3_n/DBl3_n DQS3_t
78
DDRA_DQS6_P Byte6[48~55] DDRA_DQ8 203 VSS_69 VSS_70
204 DDRA_DQ9
DDRA_DQ51 79
81
VSS_37
DQ30
VSS_38
DQ31
80
82
DDRA_DQ50
DDRA_DQ10
205
207
DQ46
VSS_71
DQ47
VSS_72
206
208 DDRA_DQ11
delete pull-up resistors for layout
C DDRA_DQ48 VSS_39 VSS_40 DDRA_DQ49 DQ42 DQ43 C
83 84 209 210
85 DQ26 DQ27 86 DDRA_DQ7 211 VSS_73 VSS_74 212 DDRA_DQ6 +3VS
VSS_41 VSS_42 DQ52 DQ53
87 88 213 214 +1.2V
89 CB5/NC CB4/NC 90 DDRA_DQ5 215 VSS_75 VSS_76 216 DDRA_DQ4

1
VSS_43 VSS_44 DQ49 DQ48
91 92 217 218
CB1/NC CB0/NC DDRA_DQS0_N VSS_77 VSS_78
93 94 219 220 RD5
95 VSS_45 VSS_46 96 DDRA_DQS0_N DDRA_DQS0_P 221 DQS6_c DM6_n/DBl6_n 222 @
97 DQS8_c DM8_n/DBl_n/NC
98 Byte0[0~7] DDRA_DQS0_P
223 DQS6_t VSS_79
224 DDRA_DQ1
1/20W_10K_5%_0201
99 DQS8_t VSS_47 100 DDRA_DQ0 225 VSS_80 DQ54 226

2
VSS_48 CB6/NC DQS5symbol 建错 VSS_81 DDRA_DQ3
101 102 227 228
CB2/NC VSS_49 DDRA_DQ2 VSS_82 DQ50 SA0_CHA_P SA1_CHA_P SA2_CHA_P
103 104 229 230
105 VSS_50 CB7/NC 106 231 DQ51 VSS_83 232 DDRA_DQ20
CB3/NC VSS_51 DRAMRST_N_R DDRA_DQ23 VSS_84 DQ60
107 108 233 234
DRAMRST_N_R

2
DDRA_CKE0 109 VSS_52 RESET_n 110 DDRA_CKE1 235 DQ61 VSS_85 236 DDRA_DQ22
DDRA_CKE0 111 CKE0 CKE1
112 DDRA_CKE1 DDRA_DQ21 237 VSS_86 DQ57
238 RD8 RD9 RD10
DDRA_BG1 VDD_1 VDD_2 DDRA_ACT_N +3VS DQ56 VSS_87 DDRA_DQS2_N
113 114 239 240 @ @ @
DDRA_BG1 DDRA_BG0 115 BG1 ACT_n 116 DDRA_ACT_N 241 VSS_88 DQS7_c 242 DDRA_DQS2_P DDRA_DQS2_N Byte2[16~23] 0_0201_5% 0_0201_5% 0_0201_5%
DDRA_BG0 BG0 ALERT_n DM7_n/DBl7_n DQS7_t DDRA_DQS2_P
117 118 243 244

1
2
DDRA_MA12 119 VDD_3 VDD_4 120 DDRA_MA11 DDRA_DQ17 245 VSS_89 VSS_90 246 DDRA_DQ19
DDRA_MA9 A12 A11 DDRA_MA7 DQ62 DQ63
121 122 RD2 247 248
A9 A7 DDRA_DQ18 VSS_91 VSS_92 DDRA_DQ16
123 124 @ 0_0402_5% 249 250
DDRA_MA8 125 VDD_5 VDD_6 126 DDRA_MA5 251 DQ58 DQ59 252
DDRA_MA6 A8 A5 DDRA_MA4 SMB_CLK_3VS VSS_93 VSS_94 SMB_DATA_3VS
127 128 253 254

1
129 A6 A4 130 SMB_CLK_3VS VDDSPD_1 255 SCL SDA 256 SA0_CHA_P SMB_DATA_3VS
VDD_7 VDD_8 VDDSPD SA0
1 257 258
VPP_1 VTT SA1_CHA_P
EMC_NS@ 259 260

ARGOS_D4AR0-26005-1P40
CD3
0.1U_25V_K_X5R_0201 PDG:0402 0.1uf*1 261
VPP_2 SA1
262
SPD Address = 0H
2 1 1 GND_1 GND_2
0402 2.2uf*1
ME@
CD4 CD5 ARGOS_D4AR0-26005-1P40
SP070015200 0.1U_6.3V_K_X7R_0201 2.2U_6.3V_M_X5R_0201
2 2 ME@
Capacitor CD3 is a defensive design and should be NO STUFF by default
SP070015200

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 DDR4 SUB CHANNEL-A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 25 of 108
5 4 3 2 1
 5 4 3 2 1

+1.2V
DDRB_CLK0_N

DDRB_DQ[0..63] 2 MD@
need Change to TBG code RD13 1 MD@ 2 1/20W_36_5%_0201 CD45 1 2 0.01U_10V_K_X7R_0201
UD1 +2.5V_DDR CD46 RD14 1 MD@ 2 1/20W_36_5%_0201
3.3P_50V_C_NPO_0201
DDRB_DQ55 D7 B1 UD2 +2.5V_DDR @ 1 Note: CLK termination must match the CLK reference plane.
DDRB_DQ49 D3 DQU7 VPP_B1
R9
DDRB_DQ53 C8 DQU6 VPP_R9 +VREF_CA_CHB DDRB_DQ28 D7 B1
DDRB_DQ50 C2 DQU5 DDRB_DQ24 D3 DQU7 VPP_B1 DDRB_CLK0_P
M1 R9
DQU4 VREFCA DQU6 VPP_R9

0.1U_6.3V_K_X5R_0201
D DDRB_DQ54 C7 DDRB_DQ29 C8 +VREF_CA_CHB DDRB_ALERT_N RD16 1 MD@ 2 1/20W_49.9_1%_0201 D
Byte6[48~55] DDRB_DQ51 C3 DQU3 B3 +1.2V 1
DDRB_DQ25 C2 DQU5 M1

CD47
1000P_50V_K_X7R_0201
DQU2 VDD_B3 DQU4 VREFCA

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
DDRB_DQ52 B8 B9 DDRB_DQ30 C7
DDRB_DQ48 A3 DQU1 VDD_B9 D1
1 1 Byte3[24~31] DDRB_DQ26 C3 DQU3 B3 +1.2V 1

CD49

CD50

CD51
1000P_50V_K_X7R_0201
DQU0 VDD_D1 DQU2 VDD_B3

0.1U_6.3V_K_X5R_0201
G7 MD@ 2 DDRB_DQ31 B8 B9 1 1
DDRB_DQS6_P VDD_G7 DDRB_DQ27 A3 DQU1 VDD_B9
B7 J1 D1

CD53

CD54
DDRB_DQS6_P DQSU_T VDD_J1 2 DQU0 VDD_D1
DDRB_DQS6_N
DDRB_DQS6_N A7 J9 MD@ MD@ 2 G7 MD@ 2
DQSU_C VDD_J9 DDRB_DQS3_P VDD_G7
L1 B7 J1
VDD_L1 DDRB_DQS3_P DQSU_T VDD_J1 2
+1.2V
E2 L9
DDRB_DQS3_N
DDRB_DQS3_N A7 J9 MD@ MD@ 2
DMU_n/DBIU_n VDD_L9 DQSU_C VDD_J9 +0.6VS
R1 L1
VDD_R1 VDD_L1
T9 E2 L9
VDD_T9 +1.2V DMU_n/DBIU_n VDD_L9 R1
DDRB_DQ58 J7 VDD_R1 DDRB_CS0_N
A1 T9 RD19 1 MD@ 2 1/20W_36_5%_0201
DDRB_DQ60 J3 DQL7 VDDQ_A1 A9 VDD_T9 DDRB_ODT0 1 MD@ 2 1/20W_36_5%_0201
RD20
DDRB_DQ62 H8 DQL6 VDDQ_A9 DDRB_DQ19 J7
C1 A1
DDRB_DQ57 H2 DQL5 VDDQ_C1 DDRB_DQ17 J3 DQL7 VDDQ_A1 DDRB_CKE0
D9 A9 RD21 1 MD@ 2 1/20W_36_5%_0201
DDRB_DQ61 H7 DQL4 VDDQ_D9 F2 DDRB_DQ20 H8 DQL6 VDDQ_A9 C1
Byte7[56~63] DDRB_DQ56 H3 DQL3 VDDQ_F2
F8 DDRB_DQ21 H2 DQL5 VDDQ_C1
D9 DDRB_MA0 RD22 1 MD@ 2 1/20W_36_5%_0201
DDRB_DQ59 F7 DQL2 VDDQ_F8 G1 DDRB_DQ23 H7 DQL4 VDDQ_D9 F2 DDRB_MA1 1 MD@ 2 1/20W_36_5%_0201
RD23
DDRB_DQ63 G2 DQL1 VDDQ_G1
G9 Byte2[16~23] DDRB_DQ16 H3 DQL3 VDDQ_F2
F8 DDRB_MA2 RD24 1 MD@ 2 1/20W_36_5%_0201
DQL0 VDDQ_G9 DDRB_DQ22 F7 DQL2 VDDQ_F8 DDRB_MA3
J2 G1 RD25 1 MD@ 2 1/20W_36_5%_0201
DDRB_DQS7_P G3 VDDQ_J2 J8 DDRB_DQ18 G2 DQL1 VDDQ_G1 G9
DDRB_DQS7_P DDRB_DQS7_N DQSL_t VDDQ_J8 DQL0 VDDQ_G9 DDRB_MA4
F3 J2 RD26 1 MD@ 2 1/20W_36_5%_0201
DDRB_DQS7_N DQSL_c DDRB_DQS2_P VDDQ_J2 DDRB_MA5
G3 J8 +1.2V RD27 1 MD@ 2 1/20W_36_5%_0201
DDRB_DQS2_P DDRB_DQS2_N DQSL_t VDDQ_J8 DDRB_MA6
E7 A2 F3 RD28 1 MD@ 2 1/20W_36_5%_0201
+1.2V DML_n/DBIL_n VSSQ_A2 DDRB_DQS2_N DQSL_c DDRB_MA7
A8 RD29 1 MD@ 2 1/20W_36_5%_0201
VSSQ_A8 C9 E7 A2
+1.2V

1
VSSQ_C9 DML_n/DBIL_n VSSQ_A2 DDRB_MA8
D2 A8 RD30 1 MD@ 2 1/20W_36_5%_0201
DDRB_CLK0_P K7 VSSQ_D2 D8 VSSQ_A8 C9 DDRB_MA9 1 MD@ 2 1/20W_36_5%_0201
DDRB_CLK0_P RD63 RD31
DDRB_CLK0_N CK_t VSSQ_D8 VSSQ_C9 DDRB_MA10
K8 E3 D2 1/16W_1.8K_1%_0402 RD32 1 MD@ 2 1/20W_36_5%_0201
DDRB_CLK0_N CK_c VSSQ_E3 DDRB_CLK0_P VSSQ_D2 DDRB_MA11
E8 K7 D8 RD33 1 MD@ 2 1/20W_36_5%_0201
DDRB_CKE0 VSSQ_E8 DDRB_CLK0_P DDRB_CLK0_N CK_t VSSQ_D8
K2 F1 K8 E3
DDRB_CKE0 DDRB_CLK0_N

2
CKE VSSQ_F1 CK_c VSSQ_E3 DDRB_MA12
H1 E8 RD34 1 MD@ 2 1/20W_36_5%_0201
DDRB_CS0_N L7 VSSQ_H1 H9 DDRB_CKE0 K2 VSSQ_E8 F1 DDRB_MA13 1 MD@ 2 1/20W_36_5%_0201
DDRB_CKE0 RD35
DDRB_CS0_N CS_n VSSQ_H9 CKE VSSQ_F1
H1 DDRB_WE_N 1 MD@ 2 1/20W_36_5%_0201
RD36
DDRB_ODT0 DDRB_CS0_N VSSQ_H1 +VREF_CA_CHB DDRB_CAS_N
K3 B2 L7 H9 RD64 1 2 RD38 1 MD@ 2 1/20W_36_5%_0201
DDRB_ODT0 ODT VSS_B2 DDRB_CS0_N CS_n VSSQ_H9 DDRB_VREF_CA_CPU
E1 1/16W_2.7_1%_0402
DDRB_ACT_N VSS_E1 DDRB_ODT0
L3 G8 K3 B2 1
DDRB_ACT_N ACT_n VSS_G8 DDRB_ODT0 ODT VSS_B2 DDRB_RAS_N
K1 E1 RD39 1 MD@ 2 1/20W_36_5%_0201
UD1_DDRB_BG1 VSS_K1 DDRB_ACT_N VSS_E1 DDRB_BG0
M9 K9 L3 G8 CD138 RD40 1 MD@ 2 1/20W_36_5%_0201
DDRB_ACT_N

1
DDRB_BG0 VSS_M9 VSS_K9 ACT_n VSS_G8 DDRB_BG1
M2 N1 K1 0.022U_25V_K_X7R_0402_YAGEO RD41 1 MD@ 2 1/20W_36_5%_0201
DDRB_BG0

1
BG0 VSS_N1 T1 UD2_DDRB_BG1 M9 VSS_K1 K9 2 RD65

1
DDRB_BA1 VSS_T1 DDRB_BG0 VSS_M9 VSS_K9 DDRB_BA0
N8 RD44 M2 N1 1/16W_1.8K_1%_0402 @ CD139 RD43 1 MD@ 2 1/20W_36_5%_0201
DDRB_BA1 DDRB_BA0 BA1 DDRB_BG0 BG0 VSS_N1 DDRB_BA1
N2 T7 1 @ 2 T1 RD66 0.1U_16V_K_X7R_0402_MURATA RD45 1 MD@ 2 1/20W_36_5%_0201
DDRB_BA0

2
BA0 NC DDRB_BA1 VSS_T1
N8 1/16W_24.9_1%_0402
DDRB_BA1

2
DDRB_RAS_N DDRB_BA0 BA1 DDRB_ACT_N
DDRB_RAS_N L8 1/20W_0_5%_0201 N2 T7 RD46 1 @ 2 RD47 1 MD@ 2 1/20W_36_5%_0201
DDRB_CAS_N RAS_n DDRB_BA0 BA0 NC DDRB_PARITY
DDRB_CAS_N M8 1/20W_0_5%_0201 RD52 1 MD@ 2 1/20W_36_5%_0201

2
DDRB_WE_N CAS_n DDRB_RAS_N
L2 DDRB_RAS_N L8
DDRB_WE_N WE_n/A14 DDRB_CAS_N RAS_n
DDRB_CAS_N M8
DDRB_MA13 T8 DRAMRST_N_R DDRB_WE_N L2 CAS_n
C
DDRB_MA13 DDRB_MA12 A13 DDRB_WE_N WE_n/A14 C
M7
DDRB_MA12 DDRB_MA11 A12/BC_n DDRB_MA13
T2 @ T8
DDRB_MA11 DDRB_MA10 A11 DRAMRST_N_R DDRB_MA13 DDRB_MA12 A13
M3 P1 CD59 1 2 0.1U_6.3V_K_X5R_0201 M7
DDRB_MA10 DDRB_MA9 A10/AP RESET_n DDRB_MA12 DDRB_MA11 A12/BC_n
R7 T2 @
DDRB_MA9 DDRB_MA8 A9 DDRB_PARITY DDRB_MA11 DDRB_MA10 A11 DRAMRST_N_R
R2 T3 M3 P1 CD60 1 2 0.1U_6.3V_K_X5R_0201
DDRB_MA8 DDRB_MA7 A8 PAR DDRB_PARITY DDRB_MA10 DDRB_MA9 A10/AP RESET_n
R8 R7
DDRB_MA7 DDRB_MA6 A7 DDRB_ALERT_N DDRB_MA9 DDRB_MA8 A9 DDRB_PARITY
P2 P9 R2 T3
DDRB_MA6 DDRB_MA5 A6 ALERT_n DDRB_MA8 DDRB_MA7 A8 PAR DDRB_PARITY
P8 R8
DDRB_MA5 DDRB_MA4 A5 UD1_DDRB_UZQ DDRB_MA7 DDRB_MA6 A7 DDRB_ALERT_N
N3 E9 P2 P9
DDRB_MA4 DDRB_MA3 A4 VSS_E9 DDRB_MA6 DDRB_MA5 A6 ALERT_n UD1_DDRB_UZQ
N7 P8 RD1756 1 2 1/20W_0_5%_0201
DDRB_MA3 DDRB_MA2 A3 UD1_DDRB_LZQ DDRB_MA5 DDRB_MA4 A5 UD2_DDRB_UZQ
R3 F9 N3 E9
DDRB_MA2 DDRB_MA1 P7 A2 ZQ DDRB_MA4 DDRB_MA3 N7 A4 VSS_E9 co-lay
DDRB_MA1 DDRB_MA0 A1 TEN_UD1_B DDRB_MA3 DDRB_MA2 A3 UD2_DDRB_LZQ
P3 N9 R3 F9
DDRB_MA0 A0 TEN DDRB_MA2 DDRB_MA1 A2 ZQ
P7
DDRB_MA1
1

DDRB_MA0 A1 TEN_UD2_B UD2_DDRB_UZQ

MD@ P3 N9 RD1757 1 2 1/20W_0_5%_0201
DDRB_MA0 A0 TEN
K4A8G165WB-BCPB_FBGA96 co-lay

1
@ RD53 MD@ RD54
1/20W_10K_5%_0201 1/20W_240_1%_0201 K4A8G165WB-BCPB_FBGA96 RD55 RD56
@ MD@ MD@
2

1/20W_10K_5%_0201 1/20W_240_1%_0201 UD3_DDRB_UZQ RD1758 1 2 1/20W_0_5%_0201

co-lay

2
UD4_DDRB_UZQ RD1759 1 2 1/20W_0_5%_0201
co-lay

SDP DDP

+2.5V_DDR
RD1755 RD1761 RD1754 RD1760
UD3 BG1 STUFF
DDRB_DQ15 +2.5V_DDR RD1763 RD1765 RD1762 RD1764
D7 B1 UD4
DDRB_DQ9 D3 DQU7 VPP_B1 R9
DDRB_DQ13 DQU6 VPP_R9 +VREF_CA_CHB DDRB_DQ39 D7 UD1_DDRB_BG1 RD1754 1
C8 B1 @ 2 1/20W_0_5%_0201 RD1756 RD1757 RD1718 RD1723
DDRB_DQ10 DQU5 DDRB_DQ34 D3 DQU7 VPP_B1 DDRB_BG1
C2 M1 R9 UZQ STUFF
0.1U_6.3V_K_X5R_0201

DDRB_DQ14 C7 DQU4 VREFCA DDRB_DQ37 C8 DQU6 VPP_R9 +VREF_CA_CHB RD1755 1 2 1/20W_0_5%_0201 RD1758 RD1759 RD1731 RD1735
Byte1[8~15] DDRB_DQ11 C3 DQU3
B3 +1.2V 1
DDRB_DQ33 C2 DQU5
M1
CD83

Byte4[32~39]
1000P_50V_K_X7R_0201

DQU2 VDD_B3 DQU4 VREFCA

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
DDRB_DQ12 B8 B9 DDRB_DQ38 C7
DQU1 VDD_B9 1 1 DQU3 +1.2V 1
DDRB_DQ8 A3 D1 DDRB_DQ35 C3 B3
CD95

CD96

CD97
1000P_50V_K_X7R_0201
DQU0 VDD_D1 DQU2 VDD_B3

0.1U_6.3V_K_X5R_0201
G7 MD@ 2 DDRB_DQ36 B8 B9 1 1
UD2_DDRB_BG1 RD1760 1 @ 2 1/20W_0_5%_0201
DDRB_DQS1_P B7 VDD_G7 J1 DDRB_DQ32 A3 DQU1 VDD_B9 D1

CD99

CD100
DDRB_DQS1_P DQSU_T VDD_J1 2 DQU0 VDD_D1
DDRB_DQS1_N
DDRB_DQS1_N A7 J9 MD@ MD@ 2 G7 MD@ 2 RD1761 1 2 1/20W_0_5%_0201
DQSU_C VDD_J9 L1 DDRB_DQS4_P B7 VDD_G7 J1
VDD_L1 DDRB_DQS4_P DQSU_T VDD_J1 2
+1.2V
E2 L9
DDRB_DQS4_N
DDRB_DQS4_N A7 J9 MD@ MD@ 2
B DMU_n/DBIU_n VDD_L9 DQSU_C VDD_J9 B
R1 L1
VDD_R1 T9 E2 VDD_L1 L9 UD3_DDRB_BG1 RD1762 1 2 1/20W_0_5%_0201
+1.2V @
VDD_T9 DMU_n/DBIU_n VDD_L9
R1
DDRB_DQ7 J7 A1 VDD_R1 T9 RD1763 1 2 1/20W_0_5%_0201
DDRB_DQ0 DQL7 VDDQ_A1 VDD_T9
J3 A9
DDRB_DQ5 DQL6 VDDQ_A9 DDRB_DQ40 J7
H8 C1 A1
DDRB_DQ2 H2 DQL5 VDDQ_C1 D9 DDRB_DQ47 J3 DQL7 VDDQ_A1 A9
Byte0[0~7] DDRB_DQ6 DQL4 VDDQ_D9 DDRB_DQ41 H8 DQL6 VDDQ_A9 UD4_DDRB_BG1 RD1764 1
source 8Gb
H7 F2 C1 @ 2 1/20W_0_5%_0201
DDRB_DQ1 H3 DQL3 VDDQ_F2 F8 DDRB_DQ46 H2 DQL5 VDDQ_C1 D9
DDRB_DQ4 F7 DQL2 VDDQ_F8
G1 Byte5[40~47] DDRB_DQ42 H7 DQL4 VDDQ_D9
F2 RD1765 1 2 1/20W_0_5%_0201
DDRB_DQ3 DQL1 VDDQ_G1 DDRB_DQ44 H3 DQL3 VDDQ_F2 Samsung K4A8G165WC-BCWE SA0000C6N00 NOT USE
G2 G9 F8
DQL0 VDDQ_G9 J2 DDRB_DQ43 F7 DQL2 VDDQ_F8 G1
DDRB_DQS0_P VDDQ_J2 DDRB_DQ45 G2 DQL1 VDDQ_G1
G3 J8 G9
DDRB_DQS0_P DDRB_DQS0_N DQSL_t VDDQ_J8 DQL0 VDDQ_G9
F3 J2 SK
DDRB_DQS0_N DQSL_c DDRB_DQS5_P G3 VDDQ_J2
J8 H5AN8G6NDJR-XNC
E7 A2
DDRB_DQS5_P DDRB_DQS5_N F3 DQSL_t VDDQ_J8 NOT USE
+1.2V DML_n/DBIL_n VSSQ_A2
VSSQ_A8
A8
C9
DDRB_DQS5_N
E7
DQSL_c
A2
RD1755,RD1761,RD1763,RD1765 must be placed very close to ball.
VSSQ_C9 +1.2V DML_n/DBIL_n VSSQ_A2 Micron MT40A512M16TB-062E:R
D2 A8
DDRB_CLK0_P K7 VSSQ_D2
D8 VSSQ_A8
C9 NOT USE
DDRB_CLK0_P
DDRB_CLK0_N
DDRB_CLK0_N K8 CK_t
CK_c
VSSQ_D8
VSSQ_E3
E3
E8 DDRB_CLK0_P K7
VSSQ_C9
VSSQ_D2
D2
D8
resistor to ball < 10mil
DDRB_CKE0 VSSQ_E8 DDRB_CLK0_P DDRB_CLK0_N CK_t VSSQ_D8
K2 F1 K8 E3 source 16Gb
DDRB_CKE0 CKE VSSQ_F1 DDRB_CLK0_N CK_c VSSQ_E3
H1 E8
DDRB_CS0_N VSSQ_H1 DDRB_CKE0 VSSQ_E8
L7 H9 K2 F1
DDRB_CS0_N CS_n VSSQ_H9 DDRB_CKE0 CKE VSSQ_F1
H1 Samsung
DDRB_ODT0 K3 B2 DDRB_CS0_N L7 VSSQ_H1 H9 K4AAG165WB-BCWE SA0000C6N00 SDP
DDRB_ODT0 ODT VSS_B2 DDRB_CS0_N CS_n VSSQ_H9
E1
DDRB_ACT_N L3 VSS_E1 G8 DDRB_ODT0 K3 B2
DDRB_ACT_N ACT_n VSS_G8 DDRB_ODT0 ODT VSS_B2
K1 E1 SK
UD3_DDRB_BG1 M9 VSS_K1
K9 DDRB_ACT_N L3 VSS_E1
G8 H5ANAG6NCJR-XNC SA0000B5K00 SDP
DDRB_BG0 VSS_M9 VSS_K9 DDRB_ACT_N ACT_n VSS_G8
M2 N1 K1
DDRB_BG0 BG0 VSS_N1 UD4_DDRB_BG1 VSS_K1
T1 M9 K9
DDRB_BA1 N8 VSS_T1 DDRB_BG0 M2 VSS_M9 VSS_K9 N1
RD57 Micron
DDRB_BA1 DDRB_BA0 N2 BA1
T7 1 @ 2
DDRB_BG0 BG0 VSS_N1
T1 MT40A1G16RC-062E:B SA0000A4K10 SDP
DDRB_BA0 BA0 NC DDRB_BA1 VSS_T1
N8 RD58
DDRB_RAS_N DDRB_BA1 DDRB_BA0 BA1
DDRB_RAS_N L8 1/20W_0_5%_0201 N2 T7 1 @ 2
DDRB_CAS_N RAS_n DDRB_BA0 BA0 NC
DDRB_CAS_N M8
DDRB_WE_N L2 CAS_n DDRB_RAS_N L8
DDRB_WE_N DDRB_RAS_N 1/20W_0_5%_0201
WE_n/A14 DDRB_CAS_N RAS_n
DDRB_CAS_N M8
DDRB_MA13 DDRB_WE_N CAS_n
T8 L2
DDRB_MA13 DDRB_MA12 A13 DDRB_WE_N WE_n/A14
M7
DDRB_MA12 DDRB_MA11 A12/BC_n DDRB_MA13
T2 @ T8
DDRB_MA11 DDRB_MA10 A11 DRAMRST_N_R DDRB_MA13 DDRB_MA12 A13
M3 P1 CD125 1 2 0.1U_6.3V_K_X5R_0201 M7
DDRB_MA10 DDRB_MA9 A10/AP RESET_n DDRB_MA12 DDRB_MA11 A12/BC_n
R7 T2 @
DDRB_MA9 DDRB_MA8 A9 DDRB_PARITY DDRB_MA11 DDRB_MA10 A11 DRAMRST_N_R
R2 T3 M3 P1 CD1261 2 0.1U_6.3V_K_X5R_0201
DDRB_MA8 DDRB_MA7 A8 PAR DDRB_PARITY DDRB_MA10 DDRB_MA9 A10/AP RESET_n
R8 R7
DDRB_MA7 DDRB_MA6 A7 DDRB_ALERT_N DDRB_MA9 DDRB_MA8 A9 DDRB_PARITY
P2 P9 R2 T3
DDRB_MA6 DDRB_MA5 A6 ALERT_n DDRB_MA8 DDRB_MA7 A8 PAR DDRB_PARITY
P8 R8
DDRB_MA5 DDRB_MA4 A5 UD3_DDRB_UZQ DDRB_MA7 DDRB_MA6 A7 DDRB_ALERT_N
N3 E9 P2 P9
A
DDRB_MA4 DDRB_MA3 A4 VSS_E9 DDRB_MA6 DDRB_MA5 A6 ALERT_n A
N7 P8
DDRB_MA3 DDRB_MA2 A3 UD3_DDRB_LZQ DDRB_MA5 DDRB_MA4 A5 UD4_DDRB_UZQ
R3 F9 N3 E9
DDRB_MA2 DDRB_MA1 A2 ZQ DDRB_MA4 DDRB_MA3 A4 VSS_E9
P7 N7
DDRB_MA1 DDRB_MA0 A1 TEN_UD3_B DDRB_MA3 DDRB_MA2 A3 UD4_DDRB_LZQ
P3 N9 R3 F9
DDRB_MA0 A0 TEN DDRB_MA2 DDRB_MA1 A2 ZQ
P7
DDRB_MA1
1

DDRB_MA0 A1 TEN_UD4_B
P3 N9
DDRB_MA0 A0 TEN
K4A8G165WB-BCPB_FBGA96 MD@
1

@ RD59 MD@ RD60 MD@

1/20W_10K_5%_0201 1/20W_240_1%_0201 K4A8G165WB-BCPB_FBGA96
@ RD61 MD@ RD62
2

1/20W_10K_5%_0201 1/20W_240_1%_0201
2

Security Classification LC Future Center Secret Data Title

Issued Date 2019/10/29 Deciphered Date 2019/10/29 DDR4 SUB CHANNEL-B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 26 of 108
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH

RB520CM-30T2R_VMN2M2
SPI ROM SPI_CS0_N_R 1
JBIOS
2 +3V_SPI

1
SPI_MISO_IO1_32MB_R 3 1 2 4 SPI_IO3_32MB_R

2
SPI_IO2_32MB_R 5 3 4 6 SPI_CLK_32MB_R R13
7 5 6 8 SPI_MOSI_IO0_32MB_R @ 1/16W_0_5%_0402
7 8

1
D4
ME@

2
CLINK_ZP91-03502-0821
D D
2
C14

0.1U_6.3V_K_X5R_0201_MURATA
1

UB1
PCH_SPI0_CS0_N R14 1 @ 2 0_0201_5% SPI_CS0_N_R 1 8 +3V_SPI
PCH_SPI0_CS0_N PCH_SPI0_SO SPI_MISO_IO1_32MB_R /CS VCC SPI_IO3_32MB_R PCH_SPI0_IO3
PCH_SPI0_SO R2004 1 2 1/20W_15_5%_0201 2 7 R2005 1 2 1/20W_49.9_1%_0201
PCH_SPI0_IO2 1 2 1/20W_49.9_1%_0201 SPI_IO2_32MB_R 3 IO1 IO3 6 SPI_CLK_32MB_R PCH_SPI0_CLK PCH_SPI0_IO3
R2006 R2007 1 2 1/20W_15_5%_0201
PCH_SPI0_IO2 IO2 CLK SPI_MOSI_IO0_32MB_R PCH_SPI0_SI PCH_SPI0_CLK
4 5 R2008 1 2 1/20W_15_5%_0201
GND IO0 9 PCH_SPI0_SI
PAD_GND 2
C15
W25R512JVEIN_WSON8_8X6 0.1U_6.3V_K_X5R_0201_MURATA
1

C C

+3VS VCC3_SUS_TPM VCC3_SUS_TPM

TPM IC +3VALW_PCH
RM1 1 @ 2 1/16W_0_5%_0402
VCC3_SUS_TPM

2 2 2 2
@ TPM@ @ TPM@
RM2 1 @ 2 0_0402_5% 2 CM1 CM2 CM3 CM4
0.1U_6.3V_K_X5R_0201_MURATA 0.1U_6.3V_K_X5R_0201_MURATA 0.1U_6.3V_K_X5R_0201_MURATA 10U_6.3V_M_X5R_0402
@ 1 1 1 1

RM3
1/20W_10K_5%_0201
1

Close to Pin1, Pin8, Pin22

UM1

22

1
ST33HTPH2X32AHE0
TPM@

VHIO2

VHIO1

VSB
TPM_IRQ_N RM4 1 @ 2 0_0201_5% TPM_IRQ_N_R 18 2
TPM_IRQ_N PIRQ#/GPIO2 NC1 3
NC2
4 TABLE of TPM (UM1)
PCH_SPI0_SI 1 TPM@ 2 1/20W_15_5%_0201 SPI_SI_TPM 21 PP/GPIO6 5
RM5
PCH_SPI0_SO RM6 1 TPM@ 2 1/20W_15_5%_0201 SPI_SO_TPM 24 MOSI/GPIO7 NC3 9 Vendor P/N LCFC P/N
B MISO NC5 10 B
NC6 11 Nuvoton NPCT760LAAYX SA0000C3000
NC7 12 VCC3_SUS_TPM
PCH_SPI0_CS2_N RM7 1 @ 2 0_0201_5% SPI_CS2_N_R_TPM 20 NC8 13 ST Micro ST33HTPH2X32AHE0 SA0000C8600
PCH_SPI0_CS2_N SCS#/GPIO5 GPIO4
14 RM12 1 @ 2 0_0201_5%
PCH_SPI0_CLK RM8 1 TPM@ 2 1/20W_15_5%_0201 SPI_CLK_R_TPM 19 NC9 15 INFINEON SLB 9672VU2.0 FW15.20SA0000C3300
SCLK NC10 16
1 TPM@ 2 1/20W_200_1%_0201 PLT_RST_N_R_TPM 17 GND1 25
RM9
PCH_PLT_RST_N PLTRST# NC11 26
NC12
6 27
GPIO3 NC13
NC14
28 RM10,RM11,RM12 stuff when using INFINEON TPM
7 31
NC4 NC15
32
NC16
29
SDA/GPIo0 30
SCL/GPIO1
GND2

GND3
23

33

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 SPI FLASH

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 27 of 108
5 4 3 2 1
 5 4 3 2 1

+1.8VGS +1.8VGS

2
RG2601 OPT@
@ 0_0201_5% RG2602
1/20W_10K_5%_0201

1
UG11A
VGA_PWRGD_R
D 1/14 PCI_EXPRESS D

1 +1.0VGS
CG2609
OPT_NS@
0.1U_6.3V_K_X5R_0201 PEX_WAKE_N,Leave unconnected and folating AG30

2
2 PEX_WAKE_N AA25
PLT_RST_VGA_N AG29 PEX_DVDD_1 U25
PLT_RST_VGA_N PEX_RST_N PEX_DVDD_2
OPT@ QG2601 V25
1 3 CLK_REQ_GPU_N AG31 PEX_DVDD_3 V26
GPU_CLKREQ_N PEX_CLKREQ_N PEX_DVDD_4
W25
CLK_PCIE3_GPU_P AE30 PEX_DVDD_5 Y25
CLK_PCIE3_GPU_P CLK_PCIE3_GPU_N AE31 PEX_REFCLK PEX_DVDD_6 Y26
LSI1012XT1G_SC-89-3
CLK_PCIE3_GPU_N PEX_REFCLK_N PEX_DVDD_7
PEG_GPU_TXB0_P OPT@ CG2601 1 2 0.22U_6.3V_K_X5R_0201 PEG_GPU_C_TXB0_P AC27
PEG_GPU_TXB0_P PEG_GPU_TXB0_N PEG_GPU_C_TXB0_N PEX_TX0
OPT@ CG2602 1 2 0.22U_6.3V_K_X5R_0201 AC28
PEG_GPU_TXB0_N PEX_TX0_N
PEG_GPU_C_RXB0_P AC30
PEG_GPU_C_RXB0_P PEG_GPU_C_RXB0_N PEX_RX0
AC31
PEG_GPU_C_RXB0_N PEX_RX0_N
PEG_GPU_TXB1_P OPT@ CG2603 1 2 0.22U_6.3V_K_X5R_0201 PEG_GPU_C_TXB1_P AA27
PEG_GPU_TXB1_P PEG_GPU_TXB1_N PEG_GPU_C_TXB1_N PEX_TX1
OPT@ CG2604 1 2 0.22U_6.3V_K_X5R_0201 AA28
PEG_GPU_TXB1_N PEX_TX1_N
PEG_GPU_C_RXB1_P AA31
PEG_GPU_C_RXB1_P PEG_GPU_C_RXB1_N AA30 PEX_RX1
PEG_GPU_C_RXB1_N PEX_RX1_N
PEG_GPU_TXB2_P OPT@ CG2605 1 2 0.22U_6.3V_K_X5R_0201 PEG_GPU_C_TXB2_P W27
PEG_GPU_TXB2_P PEG_GPU_TXB2_N PEG_GPU_C_TXB2_N PEX_TX2
OPT@ CG2606 1 2 0.22U_6.3V_K_X5R_0201 W28
PEG_GPU_TXB2_N PEX_TX2_N
PEG_GPU_C_RXB2_P W31
PEG_GPU_C_RXB2_P PEG_GPU_C_RXB2_N PEX_RX2
W30
PEG_GPU_C_RXB2_N PEX_RX2_N
PEG_GPU_TXB3_P OPT@ CG2607 1 2 0.22U_6.3V_K_X5R_0201 PEG_GPU_C_TXB3_P U28 PEX_CVDD_1 AB25
PEG_GPU_TXB3_P PEG_GPU_TXB3_N PEG_GPU_C_TXB3_N PEX_TX3
OPT@ CG2608 1 2 0.22U_6.3V_K_X5R_0201 U27 AB26
PEG_GPU_TXB3_N PEX_TX3_N PEX_CVDD_2
PEG_GPU_C_RXB3_P U30 PEX_HVDD
PEG_GPU_C_RXB3_P PEG_GPU_C_RXB3_N PEX_RX3
U31
PEG_GPU_C_RXB3_N PEX_RX3_N
C AC25 C
PEX_HVDD_1 AD25
PEX_HVDD_2 AE26
PEX_HVDD_3 AE27
PEX_HVDD_4 AE28
PEX_HVDD_5

2
OPT_NS@
RG5194
1/20W_5.6K_5%_0201 +1.8VGS

1 AD26 PEX_PLL_HVDD RG2604 1 @ 2 0_5%_0603

PEX_PLL_HVDD
RG5193 1 2 1/20W_0_5%_0201 VGA_PWRGD_R
VGA_PWRGD
OPT_NS@
1 1
OPT_NS@ OPT@
CG3804 CG2610
0.1U_10V_K_X5R_0201 1U_6.3V_M_X6S_0201
2 2

Under GPU
(below 150mils)

B B

R30 PEX_CVDD_SENSE 1 @ PAD TPG1

PEX_CVDD_SENSE

R31 PEX_TERMP 2 OPT@ 1 RG2605

PEX_TERMP
1/16W_2.49K_1%_0402

A NVIDIA_GN20-S5-GB3-64_FCBGA771 A
OPT_NS@

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 S550-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 28 of 108
5 4 3 2 1
 5 4 3 2 1

UG11I
3/14 IFPAB UG11J UG11K UG11L
4/14 IFPC 5/14 IFPD 6/14 IFPE

AF12 AF11
IFPCD_RSET IFPE_RSET
AL20
IFPA_L3_N AL21
AG26 IFPA_L3 AG11 AH9 AH8
IFPAB_RSET IFPC_AUX_SDA_N AG12 IFPD_AUX_SDA_N AG9 AF9 IFPE_AUX_SDA_N AG8
AK21 IFPC_AUX_SCL IFPD_AUX_SCL IFPE_PLLVDD IFPE_AUX_SCL
IFPA_L2_N
AJ21
IFPA_L2 AJ18 AJ12 AL8

1
IFPC_L3_N IFPD_L3_N IFPE_L3_N
AE11 AE9 AK18 AK12 AK8
D IFPAB_PLLVDD AJ23 IFPCD_PLLVDD IFPC_L3 IFPD_L3 IFPE_L3 D
RG5172
IFPA_L1_N AK23 AJ20 AK14 AL9
OPT@
IFPA_L1 IFPC_L2_N IFPD_L2_N IFPE_L2_N
AK20 AJ14 1/20W_10K_1%_0201 AK9
IFPC_L2 IFPD_L2 IFPE_L2

2
AL24 AL17 AJ15 AJ11
IFPA_L0_N AL23 IFPC_L1_N AL18 IFPD_L1_N AK15 IFPE_L1_N AK11
IFPA_L0 IFPC_L1 IFPD_L1 IFPE_L1
1

1
AJ17 AL15 AL11
AG18 IFPC_L0_N AK17 IFPD_L0_N AL14 IFPE_L0_N AL12
RG5170 RG5171
IFPA_AUX_SDA_N IFPC_L0 IFPD_L0 IFPE_L0
AG17
IFPA_AUX_SCL
OPT@ 1/20W_10K_1%_0201 OPT@ 1/20W_10K_1%_0201
2

2
AK27 AG20 AE17
IFPB_L3_N AJ27 AG21 IFP_IOVDD_9 AE18 IFP_IOVDD_1
IFPB_L3 IFP_IOVDD_10 IFP_IOVDD_2
AE20
AE21 IFP_IOVDD_3
AJ26 IFP_IOVDD_4
NVIDIA_GN20-S5-GB3-64_FCBGA771 NVIDIA_GN20-S5-GB3-64_FCBGA771
IFPB_L2_N
AK26 OPT_NS@ OPT_NS@
IFPB_L2
NVIDIA_GN20-S5-GB3-64_FCBGA771
OPT_NS@
AK24
IFPB_L1_N AJ24
IFPB_L1

AL27
IFPB_L0_N AL26
IFPB_L0

AG15
AF17 IFPB_AUX_SDA_N AG14
AF18 IFP_IOVDD_5 IFPB_AUX_SCL
AF20 IFP_IOVDD_6
AF21 IFP_IOVDD_7
IFP_IOVDD_8

NVIDIA_GN20-S5-GB3-64_FCBGA771
+1.8VGS
OPT_NS@
C CORE_PLLVDD UG11N C
8/14 XTAL_PLL

AE15

OPT_NS@
2
AE12 CORE_PLL_AVDD
GPCADC_AVDD
AF8 RG2704
SP_PLLVDD
1/20W_100K_5%_0201
AE8
VID_PLLVDD

1
150mA
UG11M
9/14 MISC2

XTALSSIN AG2 AJ1 XTALOUTBUFF

EXT_REFCLK_FL XTAL_OUTBUFF

18P_25V_J_COG_0201 1/20W_10K_5%_0201
1

1/20W_10K_5%_0201
ROM_CS0_N XTAL_IN XTAL_OUT

OPT@
V7 AK2 AJ2

RG5211

RG2703
OPT_NS@
ROM_CS_N XTAL_IN XTAL_OUT
U7 ROM_SI NVIDIA_GN20-S5-GB3-64_FCBGA771
ROM_SI V6 ROM_SO ROM_SI
ROM_SO OPT_NS@

2
AG4 ROM_SO U6 ROM_SCLK
STRAP0

OPT_GN18S@
STRAP0 AG3 STRAP0 ROM_SCLK ROM_SCLK
STRAP1 RG2705
STRAP1 STRAP1
STRAP2 AG6 1/20W_100K_5%_0201
STRAP2 STRAP2
STRAP3 AH5
STRAP3 AH6 STRAP3
STRAP4 1
STRAP4

1
STRAP4
STRAP5 AG5

OPT_NS@

CG3806
STRAP5 STRAP5

B B

RG2706 1 OPT@ 2 1/16W_10M_5%_0402 XTAL_OUT

NVIDIA_GN20-S5-GB3-64_FCBGA771

1
OPT_NS@
RG2707
@ 0_0201_5%

2
YG1
+1.8VGS +1.8VGS 4 3 XTAL_OUT_R
XTAL_IN NC2 3
0.1U_6.3V_K_X5R_0201

1
10U_6.3V_M_X6S_0402

1 1 1 2 CG2711
2

1 NC1
CG2713

RG2708 27MHZ_10PF_7R27000002 OPT@ 12P_50V_J_NPO_0402

CG2712

1
2
OPT@

OPT@ CG2710
OPT_NS@

1/20W_10K_5%_0201 OPT@
2 2
OPT@ 12P_50V_J_NPO_0402
1

2
UG12
ROM_CS0_N RG2709 1 OPT@ 2 1/20W_33_5%_0201 ROM_CS_N_R 1 8
ROM_SO ROM_SO_R CS# VCC
RG2710 1 @ 2 0_0201_5% 2 7
GPIO26_ROM_WP 3 DO HOLD# 6 ROM_SCLK_R ROM_SCLK
RG2711 1 OPT@ 2 1/20W_33_5%_0201
GPIO26_ROM_WP WP# CLK ROM_SI_R ROM_SI
4 5 RG2712 1 OPT@ 2 1/20W_33_5%_0201
GND DI change at 6/16
W25Q80EWSNIG_SO8
OPT_GN18S@

+1.8VGS

OPT_GN18S@ OPT_GN20S@
RG5116 1 2 1/20W_10K_5%_0201 GPIO26_ROM_WP RG5117 1 2 1/20W_10K_5%_0201

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 S550-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 29 of 108
5 4 3 2 1
 5 4 3 2 1

UG11B
2/14 FBA

+FB_PLLAVDD

FBA_D0 H6 G24
D FBA_D1 F6 FBA_D0 FB_PLLVDD_1 H7 D
FBA_D2 F5 FBA_D1 FB_PLLVDD_2
FBA_D3 FBA_D2
F4
FBA_D4 E3 FBA_D3
FBA_D5 E8 FBA_D4
FBA_D6 D6 FBA_D5
FBA_D7 E4 FBA_D6
FBA_D8 H4 FBA_D7
FBA_D9 J6 FBA_D8
FBA_D10 FBA_D9
J4
FBA_D11 L5 FBA_D10
FBA_D12 L4 FBA_D11
FBA_D13 H5 FBA_D12
FBA_D14 R6 FBA_D13 FBA_CMD[0..24]
FBA_D14

teknisi-indonesia.com
FBA_D15 J3 F11 FBA_CMD0
FBA_D16 B5 FBA_D15 FBA_CMD0 A12 FBA_CMD1
FBA_D17 F2 FBA_D16 FBA_CMD1 D11 FBA_CMD2
FBA_D18 FBA_D17 FBA_CMD2 FBA_CMD3
B3 B12
FBA_D19 C3 FBA_D18 FBA_CMD3 D12 FBA_CMD4
FBA_D20 FBA_D19 FBA_CMD4 FBA_CMD5
A3 C12
FBA_D21 C2 FBA_D20 FBA_CMD5 F12 FBA_CMD6
FBA_D22 B2 FBA_D21 FBA_CMD6 D14 FBA_CMD7
FBA_D23 FBA_D22 FBA_CMD7 FBA_CMD8
C1 B14
FBA_D24 M4 FBA_D23 FBA_CMD8 A14 FBA_CMD9
FBA_D25 M1 FBA_D24 FBA_CMD9 A15 FBA_CMD10
FBA_D26 M2 FBA_D25 FBA_CMD10 C14 FBA_CMD11
FBA_D27 M3 FBA_D26 FBA_CMD11 B15 FBA_CMD12
FBA_D28 FBA_D27 FBA_CMD12 FBA_CMD13
P1 A9
FBA_D29 P3 FBA_D28 FBA_CMD13 E11 FBA_CMD14
FBA_D[0..63] FBA_D30 FBA_D29 FBA_CMD14 FBA_CMD15 FBVDDQ FBVDDQ
R4 C9
FBA_D31 J2 FBA_D30 FBA_CMD15 C11 FBA_CMD16
FBA_D32 H26 FBA_D31 FBA_CMD16 E12 FBA_CMD17
FBA_D33 F27 FBA_D32 FBA_CMD17 C15 FBA_CMD18
FBA_EDC[7..0] FBA_D34 E29 FBA_D33 FBA_CMD18 A11 FBA_CMD19
FBA_D35 FBA_D34 FBA_CMD19 FBA_CMD20
F28 C8
FBA_DBI[7..0]

1
FBA_D36 E26 FBA_D35 FBA_CMD20 B8 FBA_CMD21
FBA_D37 E28 FBA_D36 FBA_CMD21 A8 FBA_CMD22 RG2801 RG2802 RG5164 RG5165
C FBA_D38
FBA_D39
F26
D26
FBA_D37
FBA_D38
FBA_CMD22
FBA_CMD23
B11
B9
FBA_CMD23
FBA_CMD24
CKE_A 1/20W_10K_1%_0201
1/20W_10K_1%_0201 CKE_B 1/20W_10K_1%_0201
1/20W_10K_1%_0201 C

FBA_D40 J28 FBA_D39 FBA_CMD24 F14 FBA_CMD25

2
FBA_D41 R27 FBA_D40 FBA_CMD25_NC F15 FBA_CMD26
FBA_D42 J26 FBA_D41 FBA_CMD26_NC E14 FBA_CMD27 FBA_CMD14 OPT@ OPT@ FBA_CMD17 OPT@ OPT@
FBA_D43 FBA_D42 FBA_CMD27 FBA_CMD28 FBA_CMD[28..52]
R26 D20
FBA_D44 L28 FBA_D43 FBA_CMD28 C24 FBA_CMD29 FBA_CMD44 FBA_CMD41
FBA_D45 FBA_D44 FBA_CMD29 FBA_CMD30
H27 F20
FBA_D46 H28 FBA_D45 FBA_CMD30 B24 FBA_CMD31
FBA_D47 J29 FBA_D46 FBA_CMD31 F21 FBA_CMD32
FBA_D48 FBA_D47 FBA_CMD32 FBA_CMD33 FBA_CMD3 FBVDDQ
B27 A24
FBA_D49 F30 FBA_D48 FBA_CMD33 D21 FBA_CMD34
FBA_D50 E30 FBA_D49 FBA_CMD34 B18 FBA_CMD35 FBA_CMD31
FBA_D51
FBA_D52
F31
B29
FBA_D50
FBA_D51
FBA_CMD35
FBA_CMD36
C17
A18
FBA_CMD36
FBA_CMD37
Debug
RESET

OPT_GN18S_NS@

OPT_GN18S_NS@
OPT@ 1

OPT@ 1
FBA_D53 C31 FBA_D52 FBA_CMD37 A17 FBA_CMD38

1
FBA_D54 C29 FBA_D53 FBA_CMD38 B17 FBA_CMD39 RG2803 RG2804
FBA_D55 FBA_D54 FBA_CMD39 FBA_CMD40
B30 D17 1/20W_10K_1%_0201 1/20W_10K_1%_0201 RG5168 RG5169
FBA_D56 M29 FBA_D55 FBA_CMD40 B23 FBA_CMD41 1/20W_60.4_1%_0201 1/20W_60.4_1%_0201
FBA_D57 M30 FBA_D56 FBA_CMD41 C23 FBA_CMD42

2
FBA_D58 M28 FBA_D57 FBA_CMD42 C21 FBA_CMD43

2
FBA_D59 M31 FBA_D58 FBA_CMD43 B21 FBA_CMD44
FBA_D60 J30 FBA_D59 FBA_CMD44 A21 FBA_CMD45 FBA_CMD27
FBA_D61 P30 FBA_D60 FBA_CMD45 A20 FBA_CMD46 FBA_CMD55

1/20W_49.9_1%_0201
FBA_D62 P29 FBA_D61 FBA_CMD46 E21 FBA_CMD47

1/20W_49.9_1%_0201
FBA_D63 FBA_D62 FBA_CMD47 FBA_CMD48
R28 C20

OPT_GN20S_NS@

OPT_GN20S_NS@
1

1
FBA_D63 FBA_CMD48 B20 FBA_CMD49 FBA_CMD25 RG5200 1 @ 2 0_0201_5%
FBA_CMD49 FBA_CMD50 FBA_CMD26
C18 RG5201 1 @ 2 0_0201_5%

RG5196

RG5197
FBA_DBI0 E6 FBA_CMD50 E20 FBA_CMD51
FBA_DBI1 P6 FBA_DQM0 FBA_CMD51 A23 FBA_CMD52
FBA_DBI2 FBA_DQM1 FBA_CMD52
E2 D15

2
FBA_DBI3 R2 FBA_DQM2 FBA_CMD53_NC E15
FBA_DBI4 E24 FBA_DQM3 FBA_CMD54_NC E18 FBA_CMD55
FBA_DBI5 P26 FBA_DQM4 FBA_CMD55 D18
FBA_DBI6 A29 FBA_DQM5 FBA_CMD56_NC E17
FBA_DBI7 FBA_DQM6 FBA_CMD57_NC
P28 F18
FBA_DQM7 FBA_CMD58_NC F17
FBA_CMD59_NC
B FBA_EDC0 B
F8
FBA_EDC1 R5 FBA_DQS_WP0
FBA_EDC2 F1 FBA_DQS_WP1 E9
FBA_EDC3 P4 FBA_DQS_WP2 FBA_CLK0 F9 FBA_CLK0_P
FBA_EDC4 FBA_DQS_WP3 FBA_CLK0_N FBA_CLK0_N
F24 F23
FBA_EDC5 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1_P
L27 E23
FBA_EDC6 C30 FBA_DQS_WP5 FBA_CLK1_N FBA_CLK1_N
FBA_EDC7 P31 FBA_DQS_WP6
FBA_DQS_WP7

D5
FBA_WCK01 C5 FBA_WCK01_P
FBA_WCK01_N FBA_WCK01_N
B6
FBA_WCK23 A6 FBA_WCK23_P
FBA_WCK23_N FBA_WCK23_N
D27
FBA_WCK45 FBA_WCK45_P
C27
FBA_WCK45_N A26 FBA_WCK45_N
FBA_WCK67 FBA_WCK67_P
B26
FBA_WCK67_N FBA_WCK67_N
L6
FBA_WCKB01 FBA_WCKB01_P
M6
FBA_WCKB01_N L1 FBA_WCKB01_N
FBA_WCKB23 FBA_WCKB23_P
L2
FBA_WCKB23_N L26 FBA_WCKB23_N
FBA_WCKB45 FBA_WCKB45_P
M26
FBA_WCKB45_N FBA_WCKB45_N
L31
FBA_WCKB67 L30 FBA_WCKB67_P
FBA_WCKB67_N FBA_WCKB67_N
OPT_GN20S@
RG2806 1 2 1/20W_2.49K_1%_0201 J31
FB_VREF
CG2801 1 2 3.9P_50V_B_NPO_0402
NVIDIA_GN20-S5-GB3-64_FCBGA771
OPT@ OPT_NS@
RG5174 1 2 1/16W_49.9_1%_0402
OPT_GN18S@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 S550-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 30 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 S550-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 31 of 108
5 4 3 2 1
 5 4 3 2 1

+1.8VGS +1.8VGS
GPU Address 0x9E
+1.8VGS

2
UG11H RG3020
1/20W_4.7K_5%_0201 RG3021 OPT@

2
7/14 MISC1 1/20W_4.7K_5%_0201 1/16W_2.2K_5%_4P2R_0404
Internal Thermal Sensor OPT@ QG3003A
I2CB_SCL 2 3

G1
OPT@ PJT7838_SOT363-6
AL6 VGA_SMB_CLK I2CB_SDA 1 4

1
I2CS_SCL AL5 VGA_SMB_DATA VGA_SMB_CLK 1 6 RPG2
OVERT_N AF2 I2CS_SDA S1 D1 EC_SMB_CLK1
OVERT OPT@
AJ5 VGA_I2CC_SCL
TS_VREF R1 I2CC_SCL
AK5 VGA_I2CC_SDA
TS_VREF I2CC_SDA 1/16W_2.2K_5%_4P2R_0404
1 RG3030 2 OPT_NS@
1
CG3002 AF1 AJ6 I2CB_SCL 1/20W_0_5%_0201 VGA_I2CC_SCL 2 3
THERMDN I2CB_SCL
OPT_NS@ AK6 I2CB_SDA VGA_I2CC_SDA 1 4
AG1 I2CB_SDA
0.1U_6.3V_K_X7R_0201 RPG3

5
2 THERMDP OPT@
QG3003B OPT@
D AF5 NVVDD_PWM_VID D

G2
GPIO0 V5 FB_GC6_EN NVVDD_PWM_VID FBVDDQ_SEL
PJT7838_SOT363-6 RG3013 1 OPT_NS@
2 1/20W_10K_5%_0201
GPIO1 GPU_EVENT_N_R VGA_SMB_DATA
AC3 4 3
1@ AJ31 GPIO2 Y6 TEST_1 1 @ S2 D2 EC_SMB_DATA1
TG3001 1@ AL29 JTAG_TCK GPIO3
Y2 GPIO4_NVVDD_EN_R RG3010 1OPT_NS@ 2 1/20W_0_5%_0201 GPIO4_NVVDD_EN TG3005 1 OPT@ 2 1/20W_10K_5%_0201
RG3014
TG3002 JTAG_TMS GPIO4 GPIO4_NVVDD_EN
1@ AK30 AD4 RG3022 2 1 1/20W_0_5%_0201
TG3003 1@ AJ30 JTAG_TDI GPIO5 Y3 PSI_VGA OPT_NS@
TG3004 JTAG_TDO GPIO6 TEST_2 PSI_VGA GPIO10_FBVREF_ALTV
1/20W_10K_5%_0201 2 OPT@ 1 RG3003 AK29 V1 @1 PU AT EC SIDE, +3VS AND 4.7K 1 OPT@
RG3031 2 1/20W_100K_5%_0201
JTAG_TRST_N GPIO7 FBVDDQ_SEL TG3006
1/20W_10K_5%_0201 2 OPT@ 1 RG3004 TESTMODE AJ29 U5
NVJTAG_SEL GPIO8
U1 VGA_ALERT_N FBVDDQ_SEL
ADC_IN_P GPIO9 GPIO10_FBVREF_ALTV
AL3 AC4
ADC_IN_P ADC_IN_N AK3 ADC_IN GPIO10 AA2 GPIO10_FBVREF_ALTV
ADC_IN_N ADC_IN_N GPIO11 VGA_AC_DET_R DG3001 2 OPT@1 VGA_AC_DET
AA7
GPIO12 VGA_AC_DET
AA4
GPIO13
AA6 RB521CM-30T2R_VMN2M-2
+1.8VGS
GPIO14
AF4 VGA_ALERT_N DG3308 2OPT_NS@
1 +1.8VGS +3VALW +3VS
GPIO15 AD2
GPIO16 RB521CM-30T2R_VMN2M-2 GPIO4_NVVDD_EN_R RG3015 1 OPT@

2
AD1 2 1/20W_10K_5%_0201
GPIO17 AF3 RG3026
GPIO18 OVERT_N
AC5 OPT@ 1/20W_10K_5%_0201 RG3016 1 OPT@ 2 1/20W_10K_5%_0201

2
GPIO19
AC1
GPIO20 AD3 VGA_ALERT_N
RG3025 RG3017 1 OPT@ 2 1/20W_10K_5%_0201
GPIO21 ADC_MUX_SEL FB_GC6_EN_R

1
AC2 OPT_NS@ OPT@ 1/20W_10K_5%_0201 FB_GC6_EN_R
GPIO22 AA3 ADC_MUX_SEL VGA_AC_DET_R
RG3023 RG3018 1 OPT@ 2 1/20W_100K_5%_0201
GPIO23
U4 1/20W_10K_5%_0201

1
GPIO24 PSI_VGA

3
Y7 OPT_GN20S@ QG3004B RG3019 1OPT_NS@ 2 1/20W_10K_5%_0201
GPIO25 AF6 GPU_GPIO26 GPIO26_ROM_WP
RG5203 1 2 1/20W_0_5%_0201
GPIO26_ROM_WP

D2
GPIO26 ADC_MUX_SEL
AD5 5 RG5175 1 OPT@ 2 1/16W_2.2K_1%_0402
GPIO27 U3 GPIO26_FP_FUSE G2 PJT7838_SOT363-6
RG5202 1 2 1/20W_0_5%_0201
GPIO28
V2 GPIO26_FP_FUSE
OPT_GN18S@ OPT@

S2
GPIO29
U2

6
GPIO30 V3
GPIO31

4
Y1 QG3004A

D1
GPIO32 AA1 FB_GC6_EN 2
G1 PJT7838_SOT363-6
GPIO33
V4 OPT@
GPIO34

S1
Y4

2
GPIO35
NVIDIA_GN20-S5-GB3-64_FCBGA771 RG3024

1
OPT_NS@ OPT@ 1/20W_10K_5%_0201

1
+3VS

2
+3VALW RG3012
OPT@ 1/20W_10K_5%_0201
OPT_NS@
FB_GC6_EN RG3027 1 2 1/20W_0_5%_0201 FB_GC6_EN_R

1
2
C C
RG3011 GPIO4_NVVDD_EN
GPIO4_NVVDD_EN
OPT@ 1/20W_10K_5%_0201

3
QG3002B

D2
5 PJT7838_SOT363-6
G2

S2
4
6
+1.8VGS
QG3002A OPT@

D1
+1.8VGS GPIO4_NVVDD_EN_R 2 PJT7838_SOT363-6
G1

0.1U_6.3V_K_X5R_0201

S1
2
RG3028 1

1
OPT@ OPT@

CG3007
1/20W_10K_5%_0201
OPT_NS@

1
2

2
GPU_EVENT_N_R 3 1 GPU_EVENT_N
GPU_EVENT_N

QG3005
LSI1012XT1G_SC-89-3
OPT@
RG3029 1 2 1/20W_0_5%_0201
OPT_NS@
+3VS +1.8VGS
2
0.1U_6.3V_K_X5R_0201

RG3009
OPT@ 1/20W_10K_5%_0201
OPT@ 1
CG3005

2 FS_OVERT# FUNCTION
5

UG3001 +3VS
B PCH_PLT_RST_N 1 B
P

PCH_PLT_RST_N B PLT_RST_VGA_N
4
PLT_RST_VGA_N

2
PXS_RST_N Y
2
PXS_RST_N
G

A
OPT@ RG5181
MC74VHC1G09DFT2G_SC70-5 OPT@ 1/20W_10K_5%_0201
3

1
1

1
OPT_NS@

RG3006 RG3032 OVERT_R_N RG5184 1 @ 2 0_0201_5% OVERT_N_NVEN For OVERT Enable

+3VS OVERT_N_NVEN
1/20W_100K_5%_0201 OPT@ 1/20W_100K_5%_0201
+1.8VGS
2

2
RG5185 1OPT_NS@ 2 1/20W_0_5%_0201 EC_WRST_N For SWG mode
EC_WRST_N
RG5182
2

OPT@ 1/20W_10K_5%_0201
RG5199
OPT@ 1/20W_10K_5%_0201

3
D
OVERT_R 5 QG24B
1

G LBSS138DW1T1G_SOT363-6
S

4
6
D
OVERT_N OPT@
2 QG24A
G LBSS138DW1T1G_SOT363-6
+1.8VGS +3VS S OVERT_RR_N
1
OPT@

0.1U_6.3V_K_X5R_0201
1
D
1
2

RG4244 1 OPT@ 2 1/20W_100K_5%_0201 PLT_RST_VGA_N RG5183 1 @ 2 0_0201_5% PLT_RST_VGA_R_N2 QG16 OPT@

CG3802
G LBSS139WT1G_SC70-3
S

3
0.1U_6.3V_K_X5R_0201

VGA_ALERT_N 3 1 PCH_VGA_ALERT_N 2
PCH_VGA_ALERT_N OPT@
1
OPT_NS@
QG3504
LSI1012XT1G_SC-89-3
CG3803

2
OPT_NS@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 S550-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 32 of 108
5 4 3 2 1
 5 4 3 2 1

+1.8VGS
X76
VRAMCFG
GPU VRAM FB Memory (GDDR6) RAMCFG[2:0] STRAP2 STRAP1 STRAP0

2
RG3101 RG3102 RG3103 Samsung 8Gb K4Z80325BC-HC14 0x0 L L L
1/20W_100K_5%_0201
1/20W_100K_5%_0201 1/20W_100K_5%_0201
@ @ @
D D
2*8Gb Hynix 8Gb H56C8H24AIR-S2C 0x2 L H L

1
STRAP0 STRAP0
STRAP1 STRAP1
STRAP2 STRAP2 Hynix 8Gb H56G32CS2DX005 0x5 H L H

Samsung 16Gb K4ZAF325BM-HC14 0x9 L M L

2*16Gb Micron 16Gb MT61K512M32KPA-14:C 0x7 H H H

2
RG3104 RG3105 RG3106
1/20W_100K_5%_0201
1/20W_100K_5%_0201 1/20W_100K_5%_0201 Hynix 16Gb H56G42AS2DX014 0x8 L L M
@ @ @

1
+1.8VGS

STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE

Default
2

2
RG3107 RG3108 RG3109 L L L 0 0 0 0
1/20W_100K_5%_0201 1/20W_100K_5%_0201 1/20W_100K_5%_0201
C OPT_NS@ OPT_NS@ OPT_NS@ C
1

1: SMB_ALT_ADDR ENABLE DEVID_SEL SMBUS_ALT_ADDR

STRAP3 STRAP3 0: SMB_ALT_ADDR DISABLE
STRAP4 STRAP4 0 (Default) 0 0x9E (Default)
STRAP5 STRAP5
1: DEVID_SEL REBRAND
1 1 0x9C (Multi-GPU usage)
0: DEVID_SEL ORIGNAL
2

RG3110 RG3111 RG3112 1: PCIE_CFG LOW POWER

1/20W_100K_5%_0201 1/20W_100K_5%_0201 1/20W_100K_5%_0201
OPT@ OPT@ OPT@ 0: PCIE_CFG HIGH POWER
PCIE_CFG VGA_DEVICE
1

0 (Default) 0 3D Device (Class Code 302h)

1: VGA_DEVICE ENABLE
0: VGA_DEVICE DISABLE 1 1 VGA Device (Default)

+1.8VGS
B B
1

RG3114
@ 0_0402_5%
2

ROM_SO ROM_SI ROM_SCLK FS_OVERT*Function

2

RG3115 RG3116 RG3117 L L L FS_OVERT*function DISABLE

1/20W_100K_5%_0201 1/20W_10K_5%_0201 1/20W_100K_5%_0201 GN20-S5
OPT_NS@ OPT_NS@ OPT_GN20S@
L L H FS_OVERT*function ENABLE(default)
1

ROM_SI
ROM_SI ROM_SO
ROM_SO ROM_SCLK
ROM_SCLK
ROM_SO ROM_SI ROM_SCLK FS_OVERT*Function
2

RG3118 RG3119 RG3120

1/20W_100K_5%_0201 1/20W_10K_5%_0201 1/20W_100K_5%_0201 L M L FS_OVERT*function DISABLE
OPT@ OPT@ OPT_GN18S@ GN18-S5
1

L L L FS_OVERT*function ENABLE(default)

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 S550-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 33 of 108
5 4 3 2 1
 5 4 3 2 1

NVVDD
FBVDDQ

UG11G NVVDD FBVDDQ

11/14 FBVDDQ

UG11E G11 For RF

G12 FBVDDQ_01
10/14 VDD
FBVDDQ_02 For RF

33P_50V_J_NPO_0402
G14

33P_50V_J_NPO_0402
FBVDDQ_03

OPT_RF_NS@
AA11 R15 G15 1 1
AA13 VDD_01 VDD_71 R17 G17 FBVDDQ_04

OPT_RF@
AA15 VDD_02 VDD_72 R19 G18 FBVDDQ_05
AA17 VDD_03 VDD_73 R21 G20 FBVDDQ_06
VDD_04 VDD_74 FBVDDQ_07 2 2
AA19 R23 G21
AA21 VDD_05 VDD_75 R9 G23 FBVDDQ_08

CG3230
VDD_06 VDD_76 FBVDDQ_09
AA23 T10 G8
D VDD_07 VDD_77 FBVDDQ_10 D

CG3258
AA9 T12 G9
AB10 VDD_08 VDD_78 T14 H25 FBVDDQ_11
VDD_09 VDD_79 FBVDDQ_12
AB12 T16 J25
AB14 VDD_10 VDD_80 T18 J7 FBVDDQ_13
AB16 VDD_11 VDD_81 T20 L25 FBVDDQ_14
AB18 VDD_12 VDD_82 T22 L7 FBVDDQ_15
AB20 VDD_13 VDD_83 U11 M25 FBVDDQ_16
AB22 VDD_14 VDD_84 U13 M7 FBVDDQ_17
AC11 VDD_15 VDD_85 U15 P25 FBVDDQ_18
VDD_16 VDD_86 FBVDDQ_19
AC13 U17 P7
AC15 VDD_17 VDD_87 U19 R25 FBVDDQ_20
AC17 VDD_18 VDD_88 U21 R7 FBVDDQ_21
AC19 VDD_19 VDD_89 U23 FBVDDQ_22
AC21 VDD_20 VDD_90 U9
VDD_21 VDD_91
AC23 V10
AC9 VDD_22 VDD_92 V12
J11 VDD_23 VDD_93 V14
VDD_24 VDD_94
J13 V16
J15 VDD_25 VDD_95 V18
VDD_26 VDD_96
J17 V20
J19 VDD_27 VDD_97 V22
J21 VDD_28 VDD_98 W11
VDD_29 VDD_99
J23 W13
J9 VDD_30 VDD_100 W15
K10 VDD_31 VDD_101 W17
K12 VDD_32 VDD_102 W19
K14 VDD_33 VDD_103 W21
VDD_34 VDD_104
K16 W23
K18 VDD_35 VDD_105 W9
K20 VDD_36 VDD_106 Y10
K22 VDD_37 VDD_107 Y12
L11 VDD_38 VDD_108 Y14
L13 VDD_39 VDD_109 Y16
L15 VDD_40 VDD_110 Y18
VDD_41 VDD_111
L17 Y20
L19 VDD_42 VDD_112 N17
L21 VDD_43 VDD_57 N19
VDD_44 VDD_58
C L23 N21 FBVDDQ C
L9 VDD_45 VDD_59 N23
M10 VDD_46 VDD_60 N9
M12 VDD_47 VDD_61 P10 H1 FBVDDQ_SENSE 1 @ PAD TPG2
M14 VDD_48 VDD_62 P12 FBVDDQ_SENSE CALIBRATION PIN GDDR6
VDD_49 VDD_63
M16 P14
M18 VDD_50 VDD_64 P16
M20 VDD_51 VDD_65
P18 H31 RG3201 1 OPT@ 2 1/16W_40.2_1%_0402 FB_CAL_x_PD_VDDQ 40.2Ohm
M22 VDD_52 VDD_66 P20 FB_CAL_PD_VDDQ
N11 VDD_53 VDD_67 P22 H30 OPT@ 2 1/16W_40.2_1%_0402
RG3202 1
N13 VDD_54 VDD_68
R11 FB_CAL_PU_GND FB_CAL_x_PU_GND 40.2Ohm
N15 VDD_55 VDD_69 R13 H29 RG3203 1 OPT@ 2 1/16W_40.2_1%_0402
VDD_56 VDD_70 Y22 FB_CAL_TERM_GND
VDD_113
Place near balls
FB_CAL_xTERM_GND 40.2Ohm
NVIDIA_GN20-S5-GB3-64_FCBGA771
OPT_NS@

trace width: 16mils

differential voltage sensing.
differential signal routing.

H2 NVVDD_VCC_SENSE
VDD_SENSE NVVDD_VSS_SENSE NVVDD_VCC_SENSE
H3
GND_SENSE NVVDD_VSS_SENSE

NVIDIA_GN20-S5-GB3-64_FCBGA771
OPT_NS@

B B

www.teknisi-indonesia.com

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 S550-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 34 of 108
5 4 3 2 1
 5 4 3 2 1

UG11F +VDD18 +1.8VGS FP_FUSE_GPU

14/14 1V8 / NC OPT_GN20S@
RG5173 1 2 1/16W_0_1%_0402
AA5 AC6
AE23 NC_1 1V8_1 AC7
AE24 NC_2 1V8_2 AD6 UG3002
NC_3 1V8_3 FP_FUSE_GPU
AF23 AD7 A2 A1
NC_4 1V8_4 VIN Vout
AF24

OPT_GN18S@
NC_5 1

1U_6.3V_K_X6S_0402
CG3315
AF25 B1 B2 GPIO26_FP_FUSE
NC_6 GND ON GPIO26_FP_FUSE
AG23
NC_7
AG24
AG27 NC_8 2 AP22913CN4-7_X1-WLB0909-4
AJ3 NC_9
NC_10 OPT_GN18S@
Y5
NC_11
FP_FUSE_GPU
D D

OPT@ +1.8VGS
AF14 FP_FUSE_GPU CG3301 1 2 1U_6.3V_K_X6S_0402
FUSE_SRC OPT_NS@ OPT_GN18S@
RG3301 1 OPT@ 2 1/20W_10K_1%_0201 RG3304 1 2 1/20W_10K_5%_0201 GPIO26_FP_FUSE RG5221 1 2 1/20W_10K_5%_0201
NVIDIA_GN20-S5-GB3-64_FCBGA771
OPT_NS@

Discharge
change at 7/3
FBVDDQ
+3VALW

1/20W_47K_5%_0201

1/16W_49.9_1%_0402
1
1
OPT@

OPT@

RG3328
RG3327

2
NVVDD_EN 3

2
+3VS
DG3306 OPT@
QG3511

1
OVERT_N_NVEN 1 2 FBVDDQ_PWR_EN_N 1 L2SK3541M3T5G_SOT723-3
OVERT_N_NVEN RG3317 OPT@
3
1 2 1/20W_10K_5%_0201
RB521CM-30T2R_VMN2M-2 OPT@
DG3304 QG3510

2
PXS_PWREN RG3313 1 @ 2 0_0201_5% 2 FBVDDQ_PWR_EN 1 L2SK3541M3T5G_SOT723-3 2
PXS_PWREN OPT@ NVVDD_EN
1 OPT@
GPIO4_NVVDD_EN NVVDD_EN
RG3314 1 @ 2 0_0201_5% 3
GPIO4_NVVDD_EN

+1.8VGS RG3315 1OPT_NS@ 2 1/20W_0_5%_0201 LBAT54AWT1G_SOT323-3

1
OPT_NS@ 2
RG3318
OPT_NS@ 1/20W_100K_5%_0201
RG3316 1 2 1/20W_0_5%_0201

2
C +5VALW +1.0VGS C

+1.0VGS_EN

1/20W_47K_5%_0201
DG3303 OPT@

1
+3VS +1.8VGS

1
PXS_PWREN

OPT@
1 2

RG3329
RG3330 RG3331
2

1 2 OPT_NS@ 1/8W_5.11_1%_0805 1/8W_5.11_1%_0805

2

RB521CM-30T2R_VMN2M-2 RG3307 RG3334 OPT_NS@ OPT@ OPT@

2
1/20W_10K_5%_0201 1 2 1V0_MAIN_EN

2
1/20W_14K_1%_0201 NVVDD_PWROK 1V0_MAIN_EN
RG3311 1/20W_0_5%_0201
OPT@ 1
1

DG3302
1

NVVDD_PWROK 2 CG3320
1 PXE_VDD_EN RG3310 1 @ 2 0_0201_5% PXE_VDD_EN_R RG3312 1 @ 2 0_0201_5% 0.1U_25V_K_X5R_0201
GPIO4_NVVDD_EN RG3308 1 @ 2 0_0201_5% 3 2 OPT_NS@

1
D QG3304
1

NVVDD_EN RG5189 1 OPT_NS@

2 1/20W_0_5%_0201 LBAT54AWT1G_SOT323-3 +1.0VGS_PWR_EN_N 2 SB000019400
2
OPT@ RG3309 DG3301 OPT_NS@ G L2N7002KWT1G_SOT323-3
1/20W_20K_1%_0201 CG3316 OPT@
OPT@ 1 2 0.22U_6.3V_K_X5R_0201 S

3
1
OPT_NS@
2

1
1 2 D
PXE_VDD_EN_R 2 QG3305
RB521CM-30T2R_VMN2M-2
G LBSS139WT1G_SC70-3
S OPT@

3
change at 7/1
FBVDDQ_PWR_EN
+5VALW NVVDD
UG3003

1/20W_47K_5%_0201
FB_GC6_EN_R RG3322 1 @ 2 0_0201_5% GC6_EN 1 4 FBVDDQ_PWR_EN
FB_GC6_EN_R NVVDD_PWROK RG3323 1OPT_NS@ 2 1/20W_10K_5%_0201 IN B OUT Y FBVDDQ_PWR_EN
2
NVVDD_PWROK IN A

1
+1.0VGS_PWROK RG5188 1 OPT@ 2 1/20W_15_5%_0201
+1.0VGS_PWROK

RG3332
3 5

OPT_NS@
GND Vcc +3VS RG3333
1
0.1U_10V_K_X5R_0201

B 1/10W_10_1%_0603 B
OPT_NS@
1 MC74VHC1G32DFT2G_SC70-5 CG3805

3 2
CG3319 OPT@ 0.1U_6.3V_K_X5R_0201
2 OPT@ D
OPT_NS@ NVVDD_EN_N 5 QG3306B
2 G LBSS138DW1T1G_SOT363-6

6
D OPT_NS@
S

4
NVVDD_EN 2 QG3306A
G
LBSS138DW1T1G_SOT363-6
S

1
OPT_NS@

QG123
+1.8VALW AON7380_DFN8-5 +1.8VGS
change at 7/3 OPT_NS@
+5VALW RG5215 1 2 1/20W_47K_5%_0201 1 1.8A
2
+1.8VGS RG678 1 OPT@ 2 1/20W_100K_5%_0201 +1.8VS_VGA_GATE_EN RG682 2 OPT@ 1 5 3
GPU_ALL_B+ 1/20W_1K_1%_0201
1 OPT_NS@

10U_10V_M_X6S_0603
1

1
+5VALW RG5204 1 OPT@ 2 1/20W_47K_5%_0201 OPT_NS@ OPT@ CG611
4
3

OPT@ D CG3808 0.1U_6.3V_K_X5R_0201 RG680 2

RG5205 1 2 1/20W_10K_5%_0201 +1.8VS_VGA_EN_N 5 1/10W_47_5%_0603

CG902
OPT_NS@
+3VALW 0.1U_6.3V_K_X5R_0201
1

OPT_NS@ G 2 2 OPT@
RG683 +1.8VS_VGA_GATE

2
QG3509B S 430K_0402_1% 1
4
6

OPT_NS@ OPT@ D 2N7002KDWH_SOT363-6 OPT@

0.047U_25V_K_X7R_0402

RG679 1 2 1/20W_0_5%_0201 PXS_PWREN_GATE 2

PXS_PWREN
2

G QG3509A 1

1
OPT@

2N7002KDWH_SOT363-6
CG610

D
1 S +1.8VS_VGA_EN_N 2 OPT@
1
1

3 PXS_PWREN_DELAY RG684 1 OPT@ 2 1/20W_0_5%_0201 OPT@ G

CG3807 RG681 2 QG5
1 0.1U_6.3V_K_X5R_0201 1/20W_100K_5%_0201 S 2N7002KW_SOT323-3
3
2 OPT_NS@
DG111 2 PXS_PWREN_DIS_DELAY
RG685 1 OPT@ 2 1/16W_150K_1%_0402
+1.8VS_VGA Discharge
2

LBAT54SWT1G_SOT323-3
OPT@

A A

+3VS
1

RG5192
VGA_PWRGD 1/20W_10K_5%_0201
OPT@
DG3307
2

FBVDDQ_PWROK RG5191 1 @ 2 0_0201_5% FBVDDQ_PWROK_R 2

FBVDDQ_PWROK Security Classification LC Future Center Secret Data Title
1
+1.0VGS_PWROK +1.0VGS_PWROK_R 3 VGA_PWRGD
RG5190 1 @ 2 0_0201_5%
+1.0VGS_PWROK Issued Date 2019/12/24 Deciphered Date 2019/12/24 S550-ICL
LBAT54AWT1G_SOT323-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
OPT@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 35 of 108
5 4 3 2 1
 5 4 3 2 1

UG11C UG11D
12/14 GND_1/2 13/14 GND_2/2

A2 D8 AF15
GND_001 GND_121 GND
A27 D9 U29
A30 GND_002 GND_122 E1 V11 GND_240
A5 GND_003 GND_123 E27 V13 GND_241
AA10 GND_004 GND_124 E31 V15 GND_242
AA12 GND_005 GND_125 E5 V17 GND_243
AA14 GND_006 GND_126 F10 V19 GND_244
AA16 GND_007 GND_127 F13 V21 GND_245
AA18 GND_008 GND_128 F16 V23 GND_246
GND_009 GND_129 GND_247
AA20 F19 V27
AA22 GND_010 GND_130 F22 V29 GND_248
GND_011 GND_131 GND_249
AA26 F25 V30
D
AA29 GND_012 GND_132 F29 V9 GND_250 D
AB11 GND_013 GND_133 F3 W10 GND_251
GND_014 GND_134 GND_252
AB13 F7 W12
AB15 GND_015 GND_135 G2 W14 GND_253
AB17 GND_016 GND_136 G26 W16 GND_254
AB19 GND_017 GND_137 G28 W18 GND_255
AB2 GND_018 GND_138 G30 W2 GND_256
AB21 GND_019 GND_139 G4 W20 GND_257
AB23 GND_020 GND_140 G6 W22 GND_258
GND_021 GND_141 GND_259
AB27 J1 W26
AB29 GND_022 GND_142 J10 W29 GND_260
AB30 GND_023 GND_143 J12 W4 GND_261
AB4 GND_024 GND_144 J14 W6 GND_262
AB6 GND_025 GND_145 J16 Y11 GND_263
GND_026 GND_146 GND_264
AB9 J18 Y13
AC10 GND_027 GND_147 J20 Y15 GND_265
AC12 GND_028 GND_148 J22 Y17 GND_266
GND_029 GND_149 GND_267
AC14 J27 Y19
AC16 GND_030 GND_150 J5 Y21 GND_268
GND_031 GND_151 GND_269
AC18 K11 Y23
AC20 GND_032 GND_152 K13 Y27 GND_270
AC22 GND_033 GND_153 K15 Y29 GND_271
GND_034 GND_154 GND_272
AC26 K17 Y30
AC29 GND_035 GND_155 K19 Y9 GND_273
AD27 GND_036 GND_156 K2 GND_274
AD29 GND_037 GND_157 K21
AD30 GND_038 GND_158 K23
GND_039 GND_159
AE14 K26
AE2 GND_040 GND_160 K28
AE29 GND_041 GND_161 K30
AE4 GND_042 GND_162 K4
AE6 GND_043 GND_163 K6
AF10 GND_044 GND_164 K9
AF13 GND_045 GND_165 L10
GND_046 GND_166
AF16 L12
AF19 GND_047 GND_167 L14
AF22 GND_048 GND_168 L16
GND_049 GND_169
C AF26 L18 C
AF27 GND_050 GND_170 L20
AF28 GND_051 GND_171 L22
AF29 GND_052 GND_172 L29
AF30 GND_053 GND_173 L3
GND_054 GND_174
AF7 M11
AG28 GND_055 GND_175 M13
GND_056 GND_176
AH10 M15
AH11 GND_057 GND_177 M17
AH12 GND_058 GND_178 M19
GND_059 GND_179
AH13 M21
AH14 GND_060 GND_180 M23
AH15 GND_061 GND_181 M27
AH16 GND_062 GND_182 M5
AH17 GND_063 GND_183 M9
AH18 GND_064 GND_184 N10
AH19 GND_065 GND_185 N12
GND_066 GND_186
AH2 N14
AH20 GND_067 GND_187 N16
AH21 GND_068 GND_188 N18
AH22 GND_069 GND_189 U26
AH23 GND_070 GND_239 N2
AH24 GND_071 GND_190 N20
AH25 GND_072 GND_191 N22
AH26 GND_073 GND_192 N26
GND_074 GND_193
AH27 N28
AH28 GND_075 GND_194 N30
GND_076 GND_195
AH30 N4
AH4 GND_077 GND_196 N6
AH7 GND_078 GND_197 P11
GND_079 GND_198
AJ8 P13
AJ9 GND_080 GND_199 P15
AK1 GND_081 GND_200 P17
AK10 GND_082 GND_201 P19
AK13 GND_083 GND_202 P2
GND_084 GND_203
AK16 P21
AK19 GND_085 GND_204 P23
AK22 GND_086 GND_205 P27
B
AK25 GND_087 GND_206 P5 B
AK28 GND_088 GND_207 P9
AK31 GND_089 GND_208 R10
AK4 GND_090 GND_209 R12
GND_091 GND_210
AK7 R14
AL2 GND_092 GND_211 R16
AL30 GND_093 GND_212 R18
B1 GND_094 GND_213 R20
B10 GND_095 GND_214 R22
GND_096 GND_215
B13 R29
B16 GND_097 GND_216 R3
B19 GND_098 GND_217 T11
GND_099 GND_218
B22 T13
B25 GND_100 GND_219 T15
GND_101 GND_220
B28 T17
B31 GND_102 GND_221 T19
B4 GND_103 GND_222 T2
GND_104 GND_223
B7 T21
C26 GND_105 GND_224 T23
GND_106 GND_225
C6 T26
D10 GND_107 GND_226 T28
D13 GND_108 GND_227 T30
D16 GND_109 GND_228 T4
D19 GND_110 GND_229 T6
D2 GND_111 GND_230 T9
D22 GND_112 GND_231 U10
D23 GND_113 GND_232 U12
D24 GND_114 GND_233 U14
D25 GND_115 GND_234 U16
D28 GND_116 GND_235 U18
D30 GND_117 GND_236 U20
D4 GND_118 GND_237 U22
GND_119 GND_238
D7
GND_120

NVIDIA_GN20-S5-GB3-64_FCBGA771
OPT_NS@
A NVIDIA_GN20-S5-GB3-64_FCBGA771 A
OPT_NS@

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 S550-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 36 of 108
5 4 3 2 1
 5 4 3 2 1

GN20-S5/GN18-S5_GDDR6_A_[31_0]
UG15D

FBVDDQ UG15C
FBA_CMD[0..24]
OPT_NS@
FBA_D[0..31] FBA_CMD1 +FBA_A_VREFC
A11 A1 UG15B H3 K1 1 2 +FBA_VREFC
A13 VSS_1 VDD_1 A14 FBA_CMD13 G11 CA0_A VREFC
UG15A RG5213
A2 VSS_2 VDD_2 E10 FBA_CMD12 G4 CA1_A
VSS_3 VDD_3
NORMAL CA2_A
1/16W_0_1%_0402
A4 E5 NORMAL FBA_CMD24 H12
B1 VSS_4 VDD_4 H13 FBA_CMD11 H5 CA3_A
x16 x8

1/20W_1K_1%_0201
VSS_5 VDD_5 FBA_D15 FBA_D5 FBA_CMD15 CA4_A
B14 H2 G2 N2 H10

1
D
C10 VSS_6 VDD_6 L13 FBA_D10 B3 DQ7_A FBA_D4 P3 DQ6_B FBA_CMD22 J12 CA5_A D

RG5216
C12 VSS_7 VDD_7 L2 FBA_D14 F2 DQ2_A FBA_D7 M2 DQ4_B FBA_CMD23 J11 CA6_A

OPT@
VSS_8 VDD_8 FBA_D12 DQ6_A BYTE0 FBA_D2 DQ7_B FBA_CMD0 CA7_A
C3 P10 E3 P2 J4
C5 VSS_9 VDD_9 P5 FBA_D8 B4 DQ4_A FBA_D1 U3 DQ5_B FBA_CMD2 J3 CA8_A
VSS_10 VDD_10 BYTE1 FBA_D11 DQ0_A FBA_D0 DQ2_B FBA_CMD10 CA9_A
D1 V1 B2 V3 J5

2
VSS_11 VDD_11 FBA_D13 DQ3_A FBA_D6 DQ1_B FBA_CMD14 CABI_n_A
D12 V14 E2 U4 G10
D14 VSS_12 VDD_12 FBA_D9 A3 DQ5_A FBA_D3 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBA_EDC1 C2 FBA_EDC0 T2 TCK
VSS_15 FBVDDQ FBA_EDC1 FBA_DBI1 EDC0_A FBA_EDC0 FBA_DBI0 EDC0_B
E4 D2 R2 F10
VSS_16 FBA_DBI1 DBI0_n_A FBA_DBI0 DBI0_n_B TDI
F1 N10
F12 VSS_17 D4 R4 TDO
VSS_18 FBA_WCKB01_P WCK_t_A FBA_WCK01_P NC3
F14 B10 D5 R5 F5
F3 VSS_19 VDDQ_1 B5 FBA_WCKB01_N WCK_c_A FBA_WCK01_N NC4 FBA_CMD5 L3 TMS
VSS_20 VDDQ_2 FBA_D21 FBA_CMD18 CA0_B
G1 C1 P13 M11
G12 VSS_21 VDDQ_3 C11 FBA_D19 U13 DQ13_B FBA_CMD7 M4 CA1_B
x16 x8
G14 VSS_22 VDDQ_4 C14 FBA_D24 B11 FBA_D23 M13 DQ11_B FBA_CMD20 L12 CA2_B
VSS_23 VDDQ_5 FBA_D31 DQ8_A
NC BYTE2 FBA_D22 DQ15_B FBA_CMD8 CA3_B
G3 C4 G13 NC N13 L5
H11 VSS_24 VDDQ_6 E1 FBA_D29 E13 DQ15_A FBA_D18 U12 DQ14_B FBA_CMD16 L10 CA4_B
NC
VSS_25 VDDQ_7 FBA_D30 DQ13_A FBA_D20 DQ10_B FBA_CMD21 CA5_B
H4 E14 BYTE3 F13 NC P12 K12
VSS_26 VDDQ_8 FBA_D28 DQ14_A FBA_D17 DQ12_B FBA_CMD19 CA6_B
L11 F11 E12 NC V12 K11
L4 VSS_27 VDDQ_9 F4 FBA_D26 B12 DQ12_A FBA_D16 U11 DQ9_B FBA_CMD6 K4 CA7_B
NC
VSS_28 VDDQ_10 FBA_D27 DQ10_A DQ8_B FBA_CMD4 CA8_B
M1 H1 B13 NC K3
M12 VSS_29 VDDQ_11 H14 FBA_D25 A12 DQ11_A FBA_EDC2 T13 FBA_CMD9 K5 CA9_B J14FBA_ZQ_1_A RG3501 1 OPT@ 2 1/16W_121_1%_0402
NC
VSS_30 VDDQ_12 DQ9_A FBA_EDC2 FBA_DBI2 EDC1_B FBA_CMD17 CABI_n_B ZQ_A
M14 J13 R13 M10
VSS_31 VDDQ_13 FBA_EDC3 FBA_DBI2 DBI1_n_B CKE_n_B
M3 J2 C13 GND K14FBA_ZQ_1_B RG3502 1 OPT@ 2 1/16W_121_1%_0402
N1 VSS_32 VDDQ_14 K13 FBA_EDC3 FBA_DBI3 D13 EDC1_A R11 ZQ_B
VSS_33 VDDQ_15 FBA_DBI3 DBI1_n_A NC FBA_WCK23_P WCK_t_B
N12 K2 R10
N14 VSS_34 VDDQ_16 L1 D11 FBA_WCK23_N WCK_c_B
NC
VSS_35 VDDQ_17 FBA_WCKB23_P NC1
N3 L14 D10 NC
VSS_36 VDDQ_18 FBA_WCKB23_N NC2 FBA_CMD3
P11 N11 J1 RESET_n
P4 VSS_37 VDDQ_19 N4 MT61K256M32JE-14-A_FBGA180
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180 @
R12 VSS_39 VDDQ_21 P14
VSS_40 VDDQ_22 @
R14 T1 K10 CK_c
VSS_41 VDDQ_23 FBA_CLK0_N
R3 T11 J10
T10 VSS_42 VDDQ_24 T14 FBA_CLK0_P CK_t G5
VSS_43 VDDQ_25 NC5
C T12 T4 C
T3 VSS_44 VDDQ_26 U10 M5
T5 VSS_45 VDDQ_27 U5 NC6
U1 VSS_46 VDDQ_28
U14 VSS_47
VSS_48
V11
V13 VSS_49
VSS_50 +1.8VGS
V2
V4 VSS_51
VSS_52
MT61K256M32JE-14-A_FBGA180
A10
VPP_1 A5 @
VPP_2 V10
VPP_3 V5
VPP_4

MT61K256M32JE-14-A_FBGA180
@

FBVDDQ

1
RG3504
1/20W_549_1%_0201
OPT_NS@
OPT_NS@

2
1 2 +FBA_VREFC
RG3503 +FBA_VREFC
16 mil

1
1/20W_931_1%_0201 1

1/20W_1K_1%_0201
CG3555

RG3505
OPT_NS@
820P_25V_K_X7R_0201

1
OPT_NS@
2

2
B B
2 QG3501
GPIO10_FBVREF_ALTV
LSI1012XT1G_SC-89-3
OPT_NS@

3
Vgs(th)≤0.9V VREFC IS NOT USED IN
x16 CONFIGURATION
1K OHM PULL-DOWN IS

teknisi-indonesia.com
IN PLACE OF THE 1.33K
FOR RV99

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 S550-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 37 of 108
5 4 3 2 1
 5 4 3 2 1

GN20-S5/GN18-S5_GDDR6_A_[63_32]
UG16D
FBA_D[32..63]
FBVDDQ UG16C
UG16A
FBA_CMD[28..52]
UG16B OPT_NS@
A11 A1 NORMAL FBA_CMD33 H3 K1 +FBA_B_VREFC 1 2
VSS_1 VDD_1 FBA_CMD45 CA0_A VREFC +FBA_VREFC
A13 A14 NORMAL G11 RG5214
A2 VSS_2 VDD_2 E10 FBA_D63 G2 FBA_CMD35 G4 CA1_A
1/16W_0_1%_0402
A4 VSS_3 VDD_3 E5 FBA_D58 B3 DQ7_A FBA_CMD46 H12 CA2_A
x16 x8
VSS_4 VDD_4 FBA_D62 DQ2_A FBA_D54 FBA_CMD36 CA3_A
B1 H13 F2 N2 H5

1/20W_1K_1%_0201
B14 VSS_5 VDD_5 H2 FBA_D60 E3 DQ6_A FBA_D52 P3 DQ6_B FBA_CMD43 H10 CA4_A
BYTE7 1

1
VSS_6 VDD_6 FBA_D56 DQ4_A FBA_D55 DQ4_B FBA_CMD48 CA5_A
C10 L13 B4 M2 J12 RG5198 CG3656
D
C12 VSS_7 VDD_7 L2 FBA_D59 B2 DQ0_A FBA_D53 P2 DQ7_B FBA_CMD47 J11 CA6_A D

OPT@
BYTE6 820P_25V_K_X7R_0201
C3 VSS_8 VDD_8 P10 FBA_D61 E2 DQ3_A FBA_D50 U3 DQ5_B FBA_CMD34 J4 CA7_A
OPT_NS@
VSS_9 VDD_9 FBA_D57 DQ5_A FBA_D49 DQ2_B FBA_CMD32 CA8_A 2
C5 P5 A3 V3 J3
D1 VSS_10 VDD_10 V1 DQ1_A FBA_D48 U4 DQ1_B FBA_CMD37 J5 CA9_A

2
VSS_11 VDD_11 FBA_EDC7 FBA_D51 DQ0_B FBA_CMD44 CABI_n_A
D12 V14 C2 U2 G10
VSS_12 VDD_12 FBA_EDC7 FBA_DBI7 EDC0_A DQ3_B CKE_n_A
D14 D2
D3 VSS_13 FBA_DBI7 DBI0_n_A FBA_EDC6 T2 N5
VSS_14 FBA_EDC6 FBA_DBI6 EDC0_B TCK
E11 D4 R2
E4 VSS_15 FBVDDQ FBA_WCKB67_P D5 WCK_t_A FBA_DBI6 DBI0_n_B F10
VSS_16 FBA_WCKB67_N WCK_c_A TDI
F1 R4 N10
VSS_17 FBA_WCK67_P NC3 TDO
F12 R5
F14 VSS_18 B10 FBA_WCK67_N NC4 F5
x16 x8
F3 VSS_19 VDDQ_1 B5 FBA_D40 B11 FBA_D38 P13 FBA_CMD29 L3 TMS
NC
G1 VSS_20 VDDQ_2 C1 FBA_D47 G13 DQ8_A FBA_D35 U13 DQ13_B FBA_CMD52 M11 CA0_B
NC
VSS_21 VDDQ_3 FBA_D45 DQ15_A FBA_D33 DQ11_B FBA_CMD40 CA1_B
G12 C11 E13 NC M13 M4
G14 VSS_22 VDDQ_4 C14 FBA_D46 F13 DQ13_A FBA_D37 N13 DQ15_B FBA_CMD50 L12 CA2_B
G3 VSS_23 VDDQ_5 C4
BYTE5 FBA_D44 E12
DQ14_A NC
FBA_D39 U12 DQ14_B FBA_CMD39 L5 CA3_B
VSS_24 VDDQ_6 FBA_D42 DQ12_A
NC BYTE4 FBA_D36 DQ10_B FBA_CMD42 CA4_B
H11 E1 B12 NC P12 L10
H4 VSS_25 VDDQ_7 E14 FBA_D43 B13 DQ10_A FBA_D32 V12 DQ12_B FBA_CMD49 K12 CA5_B
NC
VSS_26 VDDQ_8 FBA_D41 DQ11_A FBA_D34 DQ9_B FBA_CMD51 CA6_B
L11 F11 A12 NC U11 K11
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBA_CMD28 K4 CA7_B
M1 VSS_28 VDDQ_10 H1 FBA_EDC5 C13 FBA_EDC4 T13 FBA_CMD30 K3 CA8_B
GND
VSS_29 VDDQ_11 FBA_EDC5 FBA_DBI5 EDC1_A FBA_EDC4 FBA_DBI4 EDC1_B FBA_CMD38 CA9_B
M12 H14 D13 R13 K5 J14FBA_ZQ_2_A RG3601 1 OPT@ 2 1/16W_121_1%_0402
M14 VSS_30 VDDQ_12 J13 FBA_DBI5 DBI1_n_A NC FBA_DBI4 DBI1_n_B FBA_CMD41 M10 CABI_n_B ZQ_A
M3 VSS_31 VDDQ_13 J2 D11 R11 CKE_n_B K14FBA_ZQ_2_B RG3602 1 OPT@ 2 1/16W_121_1%_0402
NC
VSS_32 VDDQ_14 FBA_WCKB45_P NC1 FBA_WCK45_P WCK_t_B ZQ_B
N1 K13 D10 NC R10
N12 VSS_33 VDDQ_15 K2 FBA_WCKB45_N NC2 FBA_WCK45_N WCK_c_B
VSS_34 VDDQ_16
N14 L1
N3 VSS_35 VDDQ_17 L14 MT61K256M32JE-14-A_FBGA180
P11 VSS_36 VDDQ_18 N11 FBA_CMD31 J1
@ MT61K256M32JE-14-A_FBGA180 RESET_n
P4 VSS_37 VDDQ_19 N4
VSS_38 VDDQ_20 @
R1 P1
R12 VSS_39 VDDQ_21 P14
R14 VSS_40 VDDQ_22 T1 K10
VSS_41 VDDQ_23 FBA_CLK1_N CK_c
R3 T11 J10
VSS_42 VDDQ_24 FBA_CLK1_P CK_t
T10 T14 G5
T12 VSS_43 VDDQ_25 T4 NC5
VSS_44 VDDQ_26
C T3 U10 M5 C
T5 VSS_45 VDDQ_27 U5 NC6
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
VSS_49
V13
V2 VSS_50 +1.8VGS
VSS_51
V4
VSS_52
MT61K256M32JE-14-A_FBGA180
A10
VPP_1 @
A5
VPP_2 V10
VPP_3 V5
VPP_4

MT61K256M32JE-14-A_FBGA180
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 S550-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 38 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 39 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 40 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 41 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 42 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 43 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 44 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/01/19 Deciphered Date 2022/01/19 ThinkPad E14 GEN4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. P045-eDP MUX
Date: Wednesday, March 02, 2022 Sheet 45 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/01/19 Deciphered Date 2022/01/19 ThinkPad E14 GEN4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. P046-NV DDS LOGIC
Date: Wednesday, March 02, 2022 Sheet 46 of 108
5 4 3 2 1
 5 4 3 2 1

DMIC_CLK_CON
DMIC_DATA_CON
LCD POWER SWITCH EMC requset. Close to JLCD1 ESD request PCH_DMIC_DATA
+3VALW +LCDVDD_CON

33P_25V_J_NPO_0201_MURATA

33P_25V_J_NPO_0201_MURATA

33P_25V_J_NPO_0201_MURATA
+LCDVDD_CON LOGO_LED_CON PANEL_PWM

1
+LEDVDD +LCDVDD_CON DG6
UG1
W= 60 mil

PESD5V0H1BSF_SOD962-2
5 1 +LCDVDD_CON

EMC@
1 1 1 1

2200P_25V_K_X7R_0201

2200P_25V_K_X7R_0201
IN OUT
1 1 EMC@ EMC_NS@ EMC_NS@

4.7U_6.3V_M_X5R_0402

1U_6.3V_M_X5R_0201
2 1 1 CG34 CG35 CG36 CG3832
GND
CG23 CG24 CG10 CG11
CPU_ENVDD_EN 4 3
W= 60 mil RF_NS@ RF_NS@ 18P_25V_J_COG_0201 10P_25V_G_NPO_0201 2
1000P_50V_K_X7R_0201
2 2 2

EMC_NS@
EN OCB 2 2
1 1 RF@ RF@
2 2

2
SY6288C20AAC_SOT23-5 CG1 CG2
SA000074P00

2
1
1
RG2 2 2
CG3
1U_6.3V_M_X5R_0201 1/20W_100K_5%_0201
2

2
PCH_I2C2_SCL_TS PCH_I2C2_SDA_TS USB20_7_N USB20_7_P TOUCH_RST_N

DG11 DG12 TOUCH_EN_R

1
TOUCH_RST_N_R

PESD5V0H1BSF_SOD962-2

PESD5V0H1BSF_SOD962-2
D DG7 DG5 TOUCH_EN D

1
TABLE of POWER SWITCH (U1)

0.1U_6.3V_K_X5R_0201

1
PESD5V0H1BSF_SOD962-2

PESD5V0H1BSF_SOD962-2
+3VS_CAM
2

1/20W_100K_5%_0201

0.033U_10V_K_X5R_0201
RG34
1
+1V8_DMIC @

EMC_NS@

EMC_NS@

CG3424

CG3524
Vendor LCFC P/N Description
BL_ON 1

EMC_NS@

EMC_NS@
SILERGY SA000074P00 S IC SY6288C20AAC SOT23 5P POWER SWITCH

2
2

2
0.1U_6.3V_K_X5R_0201
CPU_EDP_HPD

CG3423
GMT SA00007S700 S IC G5247T11U SOT-23 5P POWER SWITCH

2200P_25V_K_X7R_0201
1/20W_0_5%_0201

2
RG5150

2200P_25V_K_X7R_0201
2

1
1/20W_100K_5%_0201
DMIC_CLK

RG14
EMC_NS@
1 1 1

2
CG21

CG20

RG15
EMC_NS@
FG1 LED POWER SWITCH CG22

33P_25V_J_NPO_0201_MURATA
@ @ EMC_NS@

1/20W_100K_5%_0201
1 2 2 2 2
V9B+ 2A 80 mil 2A 80 mil +LEDVDD 1

2
1 3A_32V_0497003PKRHF 1 1 1 1 1
CG4 2
CG5

CG6

CG7

CG8

CG9
1U_0603_25V6-K
0.1U_25V_K_X5R_0201

12P_50V_J_NPO_0402
0.01U_25V_K_X5R_0201

2.2P_50V_C_NPO_0402
4.7U_25V_K_X5R_0805_H1.25 @ @ @

RF@

RF@
2 2 2 2 2 2

Board ID defined by EDP cable eDP/CAMERA/DMIC/LOGO-LED CONN.

14' 15' LOGO LED JLCD1

+LEDVDD +LEDVDD W= 80 mil 1

2 1
SIZE_CTL leave as NC Conntect to GND
by EDP cable LOGO_LED_N 1 2 LOGO_LED_CON 3 2
RG6
LOGO_LED_N 3
4
TOUCH_INT_N_R 4
RG33 1/16W_2.7K_0.5%_0402 RG10 2 @ 1 0_0201_5% 5
TOUCH_INT_N LOGO_LED_CON 5
RG5 1/20W_100K_5%_0201 6
1 2 PANEL_SIZE_CTL 1 2 PANEL_SIZE_CTL 7 6
+3VS @
PANEL_SIZE_CTL PANEL_PW M 7
8
BL_ON 9 8
1/20W_100K_5%_0201
10 9
+3VL +3VL
LID_SW_N 11 10
LID_SW _N TOUCH_EN TOUCH_EN_R 11
TOUCH_EN RG11 2 @ 1 0_0201_5% 12
C 13 12 C
CPU_EDP_HPD 14 13
CPU_EDP_HPD 14
15
TOUCH_RST_N_R 15
TOUCH_RST_N RG12 2 @ 1 0_0201_5% 16
LCD_SELF_TEST_ON 17 16
CPU_EDP_ENVDD LCD_SELF_TEST_ON 17
2 1 CPU_ENVDD_D RG7 2 @ 1 0_0201_5% CPU_ENVDD_EN
+LCDVDD_CON
+LCDVDD_CON
W= 60 mil 18
CPU_EDP_ENVDD 18
DG1 RB521CM-30T2R_VMN2M-2 19
20 19
CPU_EDP_AUX_N 1 2 0.1U_6.3V_K_X5R_0201 EDP_AUX_CON_N 21 20
1 CPU_EDP_AUX_N CG13
LCD_SELF_TEST_ON 2 1 LCD_SELF_TEST_ON_DRG8 2 1 0_0201_5% CPU_EDP_AUX_P 1 2 0.1U_6.3V_K_X5R_0201 EDP_AUX_CON_P 22 21
@ CG12 CPU_EDP_AUX_P CG14
23 22
DG2 RB521CM-30T2R_VMN2M-2 @
CPU_EDP_TX0_P 1 2 0.1U_6.3V_K_X5R_0201 EDP_TX0_CON_P 24 23
0.1U_6.3V_K_X5R_0201 CG15

www.teknisi-indonesia.com
2 CPU_EDP_TX0_P CPU_EDP_TX0_N EDP_TX0_CON_N 24
CG16 1 2 0.1U_6.3V_K_X5R_0201 25
CPU_EDP_TX0_N 25
26
CPU_EDP_TX1_P 1 2 0.1U_6.3V_K_X5R_0201 EDP_TX1_CON_P 27 26
CPU_EDP_TX1_P CG17
CPU_EDP_TX1_N 1 2 0.1U_6.3V_K_X5R_0201 EDP_TX1_CON_N 28 27
CPU_EDP_TX1_N CG18
29 28
CPU_EDP_PW M 2 1 PANEL_PW M +3VS_TOUCH 30 29
CPU_EDP_PW M DMIC_DATA_CON 30
DG3 RB521CM-30T2R_VMN2M-2 31
DMIC_CLK_CON 32 31
LCD_SELF_TEST_ON 2 1 33 32
USB20_7_N 34 33
DG4 RB521CM-30T2R_VMN2M-2
CAMERA USB20_7_N
1

USB20_7_P 35 34
USB20_7_P 35
RG9 36
PCH_I2C2_SDA_TS 37 36
1/20W_10K_5%_0201 TOUCH PCH_I2C2_SCL_TS 38 37
38
RG17 2 @ 1 1/16W_0_5%_0402 +1V8_DMIC 39 41
+1.8VS
2

39 GND1
+3VS RG18 1 @ 2 0_0402_5% +3VS_CAM W= 80 mil +3VS_CAM 40
40 GND2
42
LCD_Self_test HIGHS_FC5AF401-3181H
1
CG19 ME@
0.1U_6.3V_K_X5R_0201
@
2

JCAM1
+3VS_CAM 1
+3VALW_PCH +3VS_TOUCH +3VS_TOUCH +3VS_CAM W= 80 mil 1
2
3 2
TOUCH IR_FW_FLASH_EN
IR_FW_FLASH_EN
IR_CAM_DTCT_N
4 3
4
5
IR_CAM_DTCT_N 5
6
2
1

2
1

7 6
8 7
RPG11 RPG12
8
1/16W_2.2K_5%_4P2R_0404 1 1/16W_2.2K_5%_4P2R_0404
QG9 9
10 GND1
3
4

3
4

GND2
+3VS HIGHS_FC5AF081-2931H
3 2 PCH_I2C2_SCL_TS ME@
PCH_I2C2_SCL
B L2SK3541M3T5G_SOT723-3 RG55 2 @ 1 1/20W_10K_5%_0201 TOUCH_INT_N B

1
QG10
add at 2022/1/28
3 2 PCH_I2C2_SDA_TS
PCH_I2C2_SDA
L2SK3541M3T5G_SOT723-3
+3VS
Ton=5.5ns @5V
Toff=35ns @5V
2

400K spec=300ns RG24 +3VS MAX 1.2A +3VS_CAM

CPU_EDP_ENBKL 1 @ 2 RG25 1/20W_4.7K_5%_0201
CPU_EDP_ENBKL
1/20W_0_5%_0201 @ @
PCH_I2C2_SCL RG1 1 @ 2 1/20W_0_5%_0201 PCH_I2C2_SCL_TS J17 2 1 JUMP_43X39
1

2 1
PCH_I2C2_SDA RG3 1 @ 2 1/20W_0_5%_0201 PCH_I2C2_SDA_TS BKOFF_N 1 @ 2 RG26 BL_ON
BKOFF_N
0_0201_5%

DG13 2 @ 1
RB521CM-30T2R_VMN2M-2

+3VS +3VS_TOUCH
UG6
5 1
IN OUT
TOUCH POWER SWITCH
2
GND
4.7U_6.3V_M_X5R_0402

1U_6.3V_M_X5R_0201

TOUCH_PWRON 4 3
TOUCH_PWRON EN OCB
SY6288C20AAC_SOT23-5 1 1
SA000074P00 CG3525 CG3526
1

1
RG19
CG3527 2 2
1U_6.3V_M_X5R_0201 1/20W_100K_5%_0201
2
2

RPG13
A 1 4 +1.8VS +3VS +3VS A
+1.8VS
2 3 RPG14
DMIC 1 4
1/16W_2.2K_5%_4P2R_0404 2 3
UG7
RG30 2 @ 1 1/20W_0_5%_0201 1 8 1/16W_2.2K_5%_4P2R_0404
DMIC_CLK_CODEC VCCA VCCB
RG29 2 @ 1 0_0201_5% DMIC_CLK 2 7 DMIC_CLK_CON
PCH_DMIC_CLK A0 B0
RG32 2 1 1/20W_33_5%_0201 DMIC_DATA 3 6 DMIC_DATA_CON
PCH_DMIC_DATA A1 B1

DMIC_DATA_CODEC RG31 2 @ 1 1/20W_0_5%_0201 4 5 RG35 1 2 1/20W_10K_5%_0201

+1.8VS
GND OE

FXMA2102UMX_U-MLP8_1P2X1P4

Security Classification LC Future Center Secret Data Title

DMIC_DATA RG36 1 @ 2 1/20W_0_5%_0201 DMIC_DATA_CON Issued Date 2019/12/24 Deciphered Date 2019/12/24
DMIC_CLK RG37 1 @ 2 1/20W_0_5%_0201 DMIC_CLK_CON LCD CAMERA/MIC/TOUCH SREEN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Saturday, March 12, 2022 Sheet 47 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 48 of 108
5 4 3 2 1
 5 4 3 2 1

+5VS
+3VS

+1.2V_HDMI_RT
1
+1.2V_HDMI_RT +3VS
CV543

1
0.1U_6.3V_K_X5R_0201

0_0402_5%
1
2

RV557
0_5%_0603
@

RV556
@ +1.2V_HDMI_RT
USE RT9059GQW SA00005YG00 1 1
@
1 1 1
CV530 @
1 2 2 1

2
CV509 CV505 CV538 CV502 CV522 CV521 CV526 CV534

0.01U_25V_K_X7R_0201

0.01U_25V_K_X7R_0201

0.01U_25V_K_X7R_0201

0.01U_25V_K_X7R_0201

0.1U_6.3V_K_X5R_0201

0.01U_25V_K_X7R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.01U_25V_K_X7R_0201
UV503

1
RT9059GQW_TDFN10_3X3
+1.2V_HDMI_RT 2 2 2 2 2 2 1 1 2
10 5 RV545
VCNTL POK
1/10W_470_5%_0603

2
D +1.2V_HDMI_R D
7 1 RV554 1 @ 2

+1.2V_HDMI_RT_DSG
VIN1 VOUT1
0_5%_0603

1/20W_2.49K_1%_0201

10U_6.3V_M_X5R_0402
22P_25V_J_NPO_0201_MURATA
8 2 1
VIN2 VOUT2

RV555

CV541
9 3 1
VIN3 VOUT3

CV539
@ 2

1
2 +1.2V_HDMI_RT
4 RD_PWR_1P2V_FB

1
FB D
6 11 2
SUSP_N EN GND SUSP
G QV504

1/20W_4.99K_1%_0201
10U_6.3V_M_X5R_0402

1 L2N7002KWT1G_SOT323-3 2 @ 2 @ 2 2 2 @ 2 1 1

1
S

3
CV527 CV503 CV535 CV532 CV537 CV525
CV542

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

4.7U_0402_6.3V6-M
CV507 CV533

RV553

22U_0603_6.3V6-M
2 1 1 1 1 1 1 2 2

2
change LDO at 6/30

C C

+3VS +1.2V_HDMI_RT

+3VS
UV502

24

15
18

43
46

30

11
1

6
VDDTX12_1
VDDTX12_2

VDDRX12_1
VDDRX12_2

VDDA12
VDD33_1
VDD33_2

VDD12_1
VDD12_2
SA0000CUH00

1
RV526 RV552
RT_DCIN_EN 3 37 1/20W_47K_5%_0201 1/20W_47K_5%_0201
DCIN_ENB POWERSWITCH
CV511 1 2 0.1U_0201_6.3V6-K CPU_HDMI_C_TX0_P 44 17 RT_HDMI_TX0_P
CPU_HDMI_TX0_P RT_HDMI_TX0_P

2
1 2 0.1U_0201_6.3V6-K CPU_HDMI_C_TX0_N 45 IN_D0p OUT_D0p 16 RT_HDMI_TX0_N
CV512
CPU_HDMI_TX0_N IN_D0n OUT_D0n RT_HDMI_TX0_N RT_DCIN_EN @ @ HDMI_RT_EQ
CV513 1 2 0.1U_0201_6.3V6-K CPU_HDMI_C_TX1_P 41 20 RT_HDMI_TX1_P
CPU_HDMI_TX1_P 1 2 0.1U_0201_6.3V6-K CPU_HDMI_C_TX1_N 42 IN_D1p OUT_D1p 19 RT_HDMI_TX1_N RT_HDMI_TX1_P
CV514
CPU_HDMI_TX1_N RT_HDMI_TX1_N

1
IN_D1n OUT_D1n

1
CV515 1 2 0.1U_0201_6.3V6-K CPU_HDMI_C_TX2_P 38 23 RT_HDMI_TX2_P RV550 RV548
CPU_HDMI_TX2_P 1 2 0.1U_0201_6.3V6-K CPU_HDMI_C_TX2_N 39 IN_D2p OUT_D2p 22 RT_HDMI_TX2_N RT_HDMI_TX2_P
CV516 1/20W_47K_5%_0201 1/20W_47K_5%_0201
CPU_HDMI_TX2_N IN_D2n OUT_D2n RT_HDMI_TX2_N
CV517 1 2 0.1U_0201_6.3V6-K CPU_HDMI_C_CLK_P 47 14 RT_HDMI_CLK_P
CPU_HDMI_CLK_P RT_HDMI_CLK_P

2
CPU_HDMI_C_CLK_N IN_CLKp OUT_CLKp RT_HDMI_CLK_N
CV518 1 2 0.1U_0201_6.3V6-K 48 13
CPU_HDMI_CLK_N RT_HDMI_CLK_N @

2
IN_CLKn OUT_CLKn
RV3005 1 @ 2 1/20W_0_5%_0201 HDMI_RT_RST 35 12
HDMI_RT_RST_R RESETB CEC_EN
@ 1 HDMI_RT_PDB 4 9
PDB HDMI_CEC
TV501
2 7 RT_HDMI_SNK_SCL RV3000 1 @ 2 0_0201_5%
add res at 8/1 HDMI_RT_EQ
TESTMODEB SCL_SNK
RT_HDMI_SNK_SDA
HDMI_SNK_SCL_CON
5 8 RV3001 1 @ 2 0_0201_5%
EQ SDA_SNK HDMI_SNK_SDA_CON
RV551 1 2 4.99K_0402_1% HDMI_RT_REXT 36 29 RT_HDMI_SCL RV3002 1 @ 2 0_0201_5% +3VS
B REXT CSCL EC_SMB_CLK4_R B

RV533 1 2 10K_0201_5% HDMI_RT_PRE 27 28 RT_HDMI_SDA RV3003 1 @ 2 0_0201_5%

PRE CSDA EC_SMB_DATA4_R

2
RV2998 1 @ 2 0_0201_5% CPU_DDC_CLK_R 34 40 RT_HDMI_HPD RV3004 1 @ 2 0_0201_5%
CPU_DDC_CLK SCL_SRC/AUXP HPD_SRC CPU_HDMI_HPD
RV530
RV2999 1 @ 2 0_0201_5% CPU_DDC_DATA_R 33 10 1/20W_10K_5%_0201
CPU_DDC_DATA SDA_SRC/AUXN RSV1
21 26 RT_HDMI_HPD RV534 1 2 1/20W_100K_5%_0201

1
HDMI_DET HPD_SNK RSV2
RV527 1 @ 2 10K_0201_5% HDMI_RT_I2C_ADDR 31 25 HDMI_RT_RST
+3VS I2C_ADDR NC
RV537 1 @ 2 10K_0201_5% HDMI_RT_ID 32 49
+3VS HDMI_ID EPAD 1
CV524
1U_6.3V_M_X5R_0201
PS8409AQFN48GTR2-C0_QFN48_6X6 2

+3VS
+3VS +3VS
1/20W_2.2K_5%_0201

1/20W_2.2K_5%_0201

4.7K_0201_5%

4.7K_0201_5%
2

QV501

CPU_DDC_CLK 4 3 HDMI_SNK_SCL_CON
1

S1 D1
RV524

RV541

RV525

RV547

5 2
G1 G2
@ @
A CPU_DDC_CLK @ @ A
HDMI_SNK_SDA_CON 6 1 CPU_DDC_DATA
CPU_DDC_DATA D2 S2

RT_HDMI_SCL

RT_HDMI_SDA
DMN2400UV-7_SOT563-6
@

Security Classification LCFC Highly Confidential Information Title

HDMI_RETIMER
Issued Date 2020/08/03 Deciphered Date 2020/08/03
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Serval/Tiger AMD GEN2
Date: Wednesday, March 02, 2022 Sheet 49 of 108
5 4 3 2 1
 5 4 3 2 1

+5VS_HDMI +5VS_HDMI

1/20W_2.2K_5%_0201

1/20W_2.2K_5%_0201
1

1
RV501

RV502
2
1000P_50V_K_X7R_0201
CV531
EMC_NS@

2
1
D D
JHDMI1 ME@
19
+5VS +5VS_HDMI HDMI_DET HP_DET
18
+5V
17
DDC/CEC_GND
UV501 16
6 1 HDMI_SNK_SDA_CON 15 SDA
IN OUT HDMI_SNK_SCL_CON 14 SCL
HDMI_ILIM Reserved
3 2 13 20
FAULT ILIM RT_HDMI_CLK_N 2 EMC_NS@ 1 HDMI_CLK_CON_N 12 CEC GND1
RV513 0_0402_5%
RT_HDMI_CLK_N CK-

2
4 5 2 11 21
EN GND RT_HDMI_CLK_P 2 EMC_NS@ 1 HDMI_CLK_CON_P 10 CK_shield GND2
2 RV529 CV501 RV514 0_0402_5%
RT_HDMI_CLK_P CK+

61.9K_0201_1%

4.7U_0402_6.3V6-M
CV523 7 RT_HDMI_TX0_N RV515 2 EMC_NS@ 1 0_0402_5% HDMI_TX0_CON_N 9 22
GND_PAD RT_HDMI_TX0_N D0- GND3
0.1U_0201_6.3V6-K 8
1 RT_HDMI_TX0_P 2 EMC_NS@ 1 HDMI_TX0_CON_P 7 D0_shield 23
RV516 0_0402_5%
RT_HDMI_TX0_P

1
1 RT_HDMI_TX1_N EMC_NS@ 1 HDMI_TX1_CON_N D0+ GND4
RV517 2 0_0402_5% 6
RT_HDMI_TX1_N 5 D1-
TPS2553DRVR_SON6_2X2
RT_HDMI_TX1_P EMC_NS@ 1 HDMI_TX1_CON_P D1_shield
RV518 2 0_0402_5% 4
RT_HDMI_TX1_P RT_HDMI_TX2_N EMC_NS@ 1 HDMI_TX2_CON_N D1+
RV519 2 0_0402_5% 3
RT_HDMI_TX2_N 2 D2-
RT_HDMI_TX2_P EMC_NS@ 1 HDMI_TX2_CON_P D2_shield
RV520 2 0_0402_5% 1
RT_HDMI_TX2_P D2+
SINGA_2HE3Y62-000111F
C C

LV501
1 RT_HDMI_CLK_N 4
4 3
3 HDMI_CLK_CON_N

CV529
3.3P_0201_25V9-C RT_HDMI_CLK_P 1 2 HDMI_CLK_CON_P DV503 DV501
2 1 2 HDMI_CLK_CON_N HDMI_CLK_CON_N HDMI_TX1_CON_N HDMI_TX1_CON_N
@ 1 10 1 10
Line-1 NC1 Line-1 NC1
EXC24CH500U_4P HDMI_CLK_CON_P 2 9 HDMI_CLK_CON_P HDMI_TX1_CON_P 2 9 HDMI_TX1_CON_P
EMC@ Line-2 NC2 Line-2 NC2
HDMI_TX0_CON_N 4 7 HDMI_TX0_CON_N HDMI_TX2_CON_N 4 7 HDMI_TX2_CON_N
LV502 Line-3 NC3 Line-3 NC3
RT_HDMI_TX0_N 4 3 HDMI_TX0_CON_N HDMI_TX0_CON_P 5 6 HDMI_TX0_CON_P HDMI_TX2_CON_P 5 6 HDMI_TX2_CON_P
4 3 Line-4 NC4 Line-4 NC4
3 3
RT_HDMI_TX0_P HDMI_TX0_CON_P GND1 GND1
1 2
1 2 8 8
GND2 GND2
EXC24CH500U_4P AZ1143-04F-R7G_DFN2510P10E10 AZ1143-04F-R7G_DFN2510P10E10
EMC@ EMC@ EMC@ EMC
LV503
B RT_HDMI_TX1_N 4 3 HDMI_TX1_CON_N B
4 3

RT_HDMI_TX1_P 1 2 HDMI_TX1_CON_P
1 2
DV502
EXC24CH500U_4P 1 1
+5VS_HDMI 10 9 +5VS_HDMI
EMC@
HDMI_DET 2 2 9 8 HDMI_DET
LV504
RT_HDMI_TX2_N 4 3 HDMI_TX2_CON_N HDMI_SNK_SCL_CON 4 4 7 7 HDMI_SNK_SCL_CON
4 3
HDMI_SNK_SDA_CON 5 5 6 6 HDMI_SNK_SDA_CON
RT_HDMI_TX2_P 1 2 HDMI_TX2_CON_P
1 2
3 3
EXC24CH500U_4P 8
EMC@
PUSB3FR4 DFN2510A-10
Need to use SM070006600 EMC@
changed at 10/29

A A

Security Classification LCFC Highly Confidential Information Title

HDMI_CONN
Issued Date 2020/08/03 Deciphered Date 2020/08/03
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Serval/Tiger AMD GEN2
Date: Wednesday, March 02, 2022 Sheet 50 of 108
5 4 3 2 1
 5 4 3 2 1

VINT20_IN_F VINT20_IN
TBTA_VBUS20 TBTA_VBUS20_F
QB5 QB6
AONR32314_DFN8 AONR32314_DFN8
1 8 8 1
2 7 7 2 F6101
3 6 6 3 1 2
2 5 5

2
5A_32V_0438005.WR
CB74 CB75

4
1U_25V_K_X5R_0402 10U_25V_M_X5R_0603

1
1

D D

TABLE I2C Addressing

change at 8/2 Master: EC TBTB PORT 0x23
I2C1
Slave: PD TBTC PORT 0x27
TBTA_GATE_VBUS
TBTA_GATE_VBUS
Master: PMC TBTB PORT 0x23
I2C2
TBTA_GATE_VSYS TBTC PORT 0x27
TBTA_GATE_VSYS Slave: PD
+3VALW +3VALW_PD
Master: PD TBTB PORT T.B.D.
RB198 2 @ 1 0_0402_5% I2C3
Slave: RT TBTC PORT T.B.D.

VINT20_IN +3VALW_PD VCC3_LDO_PD TBTA_VBUS20

NSR20F30NXT5G_DSN2-2
10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

1
2 2 2

1U_25V_K_X5R_0402
CB78

CB79
2

1
CB80

DB18

CB81
1 1 1 VCC3_LDO_PD
1

2
TBTB_CC1

1
2
RB203 TBTB_CC2
1/20W_100K_1%_0201

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201
C C

2
0_0201_5%

0_0201_5%
1 1

RB133

RB134
CB12

CB13
@ @
@ @
ADCIN1

G2

G8
H4

H1

H3

H8

C8
A3

A8
B8
F8
UB7 2 2

1
+5VALW
VSYS

LDO_1V5_1
LDO_1V5_2
VIN_3V3

LDO_3V3

PA_VBUS_1
PA_VBUS_2
PA_VBUS_3

PB_VBUS_1
PB_VBUS_2
PB_VBUS_3

1
@
J5 RB205
2 1 +5VALW_PD A7 1/20W_12K_1%_0201
2 1 PP5V_1
B7
C7 PP5V_2
If unused, should tie to GND
22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

2
D7 PP5V_3
JUMP_43X79 2 2 2 2
E7 PP5V_4 G4
CB84

CB82

CB85

CB83

VCC3_LDO_PD
F7 PP5V_5 ADCIN1
PP5V_6
G7
1 1 1 1 H7 PP5V_7 G3
PP5V_8 ADCIN2

A4 VCC3_LDO_PD
TBTA_GATE_VSYS PA_GATE_VSYS
E8 G5
TBTA_GATE_VBUS PA_GATE_VBUS PA_CC1 TBTA_CC1
H5
PA_CC2 TBTA_CC2
1 1
B5 TBTB_CC1 EC_SMB_DATA4 RB230 1 @ 2 1/20W_2.2K_5%_0201
PB_CC1 TBTB_CC2 EC_SMB_CLK4 RB231
@ TP6302 1 B4 A5 CB14 CB15 EC,PMIC,PD 1 @ 2 1/20W_2.2K_5%_0201
1 D8 PB_GATE_VSYS PB_CC2
@ TP6303 220P_25V_K_X7R_0201 220P_25V_K_X7R_0201
PB_GATE_VBUS 2 2
EC_I2C_INT4_N RB28 1 2 1/20W_10K_5%_0201

RPB1
TBTA_RESET_N C1 D1 EC_I2C_INT4_N PCH_SML1_CLK 1 4
TBTA_RESET_N GPIO0 I2C_EC_IRQ# EC_I2C_INT4_N PCH_SML1_DATA
CPU,PD 2 3
PCH_PM_SLP_S4_N RB138 1 @ 2 0_0201_5% PD_GPIO1 G1 E1 EC_SMB_CLK4 Slave @ 1/16W_2.2K_5%_4P2R_0404
PCH_PM_SLP_S4_N GPIO1 I2C_EC_SCL F1 EC_SMB_DATA4 EC_SMB_CLK4
TBTA_PWR_EN PD_GPIO2 I2C_EC_SDA EC_SMB_DATA4 PCH_PD_I2C_INT_N
RB208 1 @ 2 0_0201_5% A6 RB23 1 @ 2 1/20W_10K_5%_0201
TBTA_PWR_EN GPIO2
B B
H6 RPB2
GPIO3 F2 PCH_PD_I2C_INT_N TBT_I2C_SCL 1 4
USB_OC1_N 1 2 0_0201_5% PD_GPIO4 B3 I2C2S_IRQ# PCH_PD_I2C_INT_N TBT_I2C_SDA 2 3
RB209 @
USB_OC1_N GPIO4
E2 PCH_SML1_CLK
I2C2S_SCL PCH_SML1_CLK Slave 1/16W_2.2K_5%_4P2R_0404
C2 D2 PCH_SML1_DATA
GPIO5 I2C2S_SDA PCH_SML1_DATA
GPPC_B2_VRALERT_N RB210 1 @ 2 0_0201_5% PD_GPIO6 F6 BB RETIMER,PD TBT_I2C_INT_N RB17 1 2 1/20W_10K_5%_0201
GPPC_B2_VRALERT_N GPIO6
G6 B1 TBT_I2C_INT_N
GPIO7 I2C3M_IRQ# TBT_I2C_INT_N
B6 A2 TBT_I2C_SCL Master
GPIO8 I2C3M_SCL TBT_I2C_SDA TBT_I2C_SCL
A1
PCH_TBT_FORCE_PWR RB211 PD_GPIO9 I2C3M_SDA_1 TBT_I2C_SDA
1 @ 2 0_0201_5% C6 B2 VCC3_LDO_PD
PCH_TBT_FORCE_PWR GPIO9 I2C3M_SDA_2
GND

SN2011060YBGR_DSBGA50
H2

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201
1

1
1 CB91

RB216

RB217

RB218
0.1U_6.3V_K_X5R_0201

UB9 2

2
TBT_ROM_A0 1 8
A0 VCC
TBT_ROM_A1 2 7 TBT_ROM_WP 2 1
A1 WP
@ @ @ RB219 1/20W_10K_5%_0201
TBT_ROM_A2 3 6 TBT_I2C_SCL_ROM 2 @ 1 TBT_I2C_SCL
A2 SCL
RB214 0_0201_5%

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201
4 5 TBT_I2C_SDA_ROM 2 @ 1 TBT_I2C_SDA
VSS SDA

1
RB215 0_0201_5%

RB220

RB221

RB222
CAT24C256WI-GT3_SO8

Address 1010 A2 A1 A0 R/W

2
For E14-intel:1010 000 R/W

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 TBT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 51 of 108
5 4 3 2 1
 5 4 3 2 1

Burnside Bridge Re-Timer UB3D Y

TCP0_CTX_DRX0_P CB87 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CTX_C_DRX0_P J1

TBT PORTS J12 TBTA_RX0_P
TCP0_CTX_DRX0_P TCP0_CTX_DRX0_N 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CTX_C_DRX0_N J2 ASSRXp1 I IBSSRXp1 J11 TBTA_RX0_N TBTA_RX0_P
CB88
TCP0_CTX_DRX0_N ASSRXn1 BSSRXn1 TBTA_RX0_N 3VALW_TBTA

Port B - TypeC Side

TCP0_CRX_DTX0_P 2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX0_P TBTA_TX0_P

Port A - Host Side

CB18 1 G1 G12
TCP0_CRX_DTX0_P TCP0_CRX_DTX0_N 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX0_N G2 ASSTXp1 IO OBSSTXp1 G11 TBTA_TX0_N TBTA_TX0_P
CB17
TCP0_CRX_DTX0_N ASSTXn1 BSSTXn1 TBTA_TX0_N
TCP0_CTX_DRX1_P CB89 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CTX_C_DRX1_P C1 C12 TBTA_RX1_P RB74 1 @ 2 1/20W_2.2K_5%_0201 TBTA_I2C_SDA 3VALW_TBTA
TCP0_CTX_DRX1_P TCP0_CTX_DRX1_N ASSRXp2 I IBSSRXp2 TBTA_RX1_P
CB90 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CTX_C_DRX1_N C2 C11 TBTA_RX1_N
TCP0_CTX_DRX1_N ASSRXn2 BSSRXn2 TBTA_RX1_N TBTA_I2C_SCL TBT_FLASH_BUSY_N
RB91 1 @ 2 1/20W_2.2K_5%_0201 RB44 1 2 1/20W_10K_5%_0201 FLASH_BUSY# should be shared between BBR#1 and
TCP0_CRX_DTX1_P CB19 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX1_P E1 E12 TBTA_TX1_P RB45 1 @ 2 1/20W_10K_5%_0201
TCP0_CRX_DTX1_P ASSTXp2 IO TBTA_TX1_P BBR#2 with PU to PW_VCC3v3_SX_SYS
TCP0_CRX_DTX1_N CB20 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX1_N E2 OBSSTXp2 E11 TBTA_TX1_N
TCP0_CRX_DTX1_N ASSTXn2 BSSTXn2 TBTA_TX1_N TBTA_I2C_INT
RB76 1 @ 2 1/20W_10K_5%_0201
CPU_TBT_LSX0_TXD RU625 1 @ 2 0_0201_5% CPU_TBT_LSX0_TXD_R M7 M10 TBTA_SBU1
CPU_TBT_LSX0_TXD CPU_TBT_LSX0_RXD RU626 1 2 0_0201_5% CPU_TBT_LSX0_RXD_R L7 PA_LSTX_SBU1 B_SBU1 L10 TBTA_SBU2 TBTA_SBU1
@
CPU_TBT_LSX0_RXD PA_LSRX_SBU2 B_SBU2 TBTA_SBU2 +3VS
TCP0_AUX_P RB159 2 @ 1 0_0201_5% TCP0_AUX_P_R L8 POC_GPIO6:
TCP0_AUX_P TCP0_AUX_N 2 1 0_0201_5% TCP0_AUX_N_R M8 PA_AUX_P BB_TBTA_GPIO_6 1 2 1/20W_10K_5%_0201
RB160 @ RB46 Indication to S0 state for Re-timer
TCP0_AUX_N PA_AUX_N
RB47 1 @ 2 1/20W_10K_5%_0201
AC coupling caps and PU/PD on AUX lines

1
are implemented inside Burnside Bridge.

1/16W_1M_1%_0402

1/16W_1M_1%_0402
D @ @ D

RB52

RB53
3VALW_TBTA
3VALW_TBTA
RB73 1 @ 2 1/20W_10K_5%_0201 BB_FORCE_PWR:

2
BB_TBTA_PERST_N RB75 1 @ 2 1/20W_10K_5%_0201 PCH_TBT_FORCE_PWR RB50 1 @ 2 1/20W_10K_5%_0201 Connect to EC/PCH for FW update
RB51 1 2 1/20W_10K_5%_0201 '0' - by default
'1' - for debug only/FW update
INTEL-RETIMER_BGA105

3VALW_TBTA
3VALW_TBTA
BB_TBTA_POC_GPIO12 RB77 1 @ 2 1/20W_10K_5%_0201
BB_TBTA_FLSH_SHARE_EN RB54 1 @ 2 1/20W_10K_5%_0201 FLSH_SHARE_EN (iPU):
RB78 1 @ 2 1/20W_10K_5%_0201 RB55 1 2 1/20W_10K_5%_0201 '0' - Flash isn't shared, 1 Flash per Re-timer.
BB_TBTA_GPIO_5
'1' - Flash is shared between 2 Re-timers
UB3A RB79 1 2 1/20W_100K_5%_0201
TBTA_TEST_PWRGD RB80 1 2 1/20W_100_1%_0201
TBT_SPI_MOSI RB161 2 @ 1 0_0201_5% BB_SPI_DI C6 C9 TBTA_I2C_SCL RB162 2 @ 1 0_0201_5%
TBT_SPI_MISO 2 1 0_0201_5% BB_SPI_DO B4 EE_DI I2C_SCL E7 TBTA_I2C_SDA 2 1 0_0201_5% TBT_I2C_SCL 3VALW_TBTA
RB163 @ RB164 @ FLSH_MSTR_SLV (iPU):

FLASH
TBT_SPI_CS_N 2 1 0_0201_5% BB_SPI_CS_N B6 EE_DO I2C_SDA
A10 TBTA_I2C_INT 2 1 0_0201_5% TBT_I2C_SDA
RB165 @ RB166 @ Should be used only when DG_FLSH_SHARE_EN is High.
TBT_SPI_CLK BB_SPI_CLK EE_CS_N I2C_INT TBTA_FORCE_PWR RB168 TBT_I2C_INT_N BB_TBTA_FLSH_MSTR_SLV RB56
RB167 2 @ 1 0_0201_5% C7 B10 2 @ 1 0_0201_5% 1 @ 2 1/20W_10K_5%_0201 '0' - Set Re-timer to be Slave on shared flash SPI I/F.
EE_CLK FORCE_PWR A9 TBT_FLASH_BUSY_N PCH_TBT_FORCE_PWR 1 @ 2 1/20W_10K_5%_0201
RB57 '1' - Set Re-timer to be Master on shared flash SPI I/F

POC GPIO
+VCC3V3_LC_TBTA FLASH_BUSY_N BB_TBTA_GPIO_5
B9

DEBUG
POC_GPIO_5 FLSH_MSTR_SLV of BBR#1 (set as Master) should be PU

MISC &
RB65 A8 BB_TBTA_GPIO_6
1 8 TBTA_TDI A3 S0 power only POC_GPIO_6 B8 BB_TBTA_PERST_N and PD for BBR#2 (set as Slave)
TBTA_TMS TDI PERST_N TBTA_SMBUS_SCL RB175 1 PCH_SML0_CLK
2 7 C3 A7 @ 2 0_0201_5%
3 6 TBTA_TCK B5 TMS SMBUS_SCL B7 TBTA_SMBUS_SDA RB176 1 2 0_0201_5% PCH_SML0_DATA PCH_SML0_CLK
@

JTAG
TBTA_TDO TCK SMBUS_SDA BB_TBTA_FLSH_SHARE_EN PCH_SML0_DATA 3VALW_TBTA
4 5 C5 A4
TDO POC_GPIO_10
POC_GPIO_11
A5
A6
BB_TBTA_FLSH_MSTR_SLV
BB_TBTA_POC_GPIO12
XTAL TBTA_RESET_N_R 1 @ 2 1/20W_100K_5%_0201
1/16W_10K_5%_8P4R_0804 RB64
POC_GPIO_12 TBTA_XTAL_25M_IN_R TBTA_XTAL_25M_IN
L3 POC_GPIO_12 have iPU RB1 2 @ 1 0_0402_5% RB68 1 @ 2 1/20W_100K_5%_0201
1 TBTA_THERMDA M11 NC_L3
@ TP77
THERMDA
M12 Main power reset signal
TEST_EDM TBTA_XTAL_25M_OUT_R TBTA_XTAL_25M_OUT
B2 RB2 2 @ 1 0_0402_5% RESET# should be output from PD.
FUSE_VQPS_64 TBTA_RESET_N_R RB169
L11 2 @ 1 0_0201_5% Pull up or Pull down based on USB PD Controller GPIO design.
A11 RESET_N TBTA_RESET_N
MONDC TBTA_XTAL_25M_IN
Note: If the USB PD Controller has a weak pull up present during its
A12 L9 boot, a 10K to 100K Ohm pull down resistor is required to keep the

DEBUG

Main
L12 NC_A12 XTAL_25_IN M9 TBTA_XTAL_25M_OUT
MONDC_SVR XTAL_25_OUT Burnside Bridge RESET_N low during the VCC_3P3_SX power supply
TBTA_TEST_PWRGD B3 L5 TBTA_RSENSE TBTA_XTAL_25M_IN_R ramp. The USB PD controller must drive RESET_N meeting the Burnside
B11 TEST_PWR_GOOD RSENSE L4 TBTA_RBIAS RB71 1 2 1/20W_4.75K_0.5%_0201 Bridge datasheet timing requirements to take it out of reset. If the USB
TEST_EN RBIAS PD Controller can hold RESET_N low during the Burnside Bridge
A1 Place as close as VCC_3P3_SX power supply ramp, a 10K to 100K Ohm pull up and
A2 ATEST_P
possible to pins
YB1 push/pull GPIO on the USB PD controller is recommended.
ATEST_N
1 4
OSC1 NC2
INTEL-RETIMER_BGA105 Y
2 3 TBTA_XTAL_25M_OUT_R
1 NC1 OSC2
CB22 1
C 10P_50V_J_NPO_0402 C
25MHZ_10PF_7R25000006 CB23
UB3C Y 2 10P_50V_J_NPO_0402
2
B1 F12
VSS_ANA_1 VSS_ANA_12
B12 G7
D1 VSS_ANA_2 VSS_ANA_13 H1
VSS_ANA_3 VSS_ANA_14
D2 H2
D11 VSS_ANA_4 VSS_ANA_15 H11
D12
F1
VSS_ANA_5
VSS_ANA_6 GND VSS_ANA_16
VSS_ANA_17
H12
J9
BB_TBTA_PERST_N RB170 2 @ 1 0_0201_5%
PCH_PLT_RST_N
F2 VSS_ANA_7 VSS_ANA_18 K1
F7 VSS_ANA_8
VSS_ANA_9
VSS_ANA_19
VSS_ANA_20
K2 change at 6/16
F9 K11
VSS_ANA_10 VSS_ANA_21
F11 K12
VSS_1
VSS_2
VSS_3

VSS_ANA_11 VSS_ANA_22
F3
F5
G5

INTEL-RETIMER_BGA105

0.9v @850mA
For BBR,
3VALW_TBTA C3718 +VCC0V9_SVR_TBTA_IND +VCC0V9_SVR_TBTA
can be LB2
removed. 1 2

1 1 1 1 0.68UH_HMLQ25201B-R68MSR_4.4A_20% 1 1 1 1 1 1 1 1 1
22U_6.3V_M_X5R_0603
CB68

22U_6.3V_M_X5R_0603
CB69

2.2U_6.3V_M_X5R_0201
CB31

2.2U_6.3V_M_X5R_0201
CB32

CB70
47U_6.3V_M_X5R_0805_H1.25

CB71
47U_6.3V_M_X5R_0805_H1.25

CB35
18P_25V_J_COG_0201

CB36
2.2U_6.3V_M_X5R_0201

CB37
2.2U_6.3V_M_X5R_0201

CB38
2.2U_6.3V_M_X5R_0201

CB39
2.2U_6.3V_M_X5R_0201

CB40
2.2U_6.3V_M_X5R_0201

CB41
2.2U_6.3V_M_X5R_0201
Inductor must be placed on the

Pin J5

Pin E6
Pin M4

Pin M5

UB3B same side as BB. No vias allowed 3VALW_TBTA VCC3_BB_SPI

Pin G6

Pin G3

Pin G9
Pin E3

Pin E9
Pin F6
2 2 2 2 on VCC0v9_SVR_IND 2 2 2@ 2 2 2 2 2 2
L2 E6 IN
+VCC3V3_ANA_TBTA VCC3P3_ANA VCC3P3_SX 3VALW_TBTA
RB3 2 @ 1 0_0402_5% 0.1U_6.3V_K_X5R_0201 1 2 CB21
E5 M4
+VCC3V3_LC_TBTA VCC3P3_LC VCC3P3_SVR_1 M5 3.3V@ 370mA
VCC3P3_SVR_2
F6
+VCC0V9_SVR_TBTA

8
VCC0P9_SVR_ANA_1
G6 J7 UB4
VCC0P9_SVR_ANA_2 VCC3P3A
Power

VCC
E3 L1 Share Same GND plane and connect to M2 & M3 pins (SVR_VSS) of BB
VCC0P9_SVR_1 SVR_IND_1 +VCC0V9_SVR_TBTA_IND
G3 M1 OUT
VCC0P9_SVR_2 SVR_IND_2 TBT_SPI_CS_N TBT_SPI_MOSI
1 5
/CS DI(IO0)
E9 M2
G9 VCC0P9_SVR_PB_ANA_1 SVR_VSS_1 M3
VCC0P9_SVR_PB_ANA_2 SVR_VSS_2 TBT_SPI_MISO TBT_SPI_CLK
2 6
J3 DO(IO1) CLK
+VCC0V9_LC_TBTA VCC0P9_LC
B L6 J5 TBT_SPI_WP_N 3 7 TBT_SPI_HOLD_N B
+VCC0V9_LVR_TBTA VCC0P9_LVR NC_J5 +VCC3V3_ANA_TBTA +VCC3V3_LC_TBTA +VCC0V9_LC_TBTA +VCC0V9_LVR_TBTA /WP(IO2) /HOLD(IO3)
M6 J6
VCC0P9_LVR_SENSE NC_J6

INTEL-RETIMER_BGA105 Y

GND
1 1 1 1 1

Pin E5
Pin L2

CB45
2.2U_6.3V_M_X5R_0201

CB46
2.2U_6.3V_M_X5R_0201

CB47
2.2U_6.3V_M_X5R_0201

Pin L6

CB73
10U_6.3V_M_X5R_0402

CB49
2.2U_6.3V_M_X5R_0201
Pin J5 should be connected to

Pin J3
PW_VCC3v3_SX for DBR
compatibility. for BBR this pin is NC in W25Q80DVSSIG_SO8

4
the package. 2 2 2 2 2

VCC3_BB_SPI

TBT_SPI_MISO RB177 1 2 1/20W_2.2K_5%_0201

TBT_SPI_CS_N RB178 1 2 1/20W_2.2K_5%_0201
TBT_SPI_WP_N RB89 1 2 1/20W_2.2K_5%_0201
TBT_SPI_HOLD_N RB90 1 2 1/20W_2.2K_5%_0201

+3VALW 3VALW_TBTA

RB4 1 @ 2 0_5%_0603
10U_6.3V_M_X5R_0402
CB4035

0.1U_6.3V_K_X5R_0201
CB4036

1
1 1
CB4031
1U_10V_M_X5R_0201 UB4001
2 1 14 +3VTBTA
IN1_1 OUT1_2 2 2
2 13
IN1_2 OUT1_1
RB5 2 @ 1 0_0201_5% 3VTBTAON 3 12 CB4033 1 2 1000P_50V_K_X7R_0201
TBTA_PWR_EN EN1 CT1
0.01U_25V_K_X7R_0402
CB4030

1/20W_47K_5%_0201
RB4031

@ 4 11
+3VALW VBIAS GND

1 5 10 CB4034 1 2 1000P_50V_K_X7R_0201
1

EN2 CT2
6 9
7 IN2_1 OUT2_2 8 +3VTBTA
2 IN2_2 OUT2_1
+3VALW 15
2

Thermal Pad
A A
TPS22976DPUR_WSON_2X3
1
CB4032
1U_10V_M_X5R_0201
2

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 TBT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 52 of 108
5 4 3 2 1
 5 4 3 2 1

Reduce current surge in a DB3 DB4

VBUS-short event. If not AC coupling is recommended for EMC@ EMC@
needed, place 0Ohm VBUS-short protection on SSRX lines. If TBTA_RX0_R_P 1 TBTA_RX0_R_N
not needed, place 0Ohm resistor instead. 2 2 1
resistor instead. 1 2 2 1
TBTA_RX0_P RB183 1 21/20W_2.2_5%_0201 TBTA_RX0_R_P CB50 1 2 0.33U_25V_K_X5R_0201 TBTA_RX0_C_P
TBTA_RX0_P TBTA_RX0_N TBTA_RX0_R_N TBTA_RX0_C_N
Bleeding SSTX/SSRX resistors
RB184 1 21/20W_2.2_5%_0201 CB51 1 2 0.33U_25V_K_X5R_0201
TBTA_RX0_N PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 must be placed near USBC connector if 330nF cap
TBTA_TX0_P TBTA_TX0_R_P TBTA_TX0_C_P DB5 DB6 is being used. Otherwise de-populate.
RB185 1 21/20W_2.2_5%_0201 CB53 1 2 0.22U_25V_K_X5R_0201 EMC@ EMC@
TBTA_TX0_P TBTA_TX0_N TBTA_TX0_R_N TBTA_TX0_C_N
RB186 1 21/20W_2.2_5%_0201 CB54 1 2 0.22U_25V_K_X5R_0201
TBTA_TX0_N TBTA_TX0_R_P 1 TBTA_TX0_R_N TBTA_RX0_C_P
2 2 1 RB109 1 2 1/20W_220K_1%_0201
TBTA_RX1_P TBTA_RX1_R_P TBTA_RX1_C_P 1 2 2 1
RB187 1 21/20W_2.2_5%_0201 CB56 1 2 0.33U_25V_K_X5R_0201
TBTA_RX1_P TBTA_RX1_N TBTA_RX1_R_N TBTA_RX1_C_N TBTA_RX0_C_N
RB188 1 21/20W_2.2_5%_0201 CB57 1 2 0.33U_25V_K_X5R_0201 RB110 1 2 1/20W_220K_1%_0201
TBTA_RX1_N
TBTA_TX1_P RB189 1 21/20W_2.2_5%_0201 TBTA_TX1_R_P CB58 1 2 0.22U_25V_K_X5R_0201 TBTA_TX1_C_P PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 RB111 1 2 1/20W_220K_1%_0201 TBTA_RX1_C_P
TBTA_TX1_P TBTA_TX1_N TBTA_TX1_R_N TBTA_TX1_C_N DB7 DB8
D RB190 1 21/20W_2.2_5%_0201 CB59 1 2 0.22U_25V_K_X5R_0201 EMC@ EMC@ D
TBTA_TX1_N TBTA_RX1_C_N
RB112 1 2 1/20W_220K_1%_0201
TBTA_RX1_R_P 1 2 2 1 TBTA_RX1_R_N
1 2 2 1 TBTA_TX0_C_P
RB4061 1 2 1/20W_220K_1%_0201

RB4062 1 2 1/20W_220K_1%_0201 TBTA_TX0_C_N

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
DB9 DB10 TBTA_TX1_C_P
VCC3_LDO_PD EMC@ EMC@ RB4063 1 2 1/20W_220K_1%_0201
VCC3_LDO_PD
TBTA_TX1_R_P 1 2 2 1 TBTA_TX1_R_N RB4064 1 2 1/20W_220K_1%_0201 TBTA_TX1_C_N
1 2 2 1

1
1 RB118
1/20W_100K_5%_0201 PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
CB60
0.1U_6.3V_K_X5R_0201 UB6

2
2
ESD Diodes should be located as close as possible to USBC.
C4 B4 FLT_REPORT_TBTA_N
VPWR FLT
TBTA_SBU1 D1 B1 TBTA_SBU1_CON
TBTA_SBU2 D2 SBU1 C_SBU1 A1 TBTA_SBU2_CON
SBU2 C_SBU2
TBTA_CC1 D3 A2 TBTA_CC1_CON
TBTA_CC2 D4 CC1 C_CC1 B2
CC2 RPD_G1 DB11 DB12
EMC@ EMC@
A3 TBTA_CC2_CON
C_CC2 B3 TBTA_USB1_CON_N 1 2 2 1 TBTA_USB1_CON_P
RPD_G2 1 2 2 1
C1
GND1 C2
A4 GND2 C3 PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
VBIAS GND3
DB13 DB14
1 EMC@ EMC@

CB61 SN1904020YBFR_DSBGA16 TBTA_SBU1_CON 1 2 2 1 TBTA_SBU2_CON

0.1U_50V_K_X5R_0402 1 2 2 1
2

Co-Design PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

DB15 DB16
EMC@ EMC@

TBTA_CC1_CON 1 2 2 1 TBTA_CC2_CON
C 1 2 2 1 C
TBTA_SBU1 RB193 1 @ 2 1/16W_0_5%_0402 TBTA_SBU1_CON
TBTA_SBU1
TBTA_SBU2 RB194 1 @ 2 1/16W_0_5%_0402 TBTA_SBU2_CON PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
TBTA_SBU2
TBTA_CC1 RB195 1 @ 2 1/16W_0_5%_0402 TBTA_CC1_CON DB17 EMC@
TBTA_CC1 VBUS_TBTA_CON 1 8
TBTA_CC2 TBTA_CC2_CON Vbus GND4
RB196 1 @ 2 1/16W_0_5%_0402 2 7
TBTA_CC2 NC1 GND3
3 6
4 NC2 GND2 5
NC3 GND1
SP1224-01UTG_UDFN-6 FOR ESD
25
26
27
28
29

JUSBC1
VBUS_TBTA_CON VBUS_TBTA_CON
GND_5
GND_6
GND_7
GND_8
GND_9

LB4708 EMC@ VBUS_TBTA_CON

B12 A1 BLM18KG300TN1D_2P
GND_4 GND_1 1 2 VBUS_TBTA_CON
TBTA_RX0_C_P B11 A2 TBTA_TX0_C_P TBTA_VBUS20 Near Near

10P_25V_D_NPO_0201
18P_25V_J_COG_0201
SSRXP1 SSTXP1
LB4709 EMC@ Near Near
TBTA_RX0_C_N TBTA_TX0_C_N PinB9 PinB4 PinA9 PinA4

0.01U_25V_K_X5R_0201

0.01U_25V_K_X5R_0201

0.01U_25V_K_X5R_0201

0.01U_25V_K_X5R_0201

4.7U_25V_M_X5R_0603
B10 A3 BLM18KG300TN1D_2P 1 1
SSRXN1 SSTXN1 1 2 1 1 1 1 1

CB62

CB63

CB64

CB65

CB100
B9 A4 CB4037 CB4038
VBUS_4 VBUS_1
RF_NS@ RF_NS@ @
TBTA_SBU2_CON B8 A5 TBTA_CC1_CON 2 2
SBU2 CC1 1 2 2 2
EMC@ EMC@ EMC@ EMC@ 2 2 2 2 2
TBTA_USB1_CON_N B7 A6 TBTA_USB1_CON_P CB4713 CB4714 CB4715 CB4716
DN2 DP1
1000P_50V_K_X7R_0402 100P_50V_J_NPO_0402 100P_50V_J_NPO_0402 1000P_50V_K_X7R_0402
TBTA_USB1_CON_P B6 A7 TBTA_USB1_CON_N 2 1 1 1
DP2 DN1
B TBTA_CC2_CON B5 A8 TBTA_SBU1_CON B
CC2 SBU1
B4 A9
VBUS_3 VBUS_2
TBTA_TX1_C_N B3 A10 TBTA_RX1_C_N
SSTXN2 SSRXN2
TBTA_TX1_C_P B2 A11 TBTA_RX1_C_P
SSTXP2 SSRXP2
B1 A12
GND_3 GND_2
GND_10

ME@ teknisi-indonesia.com
30

HIGHS_UB1124X-A600X-1H

+3VALW

1U_6.3V_M_X5R_0201 1 2 CB52
UB5

+3VALW 0.1U_6.3V_K_X5R_0201 1 2 CB55 8 7 RB191 1 @ 2

VCC NC
1/16W_0_5%_0402
2

USB20_1_U_P 2 3 USB20_1_P EXC24CH900U_4P

HSD+ D+ USB20_1_P USB20_1_U_P TBTA_USB1_CON_P
RB105 3 4
1/20W_100K_5%_0201 USB20_1_U_N 6 5 USB20_1_N
HSD- D- USB20_1_N
USB20_1_U_N 2 1 TBTA_USB1_CON_N
1

PCH_USB20_1_ON 1 4
OE# GND LB3 EMC@
1

QB4 RB107 TS3USB31ERSER_UQFN8_1P5X1P5 RB192 1 @ 2

LSK3541G1ET2L_VMT3 1/20W_100K_5%_0201 1/16W_0_5%_0402
A 2 A
@
EC_ON_PCH
2
3

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 TBT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 53 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 54 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 55 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 TBT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 56 of 108
5 4 3 2 1
 5 4 3 2 1

CLT1 CLT2 CLT3 ILIM_SEL MOD

0 0 0 X DCH OUT held low

1 1 1 1 CDP Data Connected and Port Power Mgt. Function Active

*
* 1 1 1 0 SDP2 Data Connected

* 1 1 0 X SDP1 Data Connected

* 0 1 0 X SDP1 Data Connected

1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode

+USB_PW R_S1
1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode
PLACE NEAR USB CONN
D D
0 1 1 X DCP_Auto Data Disconnected and Port Power Mgt. Function Active
*

1
0 0 1 X DCP_Auto Data Disconnected and Power Wake Function Active DI6 1

1
AZ5725-01F.R7GR_DFN1006P2X2 1 1

AOU
EMC_NS@ CI1 CI2 + CI3
@ @
0.1U_10V_K_X5R_0201 0.1U_10V_K_X5R_0201 150U_B2_6.3VM_R35M
+5VALW +USB_PWR_S1 2 2 2

2
2
JUSB1 ME@
SN1702001RTER_WQFN16_3X3 1 4
USB20_9_CON_N 2 VBUS PGND 7
SA00008HF00
USB20_9_CON_P 3 D- GND1 10
UI1
USB32_RX1_CON_N 5 D+ GND2 11
1 16 ILIM_HI RI1 1 2 1/16W_20K_1%_0402 USB32_RX1_CON_P 6 SSRX- GND3 12
IN ILIM_HI USB32_TX1_CON_N 8 SSRX+ GND4 13
USB20_9_N 1 2 0_0201_5% USB20_9_R_N 2 15 ILIM_LO RI2 1 2 1/16W_20K_1%_0402 USB32_TX1_CON_P 9 SSTX- GND5
RI61 @ @
USB20_9_N DM_OUT ILIM_LO SSTX+
USB20_9_P RI62 1 @ 2 0_0201_5% USB20_9_R_P 3 14 SINGA_2UB2306-006111F
USB20_9_P DP_OUT GND
DC23300JK00
4 13 USB_OC0_N
ILIM_SEL FAULT USB_OC0_N
5 12
USB_CHG_EN EN OUT
AOU_USB20_9_N
debug circuit delete at 6/21
6 11
CHG_MOD1 CLT1 DM_IN
7 10 AOU_USB20_9_P
CLT2 DP_IN

E_PAD
8 9 AOU_DET_N AOU_DET_N
CHG_MOD3 CLT3 STATUS

17
1
CI4
0.1U_10V_K_X5R_0201
@
2 DI2
USB32_TX1_CON_P 1 1 10 9 USB32_TX1_CON_P

USB32_TX1_CON_N 2 2 9 8 USB32_TX1_CON_N

USB32_RX1_CON_P 4 4 7 7 USB32_RX1_CON_P

USB32_RX1_CON_N 5 5 6 6 USB32_RX1_CON_N

3 3

C 8 C

PUSB3FR4 DFN2510A-10
EMC@

USB32_TX1_N CI5 1 2 0.22U_6.3V_K_X5R_0201 USB32_TX1_C_N RI5 2 @ 1 0_0201_5% USB32_TX1_CON_N

USB32_TX1_N

USB32_TX1_P CI6 1 2 0.22U_6.3V_K_X5R_0201 USB32_TX1_C_P RI6 2 @ 1 0_0201_5% USB32_TX1_CON_P

USB32_TX1_P

USB20_9_CON_P USB20_9_CON_N

2
RI9 1 @ 2 1/16W_0_5%_0402 DI3
AZC199-02S.R7G_SOT23-3
EMC@
LI3 EMC@
AOU_USB20_9_P 4 3 USB20_9_CON_P
4 3

AOU_USB20_9_N 1 2 USB20_9_CON_N
USB32_RX1_N 2 1 0_0201_5% USB32_RX1_CON_N 1 2
USB32_RX1_N RI7 @
EXC24CH900U_4P

1
USB32_RX1_P RI8 2 @ 1 0_0201_5% USB32_RX1_CON_P RI10 1 @ 2 1/16W_0_5%_0402
USB32_RX1_P

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 USB TYPE-A CONNECTOR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 57 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 58 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 59 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/01/19 Deciphered Date 2022/01/19 ThinkPad E14 GEN4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. P060-USB HUB
Date: Wednesday, March 02, 2022 Sheet 60 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 61 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 62 of 108
5 4 3 2 1
 5 4 3 2 1

+3VS_SSD2
+3VS +3VS_SSD2

12P_50V_J_NPO_0402
2.2P_50V_C_NPO_0402
PCIE GEN4 M.2 SSD(M TYPE) 1 1

1
J10 RF13 CF14 CF15

1
JUMP_43X39 RF@ RF@
1/20W_10K_5%_0201 2 2

2
2
@
JSSD2

SSD2_DETECT_N 1 2 +3VS_SSD2
SSD2_DETECT_N GND_1 3.3V_1
3 4
PCIE4_SSD_RXA3_N GND_2 3.3V_2 DF3
5 6
PCIE4_SSD_RXA3_N PCIE4_SSD_RXA3_P PERN3 N/C_2 SSD2_PLP_INT_N PBTN_OUT_N
7 8 2 1
PCIE4_SSD_RXA3_P PERP3 N/C_3 PBTN_OUT_N
9 10
PCIE4_SSD_TXA3_N 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_SSD_C_TXA3_N 11 GND_3 DAS/DSS# 12
CF16
PCIE4_SSD_TXA3_N PCIE4_SSD_TXA3_P PCIE4_SSD_C_TXA3_P PETN3 3.3V_3 RB521CM-30T2R_VMN2M-2
CF17 1 2 0.22U_6.3V_K_X5R_0201 13 14
PCIE4_SSD_TXA3_P PETP3 3.3V_4
D 15 16 D
PCIE4_SSD_RXA2_N 17 GND_4 3.3V_5 18
PCIE4_SSD_RXA2_N PCIE4_SSD_RXA2_P PERN2 3.3V_6
19 20
PCIE4_SSD_RXA2_P PERP2 N/C_4
21 22
PCIE4_SSD_TXA2_N 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_SSD_C_TXA2_N 23 GND_5 N/C_5 24
CF18
PCIE4_SSD_TXA2_N PCIE4_SSD_TXA2_P PCIE4_SSD_C_TXA2_P PETN2 N/C_6
CF19 1 2 0.22U_6.3V_K_X5R_0201 25 26
PCIE4_SSD_TXA2_P PETP2 N/C_7
27 28
PCIE4_SSD_RXA1_N 29 GND_6 N/C_8 30
PCIE4_SSD_RXA1_N PCIE4_SSD_RXA1_P PERN1 N/C_9
31 32
PCIE4_SSD_RXA1_P PERP1 N/C_10
33 34
PCIE4_SSD_TXA1_N 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_SSD_C_TXA1_N 35 GND_7 N/C_11 36
CF20
PCIE4_SSD_TXA1_N PCIE4_SSD_TXA1_P PCIE4_SSD_C_TXA1_P PETN1 N/C_12
CF21 1 2 0.22U_6.3V_K_X5R_0201 37 38 1
PCIE4_SSD_TXA1_P PETP1 DEVSLP
39 40 TP4503
PCIE4_SSD_RXA0_N 41 GND_8 SMB_CLK 42
PCIE4_SSD_RXA0_N PERN0/SATA-B+ SMB_DATA @
PCIE4_SSD_RXA0_P 43 44
PCIE4_SSD_RXA0_P PERP0/SATA-B- SMB_ALERT#
45 46
PCIE4_SSD_TXA0_N 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_SSD_C_TXA0_N 47 GND_9 N/C_16 48
CF22
PCIE4_SSD_TXA0_N PCIE4_SSD_TXA0_P PCIE4_SSD_C_TXA0_P PETN0/SATA-A- N/C_17 SSD2_PLT_RST_N
CF23 1 2 0.22U_6.3V_K_X5R_0201 49 50 RF2 1 @ 2 0_0201_5%
PCIE4_SSD_TXA0_P PETP0/SATA-A+ PERST# SSD2_CLKREQ_N PCH_PLT_RST_N
51 52
CLK_PCIE0_SSD_N GND_10 CLKREQ# SSD2_CLKREQ_N
53 54 TP79 1
CLK_PCIE0_SSD_N CLK_PCIE0_SSD_P REFCLKN PEWAKE#
55 56 RF20 2 1 +3VS_SSD2
CLK_PCIE0_SSD_P REFCLKP N/C_18
57 58 @ 1/20W_10K_5%_0201
GND_11 N/C_19

67 68 SUSCLK_SSD2 RF171 @ 2 1/20W_0_5%_0201 SUSCLK

N/C_1 SUSCLK SUSCLK
RF18 1 @ 2 SATA_PCIE_DET2 69 70
+3VS_SSD2 PEDET 3.3V_7
1/20W_10K_5%_0201 71 72
73 GND_12 3.3V_8 74
75 GND_13 3.3V_9
GND_14 SSD2_PLT_RST_N

77 76 1 1 1 1
PEG1 PEG2
CF24 CF25 CF26 CF28
ARGOS_NASM0-S6705-TS20 @
ME@ 10U_6.3V_M_X5R_0402 0.1U_6.3V_K_X5R_0201 4.7U_6.3V_M_X5R_0402 0.1U_6.3V_K_X5R_0201
2 2 2 2
@

C C

www.teknisi-indonesia.com

+3VS_SSD1

+3VS +3VS_SSD1

12P_50V_J_NPO_0402
2.2P_50V_C_NPO_0402
1 1

1
CF1 CF2

1
PCIE GEN3 M.2 SSD(M TYPE)
J9 RF_NS@ RF_NS@

1
JUMP_43X39 RF5 2 2
@

2
1/20W_10K_5%_0201

2
JSSD1

SSD1_DETECT_N 1 2 +3VS_SSD1
SSD1_DETECT_N GND_1 3.3V_1
3 4
PCIE3_SSD_RX12_N 5 GND_2 3.3V_2 6
PCIE3_SSD_RX12_N PCIE3_SSD_RX12_P PERN3 N/C_2 SSD1_PLP_INT_N PBTN_OUT_N
7 8 DF1 2 1
PCIE3_SSD_RX12_P PERP3 N/C_3 PBTN_OUT_N
9 10 RB521CM-30T2R_VMN2M-2
PCIE3_SSD_TX12_N 1 2 0.22U_6.3V_K_X5R_0201 PCIE3_SSD_C_TX12_N 11 GND_3 DAS/DSS# 12
CF3
PCIE3_SSD_TX12_N PCIE3_SSD_TX12_P PCIE3_SSD_C_TX12_P PETN3 3.3V_3
CF4 1 2 0.22U_6.3V_K_X5R_0201 13 14
PCIE3_SSD_TX12_P PETP3 3.3V_4 +3VS_SSD1
15 16
PCIE3_SSD_RX11_N 17 GND_4 3.3V_5 18
PCIE3_SSD_RX11_N PCIE3_SSD_RX11_P PERN2 3.3V_6
19 20
PCIE3_SSD_RX11_P PERP2 N/C_4
21 22
PCIE3_SSD_TX11_N 1 2 0.22U_6.3V_K_X5R_0201 PCIE3_SSD_C_TX11_N 23 GND_5 N/C_5 24
CF5
PCIE3_SSD_TX11_N

1
PCIE3_SSD_TX11_P 1 2 0.22U_6.3V_K_X5R_0201 PCIE3_SSD_C_TX11_P 25 PETN2 N/C_6 26
CF6
PCIE3_SSD_TX11_P PETP2 N/C_7
27 28 RF6
PCIE3_SSD_RX10_N 29 GND_6 N/C_8 30
PCIE3_SSD_RX10_N PCIE3_SSD_RX10_P PERN1 N/C_9
31 32 1/20W_100K_5%_0201
PCIE3_SSD_RX10_P PERP1 N/C_10
33 34

2
B PCIE3_SSD_TX10_N 1 2 0.22U_6.3V_K_X5R_0201 PCIE3_SSD_C_TX10_N 35 GND_7 N/C_11 36 B
CF7 @
PCIE3_SSD_TX10_N PCIE3_SSD_TX10_P PCIE3_SSD_C_TX10_P PETN1 N/C_12
CF8 1 2 0.22U_6.3V_K_X5R_0201 37 38 DF2 2 1 SATA_1_DEVSLP
PCIE3_SSD_TX10_P PETP1 DEVSLP SATA_1_DEVSLP
39 40 RB521CM-30T2R_VMN2M-2
PCIE3_SSD_RX9_N 41 GND_8 SMB_CLK 42
PCIE3_SSD_RX9_N PCIE3_SSD_RX9_P PERN0/SATA-B+ SMB_DATA
43 44 RF7 1 @ 2 1/20W_10K_5%_0201
PCIE3_SSD_RX9_P PERP0/SATA-B- SMB_ALERT#
45 46
PCIE3_SSD_TX9_N 1 2 0.22U_6.3V_K_X5R_0201 PCIE3_SSD_C_TX9_N 47 GND_9 N/C_16 48
CF9
PCIE3_SSD_TX9_N PCIE3_SSD_TX9_P PCIE3_SSD_C_TX9_P PETN0/SATA-A- N/C_17 SSD1_PLT_RST_N RF4
CF10 1 2 0.22U_6.3V_K_X5R_0201 49 50 1 @ 2 0_0201_5%
PCIE3_SSD_TX9_P PETP0/SATA-A+ PERST# SSD1_CLKREQ_N PCH_PLT_RST_N
51 52
CLK_PCIE1_SSD_N GND_10 CLKREQ# SSD1_CLKREQ_N
53 54 TP78 1
CLK_PCIE1_SSD_N CLK_PCIE1_SSD_P REFCLKN PEWAKE#
55 56 RF21 2 1 +3VS_SSD1
CLK_PCIE1_SSD_P REFCLKP N/C_18
57 58 1/20W_10K_5%_0201
GND_11 N/C_19

67 68 SUSCLK_SSD1 RF8 1 @ 2 1/20W_0_5%_0201 SUSCLK

SATA_PCIE_DET1 N/C_1 SUSCLK SUSCLK
69 70
71 PEDET 3.3V_7 72
73 GND_12 3.3V_8 74
75 GND_13 3.3V_9
GND_14 SSD1_PLT_RST_N

77 76 1 1 1 1
PEG1 PEG2
CF11 CF12 CF13 CF27
ARGOS_NASM0-S6705-TS20 @
ME@ 10U_6.3V_M_X5R_0402 0.1U_6.3V_K_X5R_0201 4.7U_6.3V_M_X5R_0402 0.1U_6.3V_K_X5R_0201
+3VS_SSD1 2 2 2 2
@
1

RF1

1/20W_100K_5%_0201
2

SSD_SATA_PCIE_DET1_N RF9 1 @ 2 0_0201_5% SATA_PCIE_DET1

SSD_SATA_PCIE_DET1_N

SSD_SATA_PCIE_DET1# SSD_DET#
SATA Device GND 0--SATA
PCIe Device NC
1--PCIE

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 M.2 SOCKET PCIE GEN4 MODULE I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 63 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14 GEN4 INTEL
Date: Wednesday, March 02, 2022 Sheet 64 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title
<Title>

Size Document Number Rev

A <Doc> <RevCode>

Date: Wednesday, March 02, 2022 Sheet 65 of 108

5 4 3 2 1
 5 4 3 2 1

Close to Pin41,46 Close to Pin40 Please Close to Pin3 Close to Pin18 Close to Pin20

+5VS +5VS_CLASSD +5VS +5VS_AVDD +3VS +3VS_DVDD +1.8VALW +1.8VALW_DVDDIO +1.8VS +1.8VS_AVDD

RA1 1 @ 2 0_5%_0603 RA2 1 @ 2 0_5%_0603 RA3 1 @ 2 0_5%_0603 RA4 1 @ 2 0_5%_0603 RA5 1 @ 2 0_5%_0603

1U_6.3V_M_X5R_0201
10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402
4.7U_6.3V_M_X5R_0402

4.7U_6.3V_M_X5R_0402
0.1U_10V_K_X5R_0201

0.1U_10V_K_X5R_0201

0.1U_10V_K_X5R_0201

2.2U_10V_K_X5R_0402
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
+1.8VALW
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 CA10 CA11 CA12 CA62 CA58 CA15
@
D @ RA6 @ D
2 2 2 2 2 2 2 2 2 2 2 2 1 2 @ 2 2 2

1/10W_0_5%_0603

AGND AGND

+1.8VALW_DVDDIO +5VS_CLASSD +1.8VS_AVDD

+3VS_DVDD +5VS_AVDD

18

46

41

40

20
3
UA1

DVDD

CPVDD/AVDD2
DVDD-IO

PVDD2

PVDD1

AVDD1
2 SPKR_MUTE_N
PDB SPKR_MUTE_N
14 HDA_BCLK_R RA46 1 @ 2 0_0201_5% PCH_HDA_BCLK
HP_L_JACK_L 1 2 1/20W_47_5%_0201 HP_L_JACK_L_CODEC 27 BCLK PCH_HDA_BCLK
RA7
HP_L_JACK_L HPOUT-L 15 PCH_HDA_SYNC
HP_R_JACK_L 1 2 1/20W_47_5%_0201 HP_R_JACK_L_CODEC 26 SYNC PCH_HDA_SYNC
RA8
HP_R_JACK_L HPOUT-R 47
MIC2_VREFOL 28 JD2
C MIC2_VREFOL MIC2-VREFO-L C
48 JSENSE
MIC2_VREFOR 29 JD1 JSENSE
MIC2_VREFOR MIC2-VREFO-R
1
SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
4 MIC_DATA_R RA47 1 @ 2 1/20W_0_5%_0201 DMIC_DATA_CODEC
30 GPIO0/DMIC-DATA12 DMIC_DATA_CODEC
RING2
RING2 MIC2-L/RING2 5 MIC_CLK_R DMIC_CLK_CODEC
RA10 1 @ 2 1/20W_33_5%_0201
GPIO1/DMIC-CLK DMIC_CLK_CODEC

33P_25V_J_NPO_0201_MURATA
SLEEVE 31
SLEEVE MIC2-R/SLEEVE 6
PC_BEEP PC_BEEP_CODEC I2C-DATA
CA16 1 2 34
PC_BEEP PCBEEP 7
0.1U_6.3V_K_X5R_0201
I2C-CLK
+5VS_AVDD 1 1
8 CA17 CA18
5VSTB_CODEC NC1
RA11 1 2 33 @
5VSTB 9
1/20W_10K_5%_0201 68P_0201_25V8-J
35 NC2 2 2
+5VALW
LINE2-R 10 EMC_NS@
NC3
RA12 1 @ 2 36
LINE2-L 11
1/20W_10K_5%_0201
NC4
12
NC5

CA19 1 2 2.2U_6.3V_K_X5R_0402_YAGEO CBP 23 45 SPK_R+

CBP SPK-OUT-R+ SPK_R+
CBN 24 44 SPK_R-
CBN SPK-OUT-R- SPK_R-
43 SPK_L-
SPK-OUT-L- SPK_L-
42 SPK_L+
MIC2_CAP 32 SPK-OUT-L+ SPK_L+
MIC2-CAP 13
VREF_CODEC 38 DC DET/EAPD
VREF
LDO3_CAP_CODEC 19 16 HDA_SDIN0_R RA13 1 2 1/20W_0_5%_0201 PCH_HDA_SDIN0
B LDO3-CAP SDATA-IN PCH_HDA_SDIN0 B

LDO2_CAP_CODEC21 17 PCH_HDA_SDO
LDO2-CAP SDATA-OUT PCH_HDA_SDO
39
LDO1-CAP 25

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201
CPVEE
Thermal Pad
LDO1_CAP_CODEC

AVSS1

AVSS2
33P_25V_J_NPO_0201_MURATA

33P_25V_J_NPO_0201_MURATA

33P_25V_J_NPO_0201_MURATA

33P_25V_J_NPO_0201_MURATA

CPVEE_CODEC
ALC3287-CG_MQFN48_6X6
37

22

49

1 1 1 1
Close to UA1

2 2 2 2
1U_6.3V_K_X5R_0402
2.2U_10V_K_X5R_0402

2.2U_10V_K_X5R_0402

2.2U_10V_K_X5R_0402

2.2U_10V_K_X5R_0402

2.2U_10V_K_X5R_0402

47P_25V_J_NPO_0201

47P_25V_J_NPO_0201

EMC_NS@ CA52

EMC_NS@ CA53

EMC_NS@ CA54

EMC_NS@ CA55
CA30 CA31

1U_6.3V_K_X5R_0402

1/20W_10K_5%_0201
1 1 1 1 1 1 1 1 1 1 1 1

1
CA24 CA25 CA26 CA27 CA28 CA29 @ @ 1
CA32 RA14
@ @
2 2 2 2 2 2 2 2 2 2 2 2
2
CA20

CA21

CA22

CA23

2
@ @ @ @

AGND AGND AGND AGND AGND

PLACE UNDER ALC3287

A A
RA15 2 @ 1 0_0402_5%

CA34 1 2 0.01U_6.3V_K_X7R_0201_MURATA
EMC_NS@

CA35 1 2 0.01U_6.3V_K_X7R_0201_MURATA RA17 2 @ 1 0_0402_5%

EMC_NS@
Security Classification LC Future Center Secret Data Title

AGND AGND
Issued Date 2019/12/24 Deciphered Date 2019/12/24 AUDIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 66 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 67 of 108
5 4 3 2 1
 5 4 3 2 1

MIC2_VREFOR RA16 1 2 1/16W_2.2K_1%_0402 MIC2_VREFOR_R RA19 2 @ 1 0_0402_5%

MIC2_VREFOR
1
CA36

1U_6.3V_K_X5R_0402
D 2 D

AGND

MIC2_VREFOL RA18 1 2 1/16W_2.2K_1%_0402 MIC2_VREFOL_R RA22 2 @ 1 0_0402_5% RA20 2 @ 1 0_0201_5%

MIC2_VREFOL
1
CA37

1U_6.3V_K_X5R_0402
2 AGND

AGND
RA21 2 @ 1 0_0201_5%
MIC_SLEEVE RA27 2 @ 1 0_0402_5%
MIC_SLEEVE SLEEVE
RA23 2 @ 1 0_0201_5%
1

1
CA38 RA24 2 @ 1 0_0201_5%
RA25 EMC@
@ 1000P_50V_K_X7R_0402 RA26 2 @ 1 0_0201_5%
1/16W_0_5%_0402 2

2
AGND
AGND AGND

MIC_RING2 RA31 2 @ 1 0_0402_5%

MIC_RING2 RING2

1
CA39
RA28
@ 1000P_50V_K_X7R_0402
1/16W_0_5%_0402 2

2
C C

AGND AGND

PC Beep
+3VS

1
EC Beep RA30
1/20W_100K_5%_0201
EC_BEEP RA29 1 2 EC_BEEP_R CA56 1 @ 2 0_0201_5% RA42
EC_BEEP

2
1/16W_4.7K_5%_0402 PC_BEEP_MUX 2 @ 1 PC_BEEP
PC_BEEP
PCH Beep PCH_BEEP RA35 1 2 PCH_BEEP_R CA57 1 @ 2 0_0201_5% 0_0201_5%
PCH_BEEP

1
1/16W_4.7K_5%_0402 @ RA32 2 @ 1 0_0402_5% HP_JACK_IN_R RA33 1 2 1/20W_200K_5%_0201
JSENSE
RA43
+3VALW 1/20W_10K_5%_0201
2

3
QA1
1

RA44
B HP_JACK_IN HP_JACK_IN_MOS B
RA34 1 @ 2 1 LSK3541G1ET2L_VMT3
HP_JACK_IN
3

1/16W_100K_5%_0402 QA2 1/16W_22K_5%_0402

2
2

@
1
EC_MUTE_N_MOS 1 LSK3541G1ET2L_VMT3 CA42
@
2

2.2U_6.3V_M_X5R_0402
2
3

QA3

1 LSK3541G1ET2L_VMT3 AGND AGND

EC_MUTE_N
2

www.teknisi-indonesia.com

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 68 of 108
5 4 3 2 1
 5 4 3 2 1

SPK CONN.
JSPK1
SPK_L- LA2 1 2 BLM18PG330SN1D SPK_L-_CON 1
SPK_L- SPK_L+ SPK_L+_CON 1
LA3 1 2 BLM18PG330SN1D 2
SPK_L+ SPK_R- SPK_R-_CON 2
LA4 1 2 BLM18PG330SN1D 3 5
SPK_R- SPK_R+ 1 2 SPK_R+_CON 4 3 GND1 6
LA5 BLM18PG330SN1D
SPK_R+ 4 GND2
CVILU_CI4304M1HR0-NH
ME@
D D

1500P_25V_K_X7R_0201

1500P_25V_K_X7R_0201

1500P_25V_K_X7R_0201

1500P_25V_K_X7R_0201
1 1 1 1

2 2 2 2

EMC@ CA48

EMC@ CA49

EMC@ CA50

EMC@ CA51

C C
HP_L_JACK_L LA1 1 2 EMC@
HP_L_JACK_L
+3VS MMZ1005Y152CT_2P
HP_R_JACK_L LA6 1 2 EMC@
HP_R_JACK_L
1

MMZ1005Y152CT_2P
RA37

1000P_50V_K_X7R_0402

1000P_50V_K_X7R_0402
@
1/16W_220_5%_0402

1/16W_220_5%_0402

1/16W_10K_5%_0402
1

1 1
2

+3VS_JACK RA38 RA39 CA43 CA44

1 @ @ EMC@ EMC@
CA45
@ 2 2
2

0.1U_6.3V_K_X5R_0201
2

AGND AGND
JHP1

3 MIC_RING2
G/M MIC_RING2
1 HP_L_JACK_CONN
L/R

5
5
6 HP_JACK_IN
6 HP_JACK_IN
2 HP_R_JACK_CONN
R/L
7 4 MIC_SLEEVE
MS M/G MIC_SLEEVE
1/16W_100K_1%_0402

1
B B
1

PESD5V0S1BB_SOD523-2

PESD5V0S1BB_SOD523-2

PESD5V0S1BB_SOD523-2

PESD5V0S1BB_SOD523-2

PESD5V0S1BB_SOD523-2

DA1 DA2 DA3 DA4 DA5

0_0402_5%

LOTES_AJAK0086-P001A11 RA41
RA36

ME@ @ @ EMC@ EMC@ EMC@ EMC@ EMC@

EMC@
CA46 1 2 1U_6.3V_K_X5R_0402
2

2
2

AGND AGND
CA47 1 2 0.1U_6.3V_K_X5R_0201

AGND AGND
AGND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 AUDIO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 69 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 NA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 70 of 108
5 4 3 2 1
 Mini-Express Card(WLAN/WiMAX)
+3VALW +3VALW_PCH connect +3V_WLAN

+3VALW_PCH @
J16 2 1 JUMP_43X39
2 1

+3V_WLAN

1
UN1
RN2 5 1 RN25 1 2
IN OUT

10U_6.3V_M_X5R_0402
1/20W_75K_1%_0201

100U_6.3V_M_X5R_1206_H1.6
0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201

10U_6.3V_M_X5R_0402

0.1U_6.3V_K_X5R_0201

0.01U_25V_K_X5R_0201

10P_50V_J_NPO_0402
CN10

CN11
3.3P_50V_C_NPO_0402
@ 2 1/10W_0_5%_0603 1 1 1 1 1 1 1 1 1 1
GND

CN2

CN3

CN5

CN6

CN7

CN12

CN13

CN14
1 1

CN9
4 3 CN8
EN OCB
10U_6.3V_M_X5R_0402 RF@
SY6288C20AAC_SOT23-5 2 2 2 2 2 2 2 2 2 2
@ @ @ @ 2 2
@

1
RF@

1
2 RN4
CNVI_EN_N
1/20W_200K_5%_0201

1
QN1 @

3
RN5 SSM3K15AMFV_2-1L1B Close to Pin2/Pin4 Close to Pin72/Pin74

2
@ 1/20W_75K_1%_0201 @

2
RN26 1 @ 2
PCH_PM_SLP_WLAN_N
1/20W_0_5%_0201

RN27 1 @ 2
SUSP_N
1/20W_0_5%_0201

+3V_WLAN +3V_WLAN
JWLAN1

2
1 2 RN8
USB20_10_P GND_1 3.3V_1
3 4 1/20W_10K_5%_0201
USB20_10_P USB20_10_N 5 USB_DP 3.3V_2
6 1 @TP4504
USB20_10_N 7 USB_DN LED1_N 8

1
CNVI_WR_D1_N 9 GND_2 PCM_CLK 10 CNVI_RF_RST_N RN28 1 @ 2 0_0201_5%
+3VALW_PCH +3V_WLAN +3V_WLAN CNVI_WR_D1_N CNVI_WR_D1_P 11 WGR_D1N PCM_SYNC/RF_RESET_B
12 CNVI_RF_RESET_N
CNVI_WR_D1_P 13 WGR_D1P PCM_IN
14 CNVI_CLKREQ_R RN29 1 2 0_0201_5%
@
GND_3 PCM_OUT/CLKREQ0 CNVI_MODEM_CLKREQ
2

CNVI_WR_D0_N 15 16 1
CNVI_WR_D0_N WGR_D0N LED2_N @
2

RN43 CNVI_WR_D0_P 17 18 TP4505

CNVI_WR_D0_P 19 WGR_D0P GND_4
20
1/20W_10K_5%_0201 RN10
GND_5 UART_WAKE_N UART_WLAN_WAKE_PCH
2

@ QN2 1/20W_10K_5%_0201 CNVI_WR_CLK_N 21 22 CNVI_BRI_RSP_R RN12 1 2 1/20W_39_5%_0201 CNVI_BRI_RSP

CNVI_WR_CLK_N CNVI_WR_CLK_P 23 WGR_CLKN UART_RX/BRI_RSP CNVI_BRI_RSP
@
1

CNVI_WR_CLK_P WGR_CLKP
NC 24
1

1 3 WLAN_CLKREQ_N_R 25 NC NC 26
WLAN_CLKREQ_N
27 NC NC 28
29 NC NC 30
SSM3K15AMFV_2-1L1B 31 NC 32 CNVI_RGI_DT
33 UART_TX_RGI_DT
34 CNVI_RGI_RSP_R RN14 1 2 1/20W_39_5%_0201 CNVI_RGI_RSP CNVI_RGI_DT
PCIE3_WLAN_TX6_P CN16 1 2 0.1U_10V_K_X5R_0201 PCIE3_WLAN_C_TX6_P GND_6 UART_CTS/RGI_RSP CNVI_BRI_DT CNVI_RGI_RSP
RN30 1 @ 2 0_0201_5%
PCIE3_WLAN_TX6_P
35 36
PCIE3_WLAN_TX6_N CN15 1 2 0.1U_10V_K_X5R_0201 PCIE3_WLAN_C_TX6_N 37 PETP0 UART_CTS/BRI_DT
38 CPU_CL_RST_N RN31 1 2 1/20W_0_5%_0201 EC_TX CNVI_BRI_DT
@
PCIE3_WLAN_TX6_N 39 PETN0 CLINK_RESET
40 CPU_CL_DATA 1 2 1/20W_0_5%_0201 EC_RX
RN32 @
PCIE3_WLAN_RX6_P 41 GND_7 CLINK_DATA 42 CPU_CL_CLK
PCIE3_WLAN_RX6_P PCIE3_WLAN_RX6_N 43 PERP0 CLINK_CLK
44 CPU_CL_DATA CPU_CL_CLK
PCIE3_WLAN_RX6_N PERN0 COEX3 CPU_CL_RST_N CPU_CL_DATA
45 46
CLK_PCIE2_WLAN_P 47 GND_8 COEX2
48 CPU_CL_RST_N
CLK_PCIE2_WLAN_P CLK_PCIE2_WLAN_N 49 REFCLKP0 COEX1
50 SUSCLK_R RN33 1 @ 2 0_0201_5%
CLK_PCIE2_WLAN_N 51 REFCLKN0 SUSCLK
52 WLAN_PERST_N SUSCLK
WLAN_CLKREQ_N_R GND_9 PERST0_N BT_OFF_N
53 54 RN34 1 @ 2 0_0201_5%
PCIE_WAKE_N_WLAN 55 CLKREQ0_N W_DISABLE2_N
56 WLAN_OFF_N 1 2 PCH_BT_OFF_N
RN36 @ 0_0201_5%
57 PEWAKE0_N W_DISABLE1_N
58 WLAN_SMB_DATA 1 2 CPU_WLAN_OFF_N
RN35 @ 0_0201_5%
CNVI_WT_D1_N 59 GND_10 A4WP_I2C_DATA
60 WLAN_SMB_CLK 1 2 EC_RX
+3V_WLAN RN37 @ 0_0201_5%
CNVI_WT_D1_N CNVI_WT_D1_P 61 WP_D1N A4WP_I2C_CLK 62 EC_TX
CNVI_WT_D1_P 63 WP_D1P A4WP_IRQ_N
64 1 TP6306
GND_11 REFCLK0 @
1

CNVI_WT_D0_N 65 66
CNVI_WT_D0_N WP_D0N PERST1_N

2
RN18 CNVI_WT_D0_P 67 68 +3V_WLAN
CNVI_WT_D0_P 69 WP_D0P CLKREQ1_N
70
1/20W_200K_5%_0201 RN41
CNVI_WT_CLK_N GND_12 PEWAKE1_N
71 72 1/20W_100K_5%_0201
CNVI_WT_CLK_N CNVI_WT_CLK_P 73 WT_CLKN 3.3V_3
74
2

CNVI_WT_CLK_P 75 WT_CLKP 3.3V_4

1
PCIE_WAKE_N_WLAN GND_13
RN48 1 @ 2 1/20W_0_5%_0201
PCIE_WAKE_N 77 76
GND15 GND14
RN40 1 @ 2 0_0201_5%
PCH_WLAN_WAKE_N
ARGOS_NASE0-S6705-TSH4
ME@
+3V_WLAN SP07001AL00

WLAN_OFF_N 1/20W_10K_5%_0201 2 1 RN21

BT_OFF_N 1/20W_10K_5%_0201 2 1 RN23

WLAN_PERST_N RN39 1 @ 2 0_0201_5%

PCH_PLT_RST_N

RN42 1 @ 2 1/20W_0_5%_0201
CPU_WLAN_PERST_N

WLAN_PERST_N RN52 1 2 1/20W_100K_5%_0201

+1.8VALW

RN50 1 2 1/20W_100K_5%_0201 CNVI_RGI_DT RN49 1 @ 2 1/20W_4.7K_5%_0201

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 WLAN NGFF CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 71 of 108
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 NA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 72 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 NA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 73 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 NA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 74 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

www.teknisi-indonesia.com

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2021/03/18 Deciphered Date 2021/03/18 NA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 75 of 108
5 4 3 2 1
 A B C D E

APS G-Sensor
+3VS +3VS_GS

RS1 2 @ 1 0_0402_5%

TABLE
+3VS_GS
TABLE of G-Sersor (UG1)
+3VS_GS P/N ADDR_SEL Address
Vendor P/N LCFC P/N
RS2 1 @ 2 1/20W_10K_5%_0201 GSENSE_INT UG2 RS7 ST LIS2DWLTR SA00009AQ00
ADDR_SEL 1 12 EC_SMB_CLK1_TSEN_R 2 @ 1 0_0201_5% EC_SMB_CLK1_TSEN H 32h (W) & 33h (R)
EC_SMB_DATA1_TSEN RS5 2 @ 1 0_0201_5% EC_SMB_DATA1_TSEN_R 2 SDO/SA0 SCL/SPC
11
EC_SMB_CLK1_TSEN Kionix KX022-1020 SA000081E00 LIS2DWLTR
1
EC_SMB_DATA1_TSEN +3VS_GS 3 SDA/SDI/SDO NC
10
L 30h (W) & 31h (R) 1
4 VDD_IO CS 9 BOSCH BMA422 SA0000C1V00
GSENSE_INT GSENSE_INT_R RES GND_2
RS6 2 @ 1 0_0201_5% 5 8
+3VS_GS GSENSE_INT INT1 GND_1
1 Test_Point_12MIL 6 7
TP80 @
INT2 VDD H 3Eh (W) & 3Fh (R)
1 1 1 KX022-1020
LIS2DWLTR_LGA12_2X2 CS1 @ @ L 3Ch (W) & 3Dh (R)
1 1 SA00009AQ00 CS2 CS3
1

CS4 CS5 0.1U_6.3V_K_X5R_0201 10U_0402_6.3V6-M 100P_50V_J_NPO_0201

RS3 @ 2 2 2
@ 100P_50V_J_NPO_0201 0.1U_6.3V_K_X5R_0201 CLOSE VDD H 0X18
1/20W_10K_5%_0201 2 2 close to pin7
BMA280
CLOSE VDDIO L 0X19
2

ADDR_SEL
1

RS4
@ 0_0201_5%
2

Thermal Sensor Near UG3

REMOTE1+
Near UG3
REMOTE2+
+3VS

2
1
CS6
1
CS7 UG4 GPU NCT7718_SCL 2
RS11 2 @ 1 0_0402_5% 1 8 RS12 2 @ 1 0_0201_5%
VDD SCL EC_SMB_CLK1_TSEN
2200P_25V_K_X7R_0201 2200P_25V_K_X7R_0201
2 2 REMOTE3+ 2 7 NCT7718_SDA RS13 2 @ 1 0_0201_5%
SSD2 1 D+ SDA EC_SMB_DATA1_TSEN
UG3 REMOTE1- REMOTE2- CS11 REMOTE3- 3 6 NCT7718_ALERT_N 1 @ 2 RS15
+3VS D- ALERT# +3VS
0.1U_6.3V_K_X7R_0201 1/20W_10K_5%_0201
2 1 RS14 2 4 5
F75303M_SCL +3VS T_CRIT# GND
1 10 RS8 2 @ 1 0_0201_5% 1/20W_10K_5%_0201
VCC SCL EC_SMB_CLK1_TSEN2
NCT7718W_MSOP8
0.1U_6.3V_K_X5R_0201

REMOTE1+ 2 9 F75303M_SDA RS9 2 @ 1 0_0201_5%

DP1 SDA EC_SMB_DATA1_TSEN2
1
CS8 REMOTE1- 3 8 F75303M_ALERT_N RS16 1 @ 2
DN1 ALERT#
REMOTE2+ 4 7
1/20W_10K_5%_0201
F75303M_THERM_N RS10 1 @ 2
Near Charger NCT7718W I2
2 DP2 THERM# +3VS
5 6
1/20W_10K_5%_0201 REMOTE1+ C/ SMBusTM address is 1001100xb (x is R/W bit).
REMOTE2-
DN2 GND
1

1
CS9 C
@ 2 QS1
F75303M_MSOP10 100P_50V_J_NPO_0201 B S TR TTC4116FU NPN SC-70-3
2 E SB00001LC00

3
Address 1001_101xb REMOTE1-
Internal pull up 1.2K to 1.5V Near UG4
R for initial thermal shutdown temp REMOTE3+
1
CS12
2200P_25V_K_X7R_0201
Near Fin 2 REMOTE3-

REMOTE2+

TABLE of Thermal Sensor (UTH1) 1

1
CS10 C
@ 2 QS2
100P_50V_J_NPO_0201 B S TR TTC4116FU NPN SC-70-3
Vendor LCFC P/N Description 2 E SB00001LC00

3
FINTEK SA000046C0J S IC F75303M MSOP 10P SENSOR REMOTE2- REMOTE3+

1
CPU

1
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: @ C
CS13 2 QS3
Trace width/space:10/10 mil 2
B
100P_50V_J_NPO_0201 S TR TTC4116FU NPN SC-70-3
E SB00001LC00
Trace length:<8"

3
REMOTE3-

3 3

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:

Trace width/space:10/10 mil
Trace length:<8"

+3VALW +3VS +3VS

+3VS +3VS
RP1 RP2
2

1 4 1 4
R4650 R4651 2 3 2 3
2

2
1/20W_10K_5%_02011/20W_10K_5%_0201
G

G
1

1/16W_4.7K_5%_4P2R_0404 1/16W_4.7K_5%_4P2R_0404
@ @
6 1 6 1
S

S
EC_SMB_CLK1 EC_SMB_CLK1_TSEN2 EC_SMB_CLK1 EC_SMB_CLK1_TSEN
D

D
Q44A Q43A
L2N7002KDW1T1G_SOT363-6 L2N7002KDW1T1G_SOT363-6
5

5
SB000013A00 SB000013A00
G

G
R4654 1 @ 2 1/20W_0_5%_0201 R4648 1 @ 2 1/20W_0_5%_0201

3 4 3 4
S

S
EC_SMB_DATA1 EC_SMB_DATA1_TSEN2 EC_SMB_DATA1 EC_SMB_DATA1_TSEN
D

D
Q44B Q43B
L2N7002KDW1T1G_SOT363-6 L2N7002KDW1T1G_SOT363-6
SB000013A00 SB000013A00
R4655 1 @ 2 1/20W_0_5%_0201 R4649 1 @ 2 1/20W_0_5%_0201

change at 6/21
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 APS G-SENSOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 76 of 108
A B C D E
 5 4 3 2 1

D D

+5VS

C C
40mil

1
J12

1
JUMP_43X39 JFAN1
7
GND2

2
6
GND1
2 5
@ EC_FAN_PWM 5
4
3 4
+5VS_FAN EC_FAN_SPEED 3
2
1 2
FAN_ID 1

1 HIGHS_WS33050-S0351-HF
C88 ME@
@
0.1U_10V_K_X5R_0201
B 2 B

A
Security Classification LC Future Center Secret Data Title A

Issued Date 2019/12/24 Deciphered Date 2019/12/24

FAN CONNECTOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 77 of 108
5 4 3 2 1
 5 4 3 2 1

FPR_RESET_CON
IO_44_Pin conn

1
D D
Q39 D
FPR_RESET 2 @
G

1
+3VL_FP_R +3VALW +USB_PWR_S2
R268 S L2N7002KWT1G_SOT323-3 JIOB1

3
@ 1
2 1
1/20W_10K_5%_0201
3 2

2
4 3
+3VL_FP_R 5 4
6 5
7 6

1
8 7
+3VL 9 8
R425
9
1/16W_330_1%_0402 10
FPR_RESET_CON 10
@ R265 1 2 1/20W_10K_5%_0201 DELINK 11
DELINK 12 11
@
1 2 13 12
FPR_PWR_SHIELD 13
D Q710 R266 1 2 1/20W_10K_5%_0201 14
LAN_DET_N 14
FP_PWRON_N 2 SB000019400 @ 15
LAN_DET_N

1
FPR_DET_N 16 15
G L2N7002KWT1G_SOT323-3
FPR_DET_N PCH_PLT_RST_N 17 16
@ R269 R4641
PCH_PLT_RST_N LAN_WAKE_N 17
S
LAN_WAKE_N 18
3

LAN_CLKREQ_N 19 18
1/20W_10K_5%_0201 1/20W_47K_5%_0201 LAN_CLKREQ_N LAN_DETECT_N 20 19
LAN_DETECT_N

2
PWRBTN_LED_N 21 20
PWRBTN_LED_N PWRSWITCH_N 22 21
PWRSWITCH_N 22
LANPHYPC 23
LANPHYPC PCH_PM_SLP_LAN_N 24 23
PCH_PM_SLP_LAN_N LAN_SML0_CLK 24
25
+3VALW LAN_SML0_CLK LAN_SML0_DATA 25
26
LAN_SML0_DATA FPR_GREEN_LED 27 26
FPR_GREEN_LED FPR_PWR_SHIELD 27
28
FPR_GREEN_LED FPR_PWR_SHIELD FPR_RESET FPR_RESET_CON 28
R267 1 @ 2 1/20W_10K_5%_0201 R270 1 @ 2 29
FPR_RESET 29
1/20W_0_5%_0201 30
USB20_6_P 31 30
Finger Printer USB20_6_P USB20_6_N 32 31
USB20_6_N 32
C 33 C
PCIE3_LAN_TX3_N 34 33
PCIE3_LAN_TX3_N PCIE3_LAN_TX3_P 34
35
CPU <-- LAN PCIE3_LAN_TX3_P
36 35
+3VL +3VL_FP_R PCIE3_LAN_C_RX3_N 37 36
PCIE3_LAN_C_RX3_N PCIE3_LAN_C_RX3_P 37
38
@ CPU --> LAN PCIE3_LAN_C_RX3_P 39 38
CLK_PCIE5_LAN_P 39
R708 1 2 1/10W_0_5%_0603 40
CLK_PCIE5_LAN_P CLK_PCIE5_LAN_N 40
41
CLK_PCIE5_LAN_N 42 41
USB20_3_P 42
Q171 43 45
USB20_3_P USB20_3_N 44 43 GND1 46
LP2301ALT1G_SOT-23-3
IOB USB USB20_3_N 44 GND2
S

3 1 HIGHSTAR_FC5AF441-3181H
1 C707 ME@
1

0.1U_10V_K_X5R_0201 1
R42529 @ C11268
G

1
2

1/16W_22K_5%_0402 C706 0.1U_10V_K_X5R_0201

0.1U_10V_K_X5R_0201 2 @
2
2

+3VL 2

R42541 1 @ 2 LAN_WAKE_N
LAN_WAKE_N_EC
1

1 1/20W_0_5%_0201
1

R42531 C11274
1/20W_100K_5%_0201 0.1U_10V_K_X5R_0201 LAN_WAKE_N_PCH R42542 1 2
1/16W_22K_5%_0402 @ 1/20W_0_5%_0201
RC4156 2
2

L2N7002KDW1T1G_SOT363-6
6

D
2 L2N7002KDW1T1G_SOT363-6

SB000013A00
G
Q714A
USB POWER SWITCH
3

D S
1

5 +5VALW +USB_PWR_S2
FP_PWRON_N 1 SB000013A00
G CC1393
B Q714B B
1U_6.3V_K_X5R_0201 W=80mils U3107 W=80mils 0.1U_10V_K_X5R_0201
S @ 5 1 1 2
4

2 IN OUT
1 C90
C11275 3 USB_OC2_N
FLAG @ USB_OC2_N
0.1U_10V_K_X5R_0201
@ USB_ON_N 4 2
2 USB_ON_N EN GND
G517E2T11U_SOT23-5
1 SA000087K00
C0303

0.1U_10V_K_X5R_0201
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 IO BOARD CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 78 of 108
5 4 3 2 1
 5 4 3 2 1

+3VL

2
RE86 VCC_LPC_ESPI VCC_FSPI RE133 1 @ 2 0_0201_5%
VR_HOT_N H_PROCHOT_N
@ 0_5%_0603 +3VL_EC +3VL_EC_R +3VL_EC +3VL_EC_R

1
RE83
All capacitors close to EC 1

1
RE9 1 @ 2 0_5%_0603 2 1/16W_100_5%_0402 CE23
47P_25V_J_NPO_0201

1000P_50V_K_X7R_0201
0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1 1 1 1 1 1 1 1 CE25 @

2
CE9
CE3 CE4 CE5 CE6 CE7 CE8 0.1U_6.3V_K_X5R_0201 2
1

114
121
127
106
UE1

1
@ @ @ QE3

CE10

12

11

26
50
92

74
2 2 2 2 2 2 2 2 IT8227E-256-CX_LQFP128_14X14

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY6
VCC

VFSPI

AVCC
VCORE
RE135 1 @ 2 1/20W_0_5%_0201 H_PROCHOT_EC 2
PCH_PLT_RST_N
RE136 1 @ 2 0_0201_5% EC_ESPI_RST_N LSK3541G1ET2L_VMT3

3
EC_AGND PCH_ESPI_RST_N
RE15 1 @ 2

0_5%_0603 EC_VPP_PWREN 4 24 LOGO_LED_N_EC RE129 1 @ 2 0_0402_5% +3VS

EC_AGND EC_VPP_PWREN FPR_PWR_SHIELD_EC 5 KBRST#/GPB6 PWM0/GPA0
25 1 2 0_0402_5% LOGO_LED_N
RE183 @
D ESPI_CS_N_EC ALERT#/SERIRQ/GPM6power level with VCC PWM1/GPA1 EC_FAN_PWM PWRBTN_LED_N D
RE99 1 @ 2 0_0201_5% 6 28
PCH_ESPI_CS0_N 1 2 ESPI_IO3_EC 7 ECS#/LFRAME#/GPM5 PWM2/GPA2 29 EC_FAN_PWM EC_FAN_PWM
PCH_ESPI_IO3 RE98 @ 0_0201_5% RE165 1 2 1/20W_100K_5%_0201
ESPI_IO2_EC EIO3/LAD3/GPM3 PWM3/GPA3 EC_ON_PCH_R KBD_BL_PWM EC_FAN_SPEED
PCH_ESPI_IO2 RE96 1 @ 2 0_0201_5% 8 30 RE101 1 @ 2 0_0201_5% RE89 1 2 1/20W_100K_5%_0201
1 2 ESPI_IO1_EC 9 EIO2/LAD2/GPM2 SMCLK5/PWM4/GPA4 31 PM_SLP_SUS_N_EC 1 2 0_0201_5% EC_ON_PCH CPU_VR_READY
PCH_ESPI_IO1 RE94 @ 0_0201_5% RE118 @ RE91 1 2 1/20W_100K_5%_0201
+1.8VALW 1 2 ESPI_IO0_EC 10 EIO1/LAD1/GPM1 SMDAT5/PWM5/GPA5
32 BEEP_N_EC 1 2 0_0201_5% PCH_PM_SLP_SUS_N
VCC_LPC_ESPI PCH_ESPI_IO0 RE93 @ 0_0201_5% RE155 @
ESPI_CLK_EC EIO0/LAD0/GPM0 PWM6/SSCK/GPA6 ACIN_LED EC_BEEP
+3VL +3VALW VCC_FSPI RE100 1 @ 2 0_0201_5% 13 34
PCH_ESPI_CLK EC_WRST_N ESCK/LPCCLK/GPM4 PWM7/RIG1#/GPA7 OTP_RESET_EC ACIN_LED
RE87 1 @ 2 0_5%_0603 14 120 RE143 1 @ 2 0_0201_5%
EC_WRST_N WRST# GPC4 SUSP_N OTP_RESET
CE1
0.1U_6.3V_K_X5R_0201
15 124 +3VL_EC
PCH_PLT_RST_N PLTRST#/ECSMI#/GPD4 GPC6 SUSP_N USB_ON_N

0.1U_6.3V_K_X5R_0201
RE157 1 @ 2 0_5%_0603 16 RE92 1 @ 2 1/20W_100K_5%_0201
EC_RX 17 RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7
66
EC_TX EC_ESPI_RST_N TXD/SOUT0/LPCPD#/GPE6 ADC0/GPI0 BATT_TEMP KB_FN_N +5VALW
RE88 1 @ 2 22 67
BATT_TEMP
EC_USM_EN ERST#/LPCRST#/GPD2 ADC1/GPI1

CE2
1 1/16W_0_5%_0402 1 23 68 AOU_DET_N RE71 1 2 1/20W_100K_5%_0201
ECSCI#/GPD3 ADC2/GPI2
RE120 1 @ 2 0_0201_5% ENBKL 126 69 ACOFF
CPU_EDP_ENBKL GA20/GPB5 ADC3/GPI3 70 FAN_ID_EC 1 2 0_0201_5% ACOFF
RE125 @
2 2
ITE-IT8227E-256/CX_ ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I
DEV_DETECT_N_EC RE114 1 @ 2 0_0201_5%
FAN_ID
ADP_I +3VALW
ADC6/DSR1#/GPI6 DEV_DETECT_N

KSI[0..7]
KSI[0..7] KSI0 58
KSI0/STB#
LQFP128 ADC7/CTS1#/GPI7
73
PSYS EC_ON_PCH RE29 1 2 1/20W_100K_5%_0201
KSI1 59 78 CPU_VR_READY LAN_WAKE_N_EC RE138 1 2 1/20W_100K_5%_0201
KSO[0..17] KSI1/AFD#Don't Pull up DAC2/TACH0B/GPJ2 BKOFF_N CPU_VR_READY KB_FN_N
KSI2 60 79 RE167 1 2 1/20W_100K_5%_0201
KSO[0..17] Don't Pull up
KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT_EC BKOFF_N FAN_ID
KSI3 61 80 RE169 1 2 1/20W_10K_5%_0201
62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 VDDQ_PGOOD_EC
KSI4 RE127 2 @ 1 1/20W_0_5%_0201
VDDQ_PGOOD
KSI4Don't Pull up DAC5/RIG0#/GPJ5
KSI5 63 RE180 1 @ 2 0_0201_5%
64 KSI5Don't Pull up 85 USB_ON_N VGA_AC_DET
KSI6
65 KSI6 PS2CLK0/TMB0/CEC/GPF0
86 PBTN_OUT_N_EC USB_ON_N
KSI7 RE102 1 @ 2 0_0201_5%
VCC_LPC_ESPI KSI7 PS2DAT0/TMB1/GPF1 PCH_PWROK_EC PBTN_OUT_N
KSO0 36 87 RE156 1 @ 2 0_0201_5%
+3VL_EC KSO0/PD0 SMCLK0/GPF2 PM_SLP_S0_N_EC EC_PCH_PWROK +3VL_EC
KSO1 37 88 RE142 1 @ 2 1/20W_0_5%_0201 Battery/Charger/sensor/GPU
KSO1/PD1 SMDAT0/GPF3 PCH_PM_SLP_S0_N
KSO2 38 89 RPE2
KSO2/PD2 PS2CLK2/GPF4 CP_CLK EC_SMB_CLK1
KSO3 39 90 1 4
CP_DATA
1

KSO3/PD3 PS2DAT2/GPF5 EC_SMB_DATA1

KSO4 40 RE177 1 @ 2 0_0201_5% 2 3
PCH_ECLPM_BREAK
1

KSO4/PD4 PCH_DPWROK_EC
KSO5 41 96 RE47 2 1 1/20W_1K_5%_0201
1/16W_22K_5%_0402 42 KSO5/PD5 GPH3/ID3 97 BATT_CHG_LED_N_R RE103 1 2 0_0201_5% PCH_DPWROK
R42532 KSO6 @ 1/16W_2.2K_5%_4P2R_0404
RC4169 KSO6/PD6 GPH4/ID4 FPR_GREEN_LED_R RE117 1 BATT_CHG_LED
1/20W_100K_5%_0201 KSO7 43 98 @ 2 0_0201_5%
44 KSO7/PD7 8mA GPH5/ID5 99 LID_CTL_CP_EC FPR_GREEN_LED +3VL_EC
KSO8 RE141 1 @ 2 0_0201_5% PD/PMIC/HDMI RETIMER
2

FPR_PWR_SHIELD_EC 45 KSO8/ACK# GPH6/ID6 LID_CTL_CP

KSO9 RPE3
2

KSO9/BUSY EC_SPI_CS0_N EC_SMB_DATA4

KSO10 46 101 RE109 1 2 1/20W_49.9_1%_0201 1 4
3

D KSO11 51 KSO10/PE FSCE# 102 EC_SPI_SI RE111 1 2 1/20W_49.9_1%_0201 PCH_SPI0_CS0_N EC_SMB_CLK4 2 3

KSO11/ERR# FMOSI EC_SPI_SO PCH_SPI0_SI
5 KSO12 52 103 RE113 1 2 1/20W_49.9_1%_0201
53 KSO12/SLCT FMISO 105 EC_SPI_CLK PCH_SPI0_SO
G KSO13 RE50 1 2 1/20W_49.9_1%_0201 1/16W_2.2K_5%_4P2R_0404
Q709B KSO13 FSCK PCH_SPI0_CLK
KSO14 54
KSO14
S SB000013A00 KSO15 55 +3VL_EC
4
6

56 KSO15 108 ACIN_EC

D L2N7002KDW1T1G_SOT363-6 KSO16 RE110 1 @ 2 0_0201_5%
KSO16/SMOSI/GPC3 GPB0 LID_SW_N ACIN LID_SW_N
2 1 KSO17 57 109 RE172 1 2 1/20W_100K_5%_0201
FPR_PWR_SHIELD KSO17/SMISO/GPC5 GPB1 LID_SW_N EC_WAKE_N
G @ RE163 1 2 1/20W_100K_5%_0201
Q709A EC_I2C_INT4_N RE16 1 @ 2 1/20W_10K_5%_0201
S SB000013A00 CC1396 PWRSWITCH_N 110 82 EC_VCCST_PWRGD EC_MUTE_N RE159 1 2 1/20W_100K_5%_0201
PWRSWITCH_N
1

PWRSW/GPB3 EGAD/GPE1 EC_VCCST_PWRGD

1 L2N7002KDW1T1G_SOT363-6 2 0.1U_6.3V_K_X5R_0201 LAN_DETECT_N
111 83 EC_ON_5V ACIN_EC RE171 1 2 1/20W_100K_5%_0201
EC_SMB_CLK1 GPB4 EGCS#/GPE2 CHG_MOD1 EC_ON_5V EC_ON_1.8V
C11276 115 84 RE166 1 @ 2 1/20W_100K_5%_0201
EC_SMB_CLK1 EC_SMB_DATA1 116 SMCLK1/GPC1 EGCLK/GPE3 CHG_MOD1 EC_ON_3V
GPU,Battery,Charger,SENSOR RE115 1 2 1/20W_100K_5%_0201
EC_SMB_DATA1 PECI_EC SMDAT1/GPC2 PM_SLP_S4_N_EC EC_ON_5V
@ 0.1U_6.3V_K_X5R_0201 CPU_PECI 1/20W_43_5%_0201 RE26 1 2 117 77 RE104 1 @ 2 0_0201_5%
PCH_PM_SLP_S4_N RE119 1 2 1/20W_100K_5%_0201
C 2 ME_FLASH_EC SMCLK2/PECI/GPF6 TACH2B/GPJ1 EC_MUTE_N_R C
0_0201_5% RE154 1 @ 2 118 100 RE121 1 @ 2 0_0201_5%
EC_MUTE_N
ME_FLASH EC_RTCRST_N_ON 94 SMDAT2/PECIRQT#/GPF7 Mirror code--1 SSCE0#/GPG2 125 LCD_SELF_TEST_ON_ECRE145 1 2 0_0201_5% 1 2 AOU_DET_N
OD(1.8V in) @ SPKR_MUTE_N RE168 1 2 1/20W_100K_5%_0201
EC_SYS_PWROK CRX1/SIN1/SMCLK3/GPH1/ID1 Don't Pull up SSCE1#/GPG0 LCD_SELF_TEST_ON
95 119 RE294 1 2 1/20W_49.9_1%_0201 DE6
EC_SYS_PWROK CTX1/SOUT1/SMDAT3/GPH2/ID2 Don't Pull up FDIO3/DSR0#/GPG6 122 SYSON_EC EC_VR_ON EC_MUTE_N
RE151 1 @ 2 1/20W_0_5%_0201 RB751VM-40TE-17_UMD2M2 RE162 1 @ 2 1/20W_100K_5%_0201
FDIO2/DTR1#/SBUSY/GPG1/ID7
113 TP4_RESET SYSON EC_VR_ON RE161 1 @ 2 1/20W_100K_5%_0201
CRX0/GPC0 DELINK_EC TP4_RESET SUSP_N
123 RE160 1 @ 2 0_0201_5% RE122 1 2 1/20W_100K_5%_0201
112 CTX0/TMA0/GPB2 18 PM_SLP_S3_N_EC DELINK BKOFF_N
RE108 1 @ 2 0_0201_5%
PCH_PM_SLP_S3_N RE124 1 2 1/20W_100K_5%_0201
+3VL_EC PAD_DISABLE EC_ON_3V RING#/CK32KOUT/LPCRST#/GPB7 RI1#/GPD0
107 21
EC_ON_3V GPE4 RI2#/GPD1 LAN_WAKE_N_EC
76 EC_I2C_INT4_N
TACH2A/GPJ0
@ 48
TACH1A/TMA1/GPD7 EC_FAN_SPEED CHG_MOD3
DE1 1 2 RB751V-40_SOD323-2 47
PWRSHUT_N_EC TACH0A/GPD6 EC_SMB_CLK4 EC_FAN_SPEED +3VS
0_0201_5% RE153 1 @ 2 33 19
PWRSHUTDOWN_N GINT/CTS0#/GPD5 SMCLK4/L80HLAT/BAO/GPE0 EC_SMB_DATA4 EC_SMB_CLK4
35 20 PD, PMIC, HDMI RETIMER RPE4
EC_WRST_N EC_ON_1.8V EC_RSMRST_N_R RTS1#/GPE5 SMDAT4/L80LLAT/GPE7 EC_SMB_DATA4 CP_DATA
RE90 1 2 1/20W_100K_5%_0201
EC_RSMRST_N 1/20W_1K_5%_0201 RE80 1 2 93 3 1 4
CLKRUN#/GPH0/ID0 GPH7 USB_CHG_EN CP_CLK 2 3
1
CE11
1U_6.3V_M_X5R_0201 2 RE144 1 @ 2 0_0201_5% 1/16W_4.7K_5%_4P2R_0404
EC_WAKE_N GPJ7 EAR_PWREN
2 0_0201_5% RE126 1 @ 2 AC_PRESENT_R_EC 128 RE173 1 @ 2 1/20W_0_5%_0201
PCH_AC_PRESENT GPJ6 GSENSE_INT VDDQ_PGOOD CE14 1 2 1000P_50V_K_X7R_0201

PCH_PM_SLP_S4_N CE15 1 2 1000P_50V_K_X7R_0201

EMC_NS@
PCH_PM_SLP_S3_N

AVSS
VSS1

VSS2
VSS3
VSS4
VSS5
CE16 1 2 1000P_50V_K_X7R_0201
KSI6 EMC_NS@
PECI_EC CE17 1 2 47P_25V_J_NPO_0201
1

JSW3 EMC_NS@

27
49
91

75
1

104
@ BATT_TEMP CE19 1 2 100P_25V_J_NPO_0201
SHORT PADS EMC_NS@
2

FOR EC DEDBUG,Place on bottom side KSI7 ACIN_EC CE20 1 2 100P_25V_J_NPO_0201

EMC_NS@
JSW2 2 1 SHORT PADS PWRSWITCH_N CE21 1 2 1U_6.3V_M_X5R_0201
@ @
RE292 1 @ 2 0_0201_5% EC_WAKE_N EC_AGND PCH_PLT_RST_N CE22 1 2 220P_25V_K_X7R_0201
1 2 PWRSWITCH_N JSW1 2 1 FP_PWRON_N
+3VL_EC EMC_NS@
RE49 1/20W_100K_5%_0201 @ SHORT PADS

CPU_VR_READY CE26 1 2
0.1U_25V_K_X5R_0201

RE293 1 @ 2 1/20W_0_5%_0201
EC_RTC_RST_N FN_LED_N
1

QE2
+3VS
B RE285 1 @ 2 0_0201_5% EC_USM_EN +3VS LCD_SELF_TEST_ON1/20W_10K_5%_0201 2 1 RE137 B
EC_RTCRST_N_ON 2 EC_ANS
RPE1
100P_25V_J_NPO_0201 2 1 CE24
1

LSK3541G1ET2L_VMT3 RE182 1 @ 2 0_0201_5% 1 4

3

USM_EN_5V 2 3
RE85

2
1/20W_10K_5%_0201 20181106 Core Team Vanness

G
RE284 1 @ 2 0_0201_5% For BOE Panel Issue
USM_EN_3V 1/16W_4.7K_5%_4P2R_0404
2

6 1

S
EC_SMB_CLK4 EC_SMB_CLK4_R

D
QE5A
L2N7002KDW1T1G_SOT363-6
SB000013A00

5
EC_ANS RC4282 1 @ 2 1/20W_100K_5%_0201

G
RE279 1 @ 2 1/20W_0_5%_0201

USM_EN_5V RC4279 1 @ 2 1/20W_100K_5%_0201

ALW_PWRGD 3 4

S
ALW_PWRGD EC_SMB_DATA4 EC_SMB_DATA4_R

D
USM_EN_3V RC4280 1 @ 2 1/20W_100K_5%_0201 QE5B
RE146 1 @ 2 DE4 1 2 EC_RSMRST_N L2N7002KDW1T1G_SOT363-6
+3VALW_PG
1/20W_0_5%_0201 RB521CM-30T2R_VMN2M-2 SB000013A00
RE147 1 @ 2 RE280 1 @ 2 1/20W_0_5%_0201
+5VALW_PG
0_0201_5%
DE5 1 2 PCH_DPWROK
RB521CM-30T2R_VMN2M-2
Emergency Power Loss Early De-assertion of DSW_PWROK control circuit

+3VALW
1

RE1

1/16W_10K_1%_0402
2

DEV_DETECT_N RE2 1 2 1/16W_15K_1%_0402 SSD1_DETECT_N

SSD1_DETECT_N

RE3 1 2 1/16W_51K_1%_0402 KB_BLK_DTCT_N

KB_BLK_DTCT_N
A A

RE4 1 2 1/16W_33K_1%_0402 SSD2_DETECT_N

SSD2_DETECT_N

Vcc 3.3V
RE1 10K +/- 5%
DEVICE_DETECT1# 1.98V 1.675V 1.772V 2.759V 2.533V 3.3V
SSD1_DETECT# V V V X X X
KB_BLK_DTCT# X V X X V X
Security Classification LC Future Center Secret Data Title
SSD2_DETECT# X X V V X X
Issued Date 2019/12/24 Deciphered Date 2019/12/24 EC_IT8227E-256/BX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 79 of 108
5 4 3 2 1
 5 4 3 2 1

D D

+3VALW

1
R26
@
1/16W_300_5%_0402

2
R27 1 2 1/16W_270_1%_0402

POWER ADAPTER Bi-COLOR(ORANGE/WHITE)

6
D
BATT_CHG_LED 2 Q2A
BATT_CHG_LED G 2N7002KDWH_SOT363-6

1
C
1 @ S C

1
C17 R28
EMC_NS@ @
100P_50V_J_NPO_0201 1/16W_100K_5%_0402
2

2
JLED1
BATT_CHG_LED_R A1 C LED_C
ORG

ACIN_LED_R A2
WHI
1222A-S2ST3D-C30-2C-FTK_ORG_WHI
SC50000GM00
+3VALW

1
Not in Common pool,but in ECSL
R29

1
@ 0_0402_5%
R30
@

2
1/10W_300_5%_0603

2
R31 1 2 1/16W_330_1%_0402

3
D

teknisi-indonesia.com
B ACIN_LED 5 Q2B B
ACIN_LED G 2N7002KDWH_SOT363-6
1

1 @ S
4

C18 R32
EMC_NS@ @
100P_50V_J_NPO_0201 1/16W_100K_5%_0402
2
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 Power LED

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 80 of 108
5 4 3 2 1
 5 4 3 2 1

Keyboard CONN
+3V_KB +3V_KB
NUMLOCK_LED CAPSLK_LED +3V_KB

1
RI20 RI21

2
1/16W_300_5%_0402 1/16W_300_5%_0402
@ @ RI68 +3VS +3VALW KSI[0..7]
KSI[0..7]
@ 0_0402_5%

2
KSO[0..17]

1/16W_0_5%_0402
KSO[0..17]

2
RI11 1 @ 2 0_0201_5% RI23 1 2 NUMLOCK_LED RI12 1 @ 2 0_0201_5% RI25 1 2 CAPSLK_LED

1
D 1/20W_100_1%_0201 1/20W_100_1%_0201 D

RI67
0_0402_5%
@

RI16
6

3
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
D D @
NUMLOCK_LED_N 2 QI5A CAPSLK_LED_N 5 QI5B

1
NUMLOCK_LED_N CAPSLK_LED_N
G G JKB1

EMC_NS@

EMC_NS@
2N7002KDWH_SOT363-6 1 2N7002KDWH_SOT363-6 1

1/20W_15K_5%_0201

1/20W_15K_5%_0201

1/20W_15K_5%_0201

1/20W_15K_5%_0201

1/20W_15K_5%_0201

1/20W_15K_5%_0201

1/20W_15K_5%_0201

1/20W_15K_5%_0201
1

1
40 42

CI20

CI21
Pin# Assign

1
39 40 GND2 41
1 @ S 1 @ S RI36 RI32 RI35 RI28 RI33 RI29 RI34 RI30

4
1
NUMLOCK_LED 39 GND1
CI10 CI9 RI27 @ @ @ @ @ @ @ @ 38
EMC@ RI31 2 EMC@ @ 2 KSO17 37 38 1 SENSE3
1 37
100P_50V_J_NPO_0201 @ 100P_50V_J_NPO_0201 1/20W_100K_5%_0201 CI11 KSO16 36

2
2 1/20W_100K_5%_0201 2 TP4MIDDLE 35 36 2 SENSE7

2
34 35
0.1U_6.3V_K_X5R_0201 TP4RIGHT 3 SENSE6
2 2 TP4LEFT 33 34
32 33
CAPSLK_LED 31 32 4 DRV14
31
30 5 SENSE4
KB_FN_N 29 30
KB_FN_N F4_LED 29
28
F1_LED 27 28 6 SENSE1
FN_LED 27
26
+3V_KB +3V_KB 25 26 7 DRV0
+3V_KB 24 25
KSO11 8 SENSE2
24
KSO8 23
F4_LED F1_LED

1
22 23
RI38 KSO10 9 SENSE0

1
22
1/16W_300_5%_0402 KSO12 21
21
RI37 @ KSO9 20 10 DRV4
19 20
1/16W_300_5%_0402 KSO13
19
@ KSO15 18
11 DRV2

2
17 18
KSO5
2

17
KSO7 16
F4_LED F1_LED 16 12 SENSE5
RI13 1 @ 2 0_0201_5% RI401 2 RI14 1 @ 2 0_0201_5% RI42 1 2 KSO6 15
14 15
1/20W_100_1%_0201 1/20W_100_1%_0201 KSO3 13 DRV1
14
KSO1 13
6

3
13

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
D D KSI5 12
F4_LED_N 2 F1_LED_N 5 11 12 14 DRV3
QI6A QI6B KSO2
F4_LED_N F1_LED_N 11
G G 2N7002KDWH_SOT363-6 KSO4 10

EMC_NS@

EMC_NS@
1 1 10 15 DRV6
2N7002KDWH_SOT363-6 KSI0 9

CI22

CI23
1

1
9
1 @ S 1 @ S KSI2 8
16 DRV7
1

4
7 8
CI12 RI43 RI44 KSO0
2 2 7
EMC@ @ CI13 @ KSI1 6
5 6 17 DRV5
100P_50V_J_NPO_0201 1/20W_100K_5%_0201 EMC@ 1/20W_100K_5%_0201 KSI4
2 2 4 5
100P_50V_J_NPO_0201 KSO14 18 DRV15
2

2
4
KSI6 3
2 3
KSI7 19 DRV13
2
KSI3 1
1
20 DRV9
HIGHS_FC5AF401-3181H

2
ME@ 21 DRV12
DI4
PESD5V0U2BT_SOT23-3 22 DRV10
C EMC_NS@ C

FnLock_LED +3V_KB 23 DRV8

1
24 DRV11
Assign Purpose
1

25 VCC
RI45 VCC Vcc 3V for
1/16W_300_5%_0402 LED 26 LED1
@
LED1 LED for FnLk 27 LED2
2

RI15 1 @ 2 0_0201_5% RI471 2 FN_LED

LED2 LED for F1 28 LED3
1/20W_100_1%_0201
0.1U_6.3V_K_X5R_0201

LED3 LED for F4 29 HOTKEY

1

D
FN_LED_N 2 QI7 LED4 LED for
EMC_NS@

FN_LED_N 1 30 GND
G
CI24

2N7002KW_SOT323-3 CapsLK
31 LED4
1

1 @ S LED5 LED for

3

CI14 RI48 2
NumLock 32 MC
EMC@ @
100P_50V_J_NPO_0201 1/20W_100K_5%_0201 33 M1
2
2

34 M2
Assign Purpose
35 M3
MC Common pin
for TrackPoint 36 DRV16
click button
37 DRV17
M1 Left button
38 LED5
M2 Right button
39 NC
M3 Center button
40 NC

+3VS +5VS +5VS_TPCP +5VS +3VS

+3VS_TPCP

Track Point 1

22U_6.3V_M_X5R_0603
B

Click Pad +3VS CI15 B

1/10W_0_5%_0603
1

2
RI49 RI50
@ @ 0_5%_0603 2
Pin # Assign

2
RI51 1 VCC5(5V) RI52 2 @ 1 0_5%_0603

1
@ 0_5%_0603
2 IPD DATA
RI53 1 @ 2 1/16W_0_5%_0402 JTP1

1
+3VS_TPCP 1

+3VS_CP
3 IPD RST 1
TP4DATA 2
TP_RESET_R 3 2
JCP1 4 MIDDILE 3
1 TP4MIDDLE 4
SMB_CLK_3VS 2 1 5 4
SMB_CLK_3VS 5 RIGHT TP4RIGHT
2 5 +5VS_TPCP
3 TP4LEFT 6
3 6
TP4DATA 4 6 LEFT 7 1

22U_6.3V_M_X5R_0603
5 4 8 7
TP4CLK TP4CLK CI16
SMB_DATA_3VS 5 8
SMB_DATA_3VS 6 7 IPD GND 9
7 6 KBD_BL_PWM 10 9
LID_CTL_CP 8 7 KBD_BL_PWM KB_BLK_DTCT_N 11 10
13 2
LID_CTL_CP 8 8 IPD CLK KB_BLK_DTCT_N 11 GND1
CP_CLK 9 12 14 Grug
CP_CLK CP_DATA 9 12 GND2
10 9 LED VCC5 (5V)
CP_DATA 10
11 13
PAD_DISABLE 12 11 GND1 14
PAD_DISABLE 10 LED PWM JAE_FL10F012HA1R3000
12 GND2
ME@
11 BL detection
HIGHS_FC5AF121-2121H
ME@ 12 LED GND

RI54 1 @ 2 1/20W_100K_5%_0201 PAD_DISABLE +3VS

+3VS_TPCP

CI17 1 2 0.1U_6.3V_K_X5R_0201 LID_CTL_CP RI55 1 2 1/20W_100K_5%_0201 RI56

1 4 TP4CLK
TP4_RESET RI17 2 @ 1 0_0201_5% TP_RESET_R 2 3 TP4DATA
TP4_RESET
1/16W_4.7K_5%_4P2R_0404

+3VALW

1
RI60
@ RI58 1 @ 2 1/20W_100K_5%_0201 KB_BLK_DTCT_N
1/20W_10K_5%_0201
A TP4CLK CP_DATA A

2
RI59 1 @ 2 1/20W_100K_5%_0201 KBD_BL_PWM
TP4DATA CP_CLK
100P_50V_J_NPO_0201

100P_50V_J_NPO_0201

1 1
2

CI18 CI19
EMC_NS@ EMC_NS@ DI5
PESD5V0U2BT_SOT23-3
2 2 EMC@
1

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 CP/TPOINT/KB CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 81 of 108
5 4 3 2 1
 5 4 3 2 1

RTC BATTERY

D D

+RTCBATT +3VL VCCRTC

2
D1
Not in Common pool,but in ECSL RB751V-40_SOD323-2
JRTC1
@

1
1 1 2 R1 2 1 D2 J1 2 1 JUMP_43X39 R2002 1 2 1/20W_20K_5%_0201
1 2 2 1 RTC_RST_N
1/16W_10K_5%_0402
2
3 RB751V-40_SOD323-2
GND1 4
GND2
1 1 2

2
C1 C2 C2002 JCMOS
HIGHS_WS33020-S0351-HF 1U_6.3V_K_X5R_0402 1U_6.3V_K_X5R_0402 1U_6.3V_K_X5R_0402_MURATA SHORT PADS
ME@ @ @ @

1
2 2 1

R2003 1 2 1/20W_20K_5%_0201
SRTC_RST_N

2
C2003 JME
1U_6.3V_K_X5R_0402_MURATA SHORT PADS
@

1
1

C C

+5VALW

Earphone CONN.

1
R5
@ 0_5%_0603

2
2
EARPHONE CHARGE

+5V_EAR_C
C3
JEAR1 R2 1 @ 2 0_5%_0603 0.1U_6.3V_K_X5R_0201
1 EAR@
6 U1
GND1 1 +5V_EAR 1 2 BLM18KG300TN1D_2P +5V_EAR_L 1 6
L1 @
1 USB20_2_R_P OUT IN
2 EAR@ 1 2 R4619 +3VL
2 3 USB20_2_R_N EAR_ILIM 2 3 1/20W_100K_5%_0201
3 ILIM FAULT

EAR@
1/20W_49.9K_1%_0201
R8
4
B 4 5 BLE_PWR_EN_N 5 4 EAR_PWREN B
2 2 EAR_PWREN

1
7 5 GND EN
+5VALW C4 C3143
GND2 7
4.7U_0402_6.3V6-M 0.1U_6.3V_K_X5R_0201
GND_PAD
EAR@ EAR@
1

1 1
ELCO_046809605110846+ R6

2
ME@ 1/20W_10K_5%_0201 TPS2553DRVR_SON6_2X2
EAR@ EAR@
2

Not in Common pool,but in ECSL

1

D
Q1 2
2N7002KW_SOT323-3 G SUSP_N
EAR@
S
3

USB20_2_R_P R4 1 @ 2 0_0402_5% USB20_2_P

USB20_2_P

USB20_2_R_N R3 1 @ 2 0_0402_5% USB20_2_N

USB20_2_N
+5V_EAR +5V_EAR_L +5V_EAR_C
1

1000P_25V_K_X7R_0201
EMC_EAR@

100P_50V_J_NPO_0201
EMC_EAR@

10U_6.3V_M_X5R_0402
EAR@

0.01U_25V_K_X5R_0201
EAR@

0.1U_6.3V_K_X5R_0201
EAR@

22U_6.3V_M_X5R_0603

1000P_25V_K_X7R_0201
EMC_EAR@

100P_50V_J_NPO_0201
EMC_EAR@

1U_6.3V_K_X5R_0402
EAR@

1 1 1 1 1 1 1 1 1
@

D3 C5 C7 C9 C10 C11 C12 C6 C8 C13

1

EMC_EAR@
AZ5725-01F.R7GR_DFN1006P2X2
2 2 2 2 2 2 2 2 2
2

A A
2

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 RTC BATTERY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 82 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 AUDIO DEBUG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 83 of 108
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH/ +1.8VS

+3VALW +3VALW_PCH

+3VALW
R4629 1 @ 2
1/8W_0_5%_0805
1
+3VALW_PCH
D C3103 AONR32340C_DFN8-5 D
1U_6.3V_M_X5R_0201 U3104 @ Q711 +1.8VS
2 1 14 +3VPCH_LS J11 2 1 JUMP_43X39 +1.8VALW +1.8VS
2 VIN1_1 VOUT1_2 13 2 1
1 J15 @

1
VIN1_2 VOUT1_1
1 2 1 JUMP_43X39

0.01U_25V_K_X5R_0201
EC_ON_PCH 5 S1 2 1
3 12 C3117 1 2 1800P_25V_K_X7R_0201 C3109 2 1 R3150
EC_ON_PCH

0.01U_25V_K_X5R_0201
ON1 CT1 D S2 3
0.1U_6.3V_K_X5R_0201 1/16W_100_1%_0402
2 S3
4 11 1 C3120 @
+3VALW

G
VBIAS GND

C3145
1 0.1U_6.3V_K_X5R_0201
For DisCharge

2
0.01U_25V_K_X7R_0402
5 10 C3119 1 2 1000P_50V_K_X7R_0201 @ 2

C3144

4
ON2 CT2
@
1
6 9 2 V9B+

C3142
3

1
VIN2_1 VOUT2_2 2
@ 7 8

0_0201_5%
VIN2_2 VOUT2_1

RR53

2
2 @ 15 R3145 1 2 Q713

0.01U_25V_K_X5R_0201
GPAD
RR55 1/20W_100K_5%_0201 SUSP 1 L2SK3541M3T5G_SOT723-3

2
TPS22976DPUR_WSON14P_3X2 1/20W_0_5%_0201 @

1/20W_1M_5%_0201
1

1
1 D Q712
@ 2 SUSP

C3141

R3146
0_0201_5%
SUSP

1
G

RR54
@ 2

1
2 S 2N7002KW_SOT323-3

3
C VCCST_EN / +1.8V_LDO_EN C

UR8
PM_SLP_VCCST_OVRD RR47 1 @ 2 0_0201_5% PM_SLP_VCCST_OVRD_R 1 4 VCCST_EN_R
IN B OUT Y
2
IN A
+3VALW_PCH
3 5
GND Vcc
1

MC74VHC1G32DFT2G_SC70-5 1
RR22 +VCC1P8A_LDO
OR Gate +3VALW PU6602
1/20W_200K_5%_0201 CR45 NCP176BMX180TCG_XDFN6_1P2X1P2
0.1U_6.3V_K_X5R_0201
2

2 6 1
IN OUT

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402
1
5 2 VCC1P8A_LDO_FB 1 @ 2 PR6612
NC FB 1

PC6618
VCC1P8A_LDO_EN

PC6619
@ 4 3 1/16W_0_5%_0402
RR50 2 EN GND

EPAD
UR9 RR25 @

1
VCCIN_AUX_VID1 1 4 VCCIN_AUX_VALID 1 @ 2 VCCIN_AUX_VCCST_PRESENT 1 2 +3VALW_PCH 2
VCCIN_AUX_VID1 VCCIN_AUX_VID0 IN B OUT Y
2 1/20W_0_5%_0201 PR6613
VCCIN_AUX_VID0 IN A
0_0201_5% +3VALW_PCH @ @ @ 1/16W_0_5%_0402

7
1

3 5
GND Vcc
0.1U_6.3V_K_X5R_0201

2
RR26 1
MC74VHC1G32DFT2G_SC70-5 1 1/20W_200K_5%_0201 U8402
CR47
2

1 5 0.1U_6.3V_K_X5R_0201
CR46

IN B VCC 2
2 2 @
OR Gate IN A
RR49
+VCC1P8A_EN_AND

3 4 VCC1P8A_LDO_EN_R 1 2 VCC1P8A_LDO_EN
GNDOUT Y
1/20W_0_5%_0201
NL17SZ08DFT2G_SC70-5 @
@ AND Gate

PCH_PM_SLP_S3_N RR52 1 2 1/20W_0_5%_0201

PCH_PM_SLP_S3_N
@

B B

VCCST
+VCC1P05_OUT_FET

+3VALW_PCH 1
+3VALW_PCH
CR32
1

10U_6.3V_M_X5R_0402
RR16 2
1
1/20W_100K_5%_0201 +VCCST_CPU
CR31
+3VALW_PCH UR7 1U_6.3V_M_X5R_0201 9
2

3V3_VCCST_OVERRIDE 1 4 PM_SLP_VCCST_OVRD 2 IN_3

@
+VCCST_EN 2 IN B OUT Y
+3VALW_PCH 1 8 J14 2 1 JUMP_43X39
1

IN A IN_1 OUT_3 2 1
RR29 PCH_PM_SLP_S3_N RR38 1 @ 2 0_0201_5% 3 5 2 7
PCH_PM_SLP_S3_N GND Vcc IN_2 OUT_2
1/20W_100K_5%_0201 1
3 6
VBIAS OUT_1
MC74VHC1G32DFT2G_SC70-5 CR28
2

QR6 0.1U_6.3V_K_X5R_0201 PM_SLP_VCCST_OVRD RR34 1 2 1/20W_0_5%_0201 VCCST_EN 4 5

D OR Gate 2
@
ON GND
VCCST_OVERRIDE_N 1
G PCH_PM_SLP_S4_N RR36 1 @ 2 1/20W_0_5%_0201
PCH_PM_SLP_S4_N
S L2N7002KN3T5G_SOT883-3 VCCST_EN_R RR48 1 2 1/20W_1K_5%_0201 UR10
2

G5027CRD1D_TDFN8_3X3

1U_6.3V_M_X5R_0201
1/20W_200K_5%_0201
1

1
3

RR37

CR48
@
2

2
A A
QR7
LSI1012N3T5G_SOT883-3

1 2
VCCST_OVERRIDE
1.05V
2

RR41
1/20W_100K_5%_0201
1

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 84 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Change Lise_PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 85 of 108
5 4 3 2 1
 5 4 3 2 1

Screw Hole
HICT3 HICT1
D D
H1 H2 H3 H4 H5 PAD_C2P5D2P5N PAD_C2P5D2P5N
PAD_C8P0D2P5 PAD_C8P0D2P5 PAD_C8P0D2P5 PAD_C8P0D2P5 PAD_C8P0D2P5

@ @

1
@ @ @ @ @

1
WLAN 2280 SSD
H6 H8 H9 H10 H11
PAD_D2P3 PAD_C8P0D2P3 PAD_C8P0D2P3 PAD_C7P0D3P3 PAD_C7P0D3P3

@ @ @ @ @

1
H12 H13 H14 H15 H16 H17
PAD_CT8P0D2P5 PAD_CT6P5D4P0 PAD_CT8P0D2P5 pad_c3p0d3p0n PAD_CT8P0D2P3 pad_o2p5x3p2d2p5x3p2n

@ @ @ @ @ @

1
H18 H19 H20 H21 H22 H23 H26
Pad_CT8P0B6P8D3P4 Pad_CT8P0B6P8D3P4 Pad_CT8P0B6P8D3P4 Pad_CT8P0B6P8D3P4 PAD_D2P5 PAD_D3P0 Pad_CT8P0B6P0D3P4

@ @ @ @ @ @ @

1
C C

CPU

H24 H25
pad_c1p4d1p4n pad_c2p2d2p2n

@ @

1
SPR10 ME@ SPR9 ME@
SPR4 ME@
1 1
1 1 1
1

SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
SHIELDING_SUL-35A2M_9P2X3P3_1P

SPR6 ME@ SPR7 ME@ SPR8 ME@

1 1 1
1 1 1

SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

B B

PCB Fedical Mark PAD

FD1 FD2 FD3 FD4 FD5 FD6
www.teknisi-indonesia.com
1

@ @ @ @ @ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 SCREW HOLE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-E211
Date: Wednesday, March 02, 2022 Sheet 86 of 108
5 4 3 2 1
 5 4 3 2 1

D
+3VL D

1
PR3000
1/16W_1M_5%_0402
PT3000 under CPU bottom side for CPU thermal protection.
This is for thermal team request.
2

VMB2 400MIL 400MIL VMB 400MIL

PF3000 PL3000 EMC@
JBATT1 12A_24V_F1206HB12V024T/M BLM18KG300TN1D_2P
1
1
2
1 2 1 2
BATT+ PR3005
0_0402_5%
2 3 EC_SMB_CK1_R 1 2 @
3
4
4
5
EC_SMB_DA1_R PL3001 EMC@ +3VS
1 BLM18KG300TN1D_2P EMC@

2
9 5 6 PR3001 1 2 1/16W_0_5%_0402 1 2
10 GND1 6 7 EC_SMB_CLK1 1 2
EMC@ PC3000
+3VL

1/16W_16.5K_1%_0402
11 GND2 7 8 0.01U_25V_K_X7R_0402

2
12 GND3 8 2 PC3002
PR3002 1 2 1/16W_0_5%_0402 PR3003 @
GND4 EC_SMB_DATA1

PR3004
1000P_50V_K_X7R_0402 1/16W_0_5%_0402 1
HIGHS_WS33081-S120C-1H
ME@ PR3007 1 2 1/16W_10K_1%_0402 A/D PC3001
BATT_TEMP
0.1U 16V K X7R 0402 PU3000

1
2 1 8 NTC_V_1
BATT_OUT VCC TMSNS1

100K_0402_1%_NCP15WF104F03RC
PR3008 @ 2 7 OTP_N_002 2 1
GND RHYST1
0_0402_5%
2

2 OTP_N_003
EMC_NS@

1 3 6 PR3006
PWRSHUTDOW N_N OT1 TMSNS2
PESD5V0U2BT_SOT23-3

1/16W_10K_1%_0402

1
4 5
OT2 RHYST2

PT3000
G718TM1U_SOT23-8
PD3000
1

C C

2
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 DCIN/RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN41
Date: Wednesday, March 02, 2022 Sheet 87 of 108
5 4 3 2 1
 5 4 3 2 1

D D

PD3050
1SS355VMTE-17

PR3050
PD3051
1SS355VMTE-17 PR3051
1 2 VINT20_IN
PR3053
0_0402_SP 1/16W_100K_1%_0402
1 2 2 1 1 2 1 2 1 2
PWRSHUTDOWN_N VCCGT_VIN
@ PD3052
1/16W_10K_1%_0402 1SS355VMTE-17

2
3
E
PQ3050
B
2 PR3052
PMBT3906 1/16W_750K_5%_0402

1
C
+VCCCORE +VCCIN_AUX

1
540_0402NEW_30%_PRF15BB541NB6RC 540_0402NEW_30%_PRF15BB541NB6RC
PQ3051
3

C PMBT3904_SOT23-3 PT3050 PT3051

C C
1 2 1 2 1
B PQ3052
E 2 2N7002KW_SOT323-3
2

1
D
2 OTP_RESET
G
1 OPT@
S

3
2 1 2 1 2 1
PC3050
1U_25V_K_X7R_0603_YAGEO PT3052 PT3053 PT3054
540_0402NEW_30%_PRF15BB541NB6RC 540_0402NEW_30%_PRF15BB541NB6RC 540_0402NEW_30%_PRF15BB541NB6RC
NVVDD
Charger VDDQ
2 1

PR3054
1/16W_0_5%_0402
UMA@

close GPU MOS

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 88 of 108
5 4 3 2 1
 5 4 3 2 1

D D

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR
10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR
33U_D2_25VM_R40M
PR4002 PR4001
1/16W_56_5%_0402 1/16W_56_5%_0402
VINT20_IN PL4000 EMC@
EMC_NS@ EMC_NS@

1UH_PCMB053T-1R0MS_7A_20% PR4000 PQ4000 PC4023 PL4001 PC4022

10U_25V_K_X5R_0805_H1.25_MUR
1 2 VINT20
1W_0.01_+-1%_1206_100PPM/C
1 2 VBUS
AONY36324 330P_50V_K_X7R_0402
EMC_NS@
2.2UH_CMLE063T-2R2MS_10A_20%
1 2
330P_50V_K_X7R_0402
EMC_NS@
PQ4001
AONH36334
400MIL
V9B+

10U_25V_K_X5R_0805_H1.25_MUR

9
2 2 1

1
PC4000
PC4003 EMC_NS@

1000P_50V_K_X7R_0201

22U_B2_25VM_R100M
0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
0.01U_25V_K_X7R_0201
1

1
5 PC4012 0.047U_25V_K_X7R_0402_MURATA 7 10 +

PC4011

PC4016

PC4017

PC4018

PC4013

PC4019

PC4020

EMC@ PC4021

EMC@ PC4014

@ PC4043

@ PC4044

@ PC4045

@ PC4046

PC4042
0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

1
+ 2 4 6 4

EMC_NS@ PC4004

PC4005

PC4006

PC4007

PC4008

@ PC4009
0.047U_25V_K_X7R_0402_MURATA
EMC_NS@

EMC_NS@

1
PC4001

PC4002

1 1
1

3 CHG_BTST1_R CHG_BTST2_R 5 3

PC4010

2
2

2
PC4015 2
@

1 2

12
2 2 2 1 PR4003 PR4004
2

2 1/10W_0_5%_0603

0.033U_25V_K_X7R_0402
1/10W_0_5%_0603
0.01U_0402_25V7K 2 PQ4002

2
CHG_BTST130 25 CHG_BTST2 PC4064 AONR21357_DFN8
2 @

0.1U_25V_K_X7R_0402_MURATA
1

1
1

1
2 1 BTST1 BTST2 1 2 1 8

PC4026
1/20W_4.99_1%_0201

1/20W_4.99_1%_0201
1 2 LX1_CHG 32 23 LX2_CHG 2 7 25700 输出有震荡现象，需要加22U POS CAP

PR4005

PR4006
PC4025 @ PR4007
1 SW1 SW2
0.033U_25V_K_X7R_0402 1 PC4047 3 6 1W_0.01_+-1%_1206_100PPM/C
1 DL1_CHG DL2_CHG 100P_50V_K_X7R_0201

@
@ PR4033 100P_50V_K_X7R_0201 29 26 5 1 2
1/8W_1_5%_0805 PC4024 LODRV1 LODRV2 @ BATT+

1U_25V_K_X5R_0402
2

2
C 0.47U_25V_K_X5R_0402_YAGEO DH1_CHG 31 24 DH2_CHG PC4028 C
1 1

0.1U_25V_K_X7R_0402_MURATA
4
HIDRV1 HIDRV2

1
2 1 2

PC4032
1U_25V_K_X5R_0402

10U_25V_K_X5R_0805_H1.25_MUR
VBUS_R 1 22

PC4031
VBUS VSYS

1
PC4027

PC4029

PC4030
320MIL

2
change 0603 size to 0805 CHG_ACN 2 21 BATDRV# 2 2

0.1U_25V_K_X7R_0402_MURATA
ACN BATDRV#
VDDA

2
CHG_ACP 3 20 SRP
ACP SRP
PU4000
1 2 7 19 SRN
BQ25710_VDD VDDA SRN
BQ25710_VDD
PR4009 1 2 1/10W_10_5%_0603
BQ25710RSNR_QFN32_4X4

2
PR4008 6 28 1 2 PC4033 2.2U_10V_K_X5R_0402 PR4011 1 2 1/10W_10_5%_0603
ILIM_HIZ REGN
1/16W_10_1%_0402 PR4010
174K_0201_1% @ PC4034 1 PR4012 1 2 2 PR4013 1/20W_10K_1%_0201 PC4035 @
1 1800P_25V_K_X7R_0201 1/20W_40.2K_1%_0201 COMP1 16 17 1 2 1 2680P_25V_K_X7R_0201_MURATA
2 1 PC4036 COMP1 COMP2
@

1
PC4037 @ 33P_25V_J_NPO_0201 COMP2 1 2
1U_25V_K_X5R_0402 H_PROCHOT_N PR4024 1 2 0_0402_5% @ @ 11 18 PC4038 15P_25V_J_NPO_0201
2

1
PROCHOT# CELL_BATPRES
@ PR4031 @
PR4014 PR4027 1 2 0_0402_5% @ EC_SMB_CLK1_Charger 13 0_0402_5%
EC_SMB_CLK1 SCL 8 1 2

100K_0201_1%
EC_SMB_DATA1_Charger 12 IADPT ADP_I
PR4026 1 2 0_0402_5% @
EC_SMB_DATA1 SDA
2 9 PR4025 1 2 0_0402_5% @
IBAT
PR4030 1 2 0_0402_5% @ 4
ACIN CHRG_OK
10 PR4028 1 2 0_0402_5% @
PR4023 1 2 0_0402_5% @ 5
ENZ_OTG
PSYS
27
PSYS
VDDA

22U_6.3V_M_X5R_0603
PGND

1
15

100P_50V_K_X7R_0201

100P_50V_K_X7R_0201

100P_50V_K_X7R_0201

1/16W_137K_1%_0402
1/16W_20K_1%_0402
1

1
CMPOUT 33
PR4015 1
PAD

1
14

PR4016
PR4029 @ 10K_0201_1%
+3VALW
1

B CMPIN B

PR4032

PC4039

PC4040

PC4041

PC7804
1/16W_0_5%_0402 D PR4017
1 2 2 1/20W_82K_1%_0201

1
1
ACOFF G PQ4003 @ 2

1
2N7002KW_SOT323-3 PR4022 @

2
2

S 10K_0201_1% PR4019
3

1/20W_300K_1%_0201
PR4018 @ @

1
1/20W_10K_1%_0201
PD4000

1
PQ4004 D PR4020
@
1

1 2 2 1/20W_100K_1%_0201
BATT_OUT G

2
1SS355VMTE-17

1
S 2N7002KW_SOT323-3

3
@ PR4021
VINT20_IN For EMC,20210425
V9B+ For EMC,20210425
@
1/20W_1M_5%_0201

2
@
PC4048 EMC_NS@

PC4049 EMC_NS@

PC4050 EMC_NS@

PC4053 EMC_NS@

PC4055 EMC_NS@

PC4056 EMC_NS@

PC4057 EMC_NS@

PC4058 EMC_NS@

PC4059 EMC_NS@

PC4060 EMC_NS@

PC4061 EMC_NS@

PC4062 EMC_NS@

PC4063 EMC_NS@
1000P_25V_K_X7R_0402

1000P_25V_K_X7R_0402

1000P_25V_K_X7R_0402

1000P_25V_K_X7R_0402

1000P_25V_K_X7R_0402

1000P_25V_K_X7R_0402

1000P_25V_K_X7R_0402
0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
2 2 2 2 2 2 2
1

1
2

2
1 1 1 1 1 1 1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 BATTERY CHARGER(BQ25700A)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 89 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A
Security Classification LC Future Center Secret Data Title A

Issued Date 2019/12/24 Deciphered Date 2019/12/24 NA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 90 of 108
5 4 3 2 1
 5 4 3 2 1

PR4221
PU4201
PC4236 1/10W_10_5%_0603
1U_6.3V_K_X5R_0402 1 +3VALW_BST 2 1 +3VALW_BST_R
1 2 +3VALW_VCC 20 BOOT
VCC 2
PC4205 PL4201 @
.1U_25V_K_X7R_0603 1.5UH_PCME064T-1R5MS_12A_20% PJ4204
2 +3VALW_LX 1 1 2 +3VALW_P 2 1
V9B+ LX1 3 2 1
+3VALW

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
LX2

2200P_25V_K_X7R_0402
2

0.1U_25V_K_X5R_0402
JUMP_43X79
PJ4203 16 PR4206 @
VIN2

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X7R_0402
+3VALW_VIN

EMC_NS@

EMC_NS@
2 1 15 1/10W_2.2_5%_0603 1 1 1 1 1 1 1 1
2 1 VIN1

PC4219
@

PC4233

PC4234

PC4228

PC4229

PC4230

PC4231

PC4203
JUMP_43X79 1 1 1

1
+3VALW_SN

PC4215

PC4216

PC4217
22
VOUT 2 2 2 2 2 2 2 2 Vout=3.3V+-5%
D USM mode: 0.82V <EN<1.7V 2
Vset=3.35V typ D
2 2 2 PC4222 @
PFM mode: 2.3V <EN 17
EN 1000P_50V_K_X7R_0402 FSW=500KHz typ
PR4214 @ 1
0_0402_5% 23 +3VLP 2 1 TDC=10A
EC_ON_3V
1 2 +3VALW_EN LDO3
4 PR4222 @
+3VL OCP=12A typ
1
PGND1 OVP=Vout*120% typ

22U_6.3V_M_X5R_0603
0.1U_10V_K_X7R_0402
PC4220
1 5 0_0603_SP
PGND2

1
1/16W_1M_1%_0402
PR4203

PC4202
PUSH PULL 6
PR4202 PR4220 PGND3 7 UVP=Vout*60% typ
1/10W_2.2_5%_0603 PGND4 8 2
1/16W_68K_1%_0402 PGND5
2 1 2 +3VALW_VCCEXT 21 9
@ +5VALW 1
VCC_EXT PGND6 10

2
PGND7
11
PGND8

4.7U_6.3V_K_X5R_0402
PC4235
12
PGND9
13
USM_EN_3V_RR 2 PGND10
14
PGND11
EC_3V/5V_USM 18 19
+3VALW PGOOD AGND

1
H USM PQ4201
L PFM defualt L LSI1012XT1G_SC-89-3 RT6310BGQUF_UQFN23_3X3
2

1
USM_EN_3V
PR4200 @

3
1/16W_100K_1%_0402

2
+3VALW_PG
PR4208 @
1/16W_0_5%_0402
1 2 +3VALW_EN

C
+3VL C
1

PR4210
1

1/16W_100K_1%_0402
PR4209
1/16W_100K_1%_0402
2

D
2 PQ4202A
2

G 2N7002KDWH_SOT363-6
3

D
1

PWRSHUTDOWN_N 5 S
1
47K_0402_1%

G @

PQ4202B S
4

PR4205
2

2N7002KDWH_SOT363-6

+5VALW_EN
1

D
2 PQ4203
G 2N7002KW_SOT323-3
@
S
3

B
+3VALW B

1
PR4218
V9B+ 1/16W_100K_1%_0402
PU4200
PJ4200 SY8370C1TMC_QFN13_3X4

2
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

2 1 +5VALW_VIN 1 4
2 1 IN PG +5VALW_PG
0.1U_25V_K_X7R_0402

@
JUMP_43X79 13 +5VALW_BST
BS
1 1 1 2
PC4225

PC4226

PC4224

PC4201 PL4200
0.1U_25V_K_X7R_0402 1.5UH_PCME064T-1R5MS_12A_20% PJ4201
2 2 2 2 +5VALW_LX 1 1 2 +5VALW_P 2 1
+5VALW

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

2200P_25V_K_X7R_0402
LX1 2 1

0.1U_25V_K_X5R_0402
150U_B2_6.3VM_R35M
3 @
GND1
12 1 JUMP_43X79
LX2

2
11
USM mode: 0.82V <EN<1.7V GND2 1 1 1 1 1 1 1 1

EMC_NS@

EMC_NS@
PC4208

PC4221
PR4213 @ PR4207 @ +

PC4211

PC4213

PC4214

PC4212

PC4209

PC4210

PC4200
0_0402_5%
EC_ON_5V
1 2 PFM mode: 2.3V <EN +5VALW_EN 6
EN1
1/10W_2.2_5%_0603
+5VALW_SN 2 2 2 2 2 2 2 2 2

1
8 +5VALW_P @
OUT 2
0.1U_10V_K_X7R_0402
PC4227

push pull 1 PR4212 1 2 1/16W_10K_1%_0402 5 PC4223 @

EN2
1

1
1/16W_1M_1%_0402

+5VALW_FB
PR4219

7
PR4215 FF 1
1000P_50V_K_X7R_0402 Vout=5V+-5%
1/16W_68K_1%_0402 FSW=600KHz typ
1

2
1/16W_1M_1%_0402
PR4211

@ +5VALW_VCC 10 9 +5VLP TDC=10A

2

VCC LDO
OCP=14A typ
1 1 PC4204 1 2 470P_50V_K_X7R_0402 PR4216 1 2 1/16W_1K_1%_0402 OVP=Vout*120% typ
2

EC_3V/5V_USM PC4206 PC4207 UVP=Vout*60% typ

1

A H USM PQ4200 2
4.7U_6.3V_K_X5R_0402
2
4.7U_6.3V_K_X5R_0402 A

L PFM defualt L LSI1012XT1G_SC-89-3

2
USM_EN_5V
3

<Variant Name>
1 2
+5VLP 1
PJ4202
2
+5VL Security Classification LC Future Center Secret Data Title
JUMP_43X39
@ Issued Date 2019/12/24 Deciphered Date 2019/12/24 +3VALW/+5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 91 of 108
5 4 3 2 1
 5 4 3 2 1

D D

+3VALW to +3VS 6.2A request

+3VS load Switch VSYS15 9V--13V
+5VS load Switch +5VALW to +5VS 2.6A request
Load MOS N MOS Id =< 40A Vgs(th) Max >= 2.6V
Rds(on) >= 7.5mohm

Load MOS N MOS Id =< 40A Vgs(th) Max >= 2.6V

Rds(on) >= 7.5mohm

+5VALW PQ4250
+/- 1.5% SB00001NY00
+3VALW PQ4251
AONS32314_DFN8-5
PJ4251
@
+/- 1.5% SB00001NY00 1 2
2 1
1 +5VS
AONS32314_DFN8-5 @ 2

10U_6.3V_M_X5R_0402

1U_6.3V_K_X5R_0402
0.01U_25V_K_X5R_0201
PJ4250 5 3
1
2
2
2 1
1 +3VS JUMP_43X39
1 1 1 1 1

10U_6.3V_M_X5R_0402

1U_6.3V_K_X5R_0402
0.01U_25V_K_X5R_0201
5 3 PC4250 PC4251 PC4252 PC4253 PC4254

4
JUMP_43X39 @ @ @
1 1 1 1 1 10U_6.3V_M_X5R_0402 0.1U_6.3V_K_X5R_0201
2 2 2 2 2
PC4255 PC4256 PC4257 PC4258 PC4259
V9B+
4

@ @ @
10U_6.3V_M_X5R_0402 0.1U_6.3V_K_X5R_0201 5VS_GATE_R
2 2 2 2 2 PR4252
PR4251 1 2 0_0402_5% @ 5VS_GATE 1 2

3VS_GATE_R 1/16W_150K_5%_0402

1
1 D PQ4252
PR4250 1 2 0_0402_5% @ 5VS_GATE PC4260 PR4253 2 SUSP
C G C
0.01U_25V_K_X5R_0201 1/16W_1M_5%_0402
1

2 S 2N7002KW_SOT323-3
1

3
PC4261 PR4254 @
0.01U_25V_K_X5R_0201 1/16W_1M_5%_0402
2
2

+5VL V9B+ +5VALW

+3VS +5VS

1
PR4260 @
1/16W_300K_1%_0402
PR4255
1/16W_300K_1%_0402
PR4256 @
1/16W_1K_5%_0402 For DisCharge

1
SUSP 9V-->5.1V PR4257 PR4258
SUSP
13V-->7.4V 1/10W_470_5%_0603 1/10W_470_5%_0603

1
@
PR4259

2
1/16W_402K_1%_0402

PQ4254 PQ4255

2
2N7002KW_SOT323-3 2N7002KW_SOT323-3

1
D @ D

1
D 2 SUSP 2 SUSP
2 PQ4253 G G
SUSP_N
G 2N7002KW_SOT323-3
S S

3
S

3
B B

www.teknisi-indonesia.com

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 +3VS/+5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 92 of 108

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/01/19 Deciphered Date 2022/01/19 LPDDR5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 93 of 108

5 4 3 2 1
 5 4 3 2 1

PDG:0201 1uf*8
SO-DIMM
PDG:0603 10uf*8
PDG:7343 330uf*1(PH)

D D
+1.2V +1.2V

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

220U_B3_2.5VM_R35M
0.1U_6.3V_K_X7R_0201

100P_50V_J_NPO_0201
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+
CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 CD16 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 PDG:330uf (ph)
EMC@ EMC@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @ 2

+2.5V_DDR PDG:0402 1uf*1 +0.6VS PDG:0402 1uf*2

0603 10uf*1 0603 10uf*1 +1.2V +2.5V_DDR +0.6VS
10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

2.2U_6.3V_M_X5R_0201

2.2U_6.3V_M_X5R_0201

2.2U_6.3V_M_X5R_0201

2.2U_6.3V_M_X5R_0201

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
2.2U_6.3V_M_X5R_0201

2.2U_6.3V_M_X5R_0201

12P_50V_J_NPO_0201

12P_50V_J_NPO_0201

12P_50V_J_NPO_0201
2.2P_25V_C_COG_0201

2.2P_25V_C_COG_0201

2.2P_25V_C_COG_0201
1 1 1 1 1 1 1 1
@ @ 1 1 1 1 1 1 1 1 1 1 1 1
CD29 CD30 CD31 CD32 CD33 CD34 CD35 CD36
@ @ @ @ CD39 CD40 CD41 CD42 CD43 CD44 CD1789 CD1790 CD1791 CD1792 CD1793 CD1794
2 2 2 2 2 2 2 2 @ @ @ RF@ RF@ RF@ RF@ RF@ RF@
2 2 2 2 2 2 2 2 2 2 2 2

C C

MEMORY DOWN
PDG:
VDD/VDDQ:0201 1UF*16,0603 10UF*5
VPP:0201 1UF*8,0603 10UF*3
+1.2V VTT:0201 1UF*8,0603 10UF*2 +1.2V +1.2V +1.2V

12P_50V_J_NPO_0201

100P_50V_J_NPO_0201

100P_50V_J_NPO_0201

100P_50V_J_NPO_0201

100P_50V_J_NPO_0201
2.2P_25V_C_COG_0201
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

CD1725

10U_6.3V_M_X5R_0402

CD1726

10U_6.3V_M_X5R_0402

CD1727

10U_6.3V_M_X5R_0402

CD1730

10U_6.3V_M_X5R_0402

CD1732

10U_6.3V_M_X5R_0402

CD141

CD142

CD143

CD144
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD1709

CD1711

CD1712

CD1714

CD1715

CD1716

CD1719

CD1720

CD1721

CD1722

CD1723

CD1724

CD1777

CD1778

CD1779

CD1780
1 1 1 1 1
CD1741 CD1742
RF@ RF@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
2 2 2 2 2

B MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ B
MD@ MD@ MD@ MD@ MD@

+0.6VS +0.6VS +0.6VS +0.6VS

+0.6VS

change to 0201 package at 6/23

12P_50V_J_NPO_0201
2.2P_25V_C_COG_0201
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

100P_50V_J_NPO_0201

100P_50V_J_NPO_0201
CD145

1 1 1 1 1 1 1 1 1 1 1 1 CD146

2.2U_6.3V_M_X5R_0201

2.2U_6.3V_M_X5R_0201
CD1733

CD1734

CD1735

CD1736

CD1737

CD1738

CD1739

CD1740

CD1757

CD1758

1 1 1 1
CD1743 CD1744

CD1799

CD1800
RF@ RF@
2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2
EMC_NS@

EMC_NS@

MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@

MD@ MD@
MD@ MD@

add at 6/23
+2.5V_DDR +2.5V_DDR +2.5V_DDR +2.5V_DDR

12P_50V_J_NPO_0201
2.2P_25V_C_COG_0201
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

CD1760

10U_6.3V_M_X5R_0402

CD1761

10U_6.3V_M_X5R_0402

CD1762

10U_6.3V_M_X5R_0402

CD1763

10U_6.3V_M_X5R_0402

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

1 1
1 1 1 1 1 1 1 1
CD1785

CD1786

CD1787

CD1788

CD1781

CD1782

CD1783

CD1784

1 1 1 1 CD1768 1 CD1769 1 CD1770 1 CD1771 1 CD1797 CD1798

EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@ RF@ RF@
2 2
2 2 2 2 2 2 2 2 @
2 2 2 2 2 2 2 2
A A

MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@

MD@ MD@ MD@

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/01/19 Deciphered Date 2022/01/19 LPDDR5 Decoupling

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 94 of 108
5 4 3 2 1
 5 4 3 2 1

VREF
+5V_DRIVER
@ @
PU1001

1/16W_11K_1%_0402
1/16W_221K_1%_0402
1/16W_1.3K_1%_0402

1/16W_15.8K_1%_0402
PR1009

PR1010

PR1011

PR1012

PR1013

PR1001

PR1002
0_0402_5%

0_0402_5%
1/10W_2.2_1%_0603 PR1093 V9B+
1 2 AU1_VCC 50 1/10W_2.2_1%_0603
VCC AU1_VIN
1 52 1 2

TSEN_CORE_H 1

2
VIN
PC1004 1

SET1_H

SET2_H

SET3_H

SET4_H

TSEN_GT_H
4.7U_6.3V_K_X5R_0603
VREF 2 PC1005
0.47U_25V_K_X5R_0402_YAGEO
20 2
VREF06

1
PR1084 @

1
PR1014 0_0402_5%

PR1005

PR1015
+5V_DRIVER

1/16W_200_1%_0402

1/16W_562_1%_0402
1/16W_78.7K_1%_0402

1/16W_19.1K_1%_0402

1/16W_38.3K_1%_0402

1/16W_17.4K_1%_0402
D 1/16W_3.9_1%_0402 51 AU1_EN 1 2 D

PR1003

PR1004

PR1071

PR1072
VRON EC_VR_ON

2
1

1
PC1001
0.47U_25V_K_X5R_0402_YAGEO PR1016 PR1067
PH1001, place near at Core phase1 DRMOS 2 ANS_EN 1/20W_100K_5%_0201 1/20W_100K_5%_0201
PH1002, place near at GT phase1 DRMOS AU1_SET1
VCC: Enable; GND: Disable
24

2
AU1_SET2 SET1 AU1_ANS_EN
25 49
AU1_SET3 26 SET2 ANS_EN

1
AU1_SET4 SET3
27
SET4
PR1006 @ PQ1001 PR1068 @
PINSET_TSEN_CORE PH1001 1 2 100K_0402_1%_NCP15WF104F03RC 1/16W_100K_1%_0402 1/16W_0_5%_0402
LSI1012XT1G_SC-89-3
2 EC_ANS_R 2 1
DRVEN

1
PR1017 1 2 1/16W_110K_1%_0402 AU1_TSEN_CORE 22 PS0/1/2/3: H; PS4: L

3
TSEN_MAIN
PQ1002
PINSET_TSEN_GT PH1002 1 2 100K_0402_1%_NCP15WF104F03RC 41 LSI1012XT1G_SC-89-3

1
DRVEN VCORE_DRVEN 2

1/16W_25.5K_1%_0402

1/16W_13.3K_1%_0402

1/16W_3.83K_1%_0402

1/16W_8.06K_1%_0402
42 EC_ANS

PR1090

PR1018

PR1079

PR1019
AU1_TSEN_GT DRVEN_F
PR1007 1 2 1/16W_110K_1%_0402 23

3
1

1
TSEN_AUX1

1/16W_16.2K_1%_0402

1/16W_1.87K_1%_0402
1 2 AU1_PSYS 29

PR1020

PR1008
2

2
PSYS PSYS
PR1087 @

1/16W_0_1%_0402

1/16W_10K_1%_0402
1
1/16W_0_5%_0402 1 @ 45

1
0.01U_25V_K_X7R_0402
PWM1_MAIN VCORE_PWM1
1.6V=FFh

PR1085

PC1006
EC_ANS=H, Enable ANS

PR1078
Pull PSYS pin to
1SET1_L

1SET2_L

1SET3_L

1SET4_L
46
VCC, disable PSYS EC_ANS=L, Disable ANS

2TSEN_CORE_L
2 PWM2_MAIN VCORE_PWM2

TSEN_GT_L

2
@ 48
1/16W_100_1%_0402

1/16W_604_1%_0402

1/16W_332_1%_0402
PWM3_MAIN

1/16W_49.9_1%_0402
PR1021

PR1022

PR1023

PR1024
@ 47
+5V_DRIVER

1
PWM4_MAIN
2

1/16W_30.1K_1%_0402
PR1025

PR1026
0_0402_5%
1

2
44
PWM1_AUXI GT_PWM1

43
PWM2_AUXI

C C
PR1027 1 2 0_0201_5% @ AU1_VCLK 15 PR1029 PR1030
SVID_CLK VCLK
1/20W_845_1%_0201 1/20W_845_1%_0201
PR1028 1 2 0_0201_5% @ AU1_VDIO 16
SVID_DATA VDIO
8 AU1_ISEN1P_CORE 1 2 ISEN1PC_R 1 2
PR1031 1 2 0_0201_5% @ AU1_ALERT 17 ISEN1P_MAIN ISEN1PC
SVID_ALERT_N

1
ALERT#
+3VS 1
1/16W_75_1%_0402
1/16W_100_1%_0402
1/16W_45.3_1%_0402

@ PR1098 @
2

1
1/16W_14K_1%_0402 PC1007
H_PROCHOT_N need Pull High at EC page PR1089 0.1U_25V_K_X7R_0402
PR1082

PR1080

PR1081

2 PR1032 2
1/16W_10K_1%_0402

2
PC1002 7 AU1_ISEN1N_CORE 1 2
ISEN1N_MAIN ISEN1NC
0.1U_25V_K_X5R_0402
1

2
1 PR1033 1 2 0_0201_5% AU1_VR_HOT#
@ 18 1/16W_680_1%_0402 PC1008
VR_HOT_N VR_HOT#
1 2 PR1035 PR1036
+VCCST_CPU 1/20W_845_1%_0201 1/20W_845_1%_0201
PR1034 1 2 0_0201_5% AU1_VR_READY
@ 14 0.1U_25V_K_X7R_0402
CPU_VR_READY VR_READY AU1_ISEN2P_CORE ISEN2PC_R 1
5 1 2 2
VREF ISEN2P_MAIN ISEN2PC

1
1
PR1039 PR1088 @
PR1037 1 2 0_0201_5% @ AU1_IMON_CORE_R PR1038 1 2 AU1_IMON_CORE_R1 1 2 AU1_IMON_CORE 19 PC1009
IMON_MAIN 1/16W_14K_1%_0402
1/16W_5.9K_1%_0402 1/16W_1.74K_1%_0402 1 0.1U_25V_K_X7R_0402
PR1041 2
PC1010

2
0.01U_25V_K_X7R_0402 6 AU1_ISEN2N_CORE 1 2
PR1040 1 2 1/16W_7.68K_1%_0402 AU1_IMON_CORE_R2 PH1003 1 2 100K_0402_1%_NCP15WF104F03RC
ISEN2N_MAIN ISEN2NC
2 @ 1/16W_680_1%_0402 PC1011
PR1044 1 2
PR1042 1 2 0_0201_5% @ AU1_IMON_GT_R PR1043 1 2 AU1_IMON_GT_R1 1 2 AU1_IMON_GT 21
IMON_AUXI
1/16W_6.65K_1%_0402 1/16W_1.5K_1%_0402 1 0.1U_25V_K_X7R_0402
PC1012
PR1045

0.01U_25V_K_X7R_0402
1 2 1/16W_9.09K_1%_0402 AU1_IMON_GT_R2 PH1004 1 2 100K_0402_1%_NCP15WF104F03RC
2 @
1
AU1_IMON_AUX_R ISEN3P_MAIN
PR1046 2 1 0_0402_5% @ PR1047 1 2 1/16W_19.6K_1%_0402 1 28
IMON_AUX
PC1013
0.01U_25V_K_X7R_0402
PH1003, place near at Core phase1 IND
RX1
RX1 2 @
PH1004, place near at GT phase1 IND 2
PC1015 @ 2
ISEN3N_MAIN
0.01U_25V_K_X7R_0402
PR1051 1 2 0_0201_5% @ 1 AU1_VSEN_CORE 11
VCORE_VCC_SENSE VSEN_MAIN

PC1017 1 2 330P_50V_K_X7R_0402 PC1018 1 2 100P_50V_J_NPO_0402 AU1_COMP_CORE 10

COMP_MAIN
PR1054
PR1053
B PR1077 1 2 1/16W_11K_1%_0402 1 2 AU1_COMP_CORE_R1 1 2 B
1/16W_28.7K_1%_0402 1/16W_6.2K_1%_0402
R2 AU1_FB_CORE 9 4
R1 U28@ FB_MAIN ISEN4P_MAIN
1
PC1019 @
0.01U_25V_K_X7R_0402

PR1056 1 2 0_0201_5% @ 2 AU1_RGND_CORE 12 PR1095

VCORE_VSS_SENSE RGND_MAIN
1/16W_10K_1%_0402
3 AU1_ISEN4N_CORE 1 2 Pull ISENxN to VCC, disable this phase
ISEN4N_MAIN +5V_DRIVER
2
PC1020 @
0.01U_25V_K_X7R_0402 PR1058 PR1059
PR1057 1 2 0_0201_5% @ 1 AU1_VSEN_GT 31 1/20W_845_1%_0201 1/20W_845_1%_0201
VCCGT_VCC_SENSE VSEN_AUXI
36 AU1_ISEN1P_GT 1 2 ISEN1PG_R 1 2
ISEN1P_AUXI ISEN1PG

1
PC1021 1 2 270P_50V_K_X7R_0402 PC1022 1 2 82P_50V_G_COG_0402 AU1_COMP_GT 32
COMP_AUXI 1
PR1074 @
PR1063
1/16W_14K_1%_0402 PC1023
PR1061 1 2 1 2 AU1_COMP_GT_R1 1 2 0.1U_25V_K_X7R_0402
PR1065 2
1/16W_11.5K_1%_0402 1/16W_806_1%_0402

2
1 PR1062 1/16W_39.2K_1%_0402 AU1_FB_GT 33 37 AU1_ISEN1N_GT 1 2
PC1024 @
FB_AUXI ISEN1N_AUXI ISEN1NG
0.01U_25V_K_X7R_0402 1/16W_680_1%_0402 PC1025
1 2
PR1066 1 2 0_0201_5% @ 2 AU1_RGND_GT 30
VCCGT_VSS_SENSE RGND_AUXI
0.1U_25V_K_X7R_0402

RX1 RX2 35
PR1083 PR1092 ISEN2P_AUXI
1 2 AU1_ISENP_AUX_R 1 2
VCCIN_AUX_ISEN_P
1

1/16W_549_1%_0402 1/16W_560_1%_0402 PR1097

RS 1/16W_931_1%_0402
34 AU1_ISEN2N_GT 1 2
ISEN2N_AUXI +5V_DRIVER
2

AU1_ISENP_AUX_R1 AU1_ISENP_AUX 38 PR1091

ISENP_AUX
1/16W_10K_1%_0402
RP
1

PH1005
1 CX1 1
PC1030
CX2
PR1073 0.033U_16V_K_X7R_0402
PC1003
0.1U_25V_K_X5R_0402

10K_0402_1%_TSM0A103F34D1RZ 1/16W_4.12K_1%_0402
2 2
2

A 2 1AU1_ISENN_AUX39 A
VCCIN_AUX_ISEN_N ISENN_AUX
1
@ PR1075 @
0.01U_25V_K_X7R_0402

PH1005, place near at VCCIN_AUX phase IND 0_0402_5% 40 DBLR_PS

Cbypass DSBL_PS
PC1028

2 PS0:L, PS1: Floating; PS2/3: H; PS4: L

13 VREF_SPS
VRE_SPS VREF_SPS
53 2 Fixed 1.3V, offset the SPS reference voltage
GND
PC1029
0.22U_25V_K_X7R_0402
1
RT3624BEGQW_WQFN52_6X6

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 CPU CONTROLLER

PR7808 1 2 0_0201_5% @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 95 of 108

5 4 3 2 1
 5 4 3 2 1

+5VS PR1209 @
1/10W_0_5%_0603
2 1

VCORE_VIN PL1203 V9B+

D
+5VALW +5V_DRIVER BLM18KG300TN1D_2P
1 2 D

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X7R_0402
2 1

22U_B2_25VM_R100M

22U_B2_25VM_R100M
1 1 1 1 1 U28@ PL1204
PR1206 @ BLM18KG300TN1D_2P

PC1212

PC1214

PC1213

PC1222
0_0603_SP + + 1 2

PC1223
+5V_DRIVER 2 2 2 PL1205 VCCCORE:U28
2 2 BLM18KG300TN1D_2P
1 2 Vout=VID

1
PR1200
1/10W_2.2_5%_0603
JUMP_43X118
@
IPL2=47A,2Phase
PJ1200
2 1 ICCMAX=80A,

2
2 1
PR1210 LL=2.3mohm
1/10W_2.2_1%_0603
Fsw_max=500KHz

5
VCORE_BST1_30 2 1 VCORE_BST1_R
1
PQ1010
PC1206
1
AON6380_DFN8-5 OCP:104A
1U_25V_K_X5R_0402 PC1209
2 PU1051
4 2
0.22U_25V_K_X7R_0402
4
OVP:VID+350mV
VCORE_VCC1 8
VCC
BOOT
3 VCORE_UG1_30 +VCCCORE Ripple:PS0/PS1:+/-15mV,PS2/PS3:+/-30mV
UGATE PL1200
5
VCORE_PWM1 PWM 2 VCORE_PH1 1 4

3
2
1
PHASE
1
VCORE_DRVEN EN 7 VCORE_LG1_30 @ 2 3

2
LGATE
6
GND1
9 PR1204

5
GND2 0.15UH_PCME063TR15MS0R9_37A_20%
1/10W_2.2_5%_0603
RT9610CGQW_WDFN8_2X2 PQ1012 PQ1011
AON6324_DFN8-5 AON6324_DFN8-5

1
VCORE_SN1
@
2
4 4
PC1201
1000P_50V_K_X7R_0402
1
@

3
2
1

3
2
1
@ @

ISEN1NC

ISEN1PC
C C

VCORE_VIN

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X7R_0402

22U_B2_25VM_R100M
1 1 1 1

PC1215

PC1217

PC1216

PC1221
+

+5V_DRIVER 2 2 2
2
1

PR1201
1/10W_2.2_5%_0603
2

PR1207
1/10W_2.2_1%_0603

5
VCORE_BST2_30 2 1 VCORE_BST2_R
1
1 PQ1013
PC1207 AON6380_DFN8-5
1U_25V_K_X5R_0402 PC1210
2 PU7802 0.22U_25V_K_X7R_0402
4 2 4
VCORE_VCC2 BOOT
8
VCC
UGATE
3 VCORE_UG2_30
PL1201
+VCCCORE
5
VCORE_PWM2 PWM 2 3 VCORE_PH2 1 4
2
1
PHASE
1
VCORE_DRVEN EN VCORE_LG2_30 @
7 2 3

2
6 LGATE
GND1
9 PR1203
5

GND2 0.15UH_PCME063TR15MS0R9_37A_20%
1/10W_2.2_5%_0603
RT9610CGQW_WDFN8_2X2 PQ1014 PQ1015
AON6324_DFN8-5 AON6324_DFN8-5

1
VCORE_SN2
@
2
4 4
PC1200
B B
1000P_50V_K_X7R_0402
1
@
3
2
1

3
2
1

@ @

ISEN2NC

ISEN2PC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 VCCCORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 96 of 108
5 4 3 2 1
 5 4 3 2 1

D D

PL7004 @
BLM18KG300TN1D_2P
1 2

JUMP_43X118
VCCGT_VIN PJ7008
@ VCORE_VIN
2 1

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

22U_B2_25VM_R100M
0.1U_25V_K_X7R_0402
2 1
1

PC1414
1 1 1
+

PC1407

PC1406

PC1405
2 2 2 2
+5V_DRIVER

1 PR1400
1/10W_2.2_5%_0603
2

PR1404
1/10W_2.2_1%_0603

5
1 VCCGT_BST1_30 2 1 VCCGT_BST1_R
1 PQ1020
PC1403 AON6380_DFN8-5
1U_25V_K_X5R_0402 PC1404
2 PU7803 0.22U_25V_K_X7R_0402
4 2 4
VCCGT_VCC1 8 BOOT
VCC
3 VCCGT_UG1_30
PL1400
+VCCGT
5 UGATE
GT_PWM1 PWM 2 VCCGT_PH1 1 4

3
2
1
PHASE
C 1 C
VCORE_DRVEN EN 7 VCCGT_LG1_30 @ 2 3

2
6 LGATE
GND1 9 PR1403

5
GND2 0.15UH_PCME063TR15MS0R9_37A_20%
1/10W_2.2_5%_0603
RT9610CGQW_WDFN8_2X2 PQ1021 PQ1022
AON6324_DFN8-5 AON6324_DFN8-5

1
VCCGT_SN1
@
2
4 4
PC1401 VCCGT:
1000P_50V_K_X7R_0402
@
1
Vout:VID

3
2
1

3
2
1
@ @ IPL2=23A,1Phase
ICCMAX=40A,
ISEN1NG LL=3.2mohm
ISEN1PG
Fsw_max=400KHz
OCP:52A
OVP:VID+350mV
Ripple:Reference to EDS

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 GT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 97 of 108
5 4 3 2 1
 A
B
C
D

2
1
22U_6.3V_M_X5R_0603
C7240
+VCCCORE

2
1
2
1
2
1

22U_6.3V_M_X5R_0603
C7241 22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603
C7202 C7248

5
5

2
1
2
1
2
1

22U_6.3V_M_X5R_0603
C7242 22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603
C7203 C7249

2
1
2
1
2
1

22U_6.3V_M_X5R_0603
C7243 22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603
C7204 C7250

2
1
2
1
2
1

22U_6.3V_M_X5R_0603

E14: 22uF*24pcs+330uF*3
C7244 22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603
C7205 C7251

2
1
2
1
2
1

22U_6.3V_M_X5R_0603
C7245 22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603
C7206 C7252

2
1
2
1
2
1

22U_6.3V_M_X5R_0603
C7246 22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603
C7207 C7253
2
1
2
1
2
1

22U_6.3V_M_X5R_0603
C7247 22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603
C7208 C7254
2
1
2
1

2
1
+

22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603

Follow PDG v0.81: 47uF*8pcs+22uF*8pcs+330uF*3

PC1144 C7209 C7255
330U_B2_2.5VM_R9M
2
1

2
1
+

PC1145
CC187

330U_B2_2.5VM_R9M

4
4

RF_NS@

2
1
+

PC1146
330U_B2_2.5VM_R9M
33P_50V_J_NPO_0402
2
1

2
1
CC188

10U_6.3V_M_X5R_0402
RF_NS@

C1572
2
1

10U_6.3V_M_X5R_0402
C1573
33P_50V_J_NPO_0402

2
1
For simulation

10U_6.3V_M_X5R_0402
Near CPU

C1574

3
3

2
1
10U_6.3V_M_X5R_0402
CC1546
+VCCGT

2
1
+

2
1
2
1

PC1147
10U_6.3V_M_X5R_0402 22U_6.3V_M_X5R_0603 330U_B2_2.5VM_R9M
CC1547
C7218

@
+1.2V

2
1
2
1
2
1
+

Issued Date
2
1

10U_6.3V_M_X5R_0402 22U_6.3V_M_X5R_0603 PC1148

CC1548
C7219 330U_B2_2.5VM_R9M
10U_6.3V_M_X5R_0402
CC1563

Security Classification
@
2
1
2
1
2
1
2
1
2
1

10U_6.3V_M_X5R_0402 22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603

CC1549
C7220 C7256
10U_6.3V_M_X5R_0402 C7234
CC1564
1U_10V_K_X5R_0402
2
1
2
1
2
1
2
1
2
1

22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603

E14: 22uF*22pcs+330uF*2
4.7U_6.3V_K_X5R_0402
CC1550 C7221 C7257
10U_6.3V_M_X5R_0402 C7235
CC1565
1U_10V_K_X5R_0402
2
1
2
1
2
1
@

2018/08/02
2
1
2
1

4.7U_6.3V_K_X5R_0402 22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603

CC1551 C7222 C7258
10U_6.3V_M_X5R_0402 C7236
CC1566
1U_10V_K_X5R_0402
2
1
2
1
2
1
@
2
1
2
1

4.7U_6.3V_K_X5R_0402 22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603

For simulation

CC1552 C7223 C7259

10U_6.3V_M_X5R_0402 C7237
CC1567
1U_10V_K_X5R_0402
2
1
2
1
2
1
2
1

4.7U_6.3V_K_X5R_0402 22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603

CC1553 C7224 C7260 C7238
1U_10V_K_X5R_0402

2
2

2
1
2
1
2
1

22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603
Deciphered Date
C7225 C7261 C7239
Follow PDG v0.81: 47uF*7pcs+22uF*8pcs+330uF*2

1U_10V_K_X5R_0402
2
1
2
1

22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603
LC Future Center Secret Data
2
1

C7264 C7262
2
1
2
1
CC1560

RF_NS@

22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603
C7265 C7263
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2018/08/02

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2
1
2
1
2
1

22U_6.3V_M_X5R_0603
C7266
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
CC1544
CC1561

Near CPU

RF_NS@
RF_NS@

2
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Follow PDG v0.81: 10uF*3pcs+1uF*6pcs+placeholder*2PCS

22U_6.3V_M_X5R_0603
C7267
C
Size

Date:
2
1

Title
33P_50V_J_NPO_0402
33P_50V_J_NPO_0402 33P_50V_J_NPO_0402

2
1

22U_6.3V_M_X5R_0603
C7268
CC1545

RF_NS@

2
1

22U_6.3V_M_X5R_0603
C7269
Document Number
CPU Decoupling
33P_50V_J_NPO_0402
www.teknisi-indonesia.com

1
1

Near CPU

Wednesday, March 02, 2022

Sheet
ThinkPad E14 GEN4
98
of
108
1
Rev
A
B
C
D
 A B C D

V9B+

2
PR80
1/10W_2.2_5%_0603
PCH_DPWROK
PR235 @ 1 2 1/16W_0_1%_0402 +5VALW

1
PR81 2 1 P_LV5116A_VCC_30 P_LV5116A_VSYS_10
PR75 @ 1 2 0_0402_5% P_LV5116A_EN
ALW_PWRGD 2
1/10W_2.2_5%_0603 1
1 2 0_0402_5%
+5VALW PC91
PR76 @ 1U_10V_K_X5R_0402 PC92
DDR_VTT_PG_CTRL 1 +5VALW
0.1U_25V_K_X7R_0402 @
1 2 1

PR77 @ 1 2 1/16W_0_1%_0402 VTT_EN PR82 2 1 1 2

SYSON 1 2 1A

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
1/10W_2.2_5%_0603 2
PJ83
PR78 @ 1 2 0_0402_5% +1.8VALW_EN PC93 JUMP_43X39
EC_ON_1.8V 1U_10V_K_X5R_0402
1 PU4
PR79 @ 1 2 0_0402_5% VDDQ_VPP_EN
1 1
EC_VPP_PWREN

PC94

PC96
6
36 VSYS
@
VCC
P_LV5116A_PVCC_30 4 27 P_+1.8VALW_VIN_S 2 2 +1.8VALW
PVCC V1P8A_IN
P_VDDQ_UG_30 1
@ 160mil
PC95 4

2
VDDQ_HG P_+1.8VALW_LX_S +1.8VALW_P

PR116

PC87

PC88

PC89

PC90
2 2 2 2 25 1 2 1 2
1 2 P_VDDQ_BST_R_30 2 1 P_VDDQ_BST_30 40 V1P8A_PH1 1 2

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
VDDQ_BOOT

1
PR84 1/10W_0_5%_0603 26 PL7 PJ5
V1P8A_PH2 2 1

2200P_25V_K_X7R_0402
1U_6.3V_M_X5R_0201
PR85 1UH_PCMB053T-1R0MS_7A_20% JUMP_43X79

0.1U_25V_K_X5R_0402
0.1U_10V_K_X5R_0201

0.1U_10V_K_X5R_0201
0.1U_25V_K_X5R_0402

1
1 1 1 1 P_VDDQ_LX_30 2 29 +1.8VALW_P @ +3VALW

0.1U_10V_K_X5R_0201
1/20W_100K_5%_0201
1/10W_4.7_5%_0603

1
@ @ @ VDDQ_PH V1P8A_SNS

PC251
PC97
P_VDDQ_LX_SENS_10 P_VDDQ_VPP_IN 1A 1 1 1 1

PC252
39 9 10U_6.3V_M_X5R_0402 1 2 EMC_NS@

2
VDDQ_SWSNS VPP_IN 1 2
1
P_VDDQ_LG_30 P_VDDQ_VPP +VDDQ_OUT

PC98

PC101

PC102

PC99
3 8 PJ88
VDDQ_LG VPP 2 2 2 2
JUMP_43X39 PC100
13 P_VTT_IN_30 1A 1 2 1200P_50V_K_X7R_0402
P_VDDQ_SENS_10 12 VTT_IN 1 2 2
2 1 VDDQ_SNS 14 P_VDDQ_VTT PJ87 EMC_NS@
VTT
0.1U_25V_K_X7R_0402 PC103 @ 2 1 JUMP_43X39 EMC_NS@ EMC_NS@ +0.6VS
15

22U_6.3V_M_X5R_0603
@
1A 40mil
P_VCCIN_AUX_EN_10 23 VTT_SNS
PC104
AUX_DRVEN P_VDDQ_VTT 1 2
10U_6.3V_M_X5R_0402
28 P_LV5116A_DDR_ID_10 1 2
P_VCCIN_AUX_PWM_10 21 DDR_ID
1 PJ6
AUX_PWM P_LV5116A_AUX_CS_10
20 PR88 1 2 1/16W_300K_1%_0402 +3VALW_PCH JUMP_43X39
AUX_CS
P_LV5116A_VDDQ_CS_10 @

PC105
5 PR89 1 2 1/16W_240K_5%_0402
P_VCCIN_AUX_LXSENS_10 22 VDDQ_CS 2
1 2 0_0402_5% P_VCCIN_AUX_VCCSENSE_10 AUX_SWSNS
PR90 @ +VCCIN_AUX OCP=41A
VCCIN_AUX_VCCSENSE

2
P_VCCIN_AUX_VCCSENSE_10 19 24 P_LV5116A_V1P8A_CTRL_10 PR91 +2.5V_DDR
2 AUX_SNS V1P8A_CTRL
PC106 +VDDQ OCP=13A PR92
1000P_50V_K_X7R_0402 30 P_LV5116A_AUX_SET_10 1/16W_100K_5%_0402 1/16W_100K_5%_0402
AUX_SET P_VDDQ_VPP 1
1 2
2 1A 40mil
1 2 0_0402_5% 1 P_VCCIN_AUX_VSSSENSE_10 1 2 0_0402_5% P_LV5116A_PROCHOT# 7

22U_6.3V_M_X5R_0603
PR93 @ H_PROCHOT_N PR94 @

1
VCCIN_AUX_VSSSENSE PROCHOT# 16 PJ7
VCCIN_AUX_PGD 11 AUX_VID0 VCCIN_AUX_VID0 JUMP_43X39
PG_ARAIL 17
PR95 EMC_NS@ EMC_NS@
1 2 VDDQ_PGOOD 10 AUX_VID1 VCCIN_AUX_VID1 @

10U_6.3V_M_X5R_0402
+3VALW

2
PG_DDR P_LV5116A_CLK_3

PC107
33 1 2 0_0402_5%

2200P_25V_K_X7R_0402
1/16W_100K_5%_0402 PR96 @

0.1U_25V_K_X5R_0402
VDDQ_PGOOD SCL EC_SMB_CLK4 1 1

1
PC108
PR98 PR99
P_LV5116A_DAT_3

PC253

PC254
34 PR97 @ 1 2 0_0402_5% 1/16W_10K_5%_0402
P_LV5116A_EN 38 SDA EC_SMB_DATA4
1/16W_0_1%_0402 1/16W_10K_5%_0402

2
PR100 PMIC_EN 2 2
@

1
+3VALW 1 2 P_LV5116A_DIGITAL_CTL_10 37 @
DIGITAL_CTRL 18 P_VCCIN_AUX_VSSSENSE_10 @ @
+1.8VALW_EN 35 AUX_RGND
+5VALW +5VALW +5VALW
1 PR101 @ 1 2 0_0402_5% SLP_SUS#
PR115 +5VALW VDDQ_VPP_EN 32 41

2
SLP_S4# GND
1/20W_10K_5%_0201 @
VTT_EN 31 @ PR102 PR103 PR104
DDR_VTT_CTRL
0_0402_5% 1/16W_10K_5%_0402
2

2 1/16W_100K_5%_0402 2

VCCIN_AUX_PGD

1
LV5116BGQW_WQFN40_5X5 P_LV5116A_DDR_ID_10
P_LV5116A_V1P8A_CTRL_10 @
P_LV5116A_AUX_SET_10
DIGITAL_CTRL AUX_VID1 AUX_VID0 Vout_AUX
Control Mode

1
AUX_SET VCCIN_AUX Internal RAMP PR105 PR106 PR107 0 0 0V
High HW Control 0_0402_5% 1/16W_0_1%_0402
1/16W_0_1%_0402
High RAMP1 0 1 1.1V

2
Low SW Control @ @ @

Low RAMP2 1 0 1.65V

Floating RAMP3 1 1 1.8V

DIGITAL_CTRL V1P8A_CTRL V1P8A Sequence

High Low V1P8A follow PMIC_EN

PL14
High High V1P8A follow SLP_SUS# DDR_ID Type VPP VDDQ VTT/VDDQTX
BLM18KG300TN1D_2P
1 2
Low Low V1P8A follow PMIC_EN Low DDR4 2.5V 1.2V VDDQ/2(VTT)
P_VCCIN_AUX_VIN_S EMC@ V9B+
EMC@ EMC_NS@ PL15
BLM18KG300TN1D_2P
Low High V1P8A follow I2C Floating LPDDR4 1.8V 1.1V --
1 2 3A V9B+
EMC@ High LPDDR4X 1.8V 1.1V 0.6V(VDDQTX)
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

P_VCCIN_AUX_BST_R_30 PC110 PC255 1

PC226
22U_B2_25VM_R100M

22U_B2_25VM_R100M
@
+5VALW 1 1
1.5A
1

PC111

PC112

+
2200P_25V_K_X7R_0402

PR109 1/10W_0_5%_0603 EMC@ EMC_NS@

0.1U_25V_K_X5R_0402
5

P_VCCIN_AUX_BST_30 1 2 1 2 P_VDDQ_VIN_S 1 2
1 2

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
PQ11
2

2 2 2

2200P_25V_K_X7R_0402
PC109 PJ111

0.1U_25V_K_X5R_0402
AON6380_DFN8-5 1
2

0.22U_25V_K_X5R_0402 PQ13 1 1 JUMP_43X79

1
PC117

PC256

PC118

PC119

PC280
PR110 AONR32340C_DFN8-5 +
1/10W_2.2_5%_0603 4
PU5 @ @

2
4 P_VDDQ_UG_30 4 2 2 2
+VCCIN_AUX
1

P_VCCIN_AUX_VCC_30 8 BOOT
PL8 G @
VCC 3 P_VCCIN_AUX_UG_30 0.22UH_PCMB063T-R22MS_23A_20%

S3
S2
S1
3
2
1

P_VCCIN_AUX_PWM_10 UGATE
5
PWM 2 P_VCCIN_AUX_LX_S @ 1 2 700mil +VDDQ_OUT +1.2V
1
8A

3
2
1
P_VCCIN_AUX_EN_10 1 PHASE
330U_D2_2.5VY_R9M
EN 7 P_VCCIN_AUX_LG_30 PL9
PC114 1 PJ9
2

6 LGATE P_VDDQ_LX_30 1 2 1 2
1/10W_0_5%_0603

1U_10V_K_X5R_0402 GND1 1 2
400mil
2

2 +
PC115

EMC_NS@

EMC_NS@
9 PJ7004 PJ7005 PQ14
2

GND2
PR112

2200P_25V_K_X7R_0402
AON6324_DFN8-5 PJ8 0.47UH_PCMB063T-R47MS_18A_20% JUMP_43X118

0.1U_25V_K_X5R_0402
@ @
1

AON7380_DFN8-5
5

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
JUMPER @

330U_B2_2.5VM_R9M
RT9610CGQW_WDFN8_2X2 2
PQ12 @ 1
1

2
3 PJ10 1 1 1 1 1 1 3
1

2
+

PC281

PC121

PC122

PC123

PC124

PC125

PC126

PC257

PC258
PR185 JUMPER PJ7007
1 place close to VCCIN_ALX LMOS drain 1/10W_4.7_5%_0603 @ JUMPER

1
4 @ P_VDDQ_LG_30 4 @

1
P_VCCIN_AUX_LXSENS_10 2 2 2 2 2 2 2
1000P_50V_K_X7R_0402

EMC_NS@

1
PC120

Rdson=2.8mohm@Vth=4.5V 2 Rdson=10.5mohm@Vth=4.5V
place close to VDDQ LMOS drain
1
@
3
2
1

3
2
1
PC127 @ @
@
VCCIN_AUX_ISEN_N 1200P_50V_K_X7R_0402
2
EMC_NS@
P_VDDQ_LX_SENS_10 P_VDDQ_SENS_10
VCCIN_AUX_ISEN_P

Vout=VID
AC+DC Ripple=(-10%~+5%)*VOUT
TDC=14A Iccmax=32A
CURRENT LIMIT=45A
Max Overshoot:2.13v/500us
OVP=(1.2~1.3)*Vref
UVP=(0.45~0.55)*Vref
Fsw=600Khz

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 PWR PMIC-LV5116
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E14/E15 NM-D011
Date: Wednesday, March 02, 2022 Sheet 99 of 108
A B C D
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 1.8VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 100 of 108
5 4 3 2 1
 5 4 3 2 1

D D

+VCCIN_AUX

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402
1 1 1 1 1 1 1 1 1 1 1 1
CC189 CC190

CC98

CC102

CC103

CC104

CC105

CC106

CC1568

CC1569

CC1570

CC1571
33P_50V_J_NPO_040233P_50V_J_NPO_0402
RF_NS@ RF_NS@
2 2 2 2 2 2 2 2 2 2 2 2

Near CPU

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
1 1 1 1 1 1 1 1 1 1 1 1 1 1

C7270

C7271

C7272

C7273

C7274

C7275

C7276

C7277

C7278

C7279

C7280

C7281

C7282

C7283
C C
2 2 2 2 2 2 2 2 2 2 2 2 2 2

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
330U_B2_2.5VM_R9M

1
1 1 1 1
+
PC1149

C7284

C7285

C7286

C7287
Follow PDG v0.81: 47uF*9pcs+10uF*10pcs+330uF*1
2 2 2 2 2 E14: 22uF*18pcs+330uF*1+10uF*10pcs

For simulation
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1 1 1 1 1 1
C7288

C7289

C7290

C7291

C7292

C7293

2 2 2 2 2 2

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PCH Decoupling
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 101 of 108
5 4 3 2 1
 5 4 3 2 1

PWM-VID Specification
RT8816 PSI UP1666 PSI Phase Configuration
GN18S GN20S
1.6V~5.5V 1.6~5.5V 2Phase CCM
Vmin(V) 0.3 0.3
1.08~1.35V 1~1.4V 2Phase DEM
Vmax(V) 1.3 1.3
0.7~0.88V 0.4V~0.8V 1Phase CCM
Vboot(V) 0.8 0.75
0~0.4V 0~0.2V 1Phase DEM
Vstep(mV) 6.25 6.25
N(level) 160 160
Fpwm(KHz) 675 675 PR7028
GPU_B+ V9B+
Tdmin(nS) 9.26 9.26 GPU_ALL_B+ 1W_0.005_1%_1206_100PPM/C PL7002 OPT@
BBUP00201209121Y00
1 2
3A 1 2
T(uS) <100 <100

OPT@

OPT@
PC7000 OPT_EMC@

OPT_NS@

10U_25V_K_X5R_0603

10U_25V_K_X5R_0603
1U_25V_K_X5R_0402

22U_B2_25VM_R100M

22U_B2_25VM_R100M
0.1U_25V_K_X5R_0201

OPT@
PC7041 OPT_NS@
OPT@ PL7003 OPT@
BBUP00201209121Y00
D
+5VALW D

2
1 1 1 1 1 1 PJ7002 PJ7003 1 2
JUMPER JUMPER
+ + @ @ 1 1

1U_25V_K_X5R_0402

1U_25V_K_X5R_0402
1

1
PC7001

PC7002

PC7003

PC7040
2 2 2 2

PC7047

PC7048
1
2 2
OPT@ PR7000 2 2
1/4W_2_5%_0603 PU7000 OPT_RT8816@

2
NVVDD_PVCC 18
PVCC 2 NVVDD_HG1

OPT_NS@

OPT_NS@
UGATE1
1
OPT@ PR7003 OPT@ PC7005 OPT@ PQ7000 GPU_TGP_R- GPU_TGP_R+
+1.8VGS PC7004 1/10W_2.2_5%_0603 0.22U_25V_K_X7R_0603 OPT@

10
3
4
1U_6.3V_K_X5R_0402 1 NVVDD_BS1 1 2 1 2
2 BOOT1 1
1

21
PR7004 GND
PL7000
NVVDD
1/16W_5.1K_1%_0402 5
20 NVVDD_PH_S_1 2 6 NVVDD_PH1 1 2
PHASE1

OPT@
PR7001 @ OPT@ 7

PC7010

PC7011

PC7012

PC7013

PC7006

PC7044

PC7045
22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
330U_B2_2.5VM_R9M
2

1
0_0201_5% 8 0.24UH_PCME063T-R24MS1R145_35A_20% 1
1 2 NVVDD_PSI_R 4 PR7005 EMC_NS@
PSI_VGA PSI OPT@ 1 1 1 1 1 1 1
PR7002 OPT@ PR7006 OPT_NS@ 1/8W_1_5%_0805 +
1/20W_1K_5%_0201 1/16W_5.1K_1%_0402
+3VS 1 2 1 2 AOE6930_DFN8-10

PC7007
9

2
19 NVVDD_LG1 NVVDD_PH1_SN 2 2 2 2 2 2 2 2
13 LGATE1
PGOOD 1
NVVDD_PWROK PR7007 OPT@
1/16W_49.9K_1%_0402 PC7016 EMC_NS@
NVVDD_EN_R

OPT@

OPT@

OPT@

OPT@
1 2 3 2200P_50V_K_X7R_0402

OPT_NS@

OPT_NS@

OPT_NS@
NVVDD_EN EN 2
1
PR7029 1 2 1 2 PD7000 PC7014 OPT@
1/16W_2.2K_5%_0402 0.1U_10V_K_X7R_0402 GPU_ALL_B+
1 2 2
OPT@
RB521CM-30T2R_VMN2M-2
OPT@

10U_25V_K_X5R_0603

10U_25V_K_X5R_0603
0.1U_25V_K_X5R_0201
NVVDD_VID_R NVVDD_HG2

OPT_EMC@
1 2 5 14

OPT_NS@ PC7008
1 1 1 1

1U_25V_K_X5R_0402
NVVDD_PWM_VID VID UGATE2

PC7020

OPT@ PC7018

OPT@ PC7031
1
PR7008 @ PR7009 OPT@ PC7017 OPT@
0_0201_5% PC7015 OPT_NS@ 1/10W_2.2_5%_0603 0.22U_25V_K_X7R_0603 PQ7003
15 NVVDD_BS2 1 2 1 2 OPT@ 2 2 2 2

10
0.1U_10V_K_X7R_0402 BOOT2

3
4
2
C C
1

PC7019 OPT@
PL7001
NVVDD
0.1U_25V_K_X5R_0402 5
16 NVVDD_PH_S_2 2 6 NVVDD_PH2 1 2
2 1 NVVDD_VREF 8 PHASE2 7

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M
VREF

OPT@

OPT@

OPT@
PC7046 OPT_NS@
8 0.24UH_PCME063T-R24MS1R145_35A_20% 1 1
1

PC7036

PC7037

PC7038

PC7039

PC7035
OPT@ 1 1 2 1 1 1 1

1000P_25V_K_X7R_0402

0.1U_25V_K_X7R_0402
68P_50V_J_NPO_0201

68P_50V_J_NPO_0201
0.01U_25V_K_X7R_0402
1/16W_84.5K_1%_0402

1
+ +
OPT_UPI1666@ PR7032
1

R2 PR7011 EMC_NS@
PR7010 OPT@ AOE6930_DFN8-10 1/8W_1_5%_0805

PC7022
9
2 2 2 2 1 2 2 2 2

PC7009

PC7021
1/16W_20.5K_1%_0402
2

17 NVVDD_LG2

2
LGATE2 NVVDD_PH2_SN
2

OPT_EMC@

OPT_EMC@

OPT_EMC@

EMC_NS@

EMC_NS@
OPT_UPI1666@ PR7036
1

1
NVVDD_REFIN 7

1/16W_30K_1%_0402
REFIN
4700P_25V_K_X7R_0402_MURATA
PC7024

PC7023 EMC_NS@
PR7012 OPT_GN20S@

1
2200P_50V_K_X7R_0402 PR7014 OPT@
1/16W_13.7K_1%_0402
1

2 1/16W_100_1%_0402
1 2

2
2
OPT@

R3 R1
PR7015 OPT_GN20S@ PR7016 OPT@
R4 1/16W_2.8K_1%_0402 1/16W_6.19K_1%_0402 PR7030 @
2

1 2 1 2 NVVDD_VIDBUF 6 0_0402_5%
REFADJ 10 NVVDD_FBRTN 1 2
RGND NVVDD_VSS_SENSE
1
1

PC7025 OPT@ 1
PR7018 11 NVVDD_FB
R5 1/16W_274_1%_0402 2
4700P_25V_K_X7R_0402_MURATA VSNS
PC7026 OPT_NS@
VR Remote Sense - Tie to GPU sense points
OPT_GN20S@ 1000P_25V_K_X7R_0402
2

NVVDD_VIDBUF_RC 2
2 1NVVDD_FS 9 12 NVVDD_SS PR7031 @
PR7019 TON OCSET/SS 0_0402_5%
GPU_ALL_B+ 1/16W_475K_1%_0402 1 2
OPT_UPI1666@ PR7034

OPT_RT8816NS@ PC7029

OPT_RT8816@ PR7025
1000P_25V_K_X7R_0402

1/16W_71.5K_1%_0402
1

1
PR7021 OPT_RT8816@ OPT_RT8816@ NVVDD_VCC_SENSE
1 2
1/16W_51K_1%_0402

1/10W_2.2_5%_0603
PC7042

SS---RT
2 1 PR7022 OPT@
1/16W_100_1%_0402
1000P_50V_K_X7R_0402

2 1 1 2
PC7027

NVVDD
1U_25V_K_X5R_0402

RT8816CGQW_WQFN20_3X3
2

1
OPT_UPI1666NS@

1 2 NVVDD_FBRTN
1

PR7035 OPT_UPI1666@ PR7033

2
OPT_RT8816@

B
1/20W_0_5%_0201 1/16W_95.3K_1%_0402 B

OPT_UPI1666@ NVVDD_SS_R
2

OPT_UPI1666@ PC7043

1
1000P_50V_K_X7R_0402
2

PR7027 OPT_RT8816@
2
1/20W_0_5%_0201
1

Vboot=0.75V
Ripple=±20mV
TDC=31A
Vref=2V
FUVP:Vfb=0.2V
SUVP:Vcomp=3V
Component Value GN18S PN OVP:Vfb=2V
R5(KΩ) PR7018 309 SD00001XX0T Fsw=320KHz
R4(KΩ) PR7012 16.5K SD03416520T AOE6930:
R3(KΩ) PR7015 4.32K SD00000J28T Rdson=0.8mohm
Vgsth=1.2V/1.5V/1.9V

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/12/24 Deciphered Date 2019/12/24 GPU Controller

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ThinkPad E14 GEN4 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 02, 2022 Sheet 102 of 108
5 4 3 2 1
 5 4 3 2 1

+3VALW

2
D D
PR2100 OPT@
100K_0201_5%

1
+1.0VGS_PWROK
PJ2100

10U_0603_6.3V6-M
JUMP_43X39
1 1P0VGS_VIN

10U_0603_6.3V6-M
2 PU2100
+3VALW 2 1
1 1 PL2100
+1.0VGS

PC2101

PC2103
RT8068AZQW_WDFN10_3X3 1UH_PH041H-1R0MS_3.8A_20% @

4
@ PJ2101
10 1 1P0VGS_LX 1 2 2 1

PG
2 2 PVIN2 LX1 2 1

OPT_NS@
9 2 OPT@ OPT_EMC@
PVIN1 LX2 JUMP_43X39

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
1

OPT@

2200P_0201_25V7K
PR2103 OPT_GN20S@
1/16W_22K_1%_0402

0.1U_25V_K_X5R_0201
C OPT@ OPT_NS@ 8 3 PC2104 C
SVIN1 LX3

1
PR2102 EMC_NS@ OPT@ 1 1 2 2
4.7_0603_5% 68P_0201_25V8-J

1
1P0VGS_SN 2

OPT@ PC2107

PC2108
2
1V0_MAIN_EN PR2105 1 2 0_0402_5% @ 1VGS_EN 5 6

GND
EN FB 2 2 1 1
PC2102

NC

2
0.22U_25V_K_X5R_0402

PC2105

PC2106
680P_0201_25V7-K

2
1
1

7
11
PC2100
PR2101 OPT@ EMC_NS@
1M_0201_5%

OPT_NS@ 2

1
@

1
PR2104 OPT@
1/16W_37.4K_1%_0402
B B

2
GN20S PR2103=22K GN18S PR2103=26.1K/SD03426128T
Vout=0.953V±3% Vout=1V±3%
Vref=0.6V Vref=0.6V
OCP>4A OVP>4V
Fsw=1MHz Fsw=1MHz

A Security Classification LC Future Center Secret Data Title A

Issued Date 2019/12/24 Deciphered Date 2019/12/24 1VGS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 103 of 108
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

www.teknisi-indonesia.com

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 NA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 104 of 108
5 4 3 2 1
 5 4 3 2 1

PR7018 OPT_GN18S@ PR7012 OPT_GN18S@ PR7015 OPT_GN18S@ PR2103 OPT_GN18S@ PR1054 U15@
For U15

S RES 1/16W 309 +-1% 0402 S RES 1/16W 16.5K +-1% 0402 S RES 1/16W 4.32K +-1% 0402 S RES 1/16W 26.1K +-1% 0402 S RES 1/16W 0 +-1% 0402
SD00001XX0T SD03416520T SD00000J28T SD03426128T SD000023B0T
For GN18S

X76_OPT_US5650@ X76_OPT_NCP45492@

ZZZ15 ZZZ14

ALT. GROUP PARTS GPU US5650 JE440 ALT. GROUP PARTS GPU NCP45492 JE440
X764EA0100H X764EA0100G

D D

PR7614 OPT_US5650@ PR7610 OPT_US5650@ PR7605 OPT_US5650@ PR7613 OPT_US5650@

PR7614 OPT_NCP45492@ PR7610 OPT_NCP45492@ PR7605 OPT_NCP45492@ PR7613 OPT_NCP45492@

S RES 1/16W 332 1% 0402 S RES 1/16W 475 +-1% 0402 S RES 1/16W 499 +-1% 0402 S RES 1/16W 499 +-1% 0402
SD00002PY0T SD03447508T SD03449908T SD03449908T 1/16W_442_1%_0402 1/16W_634_1%_0402 1/16W_665_1%_0402 1/16W_665_1%_0402
SD00001WE0T SD00001KS0T SD00000JJ0T SD00000JJ0T
PR7603 OPT_US5650@ PU7601 OPT_US5650@
PR7677 OPT_US5650@ PR7603 OPT_NCP45492@ PU7601 OPT_NCP45492@ PR7618 OPT_NCP45492@

S RES 1/16W 316K +-1% 0402 S IC US5650QQKI WQFN 32P PREFILTER

SD03431638T SA00009YH00 1/16W_0_1%_0402 1/16W_237K_1%_0402 NCP45492XMNTWG_QFN32_4X4 1/16W_0_1%_0402
SD000023B0T SD03423730T SA0000AFT00 SD000023B0T
For US5650 GPU monitor For NCP45492 GPU monitor

X76_BQ25710@
X76_SC8885L@

ZZZ16
ZZZ17

ALT. GROUP PARTS CHARGER BQ25710 JE440

ALT. GROUP PARTS CHARGER SC8885L JE440
X764EA0100J
X764EU0100K

PU4000 BQ25710@ PC4025 BQ25710@ PC4026 BQ25710@ PU4000 SC8885L@ PC4009 SC8885L@

BQ25710RSNR_QFN32_4X4 0.033U_25V_K_X7R_0402 0.033U_25V_K_X7R_0402 S IC SC8885LQDER QFN 32P 33U_D2_25VM_R40M

SA00009K300 SE00000YI0T SE00000YI0T SA0000CTY00 SGA00008W00

PC4034 BQ25710@ PC4036 BQ25710@ PR4012 BQ25710@ PC4034 SC8885L@ PC4036 SC8885L@ PR4012 SC8885L@

C C

1800P_25V_K_X7R_0201 33P_25V_J_NPO_0201 1/20W_40.2K_1%_0201 1000P_25V_K_X7R_0201 10P_25V_G_NPO_0201 1/20W_100K_1%_0201

SE00000ZY0T SE174330JMT SD000013G8T SE170102KMT SE00000VV0T SD04110030T

PC4035 BQ25710@ PC4038 BQ25710@ PR4013 BQ25710@ PC4035 SC8885L@ PC4038 SC8885L@ PR4013 SC8885L@

680P_25V_K_X7R_0201_MURATA15P_25V_J_NPO_0201 1/20W_10K_1%_0201 1000P_25V_K_X7R_0201 220P_25V_K_X7R_0201 1/20W_330K_1%_0201

SE00000WYMT SE000012J0T SD0411002YT SE170102KMT SE00000RGMT SD00001ZD0T

For BQ25710 charger For SC8885L charger

X76_CPU MOS_SINOPOWER@
X76_CPU MOS_NIKO@
X76_CPU MOS_AOS@

ZZZ20
ZZZ19
ZZZ18
ALT. GROUP PARTS CPU CORE MOS JE442
ALT. GROUP PARTS CPU CORE MOS JE442
X764EU0100J
ALT. GROUP PARTS CPU CORE MOS JE442
X764EU0100H
X764EU0100G

PQ1013 AOS@ PQ1010 AOS@ PQ1020 AOS@ PQ11 AOS@ PQ1013 NIKO@ PQ1010 NIKO@ PQ1020 NIKO@ PQ11 NIKO@ PQ1013 SINOPOWER@ PQ1010 SINOPOWER@ PQ1020 SINOPOWER@ PQ11 SINOPOWER@

AON6380 AON6380 AON6380 AON6380 PK6D0BA PK6D0BA PK6D0BA PK6D0BA SM4508NHKPC SM4508NHKPC SM4508NHKPC SM4508NHKPC
SB00001FQ00 SB00001FQ00 SB00001FQ00 SB00001FQ00 SB00001BM00 SB00001BM00 SB00001BM00 SB00001BM00 SB00001HZ00 SB00001HZ00 SB00001HZ00 SB00001HZ00

B B
PQ1011 AOS@ PQ1012 AOS@ PQ1014 AOS@ PQ1015 AOS@ PQ1011 NIKO@ PQ1012 NIKO@ PQ1014 NIKO@ PQ1015 NIKO@ PQ1011 SINOPOWER@ PQ1012 SINOPOWER@ PQ1014 SINOPOWER@ PQ1015 SINOPOWER@

AON6324 AON6324 AON6324 AON6324 PK632BA PK632BA PK632BA PK632BA SM4513NHKPCTRG SM4513NHKPCTRG SM4513NHKPCTRG SM4513NHKPCTRG
SB00001H100 SB00001H100 SB00001H100 SB00001H100 SB000018K00 SB000018K00 SB000018K00 SB000018K00 SB00001J000 SB00001J000 SB00001J000 SB00001J000

PQ1021 AOS@ PQ1022 AOS@ PQ12 AOS@ PQ1021 NIKO@ PQ1022 NIKO@ PQ12 NIKO@
PQ1021 SINOPOWER@ PQ1022 SINOPOWER@ PQ12 SINOPOWER@

AON6324 AON6324 AON6324 PK632BA PK632BA PK632BA

SB00001H100 SB00001H100 SB00001H100 SB000018K00 SB000018K00 SB000018K00 SM4513NHKPCTRG SM4513NHKPCTRG SM4513NHKPCTRG
SB00001J000 SB00001J000 SB00001J000

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 NA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 104 of 108
5 4 3 2 1
 5 4 3 2 1

+3VS
D +3VS D

2
PR7619
0_0402_5%
@

1
PR7699 PR7640 @
@ 1 2 0_0402_5% 1 1/16W_10K_1%_0402
[102] GPU_TGP_R-
2
PC7601

OPT@ PC7801
680P_50V_K_X7R_0402

2
PR7601 OPT@ 1U_6.3V_K_X7R_0402
1/16W_100_1%_0402 OPT@ 2 1 2 PC7602
PC7807 OPT_NS@

1 2 1 OPT@ 1000P_50V_K_X7R_0402
[102] GPU_TGP_R+
47P_50V_J_NPO_0402

1
2 PR7602 OPT@ PR7645 OPT@ PR7641 @ PR7603
BS_OK_Threshold: 6V 1/16W_75K_1%_0402 1/16W_1K_1%_0402 1/16W_10K_1%_0402 1 2 1 2 PR7604 BS_REF: 0.05V 1/16W_237K_1%_0402 1/16W_10K_1%_0402
FBVDDQ_R+ 1 2 2 1 1 2 OVRM_SKIP OPT@
@
2

2
1 PR7806 @ PR7618

27
2 1/16W_0_1%_0402 1/16W_0_1%_0402 PU7601 1 2 PC7603 1000P_50V_K_X7R_0402
2

@ OPT@

VCC
PR7605 PC7604 25 PR7620 OPT@ PR7606
SH_IN_N1 1 SKIP 26 1 2 1 2 PR7607
1/16W_665_1%_0402 1000P_50V_K_X7R_0402 1/16W_10K_1%_0402 CM_REF: 0.845V 1/16W_365K_1%_0402 1/16W_680K_1%_0402
1 SH_IN_P1 2 SH_IN_N1 MODE_SEL 28 OVRM_EN 1 2
@ BG_REF_OUT OPT@
GND_FET BS_IN1 3 SH_IN_P1 ENABLE 31
OPT@ =1.3V OPT@
1

SH_IN_N2 BS_IN1 NC4 BS_REF

PR7698@ 1 2 0_0402_5% 4 24
[107] FBVDDQ_R- SH_IN_P2 SH_IN_N2 BS_REF BG_REF_OUT
PR7805 1 2 1/16W_49.9_1%_0402 5 23
0.1U_25V_K_X5R_0402
1

BS_IN2 6 SH_IN_P2 BG_REF_OUT 22 CM_REF_IN 1 2 PC7605

OPT@ 1000P_50V_K_X7R_0402
PC7802

SH_O2 7 BS_IN2 CM_REF_IN 21 OPT@

8 SH_O2 NC3 20
PR7608 OPT@ ADC_IN_P [32]
2

10 NC1 DIFF_OUT_P 19
1/16W_49.9_1%_0402 ADC_IN_N [32]
1 2 11 SH_O3 DIFF_OUT_N 18
[107] FBVDDQ_R+
2

0.015U_25V_K_X7R_0402
SH_IN_Nx BS_IN3 NC2

@
PC7806 OPT@

OPT@

1 12 17 PC7611 2 1
47P_50V_J_NPO_0402

13 SH_IN_P3 SH_O4 32 SH_O1

PR7610
BS_OK_Threshold: 6V 2

1/16W_634_1%_0402
14 SH_IN_N3 SH_O1 30 BS_OK
PR7609 OPT@ 47P_25V_J_NPO_0402

OPT@ PC7606

1
BS_IN4 BS_OK MUX_SEL
C 1/16W_75K_1%_0402 15 29 C
2 16 SH_IN_P4 MUX_SEL
PR7611 PR7612

GND
1

2
1 GND_FET SH_IN_N4
@

9 1 1/16W_0_1%_0402 1/16W_0_1%_0402
22

GND_FET

@
PR7614

PC7607
2

1/16W_442_1%_0402

0.015U_25V_K_X7R_0402
NCP45492XMNTWG_QFN32_4X4

33

@2

@2
PC7608 OPT@ @
1000P_50V_K_X7R_0402 +3VS 2

1
2
1
2 2
1

GND_FET

@ PR7677
1/16W_0_1%_0402
PC7609 PC7610

OPT@
PR7613 47P_25V_J_NPO_0402 47P_25V_J_NPO_0402

2
1/16W_665_1%_0402 1 1

@
1

@ PR7615
1/16W_10K_1%_0402
OPT@

1
SH_IN_N1 SH_IN_P1 SH_IN_N2 SH_IN_P2 PR7617 @ 1 2 0_0402_5% 1
[32] ADC_MUX_SEL
TC7601
PC7808 OPT_NS@

PC7809 OPT_NS@

PC7805 OPT_NS@

PC7810 OPT_NS@
47P_50V_J_NPO_0201

47P_50V_J_NPO_0201

47P_50V_J_NPO_0201

47P_50V_J_NPO_0201

PAD
2 2 2 2

@
1 1 1 1

TGP SH_IN Filter FBVDDQ SH_IN Filter

ON-NCP45492 UPI-US5650
B B
R21=PR7614=442 R21=PR7614=332
R25=PR7610=634 R25=PR7610=475
R23=PR7605=665 R23=PR7605=499
R26=PR7613=665 R26=PR7613=499
R17=PR7603=237K R17=PR7603=316K

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 GPU Monitor

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C ThinkPad E14 GEN4 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 02, 2022 Sheet 105 of 108
5 4 3 2 1
 A
B
C
D

5
5

PEX_HVDD

+1.8VGS

1
+1.0VGS

CV2022 OPT@

+VDD18
22U_6.3V_M_X6S_0603
CV2008 OPT@

OPT@
2
1
10U_6.3V_M_X6S_0402
OPT@ CG3307

LG2701
CV2020 OPT@
2
1

2
10U_6.3V_M_X5R_0402

2
1
CV2009 OPT@
10U_6.3V_M_X6S_0402
1U_6.3V_M_X5R_0201

2
1
2
1

Near GPU
CV2021 OPT@
OPT@ CG3308

BLM18KG300TN1D_2P
Near GPU

10U_6.3V_M_X6S_0402 CV2010 OPT@

30ohms (ESR=0.01) Bead

2
1
22U_6.3V_M_X6S_0603

2
1
1U_6.3V_M_X5R_0201
2
1

CG2701 OPT@

2
1
22U_6.3V_M_X6S_0603
OPT@ CG3309

2
1
Near GPU
1U_6.3V_M_X5R_0201 CG2702 OPT@

2
1
CV2005 OPT@
OPT@ CG3310 4.7U_6.3V_M_X6S_0402

Under GPU
4.7U_6.3V_M_X6S_0402

2
1
2
1

1U_6.3V_M_X5R_0201
CV2853 OPT@
CV2018 OPT@ 1U_6.3V_M_X6S_0201
4.7U_6.3V_M_X6S_0402
OPT@ CG2704
2
1

2
1
2
1

CV2854 OPT@
1U_6.3V_M_X6S_0201
CG3302 1U_6.3V_M_X6S_0201
CV2014 OPT@
OPT_NS@

2
1
2
1

1U_6.3V_M_X6S_0201
OPT@ CG2705
1U_6.3V_M_X5R_0201
CV2855 OPT@
Under GPU

2
1
2
1

1U_6.3V_M_X6S_0201
CV2015 OPT@
CG3303 1U_6.3V_M_X6S_0201
2
1

Under GPU
1U_6.3V_M_X6S_0201
OPT_NS@

2
1
CV2856 OPT@
2
1

1U_6.3V_M_X5R_0201 OPT@ CG2706 1U_6.3V_M_X6S_0201

CV2016 OPT@
Under GPU

2
1
2
1

1U_6.3V_M_X6S_0201
CG3304
OPT_NS@ 1U_6.3V_M_X6S_0201

2
1
2
1

1U_6.3V_M_X5R_0201

4
4

OPT@ CG2707
OPT_NS@ CG3305

Near GPU

2
1
2
4.7U_6.3V_M_X5R_0402 1
1U_6.3V_M_X6S_0201

OPT_NS@ CG3306
2

2
1
2

4.7U_6.3V_M_X5R_0402
PJ7006

OPT@ CG3312
1

2
1
@

4.7U_6.3V_M_X5R_0402
1

JUMP_43X39

CORE_PLLVDD
+1.8VGS

RG3302
0_0603_SP
1

@
+1.8VGS

OPT@
CG3709
1
2

10U_6.3V_M_X6S_0402
OPT@
CG3710
1
2

10U_6.3V_M_X6S_0402

3
3

OPT@
CG3711
1
2

10U_6.3V_M_X6S_0402
OPT@
CG3712
1
2

10U_6.3V_M_X6S_0402
OPT@
CG3713
1
2

10U_6.3V_M_X6S_0402
OPT@ OPT@
+FB_PLLAVDD

OPT@ CG2805 CG3689 CG3669

1
2
1
2

2
1

10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603
1U_6.3V_M_X6S_0201
OPT@ OPT@
Under GPU

OPT@ CG2806 CG3690 CG3670

1
2
1
2
Near GPU

2
1

10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603
1U_6.3V_M_X6S_0201
OPT@ OPT@
CG3691 CG3671
1
2
1
2

Under GPU

10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603
OPT@ OPT@
CG3692 CG3672
1
2
1
2

10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603
OPT@ OPT@
OPT@ CG2807 CG3693 CG3673
1
2
1
2
1
2

200mA

4.7U_6.3V_M_X6S_0402 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

OPT@ OPT@ OPT_NS@
CG2809 CG3694 CG3674
2
1
1
2
1
2

22U_6.3V_M_X6S_0603 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

Near GPU

OPT@ OPT_NS@
CG3695 CG3675
Issued Date
1
2
1
2

10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603
Security Classification
1

OPT@ OPT@
CG3696 CG3676
1
2
1
2

Place close to BGA

teknisi-indonesia.com

10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603
OPT@

OPT@ OPT@
CG3697 CG3677
LG2801
1
2
1
2

10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603
OPT@ OPT@
CG3698 CG3678
1
2
1
2

BLM18KG300TN1D_2P

2
2

10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603
2018/08/02

OPT@ OPT@
CG3699 CG3679
1
2
1
2

+1.8VGS

10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603
OPT@ OPT@
CG3700 CG3680
30ohms (ESR=0.01) 0603 Bead
1
2
1
2

10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603
OPT@ OPT_NS@
OPT@ CG3719 CG3701 CG3681
1
2
1
2
1
2

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

OPT@ OPT@
OPT@ CG3718 CG3702 CG3682
1
2
1
2
1
2

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

OPT@ OPT_NS@
Deciphered Date

OPT@ CG3717 CG3703 CG3683

1
2
1
2
1
2

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

OPT@ OPT@
OPT@ CG3716 CG3704 CG3684
LC Future Center Secret Data
1
2
1
2
1
2

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

OPT@ OPT@
OPT@ CG3715 CG3705 CG3685
1
2
1
2
1
2

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

2018/08/02

OPT@ OPT@
OPT@ CG3714 CG3706 CG3686
1
2
1
2
1
2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

OPT@ OPT@
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

OPT@ CG3666 CG3707 CG3687

1
2
1
2
1
2

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

OPT@ OPT@
OPT@ CG3667 CG3708 CG3688
1
2
1
2
1
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

Date:
Title

Custom
NVVDD

GPU Decoupling

Size Document Number

1
1

Sheet Wednesday, March 02, 2022

ThinkPad E14 GEN4
106
of
108
1
Rev
A
B
C
D
 A B C D

GPU_ALL_B+ PR2212 FBVDDQ_B+ +3VALW

1W_0.005_1%_1206_100PPM/C

1 1 2 1

2
OPT@ PR2205
1/10W_5.1_5%_0603

2
PJ2201 PJ2202
JUMPER JUMPER OPT@

1
@ @

1
FBVDDQ_R+ +FBVDDQ_3V3
MP2941_AGND
1
FBVDDQ_R- PC2219

1
1U_6.3V_K_X5R_0402 PC2202
OPT@ PR2208 OPT@ 0.22U_25V_K_X7R_0603
2 OPT@
1/16W_150K_1%_0402 PR2200
+FBVDDQ_BST1 1 2 +FBVDDQ_BST_R1 1 2

2
MP2941_AGND

18

19

13
FBVDDQ_B+

7
PU2200 1/10W_2.2_5%_0603 PL2200
PL2201 OPT@ OPT@ 0.47UH_PCMB063T-R47MS_18A_20% JUMP_43X118 FBVDDQ

3V3

BST1
FS
AGND
BBUP00201209121Y00 OPT@ @
1 2 +FBVDDQ_VIN 2 PJ2200
VIN 11A

10U_25V_K_X5R_0603

10U_25V_K_X5R_0603
+FBVDDQ_LX +FBVDDQ_P

0.01U_50V_K_X5R_0402
68P_50V_J_NPO_0201
12 1 2 2 1
SW1 2 1
1U_25V_K_X5R_0402

1U_25V_K_X5R_0402

220U_B2_6.3VM_R25M
1 1 1 1 1 1

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
PC2200

PC2201

EMC_NS@ PC2215

OPT_EMC@ PC2216

OPT@ PC2222

OPT@ PC2223

OPT@ PC2204

OPT@ PC2205

OPT@ PC2206

OPT@ PC2207

OPT@ PC2208

OPT@ PC2209

OPT@ PC2217

OPT@ PC2218

OPT@ PC7803
11 1
SW2

1
PC2224

PC2225

1 PR2202 1 1 1 1 1 1 1 1 1 1
PGND1 +
1/10W_2.2_5%_0603
2 2 2 2 2 2 3 10 +FBVDDQ_BST2 1 2+FBVDDQ_BST_R2 1 2 EMC_NS@
PGND2 BST2 Vout=1.2V/FBVDDQ_SEL=L
2 2 2 2 2 2 2 2 2 2 2 Vout=1.25V/FBVDDQ_SEL=H
OPT@

OPT@
MP2941AGL-Z_QFN19_3X4 PR2204 PC2221

220P_25V_J_X7R_0402
1/10W_2.2_5%_0603 0.22U_25V_K_X7R_0603
2

6 OPT@ OPT@ +FBVDDQ_SN Vref=0.6V 2

SS +FBVDDQ_P
16 Iout=11A
OPT_NS@

OPT_NS@

1 VOUT
PC2220 1
OCP>20A

1
3300P_50V_K_X7R_0402 5
VID +FBVDDQ_FB
+3VALW PC2210 1

PC2211
OPT@ 17 1000P_50V_K_X7R_0402 PR2203
2 FB Fsw=1MHz

OPT@
EMC_NS@ 1/16W_40.2K_1%_0402
4 2 OPT@ OVP=Vout*1.25

MODE
PGND3

2
9 +FBVDDQ_PG_R 2
UVP=Vout*0.75

CLM

2
PG
PD2200 PR2210 OPT@

EN
LRB751V-40T1G_SOD323-2 1/16W_100K_5%_0402
OPT_NS@ 2 1

14

15
8

1
PR2207 OPT@

1000P_25V_K_X7R_0402
0.1U_25V_K_X5R_0402
OPT_EMC@ PC2212

EMC_NS@ PC2213

OPT_EMC@ PC2214
68P_50V_J_NPO_0201
1
OPT@

1/16W_237K_1%_0402
1/16W_90.9K_1%_0402
1 2 1 2
FBVDDQ_PWROK

2
+FBVDDQ_FB

2
1 2

PR2211
PR2209 @

1
+FBVDDQ_EN

1/10W_487K_1%_0402
FBVDDQ_PWR_EN 1 2 0_0402_5%

OPT@
2 PR2206

1
PR2201 PC2203 1/16W_40.2K_1%_0402

1
1/16W_100K_5%_0402 0.022U_25V_K_X7R_0402_YAGEO 10A/Phase @ OPT@
OPT@ OPT@

2
1

PR2213
2 1
D
PJ2203
FBVDDQ_SEL PR2214 1 2 0_0402_5% @ FBVDDQ_SEL _R 2 PQ7004 OPT@
1 2 G LBSS139WT1G_SC70-3
MP2941_AGND
S

3
2
JUMPER PR2215
3 3

@ 1/16W_100K_5%_0402
@
CAD Note：VRAM_VDDQ_ADJ

1
L = 1.2V
H = 1.25V

Tabel---1:MODE Select Tabel---2:FS Select Tabel---3:CLM Select for per phase

State Interleaving VID Down option Resistor to GND State Fs(kHz) Resistor to GND State CLM Resistor to GND

M1 N Slew down 0 M1 500 0 M1 7A 0

M2 Y Slew down 90k M2 700 90k M2 10A 90k

M3 Y Decay 150k M3 1000 150k M3 12A 150k

M4 N Decay >230k or float M4 1200 >230k or float M4 15A >230k or float

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FBVDDQ
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom 1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ThinkPad E14 GEN4
Date: Wednesday, March 02, 2022 Sheet 107 of 108
A B C D
 A
B
C
D
OPT@ CG3746

1
2
1U_6.3V_M_X6S_0201

NV:4x1uF
OPT@ CG3747

1
2
OPT@ CG3726 1U_6.3V_M_X6S_0201

5
5

1
2
1U_6.3V_M_X6S_0201 OPT@ CG3734 OPT@ CG3748

1
2
1
2
OPT@ CG3727 1U_6.3V_M_X6S_0201 1U_6.3V_M_X6S_0201

GPU

1
2
Under GPU
1U_6.3V_M_X6S_0201 OPT@ CG3735 OPT@ CG3749

1
2
1
2
OPT@
OPT@ CG3728 CG3809 1U_6.3V_M_X6S_0201 1U_6.3V_M_X6S_0201
VRAM

1
2
1
2
1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 OPT@ CG3736 OPT@ CG3750

1
2
1
2
OPT@
OPT@ CG3729 CG3810 1U_6.3V_M_X6S_0201 1U_6.3V_M_X6S_0201

1
2
1
2
1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 OPT@ CG3737 OPT@ CG3751

1
2
1
2
OPT@

+1.8VGS
OPT@ CG3730 CG3811 1U_6.3V_M_X6S_0201 1U_6.3V_M_X6S_0201

1
2
1
2
Reserve 2x220uF 5x22uF 0805

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 OPT@ CG3752

1
2
OPT@
OPT@ CG3731 CG3812 1U_6.3V_M_X6S_0201

1
2
1
2
1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 OPT@ CG3753

1
2
OPT@
OPT@ CG3732 CG3723 1U_6.3V_M_X6S_0201
NV:6x10uF 0402 18x1uF 0201 6x22uF,

1
2
1
2
1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 OPT@ CG3762

1
2

Near GPU
Under or Close to DRAM

OPT@
OPT@ CG3733 CG3720 1U_6.3V_M_X6S_0201

1
2
1
2
1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 OPT@ CG3763

1
2
OPT@ OPT@
CG3725 CG3721 1U_6.3V_M_X6S_0201
OPT_NS@

1
2
1
2
CG3742
1
2

10U_6.3V_M_X6S_0402 10U_6.3V_M_X6S_0402 OPT@ CG3764

1
2
10U_6.3V_M_X6S_0402
OPT@ OPT@
CG3724 CG3722 1U_6.3V_M_X6S_0201
OPT_NS@

1
2
1
2
CG3759
1
2

10U_6.3V_M_X6S_0402 10U_6.3V_M_X6S_0402 OPT@1 CG3765

2

10U_6.3V_M_X6S_0402
1U_6.3V_M_X6S_0201

4
4

OPT@
OPT@ CG3766 CG3756
1
2
1
2
Around DRAM

FBVDDQ
1U_6.3V_M_X6S_0201 22U_6.3V_M_X6S_0603
OPT@
OPT@ CG3767 CG3757
1
2
1
2

1U_6.3V_M_X6S_0201 22U_6.3V_M_X6S_0603
OPT@ OPT@
OPT@ CG3768 CG3754 CG3758
1
2
1
2
1
2

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

OPT@ OPT@
OPT@ CG3769 CG3755 CG3743
1
2
1
2
1
2

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

OPT@ OPT@
OPT@ CG3770 CG3760 CG3744
OPT@
1
2
1
2
1
2

CG3817

1
2
1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603
FBVDDQ

22U_4V_M_X5R_0402
OPT@ OPT@
OPT@ CG3771 CG3761 CG3745
OPT@
1
2
1
2
1
2

CG3818
1
2

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

22U_4V_M_X5R_0402
OPT_NS@
CG3819
1
2

22U_4V_M_X5R_0402
OPT@
CG3820
1
2
FBVDDQ

22U_4V_M_X5R_0402
OPT_NS@
CG3821
1
2

22U_4V_M_X5R_0402
OPT@
CG3822
1
2

3
3

22U_4V_M_X5R_0402
OPT@
CG3823
1
2

22U_4V_M_X5R_0402 OPT@ CG3784

1
2

OPT_NS@
CG3824 1U_6.3V_M_X6S_0201
1
2

22U_4V_M_X5R_0402 OPT@ CG3785

1
2

OPT@
CG3825 1U_6.3V_M_X6S_0201
1
2

Issued Date
22U_4V_M_X5R_0402 OPT@ CG3786
1
2

OPT@
CG3826 1U_6.3V_M_X6S_0201

Security Classification
1
2

22U_4V_M_X5R_0402 OPT@ CG3787

OPT@
1
2

CG3813
OPT@
1
2

CG3827 1U_6.3V_M_X6S_0201
1
2

10U_6.3V_M_X6S_0402
22U_4V_M_X5R_0402 OPT@ CG3788
OPT@
1
2

CG3814
OPT@
1
2

CG3828 1U_6.3V_M_X6S_0201
1
2

10U_6.3V_M_X6S_0402
22U_4V_M_X5R_0402 OPT@ CG3789
OPT@
1
2

CG3815
OPT@
1
2

CG3829 1U_6.3V_M_X6S_0201

2019/12/24
1
2

10U_6.3V_M_X6S_0402
22U_4V_M_X5R_0402 OPT@ CG3790
OPT@
1
2

CG3816
OPT@
1
2

CG3830 1U_6.3V_M_X6S_0201
1
2

10U_6.3V_M_X6S_0402
22U_4V_M_X5R_0402 OPT@ CG3791
1
2

OPT@
CG3831 1U_6.3V_M_X6S_0201
1
2

22U_4V_M_X5R_0402 OPT@ CG3792

1
2
Under or Close to DRAM

1U_6.3V_M_X6S_0201

2
2

OPT@ CG3793
1
2

1U_6.3V_M_X6S_0201
OPT@
Deciphered Date
CG3772
change to X5R at 7/31
1
2

OPT@ CG3794
1
2

10U_6.3V_M_X6S_0402
1U_6.3V_M_X6S_0201
OPT@
CG3773
LC Future Center Secret Data
1
2

OPT@ CG3795
1
2

10U_6.3V_M_X6S_0402
1U_6.3V_M_X6S_0201
OPT@
OPT@ CG3796 CG3774
NV:6x10uF 0402 18x1uF 0201 6x22uF

1
2
1
2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Around DRAM

1U_6.3V_M_X6S_0201 22U_6.3V_M_X6S_0603
2019/12/24

OPT@
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

OPT@ CG3797 CG3775

1
2
1
2

1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

OPT@ OPT_NS@
OPT@ CG3798 CG3780 CG3776
1
2
1
2
1
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

OPT@ CG3738 1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 10U_6.3V_M_X6S_0402

NV:4x1uF

1
2

OPT@ OPT@
C

1U_6.3V_M_X6S_0201 OPT@ CG3799 CG3781 CG3777

1
2
1
2
1
2

Size

Date:
Title

OPT@ CG3739 1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 10U_6.3V_M_X6S_0402

1
2

OPT_NS@ OPT@
1U_6.3V_M_X6S_0201 OPT@ CG3800 CG3782 CG3778
1
2
1
2
1
2

OPT@ CG3740 1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 22U_6.3V_M_X6S_0603

1
2

OPT_NS@ OPT@
1U_6.3V_M_X6S_0201 OPT@ CG3801 CG3783 CG3779
1
2
1
2
1
2

Document Number

OPT@ CG3741 1U_6.3V_M_X6S_0201 10U_6.3V_M_X6S_0402 10U_6.3V_M_X6S_0402

1
2
+1.8VGS

1U_6.3V_M_X6S_0201
VRAM Decoupling

1
1

Wednesday, March 02, 2022

FBVDDQ

Sheet
108
of
ThinkPad E14 GEN4
108
1
Rev
A
B
C
D