32 bit ARM9 Processor Architecture Introduction
The ARM processor core originates within a British computer company called Acorn. In the mid-1980s they were looking for replacement for the 6502 processor used in their BBC computer range, which were widely used in UK schools. None of the 16-bit architectures becoming available at that time met their requirements, so they designed their own 32-bit processor. Other companies became interested in this processor, including Apple who was looking for a processor for their PDA project (which became the Newton). After much discussion this led to Acorns processor design team splitting off from Acorn at the end of 1990 to become Advanced RISC Machines Ltd, now just ARM Ltd. Thus ARM Ltd now designs the ARM family of RISC processor cores, together with a range of other supporting technologies.One important point about ARM is that it does not fabricate silicon itself, but instead just produces the design - we are an Intellectual Property (or IP) company. Instead silicon is produced by companies who license the ARM processor design. The ARM architecture is licensable. Companies that are currently or formerly ARM licensees include Alcatel, Atmel, Broadcom, Cirrus Logic, Digital Equipment Corporation, Freescale, Intel (through DEC), LG, Marvell Technology Group, NEC, NVIDIA, NXP (previously Philips), Oki, Qualcomm, Samsung, Sharp, ST Microelectronics, Symbios Logic, Texas Instruments, VLSI Technology, Yamaha and ZiiLABS. ARM processors are developed by ARM and by ARM licensees. Prominent examples of ARM Limited ARM processor families include the ARM7, ARM9, ARM11 and Cortex. Examples of ARM processors developed by major licensees include the DEC StrongARM, Freescale's i.MX, Marvell (formerly Intel) XScale, NVIDIA's Tegra, ST-Ericsson Nomadik, and Qualcomm's Snapdragon. ARM processors are used extensively in consumer electronics, including PDAs, mobile phones, iPods and other digital media and music players, hand-held game consoles, calculators and computer peripherals such as hard drives and routers.
Programmers model
The arm is 32 bit architecture. In relation to ARM; Halfword means 16 bits and Word means 32 bits. The cause of confusion here is the term word which will mean 16-bits to people with a 16bit background. Most ARMs implement two instruction sets: 32 bit ARM instruction set 16 bit Thumb instruction set
The ARM has seven basic operating modes:
USER: unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised
IRQ : entered when a low priority (normal) interrupt is raised Supervisor : entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations Undef : used to handle undefined instructions System : privileged mode using the same registers as user mode
The typical application will run in an unprivileged mode know as User mode, whereas the various exception types will be dealt with in one of the privileged modes: Fast Interrupt, Supervisor, Abort, Normal Interrupt and Undefined. The difference between the privileged and unprivileged modes is explained as: the ARM core has an output signal (nTRANS on ARM7TDMI, InTRANS, DnTRANS on 9, or encoded as part of HPROT or BPROT in AMBA) which indicates whether the current mode is privileged or unprivileged, and this can be used, for instance, by a memory controller to only allow IO access in a privileged mode. In addition some operations are only permitted in a privileged mode, such as directly changing the mode and enabling of interrupts.All current ARM cores implement system mode.This is simply a privileged version of user mode.
Registers
ARM has 37 registers all of which are 32-bits long. 1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers
The current processor mode governs which of several banks is accessible. Each mode can access a particular set of r0-r12 registers a particular r13 (the stack pointer, sp) and r14 (the link register, lr) the program counter, r15 (pc) the current program status register, cpsr
Privileged modes (except System) can also access a particular spsr (saved program status register)
The CPSR (Current Program Status Register) stores additional information about the state of the processor. In privileged modes, a particular SPSR (Saved Program Status Register) stores
a copy of the previous CPSR value when an exception occurs. This combined with the link register allows exceptions to return without corrupting processor state.
Program status word
Pink psr bits are only in certain versions of the ARM architecture. PSRs split into four 8-bit
fields that can be individually written:
Control(c)
bits 0-7 Reserved for future use Reserved for future use
Extension(x) bits 8-15 Status (s) Flags (f) bits 16-23 bits 24-31
Condition code flags
o o o o
N = Negative result from ALU Z = Zero result from ALU C = ALU operation Carried out V = ALU operation oVerflowed
Sticky Overflow flag - Q flag o Architecture 5TE/J only o Indicates if saturation has occurred
J bit o Architecture 5TEJ only o J = 1: Processor in Jazelle state
Interrupt Disable bits. o I = 1: Disables the IRQ. o F = 1: Disables the FIQ. o T Bit o Architecture xT only
o T = 0: Processor in ARM state o T = 1: Processor in Thumb state Mode bits o Specify the processor mode
Program Counter (r15)
When the processor is executing in ARM state: o All instructions are 32 bits wide o All instructions must be word aligned
o
Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned).
When the processor is executing in Thumb state: o All instructions are 16 bits wide o All instructions must be halfword aligned
o
Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned).
When the processor is executing in Jazelle state: o All instructions are 8 bits wide o Processor performs a word access to read 4 instructions at once
