StrongIRFET™

IRFB7545PbF
Application HEXFET® Power MOSFET
 Brushed motor drive applications
 BLDC motor drive applications D VDSS 60V
 Battery powered circuits
 Half-bridge and full-bridge topologies RDS(on) typ. 4.9m
G
 Synchronous rectifier applications max 5.9m
 Resonant mode power supplies S
 OR-ing and redundant power switches ID 95A
 DC/DC and AC/DC converters
 DC/AC inverters

Benefits S
D
 Improved gate, avalanche and dynamic dV/dt ruggedness G
 Fully characterized capacitance and avalanche SOA
 Enhanced body diode dV/dt and dI/dt capability TO-220AB
 Lead-free, RoHS compliant

G D S
Gate Drain Source

Base part number Package Type Standard Pack Orderable Part Number
Form Quantity
IRFB7545PbF TO-220 Tube 50 IRFB7545PbF

14 100
RDS(on), Drain-to -Source On Resistance (m )

ID = 57A

12
80
ID, Drain Current (A)

10 T J = 125°C
60

40
6

20
4
T J = 25°C

2 0
4 6 8 10 12 14 16 18 20 25 50 75 100 125 150 175
TC , Case Temperature (°C)
VGS, Gate -to -Source Voltage (V)

Fig 1. Typical On-Resistance vs. Gate Voltage Fig 2. Maximum Drain Current vs. Case Temperature

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Absolute Maximum Rating
Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 95
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 67 A
IDM Pulsed Drain Current  380
PD @TC = 25°C Maximum Power Dissipation 125 W
Linear Derating Factor 0.83 W/°C
VGS Gate-to-Source Voltage ± 20 V
TJ Operating Junction and
-55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds (1.6mm from case) 300
Mounting Torque, 6-32 or M3 Screw 10 lbf·in (1.1 N·m)
Avalanche Characteristics
Symbol Parameter Max. Units
EAS (Thermally limited) Single Pulse Avalanche Energy  140 mJ
EAS (Thermally limited) Single Pulse Avalanche Energy  235
IAR Avalanche Current  A
See Fig 15, 16, 23a, 23b
EAR Repetitive Avalanche Energy  mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case  ––– 1.21
RCS Case-to-Sink, Flat Greased Surface 0.50 ––– °C/W
RJA Junction-to-Ambient ––– 62
Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 60 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 46 ––– mV/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 4.9 5.9 m VGS = 10V, ID = 57A 
––– 6.3 –––  VGS = 6.0V, ID = 29A 
VGS(th) Gate Threshold Voltage 2.1 ––– 3.7 V VDS = VGS, ID = 100µA
––– ––– 1.0 VDS = 60V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 150 VDS = 60V,VGS = 0V,TJ =125°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG Gate Resistance ––– 2.3 ––– 

Notes:
Repetitive rating; pulse width limited by max. junction temperature.
 Limited by TJmax, starting TJ = 25°C, L = 88µH, RG = 50, IAS = 57A, VGS =10V.
ISD  57A, di/dt  810A/µs, VDD  V(BR)DSS, TJ 175°C.
Pulse width  400µs; duty cycle  2%.
 Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
 Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
 R is measured at TJ approximately 90°C.
 Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 22A, VGS =10V.

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Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 90 ––– ––– S VDS = 25V, ID = 57A
Qg Total Gate Charge ––– 75 110 ID = 57A
Qgs Gate-to-Source Charge ––– 19 ––– VDS = 30V
nC
Qgd Gate-to-Drain Charge ––– 24 ––– VGS = 10V
Qsync Total Gate Charge Sync. (Qg – Qgd) ––– 32 –––
td(on) Turn-On Delay Time ––– 12 ––– VDD = 30V
tr Rise Time ––– 72 ––– ID = 57A
ns
td(off) Turn-Off Delay Time ––– 44 ––– RG= 2.7
tf Fall Time ––– 43 ––– VGS = 10V 
Ciss Input Capacitance ––– 4010 ––– VGS = 0V
Coss Output Capacitance ––– 370 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 230 ––– ƒ = 1.0MHz, See Fig.7
pF
Effective Output Capacitance
Coss eff.(ER) ––– 370 ––– VGS = 0V, VDS = 0V to 48V
(Energy Related)
Coss eff.(TR) Output Capacitance (Time Related) ––– 470 ––– VGS = 0V, VDS = 0V to 48V
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
Continuous Source Current MOSFET symbol D

IS ––– ––– 95
(Body Diode) showing the
A G
Pulsed Source Current integral reverse
ISM ––– ––– 380
(Body Diode)  p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.2 V TJ = 25°C,IS = 57A,VGS = 0V 

dv/dt Peak Diode Recovery dv/dt ––– 12 ––– V/ns TJ = 175°C,IS = 57A,VDS = 60V
––– 33 ––– TJ = 25°C VDD = 51V
trr Reverse Recovery Time ns
––– 37 ––– TJ = 125°C IF = 57A,
––– 36 ––– TJ = 25°C di/dt = 100A/µs 
Qrr Reverse Recovery Charge nC
––– 48 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 2.0 ––– A TJ = 25°C 

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1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

100 7.0V 7.0V
6.0V 6.0V
5.5V 100 5.5V
5.0V 5.0V
BOTTOM 4.5V BOTTOM 4.5V

10
4.5V

10
4.5V
1

60µs PULSE WIDTH 60µs PULSE WIDTH

Tj = 25°C Tj = 175°C
0.1 1
0.1 1 10 100 1000 0.1 1 10 100 1000
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 3. Typical Output Characteristics Fig 4. Typical Output Characteristics

1000 2.4
ID = 57A

RDS(on) , Drain-to-Source On Resistance

V GS = 10V
2.0
ID, Drain-to-Source Current (A)

100

TJ = 175°C
1.6
(Normalized)

10
TJ = 25°C 1.2

1
0.8
V DS = 25V
60µs PULSE WIDTH
0.1 0.4
2.0 3.0 4.0 5.0 6.0 7.0 8.0 -60 -40 -20 0 20 40 60 80 100120140160180
V GS, Gate-to-Source Voltage (V) TJ , Junction Temperature (°C)

Fig 5. Typical Transfer Characteristics Fig 6. Normalized On-Resistance vs. Temperature

100000 14.0
VGS = 0V, f = 1 MHZ ID = 57A
Ciss = C gs + Cgd, C ds SHORTED
Crss = C gd
12.0 V DS= 48V
V GS, Gate-to-Source Voltage (V)

Coss = Cds + Cgd V DS= 30V

10.0
C, Capacitance (pF)

10000 V DS= 12V

Ciss 8.0

6.0
Coss
1000
4.0
Crss

2.0

100 0.0
1 10 100 0 10 20 30 40 50 60 70 80 90 100
V DS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)

Fig 8. Typical Gate Charge vs.

Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
Gate-to-Source Voltage
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1000

100µsec
1msec
100

ID, Drain-to-Source Current (A)

ISD, Reverse Drain Current (A)

100 TJ = 175°C

10 OPERATION
TJ = 25°C IN THIS
AREA
LIMITED BY
10 RDS(on) 10msec
1

Tc = 25°C DC
Tj = 175°C
V GS = 0V Single Pulse
1.0 0.1
0.2 0.6 1.0 1.4 1.8 0.1 1 10
V SD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 9. Typical Source-Drain Diode Forward Voltage Fig 10. Maximum Safe Operating Area
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

80 0.6
Id = 1.0mA
78 0.5

76 Energy (µJ) 0.4

74
0.3
72
0.2
70

0.1
68

66 0.0
-60 -40 -20 0 20 40 60 80 100120140160180 -10 0 10 20 30 40 50 60
T J , Temperature ( °C ) VDS, Drain-to-Source Voltage (V)

Fig 11. Drain-to-Source Breakdown Voltage Fig 12. Typical Coss Stored Energy

16
RDS(on), Drain-to -Source On Resistance ( m)

14 Vgs = 5.5V
Vgs = 6.0V
Vgs = 7.0V
12 Vgs = 8.0V
Vgs = 10V

10

4
0 40 80 120 160 200

ID, Drain Current (A)

Fig 13. Typical On-Resistance vs. Drain Current

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10

Thermal Response ( Z thJC ) °C/W

1
D = 0.50

0.20
0.10
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE Notes:
( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1 1
t1 , Rectangular Pulse Duration (sec)

Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
100
Avalanche Current (A)

10

1 Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.

0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02
tav (sec)

Fig 15. Avalanche Current vs. Pulse Width

150
TOP Single Pulse Notes on Repetitive Avalanche Curves , Figures 15, 16:
BOTTOM 1.0% Duty Cycle (For further info, see AN-1005 at [Link])
125 ID = 57A [Link] failures assumption:
EAR , Avalanche Energy (mJ)

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of Tjmax. This is validated for every
100 part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not
exceeded.
75
3. Equation below based on circuit and waveforms shown in Figures
23a, 23b.
50 4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
25 6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 15, 16).
0 tav = Average time in avalanche.
25 50 75 100 125 150 175 D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
Fig 16. Maximum Avalanche Energy vs. Temperature EAS (AR) = PD (ave)·tav

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4.0 12
IF = 38A
3.5 V R = 51V
V GS(th) , Gate threshold Voltage (V)

10
TJ = 25°C
3.0
TJ = 125°C
8
2.5

IRRM (A)
ID = 100µA 6
2.0 ID = 250µA
ID = 1.0mA 4
1.5
ID = 1.0A

1.0 2

0.5 0
-75 -50 -25 0 25 50 75 100 125 150 175 0 200 400 600 800 1000
TJ , Temperature ( °C ) diF /dt (A/µs)

Fig 17. Threshold Voltage vs. Temperature Fig 18. Typical Recovery Current vs. dif/dt
12 200
IF = 57A IF = 38A
V R = 51V V R = 51V
10
TJ = 25°C TJ = 25°C
150
TJ = 125°C TJ = 125°C
8
QRR (nC)
IRRM (A)

6 100

4
50
2

0 0
0 200 400 600 800 1000 0 200 400 600 800 1000
diF /dt (A/µs) diF /dt (A/µs)

Fig 19. Typical Recovery Current vs. dif/dt Fig 20. Typical Stored Charge vs. dif/dt

200
IF = 57A
V R = 51V
TJ = 25°C
150
TJ = 125°C
QRR (nC)

100

50

0
0 200 400 600 800 1000
diF /dt (A/µs)

Fig 21. Typical Stored Charge vs. dif/dt

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Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs

V(BR)DSS

15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
20V
tp 0.01 I AS

Fig 23a. Unclamped Inductive Test Circuit Fig 23b. Unclamped Inductive Waveforms

Fig 24a. Switching Time Test Circuit Fig 24b. Switching Time Waveforms
Id
Vds

Vgs

VDD
Vgs(th)

Qgs1 Qgs2 Qgd Qgodr

Fig 25a. Gate Charge Test Circuit Fig 25b. Gate Charge Waveform

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TO-220AB Package Outline (Dimensions are shown in millimeters (inches))

TO-220AB Part Marking Information

EXAM PLE: T H IS IS A N IR F 1 0 1 0
LO T C O D E 1789 IN T E R N A T IO N A L PART NUM BER
ASSEM BLED O N W W 19, 2000 R E C T IF IE R
IN T H E A S S E M B L Y L IN E "C " LO G O
D ATE C O D E
YEA R 0 = 2000
N o t e : "P " in a s s e m b ly lin e p o s it io n ASSEM BLY
in d ic a t e s "L e a d - F r e e " LO T C O D E W EEK 19
L IN E C

TO-220AB packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at [Link]

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Qualification Information†
Industrial
Qualification Level (per JEDEC JESD47F) ††

Moisture Sensitivity Level TO-220 N/A

RoHS Compliant Yes

† Qualification standards can be found at International Rectifier’s web site: [Link]

†† Applicable version of JEDEC standard at the time of product release.

Revision History
Date Comment
Updated EAS (L =1mH) = 235mJ on page 2
11/5/2014 Updated note 8 “Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 22A, VGS =10V”. on page 2
Updated package outline on page 9

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA

To contact International Rectifier, please visit [Link]

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