New Horizon College of Engineering, Bengaluru
Department: ISE
Academic Semester: 2024-25
Semester:III Section:A1 Course Code: 22ISL32 Course :Digital Logic Design
Lab In-charge:Dr Kalaivani D Contact Hours /week: 02 # of credits: 01
CIE:50 SEE:50 Exam Hours: 3 Hrs
Exp. No. /
List of Experiments / Programs Hours COs
Pgm. No.
Prerequisite Experiments / Programs / Demo
NA NA
PART-A
1 Given a 4-variable logic expression, simplify it using Entered 2 22ISL32.1
Variable Map and realize the simplified logic expression using 8:1
multiplexer IC.
2 Perform half and full adder using combinational circuits 2 22ISL32.1
3 Perform half and full subtraction using combinational circuits. 2 22ISL32.1
4 Realize JK, D and T Flip-Flops and verify its truth table 2 22ISL32.1
5 Design and implement Ring counter and Johnson counter using 4- 2 22ISL32.2
bit shift register and demonstrate its working
6 Design and implement a mod-n (n<8) synchronous up or down 2 22ISL32.2
counter using J-K Flip-Flop ICs and demonstrate its working.
PART-B
7 Simulate and verify the working of 8:1 multiplexer using Verilog 2 22ISL32.2
code.
8 Simulate and verify the working of half and full adder using 2 22ISL32.2
Verilog code.
9 Simulate and verify the working of half and full subtractor using 2 22ISL32.3
Verilog code
10 Simulate and verify the working of the JK,D and T Flip flop using 2 22ISL32.3
Verilog code
11 Simulate and verify the working of Ring and Johnson Counter 2 22ISL32.4
using Verilog code.
12 Simulate and verify mod 8 synchronous up or down counter using 2 22ISL32.4
Verilog code.
COURSE OUTCOMES: At the end of the Course, the Student will be able to:
22ISL32. Analyze and design combinational logic circuits.
1
22ISL32. Realize flip flop and verify the truth table.
2
22ISL32. Implementation of counters using flip flops.
3
22ISL32. Implementation of logic circuits using DLD.
NHCE/LPT/004
4
Mapping of CO v/s PO:
PO/ PO PO PO PO PO PO PO PO PO PO1 PO1 PO1 PSO PSO
CO 1 2 3 4 5 6 7 8 9 0 1 2 1 2
CO1 3 3 3 2 2 - - - - - - 2 3 3
CO2 3 3 3 2 2 - - - - - - 2 3 3
CO3 3 3 3 2 2 - - - - - - 2 3 3
CO4 3 3 3 2 2 - - - - - - 2 3 3
AVG 3 3 3 2 2 - - - - - - 2 3 3
Correlation levels:1-Slight (Low) 2-Moderate (Medium)3-Substantial (High)
LAB PLAN
Remarks
Program
Planned
Levels
Faculty
Actual
RBT
COs
Date
Date
Sign
Experiment / Program
#
Given a 4-variable logic
expression, simplify it using
Entered Variable Map and L2 22ISL32.1
1
realize the simplified logic
expression using 8:1
multiplexer IC.
Perform half and full adder L2
2 22ISL32.1
using combinational circuits
Perform half and full
3 subtraction using L2 22ISL32.1
combinational circuits.
Realize JK, D and T Flip-Flops
4 and verify its truth table L3 22ISL32.1
Design and implement Ring
counter and Johnson
5 counter using 4-bit shift
register and demonstrate its L4 22ISL32.2
working
Design and implement a
mod-n (n<8) synchronous
6 up or down counter using J- L4 22ISL32.2
K Flip-Flop ICs and
demonstrate its working.
Simulate and verify the
7 working of 8:1 multiplexer 22ISL32.2
L3
using Verilog code.
NHCE/LPT/004
Simulate and verify the
8 working of half and full L3 22ISL32.2
adder using Verilog code.
Simulate and verify the
working of half and full
9 L4 22ISL32.3
subtractor using Verilog
code
Simulate and verify the
10 working of the JK,D and T L4 22ISL32.3
Flip flop using Verilog code
Simulate and verify the
working of Ring and
11 L4 22ISL32.4
Johnson Counter using
Verilog code.
Simulate and verify mod 8
12 synchronous up or down L4 22ISL32.4
counter using Verilog code.
Open-Ended Experiments/programs
Additional Open-Ended
Planned Date Actual Date Remarks
Experiments/Programs
LAB Test-1
LAB Test-2
Assessment and Evaluation
Continuous Internal Evaluation (50 Marks)
Test (s) Weekly Assessment
RBT Levels
20 30
L1 Remember -
L2 Understand 10 10
L3 Apply 5 10
L4 Analyze 5 10
L5 Evaluate -
L6 Create -
Semester End Examination (50 Marks)
Exam Marks Distribution
RBT Levels
(50)
L1 Remember -
L2 Understand 10
L3 Apply 20
L4 Analyze 10
L5 Evaluate
L6 Create
LabIn-charge HoD
NHCE/LPT/004
