Fundamentals of Data Conversion: Part I.

Sebastian Hoyos
[Link]
Several of these slides were provided by

Dr. Jose Silva-Martinez and Dr. Jun Zhou

 Outline
• Fundamentals of Analog-to-Digital Converters

• Introduction

• Sampling and Quantization

• Quantization noise and distortion

• INL and DNL

• Technological related issues

• Sample and Hold

• Switching issues

• S/H Accuracy

• Active S/H

• Switch around S/H

The Smartphone market

• Global smartphone market projected to grow

 Anticipated global unit sales to approach 400 millions in 2013
(market research report from Forward Concepts Co)
 Projected revenue in 2012: $32.2 billion
(source: In-Stat Group)
Multi-standard Wireless Systems
• Multiple services
• Reuse circuits as much as possible
• Power
WiFi

• Area
• Competitiveness GSM

• Smaller Cell phone,

Bluetooth

stronger function, WCDMA

longer battery duration

GPS

• Use of digital (analog unfriendly) FM

nanometric tecnologies
WiMax &
802.20
 Multi-standard Wireless Systems
 Exponential growth in mobile computing and broadband wireless
 Major need for high dynamic range, wide-bandwidth, low power ADCs.
Bandwidth requirements for higher connectivity
Bluetooth, 802.11b
IS-95 and 802.11g
DECT 802.11a
DTV UMTS
GSM
Specturm

> 45 dB

0.05 0.8 1.0 1.9 2 2.4 5.4

Frequency (GHz)

 Higher flexibility on operational frequency and bandwidth, higher

blocker rejection, higher dynamic range
 Receiver Architectures:
 Super-heterodyne, Low-IF, Direct Conversion, High-IF, Digital Radio
What is an Analog-to-Digital Converter (ADC)?
Analog Digital
010010110010100101010
101010101001010010100
101001010100100100100
101100110010101001001
01001001010
 Continuous with no  Discrete with limited range;
apparent discontinuities ADC based on binary numbers with
limited number of bits.
 The way we interpret our
surroundings: sound, light,  The way we mathematically
temperature … etc represent and process our
world using electronic “brain”
power
R. Walden, 1999
How does an ADC work?
Analog Digital
010010110010100101010
10010100
101010101001010010100
10100101
101001010100100100100
00100110
101100110010101001001
01011001
01001001010 010
 Continuous with no  Discrete with limited range;
apparent discontinuities
Sampling

x(t)
ADC
x(nTS)
Quantization based
7
6
)
on binary numbers with
Decoding

x(nT )+q(nTlimited
111
110
number
N bits of bits.
 The way we interpret our
S S 5 101

010

surroundings: sound, light,  The way we mathematically

2
1 001
δ(t-nT )
S
0 000

temperature … etc represent and process our

world using electronic “brain”
power
 How does an ADC work?
Analog ADC
x(t) x(n)
Digital

t nTS

Quantization
noise 10010100
Sampling Quantization Decoding
7 111 10100101
00100110
6 110
x(t) x(nTS) x(nTS)+q(nTS) 5 101 N bits

01011001
2 010
1 001
δ(t-nTS) 0 000

010
x(n)
2N Levels
separated
δ(n) by 1LSB,
nTS
1LSB =
VFS* / 2N

nTS
* VFS = full scale range, Vmax-Vmin
 ADCs: Yesterday vs. Today
Example: Digital photography (8-12b ADCs)
2000 2009
CCD/ CCD/
DSP
DSP (balance control, black level
CMOS Balance CMOS
Image
AMP
Control ADC (black level
compensation , Image
AMP ADC compensation, image
stabilization, exposure levels,
Array encoding ...etc) Array noise reduction, lens shading
correction, encoding...etc)

 0.5-0.8µm CMOS with 5V supply (moderate gate density and  90nm-180nm CMOS with 1.2-1.8V supplies (high gate density
speed in DSPs) and speed in DSPs)
 2M pixel CCD sensor (low pixel scanning speed)  12M pixel CCD sensor (high pixel scanning speed)
 Some pre-ADC analog conditioning  Minimal pre-ADC analog conditioning
 ~ 2.5mV / LSB  ~ 0.5mV / LSB

 Faster DSPs capable of  ADCs are indispensable,  ADCs are becoming the
performing numerous but now need to handle bottleneck for advancement,
complex functions are smaller signals at higher and new design techniques
developed thanks to speeds with similar or need to be developed.
advanced CMOS higher resolutions.
ADCs: Tomorrow?
ADC IEEE literature survey: 2006-2008
20
Pipeline ADC
18 Applications
Today
16

Resolution (bits)
14
12
10
8 Sigma-Delta
6 Pipelined
4 Flash
2
0.01
0.1 1 10 100 1000 10000 Tomorrow
Signal Bandwidth (MHz)

 Pipeline ADC is currently most published

architecture
 Pipeline ADC is breaking the trend set by Sigma-
Delta and Flash ADCs 15M? From 1080P to 4G?
 Pipeline ADC is breaking the trend set by Sigma-
20M? 4K (2160P)? HDTV?
Delta and Flash ADCs, and driven by consumer
electronics
 Pipeline ADC is expected to be a key ADC
architecture in future applications
The development of new design techniques for high speed, low voltage and low power Pipeline
ADCs is crucial to stay on the future applications roadmap
 Design Challenges of Pipeline ADCs in Advanced
CMOS Technologies (Summary)

High Speed Low Voltage Low Power

Digital Camera Example

CCD/
DSP
(balance control, black level
CMOS
Image
AMP ADC compensation, image
stabilization, exposure levels,
Array noise reduction, lens shading
correction, encoding...etc)

 With the added speed  Reduction of Device  Many applications are

of new generations of size allows for denser portable and operated
DSPs, the ADC is integration, but device from a battery
becoming the bottleneck reliability dictate lower
 As a potentially
for overall system speed supply voltages
power hungry
 in addition to  Reduced supplies component, the ADC
increased speed, the DSP means reduced signal power needs to be
ability to perform more range, which requires a reduced to help prolong
complex tasks will require higher ADC accuracy for battery life
higher ADC resolutions the same number of bits
Super-heterodyne Receiver
Antenna
RF High IF Baseband
(0.45-5 GHz) (100-200 MHz) (< 20 MHz)
Digital
Output
LPF
Baseband
BPF LNA VGA BPF
ADC

LO1 LO2

 Invented by Armstrong in 1918

 Hardware specific radio architecture
Extensive filtering to relax ADC specs
Suitable for narrow-band applications
Design issues for multi-standard solutions
Antenna
Limited by flicker noise
RF High IF Baseband
(0.45-5 GHz) (100-200 MHz) (< 20 MHz)
Digital
Output
Not flexible
LPF
Baseband
BPF LNA VGA BPF
Hardware intensive
ADC

LO1 LO2

Excessive power at the front-end (Linearity issues)

Extensive down conversions: LO and mixers increase both
noise and power consumption
Extensive filtering: Area, Power and Noise issues
Not fully compatible for the Telecoms roadmap
Current Multi-standard designs
Antenna
Receiver for standard 1  Minimum sharing of blocks
RF IF
(1-2 GHz) (100-200 MHz)

 Area and power

BPF LNA VGA BPF
consumption overhead

LO1 LO2
 Not Flexible at all
Receiver for standard 2
IF
 Limited number of
RF
RF (1-2 GHz) (100-200 MHz)
Switch standards can be
BPF LNA VGA BPF accommodated

LO1 LO2
Introduction to Analog-to-Digital Converters
• Analog-to-Digital Converters (ADC) are necessary to convert
real world signals (which are analog in nature) to their digital
equivalents for easy processing.
• Common applications for ADCs are communication systems, TV
receivers, Digital Oscilloscopes, Audio applications..

Analog
 Efficient radio transceiver: Direct Conversion
Frequency 16-Channel Multiband
Synthesizer
Antenna Digital Receiver

IF Filter 1 4-
80 MHz channel
RF RF Filter 1 LNA & VGA Mixer ADC 1
digital
signal receiver

4- Software
channel Platform
Antenna Optional digital
receiver DSP
4-
RF Filter 2 LNA & VGA Mixer channel or
RF IF Filter 2 ADC 2
digital
signal receiver FPGAs
4-
channel
digital
receiver

 Direct conversion + broadband ADC (1 receiver per service)

 Lowpass filter is required (~ 50-100 mW)
 13-14 bits 80 MHz Lowpass ADC (500 mW from ADI)
 Bank of receivers, filters and ADCs
Recent Approaches to Broadband Receivers
 Sample rate, downsampling and filtering
R. Crochiere and L. Rabiner, Multirate Digital Signal Processing. Englewood Cliffs, NJ: Prentice Hall,
1983.

 Sampling with built-in anti-aliasing

Y. S. Poberezhskiy [Link]. “Sampling and signal reconstruction circuits performing internal
antialiasing filtering and their influence on the design of digital receivers and transmitters,”
TCASI, Jan. 2004.

 A discrete-time RF sampling receiver

R. B. Staszewski, et. al. “All-digital TX frequency synthesizer and discrete-time receiver for
Bluetooth radio in 130-nm CMOS,” IEEE J. Solid-State Circuits, Dec. 2004.

 SDR receiver
Abidi, “The path to software-defined radio receiver”, IEEE JSSC, May 2007

 Frequency-domain-sampling receivers
S. Hoyos and B. M. Sadler, “Ultra-wideband analog to digital conversion via signal expansion,” IEEE
Transactions on Vehicular Technology, Sept. 2006.
 UCLA SDR receiver

 Direct conversion with tunable LO in the freq. range 800 MHz to 6 GHz.
 Cascade of sincN filters followed by decimation to achieve the initializing needed.
 Good for narrowband signals as a single ADC can handle the bandwidth. But SDR
should also be good for wideband and ultra-wideband signals. Need parallel ADC to
sample at a fraction of Nyquist rate. Parallelization of the front-end will be needed if
want to keep the ADC sampling rate down.

A. Abidi, “The path to software-defined radio receiver”, IEEE JSSC, May 2007
Frequency-Domain ADC Based on Fourier Coefficients
1
Tc
x A/D F0 F1 F2 FN-1

R2
R1

( m+1
x A/D

RN −1 R0

 Mixers and integrators.  No signal reconstruction. Parallel

 Lower frequency sample and digital processing.
hold requirements.  Optimal bit allocation minimizes
quantization error. Some samples may
not be quantized at all.
S. Hoyos and B. M. Sadler, “Ultra-wideband analog to digital conversion via signal expansion,” IEEE Transactions on
Vehicular Technology, Sept. 2006.
Software radio transceiver: Design Issues
Antenna

LNA &
RF RF Filter BP-Σ∆-ADC
VGA
signal
Vin Dout

 Makes it sense to have a multi-standard solution based on this

architecture?
 Bandwidth required?
 Dynamic range required?
 DTV  SNRsignal=25 dB; Blockers > 45 dB; Crest factor > 20 dB
 LNA+VGA+ADC Dynamic Range over 90 dB (practical ?)
 Can you use tracking filters? (back to the past)
Ultimate goal: Reality or Dream
Reconfigurable
Antenna programs
Linear RF
T/R Power DAC
switch amplifier

DSP
RF signal
Filter
+ ADC
LNA

 Concept introduced in 1991

 Modulation/demodulation waveforms in software
 Flexible multi-standard software architecture
 Roadmap for high-resolution Receivers
1 RF A/D DSP
Anti-
RF Filter Aliasing SCF, GmC BB
Filter OP-RC
DR

2 RF A/D DSP
IF or BB
Anti-
RF Filter Aliasing Dig. Filter
Filter
DR

3 G A/D DSP

RF
RF Filter LNA Dig. Mod. Dig. Filter

 How much RF processing should be done before the ADC?

 The front-end must be scalable and configurable to fit multiple standards
 25

The single-chip Transceiver Paradigm

• Modern technologies:
“Digital intensive” System-on-Chip
(SOC) environment
 Scaling of transistor dimensions in digital CMOS
technologies
Increased intra-die variability from device scaling
Defect densities increase in newer technologies
Yields decrease as SOC chip sizes increase
Yield impact on analog specifications leads to
process corner-based overdesign
to allow for analog parameter variations
Increased test cost

Critical Analog components must be minimized M. Onabajo, 2011

 Fast CMOS ADC’s: State of the art
Trends:
Specturm
Extensive use of parallelism
Time interleaved
0.05 0.8 1.0 1.9 2 2.4 5.4 Freq (GHz) Reduced supply voltages make analog

more challenging
Resolution
16 Calibrate Headroom for amplifiers
d Research Goal Little room for cascoding
14
Pipeline Poor devices if VDS is further
12
BP Sigma-delta reduced
10 Pipeline
Pipeline InterleavedUse techniques that take advantage
8
of digital trends
6 Flash Digital circuitry is “cheap and fast”
4 Tendency is Digitally Assisted Analog
10 MS/s 100MS/s 1GS/s 10GS/s 100GS/s Circuits
Sampling rate
R. Walden, 1999
Where we were in 99? Where we are?

LTE
A Little bit of History
A Little bit of History
Jitter and noise limitations on ENOB
Classic FoM to compare ADCs

Recent Σ∆ modulators
Bandwidth (Nyquist) vs. SNDR
1.E+11
ISSCC 1997-2009
1.E+10 VLSI 1997-2009
ISSCC 2009
1.E+09 Jitter=1psrms
Jitter=100fsrms
1.E+08
BW [Hz]

1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
10 20 30 40 50 60 70 80 90 100 110 120
SNDR [dB]
B. Murmann, "ADC Performance Survey 1997-2010, [Link]
 Energy per conversion at Nyquist rate
1.E+07
1.E+06
1.E+05
P/fs [pJ]

1.E+04
1.E+03
1.E+02
ISSCC 2010
1.E+01 ISSCC 1997-2009
VLSI 1997-2009
1.E+00 FOM=100fJ/conv-step
FOM=10fJ/conv-step
1.E-01
10 20 30 40 50 60 70 80 90 100 110 120
SNDR [dB]
B. Murmann, "ADC Performance Survey 1997-2010, [Link]
Data Converters: The main issue

The quantized signal presents

a finite number of output
values that are associated
with digital codes
What the problem is?
Issues: Sampling, Holding and conversion

The quantized signal presents

a finite number of output
values that are associated
with digital codes
Properties of the
Fourier Series
 Properties of the Fourier Series

Modulation properties

Convolution in time
Relevant properties of the Fourier Series

Product in time
Relevant properties of the Fourier Series
Additional properties of the Fourier Series
Define the problem: Sampling Operation
 Sampling Operation: Nyquist Rate

According to the sampling theorem: If no alias

issues, then
Ideal sampling does not add
distortion but replicas of the
original spectrum
 Signal Sampling Theorem

Time domain
sampling

Frequency
Spectrum
 Signal Sampling employing a train of pulses
Time domain sampling with pulses

Spectrum
Alias issue if undersampling
Under-sampling of a broadband signal
S/H and Quantization errors
The sampling and Held operations generate alias
frequency components and (sinc) signal distortion,
respectively

Error is an odd function (no even harmonic

distortions, why?)

Quantization generates harmonic distortion

components when sinusoidal input signals are used

Sin (t ) = S q (t ) + Error (t )

Error Quantized
signal signal

Freq Freq
Distortion due to quantization errors
 ADC metrics: Quantization error
• Signal is sampled at given instants
• Signal is encoded to a limited number of codes resulting in quantization noise
(random signals) and distortion (periodic signals)
 What the fundamental problem is?
Mapping an
infinite resolution
analog signal into
a digital but finite
resolution
representation
Quantization noise for Random (Ramp) input signal
ADC metrics: SQNR
The maximum Signal-to-Quantization Noise ratio (SQNR)
for an N-bit ADC:

SQNRideal =
Psignal
= =
( )
2
A2 / 2 ∆ ⋅ 2 N / 2
= 6.02 N + 1.76 dB
Pnoise Pnoise ∆ / 12
2

• For an ADC with a measured SNDR, the effective number of

bits is defined as:

SNDR (dB) − 1.76

ENOB =
6.02
Quantization noise density

The dynamic range of a system is equal to the signal to noise ratio measured over a
bandwidth equal to half of the sampling (Nyquist) frequency
2
q
Then, σ2 =
12
Is the total while the quantization noise density
(quantization noise measured in a bandwidth of 1 Hz)
2σ 2 q2
Noise density = =
fs 6fs

-fs/2 fs/2
 Incommensurate fs and fin
 Sampling frequency fs is fixed.

 Input frequency fin is chosen to satisfy (a) integer

number of cycles C and (b) N / C = fs / fin is
incommensurate. An easy way is to make N a power of
2 and C a prime number. Additionally to guarantee that
the input frequency falls on a DFT freq. bin use fin =
fs/2-kfs/N, where k is an integer. Then check
inconmesurate requirement.

 Windowing lifts the need to have an integer number

of cycles. Good for measurements.

 Pick N depending on noise floor requirements: The

DFT noise floor is 10*log10(N/2) below the noise floor.
Then DFT noise floor = -SNR_0dFS -10*log10(N/2).
Practical Limitations
Digital to Analog Converters
Practical Definitions
Practical Limitations
Practical Limitations

Quite critical issue! Usually not a major issue

Practical Limitations: Offset error
 Practical Limitations

Usually not a major issue Quite critical issue!

Practical Limitations: Gain error
Practical Limitations: Differential Error
Practical Limitations
Practical Limitations: Integral error
Practical Limitations
Practical Limitations: Absolute Accuracy
 Analog to Digital Converters

Usually the effects of

the systematic offsets
can be minimized
through calibration or
accounted in digital
domain
Digital to Analog Converters
Practical Limitations
Practical Limitations
Practical Limitations

DNL must be smaller or equal to 1 LSB

Practical Limitations
Offset Voltages
Practical Limitations